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/**
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******************************************************************************
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* @file aps256xx.c
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* @modify MCD Application Team
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* @brief This file provides the APS256XX HSPI drivers.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2021 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "aps256xx.h"
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/** @addtogroup BSP
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* @{
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*/
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/** @addtogroup Components
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* @{
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*/
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/** @defgroup APS256XX APS256XX
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* @{
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*/
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/** @defgroup APS256XX_Exported_Functions APS256XX Exported Functions
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* @{
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*/
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/* Read/Write Array Commands *********************/
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/**
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* @brief Reads an amount of data from the memory.
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* @param Ctx Component object pointer
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* @param pData Pointer to data to be read
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* @param ReadAddr Read start address
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* @param Size Size of data to read
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* @param LatencyCode Latency used for the access
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* @param IOMode I/O Mode used for the access
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* @param BurstType Type of burst used for the access
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* @retval Memory status
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*/
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int32_t APS256XX_Read(XSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t ReadAddr, uint32_t Size, uint32_t LatencyCode,
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uint32_t IOMode, uint32_t BurstType)
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{
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XSPI_RegularCmdTypeDef sCommand = {0};
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/* Initialize the read command */
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sCommand.OperationType = HAL_XSPI_OPTYPE_COMMON_CFG;
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sCommand.InstructionMode = HAL_XSPI_INSTRUCTION_8_LINES;
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sCommand.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS;
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sCommand.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE;
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sCommand.Instruction = ((BurstType == 0U) ? APS256XX_READ_LINEAR_BURST_CMD : APS256XX_READ_CMD);
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sCommand.AddressMode = HAL_XSPI_ADDRESS_8_LINES;
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sCommand.AddressWidth = HAL_XSPI_ADDRESS_32_BITS;
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sCommand.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_ENABLE;
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sCommand.Address = ReadAddr;
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sCommand.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE;
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sCommand.DataMode = ((IOMode == 0U) ? HAL_XSPI_DATA_8_LINES : HAL_XSPI_DATA_16_LINES);
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sCommand.DataDTRMode = HAL_XSPI_DATA_DTR_ENABLE;
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sCommand.DataLength = Size;
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sCommand.DummyCycles = (LatencyCode - 1U);
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sCommand.DQSMode = HAL_XSPI_DQS_ENABLE;
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#if defined (XSPI_CCR_SIOO)
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sCommand.SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD;
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#endif
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/* Configure the command */
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if (HAL_XSPI_Command(Ctx, &sCommand, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
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{
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return APS256XX_ERROR;
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}
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/* Reception of the data */
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if (HAL_XSPI_Receive(Ctx, pData, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
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{
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return APS256XX_ERROR;
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}
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return APS256XX_OK;
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}
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/**
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* @brief Reads an amount of data in DMA mode from the memory.
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* @param Ctx Component object pointer
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* @param pData Pointer to data to be read
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* @param ReadAddr Read start address
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* @param Size Size of data to read
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* @param LatencyCode Latency used for the access
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* @param IOMode I/O Mode used for the access
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* @param BurstType Type of burst used for the access
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* @retval Memory status
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*/
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int32_t APS256XX_Read_DMA(XSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t ReadAddr, uint32_t Size,
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uint32_t LatencyCode, uint32_t IOMode, uint32_t BurstType)
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{
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XSPI_RegularCmdTypeDef sCommand = {0};
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/* Initialize the read command */
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sCommand.OperationType = HAL_XSPI_OPTYPE_COMMON_CFG;
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sCommand.InstructionMode = HAL_XSPI_INSTRUCTION_8_LINES;
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sCommand.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS;
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sCommand.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE;
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sCommand.Instruction = ((BurstType == 0U) ? APS256XX_READ_LINEAR_BURST_CMD : APS256XX_READ_CMD);
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sCommand.AddressMode = HAL_XSPI_ADDRESS_8_LINES;
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sCommand.AddressWidth = HAL_XSPI_ADDRESS_32_BITS;
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sCommand.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_ENABLE;
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sCommand.Address = ReadAddr;
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sCommand.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE;
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sCommand.DataMode = ((IOMode == 0U) ? HAL_XSPI_DATA_8_LINES : HAL_XSPI_DATA_16_LINES);
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sCommand.DataDTRMode = HAL_XSPI_DATA_DTR_ENABLE;
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sCommand.DataLength = Size;
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sCommand.DummyCycles = (LatencyCode - 1U);
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sCommand.DQSMode = HAL_XSPI_DQS_ENABLE;
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#if defined (XSPI_CCR_SIOO)
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sCommand.SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD;
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#endif
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/* Configure the command */
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if (HAL_XSPI_Command(Ctx, &sCommand, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
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{
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return APS256XX_ERROR;
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}
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/* Reception of the data */
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if (HAL_XSPI_Receive_DMA(Ctx, pData) != HAL_OK)
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{
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return APS256XX_ERROR;
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}
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return APS256XX_OK;
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}
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/**
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* @brief Writes an amount of data to the memory.
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* @param Ctx Component object pointer
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* @param pData Pointer to data to be written
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* @param WriteAddr Write start address
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* @param Size Size of data to write
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* @param LatencyCode Latency used for the access
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* @param IOMode I/O Mode used for the access
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* @param BurstType Type of burst used for the access
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* @retval Memory status
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*/
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int32_t APS256XX_Write(XSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t WriteAddr, uint32_t Size, uint32_t LatencyCode,
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uint32_t IOMode, uint32_t BurstType)
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{
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XSPI_RegularCmdTypeDef sCommand = {0};
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/* Initialize the write command */
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sCommand.OperationType = HAL_XSPI_OPTYPE_COMMON_CFG;
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sCommand.InstructionMode = HAL_XSPI_INSTRUCTION_8_LINES;
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sCommand.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS;
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sCommand.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE;
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sCommand.Instruction = ((BurstType == 0U) ? APS256XX_WRITE_LINEAR_BURST_CMD : APS256XX_WRITE_CMD);
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sCommand.AddressMode = HAL_XSPI_ADDRESS_8_LINES;
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sCommand.AddressWidth = HAL_XSPI_ADDRESS_32_BITS;
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sCommand.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_ENABLE;
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sCommand.Address = WriteAddr;
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sCommand.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE;
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sCommand.DataMode = ((IOMode == 0U) ? HAL_XSPI_DATA_8_LINES : HAL_XSPI_DATA_16_LINES);
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sCommand.DataDTRMode = HAL_XSPI_DATA_DTR_ENABLE;
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sCommand.DataLength = Size;
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sCommand.DummyCycles = (LatencyCode - 1U);
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sCommand.DQSMode = HAL_XSPI_DQS_ENABLE;
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#if defined (XSPI_CCR_SIOO)
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sCommand.SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD;
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#endif
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/* Configure the command */
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if (HAL_XSPI_Command(Ctx, &sCommand, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
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{
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return APS256XX_ERROR;
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}
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/* Transmission of the data */
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if (HAL_XSPI_Transmit(Ctx, pData, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
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{
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return APS256XX_ERROR;
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}
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return APS256XX_OK;
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}
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/**
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* @brief Writes an amount of data in DMA mode to the memory.
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* @param Ctx Component object pointer
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* @param pData Pointer to data to be written
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* @param WriteAddr Write start address
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* @param Size Size of data to write
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* @param LatencyCode Latency used for the access
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* @param IOMode I/O Mode used for the access
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* @param BurstType Type of burst used for the access
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* @retval Memory status
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*/
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int32_t APS256XX_Write_DMA(XSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t WriteAddr, uint32_t Size,
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uint32_t LatencyCode, uint32_t IOMode, uint32_t BurstType)
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{
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XSPI_RegularCmdTypeDef sCommand = {0};
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/* Initialize the write command */
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sCommand.OperationType = HAL_XSPI_OPTYPE_COMMON_CFG;
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sCommand.InstructionMode = HAL_XSPI_INSTRUCTION_8_LINES;
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sCommand.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS;
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sCommand.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE;
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sCommand.Instruction = ((BurstType == 0U) ? APS256XX_WRITE_LINEAR_BURST_CMD : APS256XX_WRITE_CMD);
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sCommand.AddressMode = HAL_XSPI_ADDRESS_8_LINES;
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sCommand.AddressWidth = HAL_XSPI_ADDRESS_32_BITS;
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sCommand.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_ENABLE;
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sCommand.Address = WriteAddr;
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sCommand.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE;
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sCommand.DataMode = ((IOMode == 0U) ? HAL_XSPI_DATA_8_LINES : HAL_XSPI_DATA_16_LINES);
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sCommand.DataDTRMode = HAL_XSPI_DATA_DTR_ENABLE;
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sCommand.DataLength = Size;
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sCommand.DummyCycles = (LatencyCode - 1U);
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sCommand.DQSMode = HAL_XSPI_DQS_ENABLE;
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#if defined (XSPI_CCR_SIOO)
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sCommand.SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD;
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#endif
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/* Configure the command */
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if (HAL_XSPI_Command(Ctx, &sCommand, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
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{
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return APS256XX_ERROR;
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}
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/* Transmission of the data */
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if (HAL_XSPI_Transmit_DMA(Ctx, pData) != HAL_OK)
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{
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return APS256XX_ERROR;
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}
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return APS256XX_OK;
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}
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/**
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* @brief Enable memory mapped mode for the memory.
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* @param Ctx Component object pointer
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* @param ReadLatencyCode Latency used for the read access
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* @param WriteLatencyCode Latency used for the write access
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* @param IOMode I/O Mode used for the access
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* @param BurstType Type of burst used for the access
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* @retval Memory status
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*/
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int32_t APS256XX_EnableMemoryMappedMode(XSPI_HandleTypeDef *Ctx, uint32_t ReadLatencyCode, uint32_t WriteLatencyCode,
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uint32_t IOMode, uint32_t BurstType)
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{
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XSPI_RegularCmdTypeDef sCommand = {0};
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XSPI_MemoryMappedTypeDef sMemMappedCfg = {0};
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/* Initialize the write command */
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sCommand.OperationType = HAL_XSPI_OPTYPE_WRITE_CFG;
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sCommand.InstructionMode = HAL_XSPI_INSTRUCTION_8_LINES;
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sCommand.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS;
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sCommand.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE;
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sCommand.Instruction = ((BurstType == 0U) ? APS256XX_WRITE_LINEAR_BURST_CMD : APS256XX_WRITE_CMD);
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sCommand.AddressMode = HAL_XSPI_ADDRESS_8_LINES;
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sCommand.AddressWidth = HAL_XSPI_ADDRESS_32_BITS;
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sCommand.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_ENABLE;
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sCommand.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE;
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sCommand.DataMode = ((IOMode == 0U) ? HAL_XSPI_DATA_8_LINES : HAL_XSPI_DATA_16_LINES);
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sCommand.DataDTRMode = HAL_XSPI_DATA_DTR_ENABLE;
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sCommand.DummyCycles = (WriteLatencyCode - 1U);
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sCommand.DQSMode = HAL_XSPI_DQS_ENABLE;
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#if defined (XSPI_CCR_SIOO)
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sCommand.SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD;
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#endif
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if (HAL_XSPI_Command(Ctx, &sCommand, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
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{
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return APS256XX_ERROR;
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}
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/* Initialize the read command */
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sCommand.OperationType = HAL_XSPI_OPTYPE_READ_CFG;
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sCommand.Instruction = ((BurstType == 0U) ? APS256XX_READ_LINEAR_BURST_CMD : APS256XX_READ_CMD);
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sCommand.DummyCycles = (ReadLatencyCode - 1U);
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if (HAL_XSPI_Command(Ctx, &sCommand, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
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{
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return APS256XX_ERROR;
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}
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/* Activation of memory-mapped mode */
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sMemMappedCfg.TimeOutActivation = HAL_XSPI_TIMEOUT_COUNTER_DISABLE;
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if (HAL_XSPI_MemoryMapped(Ctx, &sMemMappedCfg) != HAL_OK)
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{
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return APS256XX_ERROR;
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}
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return APS256XX_OK;
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}
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/* Register/Setting Commands **************************************************/
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/**
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* @brief Read mode register value
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* @param Ctx Component object pointer
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* @param Address Register address
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* @param Value Register value pointer
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* @param LatencyCode Latency used for the access
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* @retval error status
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*/
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int32_t APS256XX_ReadReg(XSPI_HandleTypeDef *Ctx, uint32_t Address, uint8_t *Value, uint32_t LatencyCode)
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{
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XSPI_RegularCmdTypeDef sCommand = {0};
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/* Initialize the read register command */
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sCommand.OperationType = HAL_XSPI_OPTYPE_COMMON_CFG;
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sCommand.InstructionMode = HAL_XSPI_INSTRUCTION_8_LINES;
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sCommand.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS;
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sCommand.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE;
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sCommand.Instruction = APS256XX_READ_REG_CMD;
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sCommand.AddressMode = HAL_XSPI_ADDRESS_8_LINES;
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sCommand.AddressWidth = HAL_XSPI_ADDRESS_32_BITS;
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sCommand.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_ENABLE;
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sCommand.Address = Address;
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sCommand.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE;
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sCommand.DataMode = HAL_XSPI_DATA_8_LINES;
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sCommand.DataDTRMode = HAL_XSPI_DATA_DTR_ENABLE;
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sCommand.DataLength = 2;
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sCommand.DummyCycles = (LatencyCode - 1U);
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sCommand.DQSMode = HAL_XSPI_DQS_ENABLE;
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#if defined (XSPI_CCR_SIOO)
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sCommand.SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD;
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#endif
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/* Configure the command */
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if (HAL_XSPI_Command(Ctx, &sCommand, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
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{
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return APS256XX_ERROR;
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}
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/* Reception of the data */
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if (HAL_XSPI_Receive(Ctx, (uint8_t *)Value, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
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{
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return APS256XX_ERROR;
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}
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return APS256XX_OK;
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}
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/**
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* @brief Write mode register
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* @param Ctx Component object pointer
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* @param Address Register address
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* @param Value Value to write to register
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* @retval error status
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||||
*/
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int32_t APS256XX_WriteReg(XSPI_HandleTypeDef *Ctx, uint32_t Address, uint8_t Value)
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{
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XSPI_RegularCmdTypeDef sCommand = {0};
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||||
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||||
/* Initialize the write register command */
|
||||
sCommand.OperationType = HAL_XSPI_OPTYPE_COMMON_CFG;
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sCommand.InstructionMode = HAL_XSPI_INSTRUCTION_8_LINES;
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sCommand.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS;
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sCommand.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE;
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sCommand.Instruction = APS256XX_WRITE_REG_CMD;
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sCommand.AddressMode = HAL_XSPI_ADDRESS_8_LINES;
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sCommand.AddressWidth = HAL_XSPI_ADDRESS_32_BITS;
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sCommand.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_ENABLE;
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sCommand.Address = Address;
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sCommand.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE;
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sCommand.DataMode = HAL_XSPI_DATA_8_LINES;
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sCommand.DataDTRMode = HAL_XSPI_DATA_DTR_ENABLE;
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sCommand.DataLength = 2;
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sCommand.DummyCycles = 0;
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sCommand.DQSMode = HAL_XSPI_DQS_DISABLE;
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#if defined (XSPI_CCR_SIOO)
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sCommand.SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD;
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#endif
|
||||
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/* Configure the command */
|
||||
if (HAL_XSPI_Command(Ctx, &sCommand, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
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return APS256XX_ERROR;
|
||||
}
|
||||
|
||||
/* Transmission of the data */
|
||||
if (HAL_XSPI_Transmit(Ctx, (uint8_t *)(&Value), HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
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||||
return APS256XX_ERROR;
|
||||
}
|
||||
|
||||
return APS256XX_OK;
|
||||
}
|
||||
|
||||
/* ID Commands ****************************************************************/
|
||||
/**
|
||||
* @brief Read Flash IDs.
|
||||
* Vendor ID, Device ID, Device Density
|
||||
* @param Ctx Component object pointer
|
||||
* @param ID IDs pointer (2 * 8-bits value)
|
||||
* @param LatencyCode Latency used for the access
|
||||
* @retval error status
|
||||
*/
|
||||
int32_t APS256XX_ReadID(XSPI_HandleTypeDef *Ctx, uint8_t *ID, uint32_t LatencyCode)
|
||||
{
|
||||
/* Read the Mode Register 1 and 2 */
|
||||
if (APS256XX_ReadReg(Ctx, APS256XX_MR1_ADDRESS, ID, LatencyCode) != APS256XX_OK)
|
||||
{
|
||||
return APS256XX_ERROR;
|
||||
}
|
||||
|
||||
/* Keep only Vendor ID from Mode Register 1 */
|
||||
*ID &= (APS256XX_MR1_VENDOR_ID);
|
||||
|
||||
/* Keep only Device ID and Device Density from Mode Register 2 */
|
||||
*(ID + 1) &= (APS256XX_MR2_DEVICE_ID | APS256XX_MR2_DENSITY);
|
||||
|
||||
return APS256XX_OK;
|
||||
}
|
||||
|
||||
/* Power down Commands ********************************************************/
|
||||
/**
|
||||
* @brief Memory enter deep power-down command
|
||||
* @param Ctx Component object pointer
|
||||
* @retval error status
|
||||
*/
|
||||
int32_t APS256XX_EnterPowerDown(XSPI_HandleTypeDef *Ctx)
|
||||
{
|
||||
/* Update the deep power down value of the MR6 register */
|
||||
if (APS256XX_WriteReg(Ctx, APS256XX_MR6_ADDRESS, APS256XX_MR6_HS_HALF_SPEED_MODE) != APS256XX_OK)
|
||||
{
|
||||
return APS256XX_ERROR;
|
||||
}
|
||||
|
||||
/* --- Memory enter deep power down as soon nCS goes high --- */
|
||||
/* --- At least 500us should be respected before leaving deep power down --- */
|
||||
|
||||
return APS256XX_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Flash leave deep power-down command
|
||||
* @param Ctx Component object pointer
|
||||
* @param LatencyCode Latency used for the access
|
||||
* @retval error status
|
||||
*/
|
||||
int32_t APS256XX_LeavePowerDown(XSPI_HandleTypeDef *Ctx)
|
||||
{
|
||||
/* --- A dummy command is sent to the memory, as the nCS should be low for at least 60 ns --- */
|
||||
/* --- Memory takes 150us max to leave deep power down --- */
|
||||
|
||||
XSPI_RegularCmdTypeDef sCommand = {0};
|
||||
|
||||
/* Initialize the command */
|
||||
sCommand.OperationType = HAL_XSPI_OPTYPE_COMMON_CFG;
|
||||
sCommand.InstructionMode = HAL_XSPI_INSTRUCTION_8_LINES;
|
||||
sCommand.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS;
|
||||
sCommand.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE;
|
||||
sCommand.Instruction = APS256XX_READ_CMD;
|
||||
sCommand.AddressMode = HAL_XSPI_ADDRESS_8_LINES;
|
||||
sCommand.AddressWidth = HAL_XSPI_ADDRESS_32_BITS;
|
||||
sCommand.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_DISABLE;
|
||||
sCommand.Address = 0;
|
||||
sCommand.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE;
|
||||
sCommand.DataMode = HAL_XSPI_DATA_NONE;
|
||||
sCommand.DataLength = 0;
|
||||
sCommand.DummyCycles = 0;
|
||||
sCommand.DQSMode = HAL_XSPI_DQS_DISABLE;
|
||||
#if defined (XSPI_CCR_SIOO)
|
||||
sCommand.SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD;
|
||||
#endif
|
||||
|
||||
/* Configure the command */
|
||||
if (HAL_XSPI_Command(Ctx, &sCommand, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return APS256XX_ERROR;
|
||||
}
|
||||
|
||||
return APS256XX_OK;
|
||||
}
|
||||
|
||||
/* Reset Command **************************************************************/
|
||||
/**
|
||||
* @brief Reset the memory
|
||||
* @param Ctx Component object pointer
|
||||
* @retval error status
|
||||
*/
|
||||
int32_t APS256XX_Reset(XSPI_HandleTypeDef *Ctx)
|
||||
{
|
||||
XSPI_RegularCmdTypeDef sCommand = {0};
|
||||
|
||||
/* Initialize the command */
|
||||
sCommand.OperationType = HAL_XSPI_OPTYPE_COMMON_CFG;
|
||||
sCommand.InstructionMode = HAL_XSPI_INSTRUCTION_8_LINES;
|
||||
sCommand.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS;
|
||||
sCommand.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE;
|
||||
sCommand.Instruction = APS256XX_RESET_CMD;
|
||||
sCommand.AddressMode = HAL_XSPI_ADDRESS_8_LINES;
|
||||
sCommand.AddressWidth = HAL_XSPI_ADDRESS_24_BITS;
|
||||
sCommand.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_DISABLE;
|
||||
sCommand.Address = 0;
|
||||
sCommand.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE;
|
||||
sCommand.DataMode = HAL_XSPI_DATA_NONE;
|
||||
sCommand.DataLength = 0;
|
||||
sCommand.DummyCycles = 0;
|
||||
sCommand.DQSMode = HAL_XSPI_DQS_DISABLE;
|
||||
#if defined (XSPI_CCR_SIOO)
|
||||
sCommand.SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD;
|
||||
#endif
|
||||
|
||||
/* Configure the command */
|
||||
if (HAL_XSPI_Command(Ctx, &sCommand, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return APS256XX_ERROR;
|
||||
}
|
||||
|
||||
/* Need to wait tRST */
|
||||
HAL_Delay(1);
|
||||
return 0/*APS256XX_OK*/;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
Reference in new issue
Block a user