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Copyright 2023 STMicroelectronics.
|
||||
All rights reserved.
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||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
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are permitted provided that the following conditions are met:
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||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
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||||
3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
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||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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@@ -0,0 +1,6 @@
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||||
This software component is provided to you as part of a software package and
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applicable license terms are in the Package_license file. If you received this
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software component outside of a package or without applicable license terms,
|
||||
the terms of the BSD-3-Clause license shall apply.
|
||||
You may obtain a copy of the BSD-3-Clause at:
|
||||
https://opensource.org/licenses/BSD-3-Clause
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<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">
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<head>
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<meta charset="utf-8" />
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<meta name="generator" content="pandoc" />
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<meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
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<title>Release Notes for MX66UW1G45G OCTOSPI Component Driver</title>
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<style type="text/css">
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code{white-space: pre-wrap;}
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span.smallcaps{font-variant: small-caps;}
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span.underline{text-decoration: underline;}
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div.column{display: inline-block; vertical-align: top; width: 50%;}
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</style>
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<link rel="stylesheet" href="_htmresc/mini-st_2020.css" />
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||||
<!--[if lt IE 9]>
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<script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
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<![endif]-->
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<link rel="icon" type="image/x-icon" href="_htmresc/favicon.png" />
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</head>
|
||||
<body>
|
||||
<div class="row">
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<div class="col-sm-12 col-lg-4">
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<center>
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<h1 id="release-notes-for-mx66uw1g45g-component-driver">Release Notes for <mark>MX66UW1G45G</mark> Component Driver</h1>
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<p>Copyright © 2023 STMicroelectronics<br />
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</p>
|
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<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo_2020.png" alt="ST logo" /></a>
|
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</center>
|
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<h1 id="purpose">Purpose</h1>
|
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<p>This driver provides a set of functions offered by MX66UW1G45G OCTOSPI component</p>
|
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</div>
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<div class="col-sm-12 col-lg-8">
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<h1 id="update-history">Update History</h1>
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<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section2" checked aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 08-December-2023</strong></label>
|
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<div>
|
||||
<h2 id="main-changes">Main Changes</h2>
|
||||
<ul>
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<li>Add implementation of release power-down command</li>
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<li>Correct DataLength in case of MX66UW1G45G_DTR_TRANSFER</li>
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</ul>
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<h2 id="section"></h2>
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</div>
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</div>
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<div class="collapse">
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<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 31-May-2023</strong></label>
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<div>
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<h2 id="main-changes-1">Main Changes</h2>
|
||||
<ul>
|
||||
<li>First official release of <strong>MX66UW1G45G</strong> octal SPI driver</li>
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</ul>
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<h2 id="section-1"></h2>
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</div>
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</div>
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</div>
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</div>
|
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<footer class="sticky">
|
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For complete documentation on <mark>STM32 Microcontrollers</mark> , visit: <span style="font-color: blue;"><a href="http://www.st.com/STM32">www.st.com</a></span>
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</footer>
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</body>
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</html>
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---
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pagetitle: Release Notes for MX66UW1G45G OCTOSPI Component Driver
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lang: en
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header-includes: <link rel="icon" type="image/x-icon" href="_htmresc/favicon.png" />
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---
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::: {.row}
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::: {.col-sm-12 .col-lg-4}
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<center>
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# Release Notes for <mark>MX66UW1G45G</mark> Component Driver
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Copyright © 2023 STMicroelectronics\
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[](https://www.st.com){.logo}
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</center>
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|
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# Purpose
|
||||
|
||||
This driver provides a set of functions offered by MX66UW1G45G OCTOSPI component
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|
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:::
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::: {.col-sm-12 .col-lg-8}
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# Update History
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::: {.collapse}
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<input type="checkbox" id="collapse-section2" checked aria-hidden="true">
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<label for="collapse-section2" aria-hidden="true">__V1.1.0 / 08-December-2023__</label>
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<div>
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## Main Changes
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- Add implementation of release power-down command
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- Correct DataLength in case of MX66UW1G45G_DTR_TRANSFER
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|
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##
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</div>
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:::
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||||
|
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::: {.collapse}
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||||
<input type="checkbox" id="collapse-section1" aria-hidden="true">
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||||
<label for="collapse-section1" aria-hidden="true">__V1.0.0 / 31-May-2023__</label>
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||||
<div>
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## Main Changes
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||||
|
||||
- First official release of **MX66UW1G45G** octal SPI driver
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##
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</div>
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:::
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||||
|
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:::
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:::
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||||
|
||||
<footer class="sticky">
|
||||
For complete documentation on <mark>STM32 Microcontrollers</mark> ,
|
||||
visit: [[www.st.com](http://www.st.com/STM32)]{style="font-color: blue;"}
|
||||
</footer>
|
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@@ -0,0 +1,2 @@
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/**
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******************************************************************************
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* @file mx66uw1g45g.h
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* @modify MCD Application Team
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* @brief This file contains all the description of the
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* MX66UW1G45G XSPI memory.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2023 STMicroelectronics.
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* All rights reserved.
|
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*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
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||||
* in the root directory of this software component.
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||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
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*
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******************************************************************************
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||||
*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef MX66UW1G45G_H
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#define MX66UW1G45G_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "mx66uw1g45g_conf.h"
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/** @addtogroup BSP
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* @{
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*/
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/** @addtogroup Components
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* @{
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*/
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/** @addtogroup MX66UW1G45G
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* @{
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*/
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/** @defgroup MX66UW1G45G_Exported_Constants MX66UW1G45G Exported Constants
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* @{
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*/
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/**
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* @brief MX66UW1G45G Size configuration
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*/
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#define MX66UW1G45G_BLOCK_64K (uint32_t)(64 * 1024) /* 1024 blocks of 64KBytes */
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#define MX66UW1G45G_BLOCK_4K (uint32_t)(4 * 1024) /* 16384 sectors of 4KBytes */
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#define MX66UW1G45G_FLASH_SIZE (uint32_t)(1024*1024*1024/8) /* 1 Gbits => 128MBytes */
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#define MX66UW1G45G_PAGE_SIZE (uint32_t)256 /* 262144 pages of 256 Bytes */
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/**
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* @brief MX66UW1G45G Timing configuration
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*/
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#define MX66UW1G45G_BULK_ERASE_MAX_TIME 460000U
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#define MX66UW1G45G_BLOCK_ERASE_MAX_TIME 1000U
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#define MX66UW1G45G_BLOCK_4K_ERASE_MAX_TIME 400U
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#define MX66UW1G45G_WRITE_REG_MAX_TIME 40U
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#define MX66UW1G45G_RESET_MAX_TIME 100U /* when SWreset during erase operation */
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#define MX66UW1G45G_AUTOPOLLING_INTERVAL_TIME 0x10U
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/**
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* @brief MX66UW1G45G Error codes
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*/
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#define MX66UW1G45G_OK (0)
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#define MX66UW1G45G_ERROR (-1)
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/**
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* @brief re-definition of legacy memory mapped functions
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*/
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#define MX66UW1G45G_EnableMemoryMappedModeDTR MX66UW1G45G_EnableDTRMemoryMappedMode
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#define MX66UW1G45G_EnableMemoryMappedModeSTR MX66UW1G45G_EnableSTRMemoryMappedMode
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/******************************************************************************
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* @brief MX66UW1G45G Commands
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****************************************************************************/
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/*******************************************************************/
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/********************************* SPI ****************************/
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/*******************************************************************/
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/***** READ/WRITE MEMORY Operations with 3-Byte Address ****************************/
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#define MX66UW1G45G_READ_CMD 0x03U /*!< Normal Read 3 Byte Address */
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#define MX66UW1G45G_FAST_READ_CMD 0x0BU /*!< Fast Read 3 Byte Address */
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#define MX66UW1G45G_PAGE_PROG_CMD 0x02U /*!< Page Program 3 Byte Address */
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||||
#define MX66UW1G45G_SECTOR_ERASE_4K_CMD 0x20U /*!< SubSector Erase 4KB 3 Byte Address */
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#define MX66UW1G45G_BLOCK_ERASE_64K_CMD 0xD8U /*!< Sector Erase 64KB 3 Byte Address */
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#define MX66UW1G45G_BULK_ERASE_CMD 0x60U /*!< Bulk Erase */
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||||
/***** READ/WRITE MEMORY Operations with 4-Byte Address ****************************/
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#define MX66UW1G45G_4_BYTE_ADDR_READ_CMD 0x13U /*!< Normal Read 4 Byte address */
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#define MX66UW1G45G_4_BYTE_ADDR_FAST_READ_CMD 0x0CU /*!< Fast Read 4 Byte address */
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#define MX66UW1G45G_4_BYTE_PAGE_PROG_CMD 0x12U /*!< Page Program 4 Byte Address */
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||||
#define MX66UW1G45G_4_BYTE_SECTOR_ERASE_4K_CMD 0x21U /*!< SubSector Erase 4KB 4 Byte Address */
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||||
#define MX66UW1G45G_4_BYTE_BLOCK_ERASE_64K_CMD 0xDCU /*!< Sector Erase 64KB 4 Byte Address */
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||||
|
||||
/***** Setting commands ************************************************************/
|
||||
#define MX66UW1G45G_WRITE_ENABLE_CMD 0x06U /*!< Write Enable */
|
||||
#define MX66UW1G45G_WRITE_DISABLE_CMD 0x04U /*!< Write Disable */
|
||||
#define MX66UW1G45G_PROG_ERASE_SUSPEND_CMD 0xB0U /*!< Program/Erase suspend */
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||||
#define MX66UW1G45G_PROG_ERASE_RESUME_CMD 0x30U /*!< Program/Erase resume */
|
||||
#define MX66UW1G45G_ENTER_DEEP_POWER_DOWN_CMD 0xB9U /*!< Enter deep power down */
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||||
#define MX66UW1G45G_RELEASE_DEEP_POWER_DOWN_CMD 0xABU /*!< Release from deep power down */
|
||||
#define MX66UW1G45G_SET_BURST_LENGTH_CMD 0xC0U /*!< Set burst length */
|
||||
#define MX66UW1G45G_ENTER_SECURED_OTP_CMD 0xB1U /*!< Enter secured OTP) */
|
||||
#define MX66UW1G45G_EXIT_SECURED_OTP_CMD 0xC1U /*!< Exit secured OTP) */
|
||||
|
||||
/***** RESET commands ************************************************************/
|
||||
#define MX66UW1G45G_NOP_CMD 0x00U /*!< No operation */
|
||||
#define MX66UW1G45G_RESET_ENABLE_CMD 0x66U /*!< Reset Enable */
|
||||
#define MX66UW1G45G_RESET_MEMORY_CMD 0x99U /*!< Reset Memory */
|
||||
|
||||
/***** Register Commands (SPI) ****************************************************/
|
||||
#define MX66UW1G45G_READ_ID_CMD 0x9FU /*!< Read IDentification */
|
||||
#define MX66UW1G45G_READ_SERIAL_FLASH_DISCO_PARAM_CMD 0x5AU /*!< Read Serial Flash Discoverable Parameter */
|
||||
#define MX66UW1G45G_READ_STATUS_REG_CMD 0x05U /*!< Read Status Register */
|
||||
#define MX66UW1G45G_READ_CFG_REG_CMD 0x15U /*!< Read configuration Register */
|
||||
#define MX66UW1G45G_WRITE_STATUS_REG_CMD 0x01U /*!< Write Status Register */
|
||||
#define MX66UW1G45G_READ_CFG_REG2_CMD 0x71U /*!< Read configuration Register2 */
|
||||
#define MX66UW1G45G_WRITE_CFG_REG2_CMD 0x72U /*!< Write configuration Register2 */
|
||||
#define MX66UW1G45G_READ_FAST_BOOT_REG_CMD 0x16U /*!< Read fast boot Register */
|
||||
#define MX66UW1G45G_WRITE_FAST_BOOT_REG_CMD 0x17U /*!< Write fast boot Register */
|
||||
#define MX66UW1G45G_ERASE_FAST_BOOT_REG_CMD 0x18U /*!< Erase fast boot Register */
|
||||
#define MX66UW1G45G_READ_SECURITY_REG_CMD 0x2BU /*!< Read security Register */
|
||||
#define MX66UW1G45G_WRITE_SECURITY_REG_CMD 0x2FU /*!< Write security Register */
|
||||
#define MX66UW1G45G_READ_LOCK_REG_CMD 0x2DU /*!< Read lock Register */
|
||||
#define MX66UW1G45G_WRITE_LOCK_REG_CMD 0x2CU /*!< Write lock Register */
|
||||
|
||||
#define MX66UW1G45G_READ_DPB_REG_CMD 0xE0U /*!< Read DPB register */
|
||||
#define MX66UW1G45G_WRITE_DPB_REG_CMD 0xE1U /*!< Write DPB register */
|
||||
#define MX66UW1G45G_READ_SPB_STATUS_CMD 0xE2U /*!< Read SPB status */
|
||||
#define MX66UW1G45G_WRITE_SPB_BIT_CMD 0xE3U /*!< SPB bit program */
|
||||
#define MX66UW1G45G_ERASE_ALL_SPB_CMD 0xE4U /*!< Erase all SPB bit */
|
||||
#define MX66UW1G45G_WRITE_PROTECT_SEL_CMD 0x68U /*!< Write Protect selection */
|
||||
#define MX66UW1G45G_GANG_BLOCK_LOCK_CMD 0x7EU /*!< Gang block lock: whole chip write protect */
|
||||
#define MX66UW1G45G_GANG_BLOCK_UNLOCK_CMD 0x98U /*!< Gang block unlock: whole chip write unprotect */
|
||||
#define MX66UW1G45G_READ_PASSWORD_REGISTER_CMD 0x27U /*!< Read Password */
|
||||
#define MX66UW1G45G_WRITE_PASSWORD_REGISTER_CMD 0x28U /*!< Write Password */
|
||||
#define MX66UW1G45G_PASSWORD_UNLOCK_CMD 0x29U /*!< Unlock Password */
|
||||
|
||||
|
||||
/*******************************************************************/
|
||||
/********************************* OPI ****************************/
|
||||
/*******************************************************************/
|
||||
|
||||
/***** READ/WRITE MEMORY Operations ****************************/
|
||||
#define MX66UW1G45G_OCTA_READ_CMD 0xEC13U /*!< Octa IO Read */
|
||||
#define MX66UW1G45G_OCTA_READ_DTR_CMD 0xEE11U /*!< Octa IO Read DTR */
|
||||
#define MX66UW1G45G_OCTA_PAGE_PROG_CMD 0x12EDU /*!< Octa Page Program */
|
||||
#define MX66UW1G45G_OCTA_SECTOR_ERASE_4K_CMD 0x21DEU /*!< Octa SubSector Erase 4KB */
|
||||
#define MX66UW1G45G_OCTA_BLOCK_ERASE_64K_CMD 0xDC23U /*!< Octa Sector Erase 64KB 3 */
|
||||
#define MX66UW1G45G_OCTA_BULK_ERASE_CMD 0x609FU /*!< Octa Bulk Erase */
|
||||
|
||||
/***** Setting commands ************************************************************/
|
||||
#define MX66UW1G45G_OCTA_WRITE_ENABLE_CMD 0x06F9U /*!< Octa Write Enable */
|
||||
#define MX66UW1G45G_OCTA_WRITE_DISABLE_CMD 0x04FBU /*!< Octa Write Disable */
|
||||
#define MX66UW1G45G_OCTA_PROG_ERASE_SUSPEND_CMD 0xB04FU /*!< Octa Program/Erase suspend */
|
||||
#define MX66UW1G45G_OCTA_PROG_ERASE_RESUME_CMD 0x30CFU /*!< Octa Program/Erase resume */
|
||||
#define MX66UW1G45G_OCTA_ENTER_DEEP_POWER_DOWN_CMD 0xB946U /*!< Octa Enter deep power down */
|
||||
#define MX66UW1G45G_OCTA_RELEASE_DEEP_POWER_DOWN_CMD 0xAB54U /*!< Octa Release from deep power down */
|
||||
#define MX66UW1G45G_OCTA_SET_BURST_LENGTH_CMD 0xC03FU /*!< Octa Set burst length */
|
||||
#define MX66UW1G45G_OCTA_ENTER_SECURED_OTP_CMD 0xB14EU /*!< Octa Enter secured OTP) */
|
||||
#define MX66UW1G45G_OCTA_EXIT_SECURED_OTP_CMD 0xC13EU /*!< Octa Exit secured OTP) */
|
||||
|
||||
/***** RESET commands ************************************************************/
|
||||
#define MX66UW1G45G_OCTA_NOP_CMD 0x00FFU /*!< Octa No operation */
|
||||
#define MX66UW1G45G_OCTA_RESET_ENABLE_CMD 0x6699U /*!< Octa Reset Enable */
|
||||
#define MX66UW1G45G_OCTA_RESET_MEMORY_CMD 0x9966U /*!< Octa Reset Memory */
|
||||
|
||||
/***** Register Commands (OPI) ****************************************************/
|
||||
#define MX66UW1G45G_OCTA_READ_ID_CMD 0x9F60U /*!< Octa Read IDentification */
|
||||
#define MX66UW1G45G_OCTA_READ_SERIAL_FLASH_DISCO_PARAM_CMD 0x5AA5U /*!< Octa Read Serial Flash Discoverable Parameter */
|
||||
#define MX66UW1G45G_OCTA_READ_STATUS_REG_CMD 0x05FAU /*!< Octa Read Status Register */
|
||||
#define MX66UW1G45G_OCTA_READ_CFG_REG_CMD 0x15EAU /*!< Octa Read configuration Register */
|
||||
#define MX66UW1G45G_OCTA_WRITE_STATUS_REG_CMD 0x01FEU /*!< Octa Write Status Register */
|
||||
#define MX66UW1G45G_OCTA_READ_CFG_REG2_CMD 0x718EU /*!< Octa Read configuration Register2 */
|
||||
#define MX66UW1G45G_OCTA_WRITE_CFG_REG2_CMD 0x728DU /*!< Octa Write configuration Register2 */
|
||||
#define MX66UW1G45G_OCTA_READ_FAST_BOOT_REG_CMD 0x16E9U /*!< Octa Read fast boot Register */
|
||||
#define MX66UW1G45G_OCTA_WRITE_FAST_BOOT_REG_CMD 0x17E8U /*!< Octa Write fast boot Register */
|
||||
#define MX66UW1G45G_OCTA_ERASE_FAST_BOOT_REG_CMD 0x18E7U /*!< Octa Erase fast boot Register */
|
||||
#define MX66UW1G45G_OCTA_READ_SECURITY_REG_CMD 0x2BD4U /*!< Octa Read security Register */
|
||||
#define MX66UW1G45G_OCTA_WRITE_SECURITY_REG_CMD 0x2FD0U /*!< Octa Write security Register */
|
||||
#define MX66UW1G45G_OCTA_READ_LOCK_REG_CMD 0x2DD2U /*!< Octa Read lock Register */
|
||||
#define MX66UW1G45G_OCTA_WRITE_LOCK_REG_CMD 0x2CD3U /*!< Octa Write lock Register */
|
||||
#define MX66UW1G45G_OCTA_READ_DPB_REG_CMD 0xE01FU /*!< Octa Read DPB register */
|
||||
#define MX66UW1G45G_OCTA_WRITE_DPB_REG_CMD 0xE11EU /*!< Octa Write DPB register */
|
||||
#define MX66UW1G45G_OCTA_READ_SPB_STATUS_CMD 0xE21DU /*!< Octa Read SPB status */
|
||||
#define MX66UW1G45G_OCTA_WRITE_SPB_BIT_CMD 0xE31CU /*!< Octa SPB bit program */
|
||||
#define MX66UW1G45G_OCTA_ERASE_ALL_SPB_CMD 0xE41BU /*!< Octa Erase all SPB bit */
|
||||
#define MX66UW1G45G_OCTA_WRITE_PROTECT_SEL_CMD 0x6897U /*!< Octa Write Protect selection */
|
||||
#define MX66UW1G45G_OCTA_GANG_BLOCK_LOCK_CMD 0x7E81U /*!< Octa Gang block lock: whole chip write protect */
|
||||
#define MX66UW1G45G_OCTA_GANG_BLOCK_UNLOCK_CMD 0x9867U /*!< Octa Gang block unlock: whole chip write unprote*/
|
||||
#define MX66UW1G45G_OCTA_READ_PASSWORD_REGISTER_CMD 0x27D8U /*!< Octa Read Password */
|
||||
#define MX66UW1G45G_OCTA_WRITE_PASSWORD_REGISTER_CMD 0x28D7U /*!< Octa Write Password */
|
||||
#define MX66UW1G45G_OCTA_PASSWORD_UNLOCK_CMD 0x29D6U /*!< Octa Unlock Password */
|
||||
|
||||
/******************************************************************************
|
||||
* @brief MX66UW1G45G Registers
|
||||
****************************************************************************/
|
||||
/* Status Register */
|
||||
#define MX66UW1G45G_SR_WIP 0x01U /*!< Write in progress */
|
||||
#define MX66UW1G45G_SR_WEL 0x02U /*!< Write enable latch */
|
||||
#define MX66UW1G45G_SR_PB 0x3CU /*!< Block protected against program and erase operations */
|
||||
|
||||
/* Configuration Register 1 */
|
||||
#define MX66UW1G45G_CR1_ODS 0x07U /*!< Output driver strength */
|
||||
#define MX66UW1G45G_CR1_TB 0x08U /*!< Top / bottom selected */
|
||||
#define MX66UW1G45G_CR1_PBE 0x10U /*!< Preamble bit enable */
|
||||
|
||||
/* Configuration Register 2 */
|
||||
/* Address : 0x00000000 */
|
||||
#define MX66UW1G45G_CR2_REG1_ADDR 0x00000000U /*!< CR2 register address 0x00000000 */
|
||||
#define MX66UW1G45G_CR2_SOPI 0x01U /*!< STR OPI Enable */
|
||||
#define MX66UW1G45G_CR2_DOPI 0x02U /*!< DTR OPI Enable */
|
||||
/* Address : 0x00000200 */
|
||||
#define MX66UW1G45G_CR2_REG2_ADDR 0x00000200U /*!< CR2 register address 0x00000200 */
|
||||
#define MX66UW1G45G_CR2_DQSPRC 0x01U /*!< DTR DQS pre-cycle */
|
||||
#define MX66UW1G45G_CR2_DOS 0x02U /*!< DQS on STR mode */
|
||||
/* Address : 0x00000300 */
|
||||
#define MX66UW1G45G_CR2_REG3_ADDR 0x00000300U /*!< CR2 register address 0x00000300 */
|
||||
#define MX66UW1G45G_CR2_DC 0x07U /*!< Dummy cycle */
|
||||
#define MX66UW1G45G_CR2_DC_20_CYCLES 0x00U /*!< 20 Dummy cycles */
|
||||
#define MX66UW1G45G_CR2_DC_18_CYCLES 0x01U /*!< 18 Dummy cycles */
|
||||
#define MX66UW1G45G_CR2_DC_16_CYCLES 0x02U /*!< 16 Dummy cycles */
|
||||
#define MX66UW1G45G_CR2_DC_14_CYCLES 0x03U /*!< 14 Dummy cycles */
|
||||
#define MX66UW1G45G_CR2_DC_12_CYCLES 0x04U /*!< 12 Dummy cycles */
|
||||
#define MX66UW1G45G_CR2_DC_10_CYCLES 0x05U /*!< 10 Dummy cycles */
|
||||
#define MX66UW1G45G_CR2_DC_8_CYCLES 0x06U /*!< 8 Dummy cycles */
|
||||
#define MX66UW1G45G_CR2_DC_6_CYCLES 0x07U /*!< 6 Dummy cycles */
|
||||
/* Address : 0x00000500 */
|
||||
#define MX66UW1G45G_CR2_REG4_ADDR 0x00000500U /*!< CR2 register address 0x00000500 */
|
||||
#define MX66UW1G45G_CR2_PPTSEL 0x01U /*!< Preamble pattern selection */
|
||||
/* Address : 0x40000000 */
|
||||
#define MX66UW1G45G_CR2_REG5_ADDR 0x40000000U /*!< CR2 register address 0x40000000 */
|
||||
#define MX66UW1G45G_CR2_DEFSOPI 0x01U /*!< Enable SOPI after power on reset */
|
||||
#define MX66UW1G45G_CR2_DEFDOPI 0x02U /*!< Enable DOPI after power on reset */
|
||||
|
||||
/* Security Register */
|
||||
#define MX66UW1G45G_SECR_SOI 0x01U /*!< Secured OTP indicator */
|
||||
#define MX66UW1G45G_SECR_LDSO 0x02U /*!< Lock-down secured OTP */
|
||||
#define MX66UW1G45G_SECR_PSB 0x04U /*!< Program suspend bit */
|
||||
#define MX66UW1G45G_SECR_ESB 0x08U /*!< Erase suspend bit */
|
||||
#define MX66UW1G45G_SECR_P_FAIL 0x20U /*!< Program fail flag */
|
||||
#define MX66UW1G45G_SECR_E_FAIL 0x40U /*!< Erase fail flag */
|
||||
#define MX66UW1G45G_SECR_WPSEL 0x80U /*!< Write protection selection */
|
||||
|
||||
#define XSPI_ALTERNATE_BYTE_PATTERN 0x00U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MX66UW1G45G_Exported_Types MX66UW1G45G Exported Types
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FlashSize; /*!< Size of the flash */
|
||||
uint32_t EraseSectorSize; /*!< Size of sectors for the erase operation */
|
||||
uint32_t EraseSectorsNumber; /*!< Number of sectors for the erase operation */
|
||||
uint32_t EraseSubSectorSize; /*!< Size of subsector for the erase operation */
|
||||
uint32_t EraseSubSectorNumber; /*!< Number of subsector for the erase operation */
|
||||
uint32_t EraseSubSector1Size; /*!< Size of subsector 1 for the erase operation */
|
||||
uint32_t EraseSubSector1Number; /*!< Number of subsector 1 for the erase operation */
|
||||
uint32_t ProgPageSize; /*!< Size of pages for the program operation */
|
||||
uint32_t ProgPagesNumber; /*!< Number of pages for the program operation */
|
||||
} MX66UW1G45G_Info_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
MX66UW1G45G_SPI_MODE = 0, /*!< 1-1-1 commands, Power on H/W default setting */
|
||||
MX66UW1G45G_OPI_MODE /*!< 8-8-8 commands */
|
||||
} MX66UW1G45G_Interface_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
MX66UW1G45G_STR_TRANSFER = 0, /*!< Single Transfer Rate */
|
||||
MX66UW1G45G_DTR_TRANSFER /*!< Double Transfer Rate */
|
||||
} MX66UW1G45G_Transfer_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
MX66UW1G45G_ERASE_4K = 0, /*!< 4K size Sector erase */
|
||||
MX66UW1G45G_ERASE_64K, /*!< 64K size Block erase */
|
||||
MX66UW1G45G_ERASE_BULK /*!< Whole bulk erase */
|
||||
} MX66UW1G45G_Erase_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
MX66UW1G45G_3BYTES_SIZE = 0, /*!< 3 Bytes address mode */
|
||||
MX66UW1G45G_4BYTES_SIZE /*!< 4 Bytes address mode */
|
||||
} MX66UW1G45G_AddressWidth_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MX66UW1G45G_Exported_Functions MX66UW1G45G Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/* Function by commands combined */
|
||||
int32_t MX66UW1G45G_GetFlashInfo(MX66UW1G45G_Info_t *pInfo);
|
||||
int32_t MX66UW1G45G_AutoPollingMemReady(XSPI_HandleTypeDef *Ctx, MX66UW1G45G_Interface_t Mode,
|
||||
MX66UW1G45G_Transfer_t Rate);
|
||||
|
||||
/* Read/Write Array Commands **************************************************/
|
||||
int32_t MX66UW1G45G_ReadSTR(XSPI_HandleTypeDef *Ctx, MX66UW1G45G_Interface_t Mode,
|
||||
MX66UW1G45G_AddressWidth_t AddressWidth, uint8_t *pData, uint32_t ReadAddr, uint32_t Size);
|
||||
int32_t MX66UW1G45G_ReadDTR(XSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t ReadAddr, uint32_t Size);
|
||||
int32_t MX66UW1G45G_PageProgram(XSPI_HandleTypeDef *Ctx, MX66UW1G45G_Interface_t Mode,
|
||||
MX66UW1G45G_AddressWidth_t AddressWidth, uint8_t *pData, uint32_t WriteAddr,
|
||||
uint32_t Size);
|
||||
int32_t MX66UW1G45G_PageProgramDTR(XSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t WriteAddr, uint32_t Size);
|
||||
int32_t MX66UW1G45G_BlockErase(XSPI_HandleTypeDef *Ctx, MX66UW1G45G_Interface_t Mode, MX66UW1G45G_Transfer_t Rate,
|
||||
MX66UW1G45G_AddressWidth_t AddressWidth, uint32_t BlockAddress,
|
||||
MX66UW1G45G_Erase_t BlockSize);
|
||||
int32_t MX66UW1G45G_ChipErase(XSPI_HandleTypeDef *Ctx, MX66UW1G45G_Interface_t Mode, MX66UW1G45G_Transfer_t Rate);
|
||||
int32_t MX66UW1G45G_EnableMemoryMappedModeSTR(XSPI_HandleTypeDef *Ctx, MX66UW1G45G_Interface_t Mode,
|
||||
MX66UW1G45G_AddressWidth_t AddressWidth);
|
||||
int32_t MX66UW1G45G_EnableMemoryMappedModeDTR(XSPI_HandleTypeDef *Ctx, MX66UW1G45G_Interface_t Mode);
|
||||
int32_t MX66UW1G45G_Suspend(XSPI_HandleTypeDef *Ctx, MX66UW1G45G_Interface_t Mode, MX66UW1G45G_Transfer_t Rate);
|
||||
int32_t MX66UW1G45G_Resume(XSPI_HandleTypeDef *Ctx, MX66UW1G45G_Interface_t Mode, MX66UW1G45G_Transfer_t Rate);
|
||||
|
||||
/* Register/Setting Commands **************************************************/
|
||||
int32_t MX66UW1G45G_WriteEnable(XSPI_HandleTypeDef *Ctx, MX66UW1G45G_Interface_t Mode, MX66UW1G45G_Transfer_t Rate);
|
||||
int32_t MX66UW1G45G_WriteDisable(XSPI_HandleTypeDef *Ctx, MX66UW1G45G_Interface_t Mode, MX66UW1G45G_Transfer_t Rate);
|
||||
int32_t MX66UW1G45G_ReadStatusRegister(XSPI_HandleTypeDef *Ctx, MX66UW1G45G_Interface_t Mode,
|
||||
MX66UW1G45G_Transfer_t Rate, uint8_t *Value);
|
||||
int32_t MX66UW1G45G_WriteStatusRegister(XSPI_HandleTypeDef *Ctx, MX66UW1G45G_Interface_t Mode,
|
||||
MX66UW1G45G_Transfer_t Rate, uint8_t Value);
|
||||
int32_t MX66UW1G45G_WriteCfgRegister(XSPI_HandleTypeDef *Ctx, MX66UW1G45G_Interface_t Mode,
|
||||
MX66UW1G45G_Transfer_t Rate, uint8_t Value);
|
||||
int32_t MX66UW1G45G_ReadCfgRegister(XSPI_HandleTypeDef *Ctx, MX66UW1G45G_Interface_t Mode,
|
||||
MX66UW1G45G_Transfer_t Rate, uint8_t *Value);
|
||||
int32_t MX66UW1G45G_WriteCfg2Register(XSPI_HandleTypeDef *Ctx, MX66UW1G45G_Interface_t Mode,
|
||||
MX66UW1G45G_Transfer_t Rate, uint32_t WriteAddr, uint8_t Value);
|
||||
int32_t MX66UW1G45G_ReadCfg2Register(XSPI_HandleTypeDef *Ctx, MX66UW1G45G_Interface_t Mode,
|
||||
MX66UW1G45G_Transfer_t Rate, uint32_t ReadAddr, uint8_t *Value);
|
||||
int32_t MX66UW1G45G_WriteSecurityRegister(XSPI_HandleTypeDef *Ctx, MX66UW1G45G_Interface_t Mode,
|
||||
MX66UW1G45G_Transfer_t Rate, uint8_t Value);
|
||||
int32_t MX66UW1G45G_ReadSecurityRegister(XSPI_HandleTypeDef *Ctx, MX66UW1G45G_Interface_t Mode,
|
||||
MX66UW1G45G_Transfer_t Rate, uint8_t *Value);
|
||||
|
||||
/* ID/Security Commands *******************************************************/
|
||||
int32_t MX66UW1G45G_ReadID(XSPI_HandleTypeDef *Ctx, MX66UW1G45G_Interface_t Mode, MX66UW1G45G_Transfer_t Rate,
|
||||
uint8_t *ID);
|
||||
|
||||
/* Reset Commands *************************************************************/
|
||||
int32_t MX66UW1G45G_ResetEnable(XSPI_HandleTypeDef *Ctx, MX66UW1G45G_Interface_t Mode, MX66UW1G45G_Transfer_t Rate);
|
||||
int32_t MX66UW1G45G_ResetMemory(XSPI_HandleTypeDef *Ctx, MX66UW1G45G_Interface_t Mode, MX66UW1G45G_Transfer_t Rate);
|
||||
int32_t MX66UW1G45G_NoOperation(XSPI_HandleTypeDef *Ctx, MX66UW1G45G_Interface_t Mode, MX66UW1G45G_Transfer_t Rate);
|
||||
int32_t MX66UW1G45G_EnterPowerDown(XSPI_HandleTypeDef *Ctx, MX66UW1G45G_Interface_t Mode,
|
||||
MX66UW1G45G_Transfer_t Rate);
|
||||
int32_t MX66UW1G45G_ReleasePowerDown(XSPI_HandleTypeDef *Ctx, MX66UW1G45G_Interface_t Mode,
|
||||
MX66UW1G45G_Transfer_t Rate);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* MX66UW1G45G_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -0,0 +1,51 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file mx66uw1g45g_conf.h
|
||||
* @author MCD Application Team
|
||||
* @brief MX66UW1G45G OctoSPI memory configuration template file.
|
||||
* This file should be copied to the application folder and renamed
|
||||
* to mx66uw1g45g_conf.h
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef MX66UW1G45G_CONF_H
|
||||
#define MX66UW1G45G_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32xxxx_hal.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
#define CONF_OSPI_ODS MX66UW1G45G_CR_ODS_24 /* MX66UW1G45G Output Driver Strength */
|
||||
|
||||
#define DUMMY_CYCLES_READ 8U
|
||||
#define DUMMY_CYCLES_READ_OCTAL 6U
|
||||
#define DUMMY_CYCLES_READ_OCTAL_DTR 6U
|
||||
#define DUMMY_CYCLES_REG_OCTAL 4U
|
||||
#define DUMMY_CYCLES_REG_OCTAL_DTR 5U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* MX66UW1G45G_CONF_H */
|
||||
Reference in new issue
Block a user