CubeMX: SPI4 + SDMMC1/FatFs + I2S6, audio BSP et debug VS Code (Linux)
Regeneration CubeMX (Appli) preparant le driver ST67W611M1 et la carte SD : - SPI4 (PE12/13/14, CS PF8) + DMA GPDMA1 canaux 4/5, SPI_RDY (PD12/EXTI12), CHIP_EN (PD13) et BOOT (PD15) pour la X-NUCLEO-67W61M1 sur l'Arduino - SDMMC1 + FatFs (appels d'init non generes dans main, IRQ SDMMC1 prio 14), PM14 en open-drain ; I2S6_CK sur PA5 pour liberer PC12 (SDMMC1_CK) - HAL UART retire ; USE_BSP_COM_FEATURE=0 - Audio preserve : ADF 4/16/24, prio IRQ 2, DMA canal 0 en priorite haute, GPDMA1_Channel2_IRQHandler deplace dans audio_irq.c (hors fichiers generes), BSP_MX_I2S6_Init (renommage dans le BSP pour eviter le conflit avec CubeMX) - Middlewares/ST/ST67W6X_Network_Driver, FatFs et sources HAL SPI/SD ajoutes (driver ST67 pas encore integre au build) Build et debug sous Linux : - gcc/toolchain-env.sh, gdbserver.sh, arm-gdb.sh : outils de STM32CubeIDE par glob ; flash.sh les retrouve ; ruby_compat.rb pour Ruby >= 3.2 (TouchGFX) - makefile_appli : sources SD/SPI/FatFs/audio_irq ; chmod +x des .out TouchGFX - Objets de build (*.o, *.d, *.su) retires de l'index (deja dans .gitignore) - AGENTS.md : toolchain Linux, configs VS Code (cppdbg et ST stlinkgdbtarget), pieges de l'extension ST (.settings/ide.store.json, preRunCommands reset) Verifie sur carte : audio OK, debug Appli/Boot OK. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
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/**
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******************************************************************************
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* @file stm32h7rsxx_ll_dlyb.c
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* @author MCD Application Team
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* @brief DelayBlock Low Layer HAL module driver.
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*
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* This file provides firmware functions to manage the following
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* functionalities of the DelayBlock peripheral:
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* + input clock frequency
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* + up to 12 oversampling phases
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*
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2022 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@verbatim
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==============================================================================
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##### DelayBlock peripheral features #####
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==============================================================================
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[..] The DelayBlock is used to generate an Output clock which is de-phased from the Input
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clock. The phase of the Output clock is programmed by FW. The Output clock is then used
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to clock the receive data in i.e. a SDMMC, OSPI or QSPI interface.
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The delay is Voltage and Temperature dependent, which may require FW to do re-tuning
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and recenter the Output clock phase to the receive data.
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[..] The DelayBlock features include the following:
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(+) Input clock frequency.
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(+) Up to 12 oversampling phases.
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##### How to use this driver #####
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==============================================================================
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[..]
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This driver is a considered as a driver of service for external devices drivers
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that interfaces with the DELAY peripheral.
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The LL_DLYB_SetDelay() function, configure the Delay value configured on SEL and UNIT.
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The LL_DLYB_GetDelay() function, return the Delay value configured on SEL and UNIT.
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The LL_DLYB_GetClockPeriod()function, get the clock period.
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@endverbatim
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32h7rsxx_hal.h"
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/** @addtogroup STM32H7RSxx_LL_Driver
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* @{
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*/
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/** @defgroup DLYB_LL DLYB
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* @brief DLYB LL module driver.
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* @{
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*/
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#if defined(HAL_SD_MODULE_ENABLED)
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#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2)
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/**
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@cond 0
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*/
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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#define DLYB_TIMEOUT 0xFFU
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#define DLYB_LNG_10_0_MASK 0x07FF0000U
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#define DLYB_LNG_11_10_MASK 0x0C000000U
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/**
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@endcond
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup DLYB_LL_Exported_Functions
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* @brief Configuration and control functions
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*
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@verbatim
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===============================================================================
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##### Control functions #####
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===============================================================================
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[..] This section provides functions allowing to
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(+) Control the DLYB.
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@endverbatim
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* @{
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*/
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/** @addtogroup DLYB_Control_Functions DLYB Control functions
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* @{
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*/
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/**
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* @brief Set the Delay value configured on SEL and UNIT.
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* @param DLYBx: Pointer to DLYB instance.
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* @param pdlyb_cfg: Pointer to DLYB configuration structure.
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* @retval An ErrorStatus enumeration value:
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* - SUCCESS: the Delay value is set.
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* - ERROR: the Delay value is not set.
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*/
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void LL_DLYB_SetDelay(DLYB_TypeDef *DLYBx, const LL_DLYB_CfgTypeDef *pdlyb_cfg)
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{
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/* Check the DelayBlock instance */
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assert_param(IS_DLYB_ALL_INSTANCE(DLYBx));
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/* Enable the length sampling */
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SET_BIT(DLYBx->CR, DLYB_CR_SEN);
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/* Update the UNIT and SEL field */
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DLYBx->CFGR = (pdlyb_cfg->PhaseSel) | ((pdlyb_cfg->Units) << DLYB_CFGR_UNIT_Pos);
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/* Disable the length sampling */
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CLEAR_BIT(DLYBx->CR, DLYB_CR_SEN);
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}
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/**
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* @brief Get the Delay value configured on SEL and UNIT.
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* @param DLYBx: Pointer to DLYB instance.
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* @param pdlyb_cfg: Pointer to DLYB configuration structure.
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* @retval An ErrorStatus enumeration value:
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* - SUCCESS: the Delay value is received.
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* - ERROR: the Delay value is not received.
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*/
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void LL_DLYB_GetDelay(const DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg)
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{
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/* Check the DelayBlock instance */
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assert_param(IS_DLYB_ALL_INSTANCE(DLYBx));
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/* Fill the DelayBlock configuration structure with SEL and UNIT value */
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pdlyb_cfg->Units = ((DLYBx->CFGR & DLYB_CFGR_UNIT) >> DLYB_CFGR_UNIT_Pos);
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pdlyb_cfg->PhaseSel = (DLYBx->CFGR & DLYB_CFGR_SEL);
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}
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/**
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* @brief Get the clock period.
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* @param DLYBx: Pointer to DLYB instance.
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* @param pdlyb_cfg: Pointer to DLYB configuration structure.
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* @retval An ErrorStatus enumeration value:
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* - SUCCESS: there is a valid period detected and stored in pdlyb_cfg.
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* - ERROR: there is no valid period detected.
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*/
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uint32_t LL_DLYB_GetClockPeriod(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg)
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{
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uint32_t i = 0U;
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uint32_t nb ;
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uint32_t lng ;
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uint32_t tickstart;
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/* Check the DelayBlock instance */
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assert_param(IS_DLYB_ALL_INSTANCE(DLYBx));
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/* Enable the length sampling */
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SET_BIT(DLYBx->CR, DLYB_CR_SEN);
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/* Delay line length detection */
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while (i < DLYB_MAX_UNIT)
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{
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/* Set the Delay of the UNIT(s)*/
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DLYBx->CFGR = DLYB_MAX_SELECT | (i << DLYB_CFGR_UNIT_Pos);
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/* Waiting for a LNG valid value */
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tickstart = HAL_GetTick();
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while ((DLYBx->CFGR & DLYB_CFGR_LNGF) == 0U)
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{
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if ((HAL_GetTick() - tickstart) >= DLYB_TIMEOUT)
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{
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/* New check to avoid false timeout detection in case of preemption */
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if ((DLYBx->CFGR & DLYB_CFGR_LNGF) == 0U)
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{
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return (uint32_t) HAL_TIMEOUT;
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}
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}
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}
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if ((DLYBx->CFGR & DLYB_LNG_10_0_MASK) != 0U)
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{
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if ((DLYBx->CFGR & (DLYB_CFGR_LNG_11 | DLYB_CFGR_LNG_10)) != DLYB_LNG_11_10_MASK)
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{
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/* Delay line length is configured to one input clock period*/
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break;
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}
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}
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i++;
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}
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if (DLYB_MAX_UNIT != i)
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{
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/* Determine how many unit delays (nb) span one input clock period */
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lng = (DLYBx->CFGR & DLYB_CFGR_LNG) >> 16U;
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nb = 10U;
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while ((nb > 0U) && ((lng >> nb) == 0U))
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{
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nb--;
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}
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if (nb != 0U)
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{
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pdlyb_cfg->PhaseSel = nb ;
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pdlyb_cfg->Units = i ;
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/* Disable the length sampling */
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DLYBx->CR = DLYB_CR_SEN;
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return (uint32_t)SUCCESS;
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}
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}
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/* Disable the length sampling */
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DLYBx->CR = DLYB_CR_SEN;
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return (uint32_t)ERROR;
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#endif /* DLYB_SDMMC1 || DLYB_SDMMC2 */
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#endif /* HAL_SD_MODULE_ENABLED */
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/**
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* @}
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*/
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/**
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* @}
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*/
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