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Copyright 2020(-2023) STMicroelectronics.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
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||||
list of conditions and the following disclaimer.
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||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
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may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
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||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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@@ -0,0 +1,6 @@
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||||
This software component is provided to you as part of a software package and
|
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applicable license terms are in the Package_license file. If you received this
|
||||
software component outside of a package or without applicable license terms,
|
||||
the terms of the BSD-3-Clause license shall apply.
|
||||
You may obtain a copy of the BSD-3-Clause at:
|
||||
https://opensource.org/licenses/BSD-3-Clause
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||||
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||||
<!DOCTYPE html>
|
||||
<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">
|
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<head>
|
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<meta charset="utf-8" />
|
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<meta name="generator" content="pandoc" />
|
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<meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
|
||||
<title>Release Notes for APS256XX 16-Bits OCTOSPI Component Driver</title>
|
||||
<style type="text/css">
|
||||
code{white-space: pre-wrap;}
|
||||
span.smallcaps{font-variant: small-caps;}
|
||||
span.underline{text-decoration: underline;}
|
||||
div.column{display: inline-block; vertical-align: top; width: 50%;}
|
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</style>
|
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<link rel="stylesheet" href="_htmresc/mini-st_2020.css" />
|
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<!--[if lt IE 9]>
|
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<script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
|
||||
<![endif]-->
|
||||
<link rel="icon" type="image/x-icon" href="_htmresc/favicon.png" />
|
||||
</head>
|
||||
<body>
|
||||
<div class="row">
|
||||
<div class="col-sm-12 col-lg-4">
|
||||
<center>
|
||||
<h1 id="release-notes-for-aps256xx-component-driver">Release Notes for <mark>APS256XX</mark> Component Driver</h1>
|
||||
<p>Copyright © 2020 STMicroelectronics<br />
|
||||
</p>
|
||||
<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo_2020.png" alt="ST logo" /></a>
|
||||
</center>
|
||||
<h1 id="purpose">Purpose</h1>
|
||||
<p>This driver provides a set of functions offered by APS256XX 16-Bits OCTOSPI component</p>
|
||||
</div>
|
||||
<div class="col-sm-12 col-lg-8">
|
||||
<h1 id="update-history">Update History</h1>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section6" checked aria-hidden="true"> <label for="collapse-section6" aria-hidden="true"><strong>V1.0.6 / 08-December-2023</strong></label>
|
||||
<div>
|
||||
<h2 id="main-changes">Main Changes</h2>
|
||||
<ul>
|
||||
<li>Set correct bit in MR6 register to enter power down</li>
|
||||
<li>Correct MISRA-C 2012 warning</li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true"><strong>V1.0.5 / 12-December-2022</strong></label>
|
||||
<div>
|
||||
<h2 id="main-changes-1">Main Changes</h2>
|
||||
<ul>
|
||||
<li>Add XSPI_CCR_SIOO macro</li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.0.4 / 09-February-2022</strong></label>
|
||||
<div>
|
||||
<h2 id="main-changes-2">Main Changes</h2>
|
||||
<ul>
|
||||
<li>Update license</li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.0.3 / 06-October-2021</strong></label>
|
||||
<div>
|
||||
<h2 id="main-changes-3">Main Changes</h2>
|
||||
<ul>
|
||||
<li>Initialize sCommand structure as 0 in “Enable Memory mapped” API to avoid Issues related to non-filled sCommand field</li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.0.2 / 23-September-2021</strong></label>
|
||||
<div>
|
||||
<h2 id="main-changes-4">Main Changes</h2>
|
||||
<ul>
|
||||
<li>Code formatting and spelling</li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.0.1 / 30-April-2021</strong></label>
|
||||
<div>
|
||||
<h2 id="main-changes-5">Main Changes</h2>
|
||||
<ul>
|
||||
<li>Code formatting and spelling</li>
|
||||
<li>Update memory Command configuration values</li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 27-March-2020</strong></label>
|
||||
<div>
|
||||
<h2 id="main-changes-6">Main Changes</h2>
|
||||
<ul>
|
||||
<li>First Official Release of APS256XX 16-bits SPI Component drivers in line with STM32Cube BSP drivers development guidelines (UM2298)</li>
|
||||
<li>The component drivers are composed of
|
||||
<ul>
|
||||
<li>component core drivers files: aps256xx.h/.c</li>
|
||||
<li>component configuration file: aps256xx_conf_template.h</li>
|
||||
</ul></li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
<footer class="sticky">
|
||||
For complete documentation on <mark>STM32 Microcontrollers</mark> , visit: <span style="font-color: blue;"><a href="http://www.st.com/STM32">www.st.com</a></span>
|
||||
</footer>
|
||||
</body>
|
||||
</html>
|
||||
@@ -0,0 +1,120 @@
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---
|
||||
pagetitle: Release Notes for APS256XX 16-Bits OCTOSPI Component Driver
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lang: en
|
||||
header-includes: <link rel="icon" type="image/x-icon" href="_htmresc/favicon.png" />
|
||||
---
|
||||
::: {.row}
|
||||
::: {.col-sm-12 .col-lg-4}
|
||||
|
||||
<center>
|
||||
# Release Notes for <mark>APS256XX</mark> Component Driver
|
||||
Copyright © 2020 STMicroelectronics\
|
||||
|
||||
[](https://www.st.com){.logo}
|
||||
</center>
|
||||
|
||||
# Purpose
|
||||
|
||||
This driver provides a set of functions offered by APS256XX 16-Bits OCTOSPI component
|
||||
|
||||
:::
|
||||
|
||||
::: {.col-sm-12 .col-lg-8}
|
||||
# Update History
|
||||
|
||||
::: {.collapse}
|
||||
<input type="checkbox" id="collapse-section6" checked aria-hidden="true">
|
||||
<label for="collapse-section6" aria-hidden="true">__V1.0.6 / 08-December-2023__</label>
|
||||
<div>
|
||||
|
||||
## Main Changes
|
||||
|
||||
- Set correct bit in MR6 register to enter power down
|
||||
- Correct MISRA-C 2012 warning
|
||||
|
||||
</div>
|
||||
:::
|
||||
|
||||
::: {.collapse}
|
||||
<input type="checkbox" id="collapse-section5" aria-hidden="true">
|
||||
<label for="collapse-section5" aria-hidden="true">__V1.0.5 / 12-December-2022__</label>
|
||||
<div>
|
||||
|
||||
## Main Changes
|
||||
|
||||
- Add XSPI_CCR_SIOO macro
|
||||
|
||||
</div>
|
||||
:::
|
||||
|
||||
::: {.collapse}
|
||||
<input type="checkbox" id="collapse-section4" aria-hidden="true">
|
||||
<label for="collapse-section4" aria-hidden="true">__V1.0.4 / 09-February-2022__</label>
|
||||
<div>
|
||||
|
||||
## Main Changes
|
||||
|
||||
- Update license
|
||||
|
||||
</div>
|
||||
:::
|
||||
|
||||
::: {.collapse}
|
||||
<input type="checkbox" id="collapse-section4" aria-hidden="true">
|
||||
<label for="collapse-section4" aria-hidden="true">__V1.0.3 / 06-October-2021__</label>
|
||||
<div>
|
||||
|
||||
## Main Changes
|
||||
|
||||
- Initialize sCommand structure as 0 in “Enable Memory mapped” API to avoid Issues related to non-filled sCommand field
|
||||
|
||||
</div>
|
||||
:::
|
||||
|
||||
::: {.collapse}
|
||||
<input type="checkbox" id="collapse-section3" aria-hidden="true">
|
||||
<label for="collapse-section3" aria-hidden="true">__V1.0.2 / 23-September-2021__</label>
|
||||
<div>
|
||||
|
||||
## Main Changes
|
||||
|
||||
- Code formatting and spelling
|
||||
|
||||
</div>
|
||||
:::
|
||||
|
||||
::: {.collapse}
|
||||
<input type="checkbox" id="collapse-section2" aria-hidden="true">
|
||||
<label for="collapse-section2" aria-hidden="true">__V1.0.1 / 30-April-2021__</label>
|
||||
<div>
|
||||
|
||||
## Main Changes
|
||||
|
||||
- Code formatting and spelling
|
||||
- Update memory Command configuration values
|
||||
|
||||
</div>
|
||||
:::
|
||||
|
||||
::: {.collapse}
|
||||
<input type="checkbox" id="collapse-section1" aria-hidden="true">
|
||||
<label for="collapse-section1" aria-hidden="true">__V1.0.0 / 27-March-2020__</label>
|
||||
<div>
|
||||
|
||||
## Main Changes
|
||||
|
||||
- First Official Release of APS256XX 16-bits SPI Component drivers in line with STM32Cube BSP drivers development guidelines (UM2298)
|
||||
- The component drivers are composed of
|
||||
- component core drivers files: aps256xx.h/.c
|
||||
- component configuration file: aps256xx_conf_template.h
|
||||
|
||||
</div>
|
||||
:::
|
||||
|
||||
:::
|
||||
:::
|
||||
|
||||
<footer class="sticky">
|
||||
For complete documentation on <mark>STM32 Microcontrollers</mark> ,
|
||||
visit: [[www.st.com](http://www.st.com/STM32)]{style="font-color: blue;"}
|
||||
</footer>
|
||||
@@ -0,0 +1,2 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<svg xmlns="http://www.w3.org/2000/svg" viewBox="0 0 200 200"><g fill="#13254a"><path d="M100 .212C44.868.212 0 44.889 0 99.788c0 55.132 44.868 100 100 100s100-44.868 100-100C200 44.889 155.132.212 100 .212zm0 181.164c-44.974 0-81.587-36.614-81.587-81.587 0-44.762 36.614-81.164 81.587-81.164 44.995 0 81.587 36.402 81.587 81.164 0 44.973-36.592 81.587-81.587 81.587z" style="fill: #e6007e;"/><path d="M141.1 88.127h-29.439V58.688c0-6.392-5.185-11.598-11.598-11.598-6.413 0-11.619 5.206-11.619 11.598v29.439H58.476c-6.392 0-11.598 5.185-11.598 11.598 0 6.413 5.206 11.619 11.598 11.619h29.968v29.968c0 6.392 5.206 11.598 11.619 11.598 6.413 0 11.598-5.206 11.598-11.598v-29.968H141.1c6.392 0 11.598-5.206 11.598-11.619 0-6.413-5.206-11.598-11.598-11.598z" style="fill: #e6007e;"/></g></svg>
|
||||
|
After Width: | Height: | Size: 832 B |
@@ -0,0 +1,2 @@
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||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<svg xmlns="http://www.w3.org/2000/svg" viewBox="0 0 200 200"><g fill="#03234b"><path d="M170.934 64.569l-.04-.055-29.049 40.038-.057.079h14.867a59.366 59.366 0 0 1-1.488 15.615c-1.158 5.318-3.807 13.448-9.848 21.977-2.766 4.118-6.375 7.726-9.208 10.408-3.426 2.857-7.461 6.095-12 8.376-8.121 4.568-17.881 7.138-28.225 7.432-10.907.248-20.201-2.61-26.072-5.052-8.283-3.479-14.111-7.807-16.85-10.078-1.254-.956-2.25-1.907-3.057-2.676a28.662 28.662 0 0 0-1.157-1.069 158.874 158.874 0 0 0-1.479-1.362l-4.435-3.956 3.569 4.81.183.243c.2.263.548.722 1.048 1.389.276.334.579.747.93 1.226l.008.01c.689.939 1.546 2.107 2.664 3.322 3 3.536 8.178 8.801 15.808 13.801 5.969 3.866 15.672 8.901 28.001 10.935a79.05 79.05 0 0 0 12.485.998c7.97 0 15.651-1.228 22.828-3.649 6.366-1.877 12.192-4.981 17.053-7.771 6.16-3.936 10.817-7.586 14.654-11.488 8.084-7.899 14.884-17.913 19.15-28.199 3.259-7.594 5.456-15.727 6.529-24.175l.055-.425.083-.641H200l-29.066-40.063zM58.159 99.232l-12.655.563c-.097-.881-.159-1.986-.227-3.474a59.184 59.184 0 0 1 1.446-16.56c1.157-5.316 3.804-13.444 9.848-21.977 2.168-3.228 5.009-6.44 9.208-10.415 3.41-2.849 7.432-6.08 12.005-8.375 8.114-4.568 17.87-7.138 28.213-7.432 10.9-.25 20.196 2.607 26.072 5.045 8.258 3.473 14.105 7.812 16.857 10.091 1.257.951 2.253 1.904 3.057 2.673l.017.016c.43.411.801.766 1.136 1.051.475.438.841.777 1.091 1.01l.138.128.248.229 4.04 3.613-3.165-4.456c-.058-.083-.312-.417-.73-.971l-.507-.67a28.922 28.922 0 0 1-.901-1.192l-.02-.027c-.69-.945-1.548-2.121-2.677-3.346-3.002-3.537-8.182-8.803-15.813-13.801-5.964-3.865-15.662-8.9-27.997-10.935-8.484-1.363-21.496-2.009-35.313 2.651-6.355 1.88-12.186 4.983-17.054 7.772-6.163 3.944-10.82 7.595-14.654 11.488-8.079 7.894-14.882 17.909-19.155 28.2-3.268 7.624-5.463 15.757-6.523 24.173-.436 3.281-.642 5.421-.664 6.926L0 101.831l30.683 38.727.042.053 27.38-41.298.054-.081z" style="fill: #e6007e;"/></g></svg>
|
||||
|
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/**
|
||||
******************************************************************************
|
||||
* @file aps256xx.c
|
||||
* @modify MCD Application Team
|
||||
* @brief This file provides the APS256XX HSPI drivers.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "aps256xx.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Components
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup APS256XX APS256XX
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup APS256XX_Exported_Functions APS256XX Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Read/Write Array Commands *********************/
|
||||
/**
|
||||
* @brief Reads an amount of data from the memory.
|
||||
* @param Ctx Component object pointer
|
||||
* @param pData Pointer to data to be read
|
||||
* @param ReadAddr Read start address
|
||||
* @param Size Size of data to read
|
||||
* @param LatencyCode Latency used for the access
|
||||
* @param IOMode I/O Mode used for the access
|
||||
* @param BurstType Type of burst used for the access
|
||||
* @retval Memory status
|
||||
*/
|
||||
int32_t APS256XX_Read(XSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t ReadAddr, uint32_t Size, uint32_t LatencyCode,
|
||||
uint32_t IOMode, uint32_t BurstType)
|
||||
{
|
||||
XSPI_RegularCmdTypeDef sCommand = {0};
|
||||
|
||||
/* Initialize the read command */
|
||||
sCommand.OperationType = HAL_XSPI_OPTYPE_COMMON_CFG;
|
||||
sCommand.InstructionMode = HAL_XSPI_INSTRUCTION_8_LINES;
|
||||
sCommand.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS;
|
||||
sCommand.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE;
|
||||
sCommand.Instruction = ((BurstType == 0U) ? APS256XX_READ_LINEAR_BURST_CMD : APS256XX_READ_CMD);
|
||||
sCommand.AddressMode = HAL_XSPI_ADDRESS_8_LINES;
|
||||
sCommand.AddressWidth = HAL_XSPI_ADDRESS_32_BITS;
|
||||
sCommand.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_ENABLE;
|
||||
sCommand.Address = ReadAddr;
|
||||
sCommand.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE;
|
||||
sCommand.DataMode = ((IOMode == 0U) ? HAL_XSPI_DATA_8_LINES : HAL_XSPI_DATA_16_LINES);
|
||||
sCommand.DataDTRMode = HAL_XSPI_DATA_DTR_ENABLE;
|
||||
sCommand.DataLength = Size;
|
||||
sCommand.DummyCycles = (LatencyCode - 1U);
|
||||
sCommand.DQSMode = HAL_XSPI_DQS_ENABLE;
|
||||
#if defined (XSPI_CCR_SIOO)
|
||||
sCommand.SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD;
|
||||
#endif
|
||||
/* Configure the command */
|
||||
if (HAL_XSPI_Command(Ctx, &sCommand, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return APS256XX_ERROR;
|
||||
}
|
||||
|
||||
/* Reception of the data */
|
||||
if (HAL_XSPI_Receive(Ctx, pData, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return APS256XX_ERROR;
|
||||
}
|
||||
|
||||
return APS256XX_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads an amount of data in DMA mode from the memory.
|
||||
* @param Ctx Component object pointer
|
||||
* @param pData Pointer to data to be read
|
||||
* @param ReadAddr Read start address
|
||||
* @param Size Size of data to read
|
||||
* @param LatencyCode Latency used for the access
|
||||
* @param IOMode I/O Mode used for the access
|
||||
* @param BurstType Type of burst used for the access
|
||||
* @retval Memory status
|
||||
*/
|
||||
int32_t APS256XX_Read_DMA(XSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t ReadAddr, uint32_t Size,
|
||||
uint32_t LatencyCode, uint32_t IOMode, uint32_t BurstType)
|
||||
{
|
||||
XSPI_RegularCmdTypeDef sCommand = {0};
|
||||
|
||||
/* Initialize the read command */
|
||||
sCommand.OperationType = HAL_XSPI_OPTYPE_COMMON_CFG;
|
||||
sCommand.InstructionMode = HAL_XSPI_INSTRUCTION_8_LINES;
|
||||
sCommand.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS;
|
||||
sCommand.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE;
|
||||
sCommand.Instruction = ((BurstType == 0U) ? APS256XX_READ_LINEAR_BURST_CMD : APS256XX_READ_CMD);
|
||||
sCommand.AddressMode = HAL_XSPI_ADDRESS_8_LINES;
|
||||
sCommand.AddressWidth = HAL_XSPI_ADDRESS_32_BITS;
|
||||
sCommand.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_ENABLE;
|
||||
sCommand.Address = ReadAddr;
|
||||
sCommand.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE;
|
||||
sCommand.DataMode = ((IOMode == 0U) ? HAL_XSPI_DATA_8_LINES : HAL_XSPI_DATA_16_LINES);
|
||||
sCommand.DataDTRMode = HAL_XSPI_DATA_DTR_ENABLE;
|
||||
sCommand.DataLength = Size;
|
||||
sCommand.DummyCycles = (LatencyCode - 1U);
|
||||
sCommand.DQSMode = HAL_XSPI_DQS_ENABLE;
|
||||
#if defined (XSPI_CCR_SIOO)
|
||||
sCommand.SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD;
|
||||
#endif
|
||||
|
||||
/* Configure the command */
|
||||
if (HAL_XSPI_Command(Ctx, &sCommand, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return APS256XX_ERROR;
|
||||
}
|
||||
|
||||
/* Reception of the data */
|
||||
if (HAL_XSPI_Receive_DMA(Ctx, pData) != HAL_OK)
|
||||
{
|
||||
return APS256XX_ERROR;
|
||||
}
|
||||
|
||||
return APS256XX_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes an amount of data to the memory.
|
||||
* @param Ctx Component object pointer
|
||||
* @param pData Pointer to data to be written
|
||||
* @param WriteAddr Write start address
|
||||
* @param Size Size of data to write
|
||||
* @param LatencyCode Latency used for the access
|
||||
* @param IOMode I/O Mode used for the access
|
||||
* @param BurstType Type of burst used for the access
|
||||
* @retval Memory status
|
||||
*/
|
||||
int32_t APS256XX_Write(XSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t WriteAddr, uint32_t Size, uint32_t LatencyCode,
|
||||
uint32_t IOMode, uint32_t BurstType)
|
||||
{
|
||||
XSPI_RegularCmdTypeDef sCommand = {0};
|
||||
|
||||
/* Initialize the write command */
|
||||
sCommand.OperationType = HAL_XSPI_OPTYPE_COMMON_CFG;
|
||||
sCommand.InstructionMode = HAL_XSPI_INSTRUCTION_8_LINES;
|
||||
sCommand.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS;
|
||||
sCommand.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE;
|
||||
sCommand.Instruction = ((BurstType == 0U) ? APS256XX_WRITE_LINEAR_BURST_CMD : APS256XX_WRITE_CMD);
|
||||
sCommand.AddressMode = HAL_XSPI_ADDRESS_8_LINES;
|
||||
sCommand.AddressWidth = HAL_XSPI_ADDRESS_32_BITS;
|
||||
sCommand.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_ENABLE;
|
||||
sCommand.Address = WriteAddr;
|
||||
sCommand.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE;
|
||||
sCommand.DataMode = ((IOMode == 0U) ? HAL_XSPI_DATA_8_LINES : HAL_XSPI_DATA_16_LINES);
|
||||
sCommand.DataDTRMode = HAL_XSPI_DATA_DTR_ENABLE;
|
||||
sCommand.DataLength = Size;
|
||||
sCommand.DummyCycles = (LatencyCode - 1U);
|
||||
sCommand.DQSMode = HAL_XSPI_DQS_ENABLE;
|
||||
#if defined (XSPI_CCR_SIOO)
|
||||
sCommand.SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD;
|
||||
#endif
|
||||
|
||||
/* Configure the command */
|
||||
if (HAL_XSPI_Command(Ctx, &sCommand, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return APS256XX_ERROR;
|
||||
}
|
||||
|
||||
/* Transmission of the data */
|
||||
if (HAL_XSPI_Transmit(Ctx, pData, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return APS256XX_ERROR;
|
||||
}
|
||||
|
||||
return APS256XX_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes an amount of data in DMA mode to the memory.
|
||||
* @param Ctx Component object pointer
|
||||
* @param pData Pointer to data to be written
|
||||
* @param WriteAddr Write start address
|
||||
* @param Size Size of data to write
|
||||
* @param LatencyCode Latency used for the access
|
||||
* @param IOMode I/O Mode used for the access
|
||||
* @param BurstType Type of burst used for the access
|
||||
* @retval Memory status
|
||||
*/
|
||||
int32_t APS256XX_Write_DMA(XSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t WriteAddr, uint32_t Size,
|
||||
uint32_t LatencyCode, uint32_t IOMode, uint32_t BurstType)
|
||||
{
|
||||
XSPI_RegularCmdTypeDef sCommand = {0};
|
||||
|
||||
/* Initialize the write command */
|
||||
sCommand.OperationType = HAL_XSPI_OPTYPE_COMMON_CFG;
|
||||
sCommand.InstructionMode = HAL_XSPI_INSTRUCTION_8_LINES;
|
||||
sCommand.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS;
|
||||
sCommand.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE;
|
||||
sCommand.Instruction = ((BurstType == 0U) ? APS256XX_WRITE_LINEAR_BURST_CMD : APS256XX_WRITE_CMD);
|
||||
sCommand.AddressMode = HAL_XSPI_ADDRESS_8_LINES;
|
||||
sCommand.AddressWidth = HAL_XSPI_ADDRESS_32_BITS;
|
||||
sCommand.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_ENABLE;
|
||||
sCommand.Address = WriteAddr;
|
||||
sCommand.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE;
|
||||
sCommand.DataMode = ((IOMode == 0U) ? HAL_XSPI_DATA_8_LINES : HAL_XSPI_DATA_16_LINES);
|
||||
sCommand.DataDTRMode = HAL_XSPI_DATA_DTR_ENABLE;
|
||||
sCommand.DataLength = Size;
|
||||
sCommand.DummyCycles = (LatencyCode - 1U);
|
||||
sCommand.DQSMode = HAL_XSPI_DQS_ENABLE;
|
||||
#if defined (XSPI_CCR_SIOO)
|
||||
sCommand.SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD;
|
||||
#endif
|
||||
|
||||
/* Configure the command */
|
||||
if (HAL_XSPI_Command(Ctx, &sCommand, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return APS256XX_ERROR;
|
||||
}
|
||||
|
||||
/* Transmission of the data */
|
||||
if (HAL_XSPI_Transmit_DMA(Ctx, pData) != HAL_OK)
|
||||
{
|
||||
return APS256XX_ERROR;
|
||||
}
|
||||
|
||||
return APS256XX_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable memory mapped mode for the memory.
|
||||
* @param Ctx Component object pointer
|
||||
* @param ReadLatencyCode Latency used for the read access
|
||||
* @param WriteLatencyCode Latency used for the write access
|
||||
* @param IOMode I/O Mode used for the access
|
||||
* @param BurstType Type of burst used for the access
|
||||
* @retval Memory status
|
||||
*/
|
||||
int32_t APS256XX_EnableMemoryMappedMode(XSPI_HandleTypeDef *Ctx, uint32_t ReadLatencyCode, uint32_t WriteLatencyCode,
|
||||
uint32_t IOMode, uint32_t BurstType)
|
||||
{
|
||||
XSPI_RegularCmdTypeDef sCommand = {0};
|
||||
XSPI_MemoryMappedTypeDef sMemMappedCfg = {0};
|
||||
|
||||
/* Initialize the write command */
|
||||
sCommand.OperationType = HAL_XSPI_OPTYPE_WRITE_CFG;
|
||||
sCommand.InstructionMode = HAL_XSPI_INSTRUCTION_8_LINES;
|
||||
sCommand.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS;
|
||||
sCommand.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE;
|
||||
sCommand.Instruction = ((BurstType == 0U) ? APS256XX_WRITE_LINEAR_BURST_CMD : APS256XX_WRITE_CMD);
|
||||
sCommand.AddressMode = HAL_XSPI_ADDRESS_8_LINES;
|
||||
sCommand.AddressWidth = HAL_XSPI_ADDRESS_32_BITS;
|
||||
sCommand.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_ENABLE;
|
||||
sCommand.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE;
|
||||
sCommand.DataMode = ((IOMode == 0U) ? HAL_XSPI_DATA_8_LINES : HAL_XSPI_DATA_16_LINES);
|
||||
sCommand.DataDTRMode = HAL_XSPI_DATA_DTR_ENABLE;
|
||||
sCommand.DummyCycles = (WriteLatencyCode - 1U);
|
||||
sCommand.DQSMode = HAL_XSPI_DQS_ENABLE;
|
||||
#if defined (XSPI_CCR_SIOO)
|
||||
sCommand.SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD;
|
||||
#endif
|
||||
|
||||
if (HAL_XSPI_Command(Ctx, &sCommand, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return APS256XX_ERROR;
|
||||
}
|
||||
|
||||
/* Initialize the read command */
|
||||
sCommand.OperationType = HAL_XSPI_OPTYPE_READ_CFG;
|
||||
sCommand.Instruction = ((BurstType == 0U) ? APS256XX_READ_LINEAR_BURST_CMD : APS256XX_READ_CMD);
|
||||
sCommand.DummyCycles = (ReadLatencyCode - 1U);
|
||||
|
||||
if (HAL_XSPI_Command(Ctx, &sCommand, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return APS256XX_ERROR;
|
||||
}
|
||||
|
||||
/* Activation of memory-mapped mode */
|
||||
sMemMappedCfg.TimeOutActivation = HAL_XSPI_TIMEOUT_COUNTER_DISABLE;
|
||||
|
||||
if (HAL_XSPI_MemoryMapped(Ctx, &sMemMappedCfg) != HAL_OK)
|
||||
{
|
||||
return APS256XX_ERROR;
|
||||
}
|
||||
|
||||
return APS256XX_OK;
|
||||
}
|
||||
|
||||
/* Register/Setting Commands **************************************************/
|
||||
/**
|
||||
* @brief Read mode register value
|
||||
* @param Ctx Component object pointer
|
||||
* @param Address Register address
|
||||
* @param Value Register value pointer
|
||||
* @param LatencyCode Latency used for the access
|
||||
* @retval error status
|
||||
*/
|
||||
int32_t APS256XX_ReadReg(XSPI_HandleTypeDef *Ctx, uint32_t Address, uint8_t *Value, uint32_t LatencyCode)
|
||||
{
|
||||
XSPI_RegularCmdTypeDef sCommand = {0};
|
||||
|
||||
/* Initialize the read register command */
|
||||
sCommand.OperationType = HAL_XSPI_OPTYPE_COMMON_CFG;
|
||||
sCommand.InstructionMode = HAL_XSPI_INSTRUCTION_8_LINES;
|
||||
sCommand.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS;
|
||||
sCommand.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE;
|
||||
sCommand.Instruction = APS256XX_READ_REG_CMD;
|
||||
sCommand.AddressMode = HAL_XSPI_ADDRESS_8_LINES;
|
||||
sCommand.AddressWidth = HAL_XSPI_ADDRESS_32_BITS;
|
||||
sCommand.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_ENABLE;
|
||||
sCommand.Address = Address;
|
||||
sCommand.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE;
|
||||
sCommand.DataMode = HAL_XSPI_DATA_8_LINES;
|
||||
sCommand.DataDTRMode = HAL_XSPI_DATA_DTR_ENABLE;
|
||||
sCommand.DataLength = 2;
|
||||
sCommand.DummyCycles = (LatencyCode - 1U);
|
||||
sCommand.DQSMode = HAL_XSPI_DQS_ENABLE;
|
||||
#if defined (XSPI_CCR_SIOO)
|
||||
sCommand.SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD;
|
||||
#endif
|
||||
|
||||
/* Configure the command */
|
||||
if (HAL_XSPI_Command(Ctx, &sCommand, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return APS256XX_ERROR;
|
||||
}
|
||||
|
||||
/* Reception of the data */
|
||||
if (HAL_XSPI_Receive(Ctx, (uint8_t *)Value, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return APS256XX_ERROR;
|
||||
}
|
||||
|
||||
return APS256XX_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write mode register
|
||||
* @param Ctx Component object pointer
|
||||
* @param Address Register address
|
||||
* @param Value Value to write to register
|
||||
* @retval error status
|
||||
*/
|
||||
int32_t APS256XX_WriteReg(XSPI_HandleTypeDef *Ctx, uint32_t Address, uint8_t Value)
|
||||
{
|
||||
XSPI_RegularCmdTypeDef sCommand = {0};
|
||||
|
||||
/* Initialize the write register command */
|
||||
sCommand.OperationType = HAL_XSPI_OPTYPE_COMMON_CFG;
|
||||
sCommand.InstructionMode = HAL_XSPI_INSTRUCTION_8_LINES;
|
||||
sCommand.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS;
|
||||
sCommand.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE;
|
||||
sCommand.Instruction = APS256XX_WRITE_REG_CMD;
|
||||
sCommand.AddressMode = HAL_XSPI_ADDRESS_8_LINES;
|
||||
sCommand.AddressWidth = HAL_XSPI_ADDRESS_32_BITS;
|
||||
sCommand.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_ENABLE;
|
||||
sCommand.Address = Address;
|
||||
sCommand.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE;
|
||||
sCommand.DataMode = HAL_XSPI_DATA_8_LINES;
|
||||
sCommand.DataDTRMode = HAL_XSPI_DATA_DTR_ENABLE;
|
||||
sCommand.DataLength = 2;
|
||||
sCommand.DummyCycles = 0;
|
||||
sCommand.DQSMode = HAL_XSPI_DQS_DISABLE;
|
||||
#if defined (XSPI_CCR_SIOO)
|
||||
sCommand.SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD;
|
||||
#endif
|
||||
|
||||
/* Configure the command */
|
||||
if (HAL_XSPI_Command(Ctx, &sCommand, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return APS256XX_ERROR;
|
||||
}
|
||||
|
||||
/* Transmission of the data */
|
||||
if (HAL_XSPI_Transmit(Ctx, (uint8_t *)(&Value), HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return APS256XX_ERROR;
|
||||
}
|
||||
|
||||
return APS256XX_OK;
|
||||
}
|
||||
|
||||
/* ID Commands ****************************************************************/
|
||||
/**
|
||||
* @brief Read Flash IDs.
|
||||
* Vendor ID, Device ID, Device Density
|
||||
* @param Ctx Component object pointer
|
||||
* @param ID IDs pointer (2 * 8-bits value)
|
||||
* @param LatencyCode Latency used for the access
|
||||
* @retval error status
|
||||
*/
|
||||
int32_t APS256XX_ReadID(XSPI_HandleTypeDef *Ctx, uint8_t *ID, uint32_t LatencyCode)
|
||||
{
|
||||
/* Read the Mode Register 1 and 2 */
|
||||
if (APS256XX_ReadReg(Ctx, APS256XX_MR1_ADDRESS, ID, LatencyCode) != APS256XX_OK)
|
||||
{
|
||||
return APS256XX_ERROR;
|
||||
}
|
||||
|
||||
/* Keep only Vendor ID from Mode Register 1 */
|
||||
*ID &= (APS256XX_MR1_VENDOR_ID);
|
||||
|
||||
/* Keep only Device ID and Device Density from Mode Register 2 */
|
||||
*(ID + 1) &= (APS256XX_MR2_DEVICE_ID | APS256XX_MR2_DENSITY);
|
||||
|
||||
return APS256XX_OK;
|
||||
}
|
||||
|
||||
/* Power down Commands ********************************************************/
|
||||
/**
|
||||
* @brief Memory enter deep power-down command
|
||||
* @param Ctx Component object pointer
|
||||
* @retval error status
|
||||
*/
|
||||
int32_t APS256XX_EnterPowerDown(XSPI_HandleTypeDef *Ctx)
|
||||
{
|
||||
/* Update the deep power down value of the MR6 register */
|
||||
if (APS256XX_WriteReg(Ctx, APS256XX_MR6_ADDRESS, APS256XX_MR6_HS_HALF_SPEED_MODE) != APS256XX_OK)
|
||||
{
|
||||
return APS256XX_ERROR;
|
||||
}
|
||||
|
||||
/* --- Memory enter deep power down as soon nCS goes high --- */
|
||||
/* --- At least 500us should be respected before leaving deep power down --- */
|
||||
|
||||
return APS256XX_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Flash leave deep power-down command
|
||||
* @param Ctx Component object pointer
|
||||
* @param LatencyCode Latency used for the access
|
||||
* @retval error status
|
||||
*/
|
||||
int32_t APS256XX_LeavePowerDown(XSPI_HandleTypeDef *Ctx)
|
||||
{
|
||||
/* --- A dummy command is sent to the memory, as the nCS should be low for at least 60 ns --- */
|
||||
/* --- Memory takes 150us max to leave deep power down --- */
|
||||
|
||||
XSPI_RegularCmdTypeDef sCommand = {0};
|
||||
|
||||
/* Initialize the command */
|
||||
sCommand.OperationType = HAL_XSPI_OPTYPE_COMMON_CFG;
|
||||
sCommand.InstructionMode = HAL_XSPI_INSTRUCTION_8_LINES;
|
||||
sCommand.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS;
|
||||
sCommand.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE;
|
||||
sCommand.Instruction = APS256XX_READ_CMD;
|
||||
sCommand.AddressMode = HAL_XSPI_ADDRESS_8_LINES;
|
||||
sCommand.AddressWidth = HAL_XSPI_ADDRESS_32_BITS;
|
||||
sCommand.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_DISABLE;
|
||||
sCommand.Address = 0;
|
||||
sCommand.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE;
|
||||
sCommand.DataMode = HAL_XSPI_DATA_NONE;
|
||||
sCommand.DataLength = 0;
|
||||
sCommand.DummyCycles = 0;
|
||||
sCommand.DQSMode = HAL_XSPI_DQS_DISABLE;
|
||||
#if defined (XSPI_CCR_SIOO)
|
||||
sCommand.SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD;
|
||||
#endif
|
||||
|
||||
/* Configure the command */
|
||||
if (HAL_XSPI_Command(Ctx, &sCommand, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return APS256XX_ERROR;
|
||||
}
|
||||
|
||||
return APS256XX_OK;
|
||||
}
|
||||
|
||||
/* Reset Command **************************************************************/
|
||||
/**
|
||||
* @brief Reset the memory
|
||||
* @param Ctx Component object pointer
|
||||
* @retval error status
|
||||
*/
|
||||
int32_t APS256XX_Reset(XSPI_HandleTypeDef *Ctx)
|
||||
{
|
||||
XSPI_RegularCmdTypeDef sCommand = {0};
|
||||
|
||||
/* Initialize the command */
|
||||
sCommand.OperationType = HAL_XSPI_OPTYPE_COMMON_CFG;
|
||||
sCommand.InstructionMode = HAL_XSPI_INSTRUCTION_8_LINES;
|
||||
sCommand.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS;
|
||||
sCommand.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE;
|
||||
sCommand.Instruction = APS256XX_RESET_CMD;
|
||||
sCommand.AddressMode = HAL_XSPI_ADDRESS_8_LINES;
|
||||
sCommand.AddressWidth = HAL_XSPI_ADDRESS_24_BITS;
|
||||
sCommand.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_DISABLE;
|
||||
sCommand.Address = 0;
|
||||
sCommand.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE;
|
||||
sCommand.DataMode = HAL_XSPI_DATA_NONE;
|
||||
sCommand.DataLength = 0;
|
||||
sCommand.DummyCycles = 0;
|
||||
sCommand.DQSMode = HAL_XSPI_DQS_DISABLE;
|
||||
#if defined (XSPI_CCR_SIOO)
|
||||
sCommand.SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD;
|
||||
#endif
|
||||
|
||||
/* Configure the command */
|
||||
if (HAL_XSPI_Command(Ctx, &sCommand, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return APS256XX_ERROR;
|
||||
}
|
||||
|
||||
/* Need to wait tRST */
|
||||
HAL_Delay(1);
|
||||
return 0/*APS256XX_OK*/;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -0,0 +1,287 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file aps256xx.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains all the description of the APS256XX 16bits-HSPI PSRAM memory.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef APS256XX_H
|
||||
#define APS256XX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "aps256xx_conf.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Components
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup APS256XX
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup APS256XX_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup APS256XX_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief APS256XX Configuration
|
||||
*/
|
||||
#define APS256XX_RAM_SIZE 0x2000000U /* 256 MBits => 32 MBytes */
|
||||
|
||||
/**
|
||||
* @brief APS256XX Error codes
|
||||
*/
|
||||
#define APS256XX_OK (0)
|
||||
#define APS256XX_ERROR (-1)
|
||||
|
||||
/******************************************************************************
|
||||
* @brief APS256XX Registers
|
||||
****************************************************************************/
|
||||
/* Mode Register 0 */
|
||||
#define APS256XX_MR0_ADDRESS 0x00000000U
|
||||
|
||||
#define APS256XX_MR0_DRIVE_STRENGTH 0x03U /*!< Drive Strength */
|
||||
#define APS256XX_MR0_DS_FULL 0x00U /*!< Drive Strength : Full (25 Ohm) */
|
||||
#define APS256XX_MR0_DS_HALF 0x01U /*!< Drive Strength : Half (50 Ohm) */
|
||||
#define APS256XX_MR0_DS_QUART 0x02U /*!< Drive Strength : 1/4 (100 Ohm) */
|
||||
#define APS256XX_MR0_DS_EIGHT 0x03U /*!< Drive Strength : 1/8 (200 Ohm) */
|
||||
|
||||
#define APS256XX_MR0_READ_LATENCY_CODE 0x1CU /*!< Read Latency Code */
|
||||
#define APS256XX_MR0_RLC_3 0x00U /*!< Read Latency Code : 3 */
|
||||
#define APS256XX_MR0_RLC_4 0x04U /*!< Read Latency Code : 4 */
|
||||
#define APS256XX_MR0_RLC_5 0x08U /*!< Read Latency Code : 5 */
|
||||
#define APS256XX_MR0_RLC_6 0x0CU /*!< Read Latency Code : 6 */
|
||||
#define APS256XX_MR0_RLC_7 0x10U /*!< Read Latency Code : 7 */
|
||||
|
||||
#define APS256XX_MR0_LATENCY_TYPE 0x20U /*!< Latency Type */
|
||||
|
||||
/* Mode Register 1 */
|
||||
#define APS256XX_MR1_ADDRESS 0x00000001U
|
||||
|
||||
#define APS256XX_MR1_VENDOR_ID 0x1FU /*!< Vendor Identifier */
|
||||
#define APS256XX_MR1_VENDOR_ID_APM 0x0DU /*!< Vendor Identifier : APM */
|
||||
|
||||
#define APS256XX_MR1_ULP 0x80U /*!< Ultra Low Power Device */
|
||||
|
||||
/* Mode Register 2 */
|
||||
#define APS256XX_MR2_ADDRESS 0x00000002U
|
||||
|
||||
#define APS256XX_MR2_DENSITY 0x07U /*!< Device Density */
|
||||
#define APS256XX_MR2_DENSITY_128_MB 0x05U /*!< Device Density : 128 Mb */
|
||||
#define APS256XX_MR2_DENSITY_256_MB 0x07U /*!< Device Density : 256 Mb */
|
||||
#define APS256XX_MR2_DENSITY_512_MB 0x06U /*!< Device Density : 512 Mb */
|
||||
|
||||
#define APS256XX_MR2_DEVICE_ID 0x18U /*!< Device Identifier */
|
||||
#define APS256XX_MR2_DEVID_GEN_1 0x00U /*!< Device Identifier : Generation 1 */
|
||||
#define APS256XX_MR2_DEVID_GEN_2 0x08U /*!< Device Identifier : Generation 2 */
|
||||
#define APS256XX_MR2_DEVID_GEN_3 0x10U /*!< Device Identifier : Generation 3 */
|
||||
#define APS256XX_MR2_DEVID_GEN_4 0x18U /*!< Device Identifier : Generation 4 */
|
||||
|
||||
#define APS256XX_MR2_KGD 0xE0U /*!< Good-Die Identifier */
|
||||
#define APS256XX_MR2_KGD_GOOD_DIE_ID 0xC0U /*!< Good-Die Identifier : PASS */
|
||||
|
||||
/* Mode Register 3 */
|
||||
#define APS256XX_MR3_ADDRESS 0x00000003U
|
||||
|
||||
#define APS256XX_MR3_SRF 0x30U /*!< Self Refresh Flag */
|
||||
#define APS256XX_MR3_SRF_0_5X 0x10U /*!< Self Refresh Flag : 0.5x Refresh */
|
||||
#define APS256XX_MR3_SRF_1X 0x00U /*!< Self Refresh Flag : 1x Refresh */
|
||||
#define APS256XX_MR3_SRF_4X 0x20U /*!< Self Refresh Flag : 4x Refresh */
|
||||
|
||||
#define APS256XX_MR3_RBXEN 0x80U /*!< Row Boundary Crossing Enable */
|
||||
|
||||
/* Mode Register 4 */
|
||||
#define APS256XX_MR4_ADDRESS 0x00000004U
|
||||
|
||||
#define APS256XX_MR4_PASR 0x07U /*!< Partially Address Space Refresh */
|
||||
#define APS256XX_MR4_PASR_FULL 0x00U /*!< PASR : Full Array */
|
||||
#define APS256XX_MR4_PASR_BOTTOM_HALF 0x01U /*!< PASR : Bottom 1/2 Array */
|
||||
#define APS256XX_MR4_PASR_BOTTOM_QUART 0x02U /*!< PASR : Bottom 1/4 Array */
|
||||
#define APS256XX_MR4_PASR_BOTTOM_EIGHT 0x03U /*!< PASR : Bottom 1/8 Array */
|
||||
#define APS256XX_MR4_PASR_NONE 0x04U /*!< PASR : None */
|
||||
#define APS256XX_MR4_PASR_TOP_HALF 0x05U /*!< PASR : Top 1/2 Array */
|
||||
#define APS256XX_MR4_PASR_TOP_QUART 0x06U /*!< PASR : Top 1/4 Array */
|
||||
#define APS256XX_MR4_PASR_TOP_EIGHT 0x07U /*!< PASR : Top 1/8 Array */
|
||||
|
||||
#define APS256XX_MR4_RF_RATE 0x18U /*!< Refresh Frequency Setting */
|
||||
#define APS256XX_MR4_RF_4X 0x00U /*!< RF : Always 4x Refresh */
|
||||
#define APS256XX_MR4_RF_1X 0x08U /*!< RF : Enables 1x Refresh */
|
||||
#define APS256XX_MR4_RF_0_5X 0x18U /*!< RF : Enables 0.5x Refresh */
|
||||
|
||||
#define APS256XX_MR4_WRITE_LATENCY_CODE 0xE0U /*!< Write Latency Code */
|
||||
#define APS256XX_MR4_WLC_3 0x00U /*!< Write Latency Code : 3 */
|
||||
#define APS256XX_MR4_WLC_4 0x80U /*!< Write Latency Code : 4 */
|
||||
#define APS256XX_MR4_WLC_5 0x40U /*!< Write Latency Code : 5 */
|
||||
#define APS256XX_MR4_WLC_6 0xC0U /*!< Write Latency Code : 6 */
|
||||
#define APS256XX_MR4_WLC_7 0x20U /*!< Write Latency Code : 7 */
|
||||
|
||||
/* Mode Register 6 */
|
||||
#define APS256XX_MR6_ADDRESS 0x00000006U
|
||||
|
||||
#define APS256XX_MR6_HALF_SLEEP 0xF0U /*!< Half Sleep */
|
||||
#define APS256XX_MR6_HS_HALF_SPEED_MODE 0xF0U /*!< Half Sleep : Half Speed Mode */
|
||||
#define APS256XX_MR6_HS_DEEP_POWER_DOWN 0xC0U /*!< Half Sleep : Deep Power Down Mode */
|
||||
|
||||
/* Mode Register 8 */
|
||||
#define APS256XX_MR8_ADDRESS 0x00000008U
|
||||
|
||||
#define APS256XX_MR8_BL 0x03U /*!< Burst Length */
|
||||
#define APS256XX_MR8_BL_16_BYTES 0x00U /*!< Burst Length : 16 Byte/Word Wrap */
|
||||
#define APS256XX_MR8_BL_32_BYTES 0x01U /*!< Burst Length : 32 Byte/Word Wrap */
|
||||
#define APS256XX_MR8_BL_64_BYTES 0x02U /*!< Burst Length : 64 Byte/Word Wrap */
|
||||
#define APS256XX_MR8_BL_2K_BYTES 0x03U /*!< Burst Length : 2K Byte/1K Word Wrap */
|
||||
|
||||
#define APS256XX_MR8_BT 0x04U /*!< Burst Type */
|
||||
|
||||
#define APS256XX_MR8_RBX 0x08U /*!< Row Boundary Crossing Read Enable */
|
||||
|
||||
#define APS256XX_MR8_X8_X16 0x40U /*!< IO X8/X16 Mode */
|
||||
|
||||
/******************************************************************************
|
||||
* @brief APS256XX Commands
|
||||
****************************************************************************/
|
||||
/* Read Operations */
|
||||
#define APS256XX_READ_CMD 0x00U /*!< Synchronous Read */
|
||||
#define APS256XX_READ_LINEAR_BURST_CMD 0x20U /*!< Linear Burst Read */
|
||||
|
||||
/* Write Operations */
|
||||
#define APS256XX_WRITE_CMD 0x80U /*!< Synchronous Write */
|
||||
#define APS256XX_WRITE_LINEAR_BURST_CMD 0xA0U /*!< Linear Burst Write */
|
||||
|
||||
/* Reset Operations */
|
||||
#define APS256XX_RESET_CMD 0xFFU /*!< Global Reset */
|
||||
|
||||
/* Register Operations */
|
||||
#define APS256XX_READ_REG_CMD 0x40U /*!< Mode Register Read */
|
||||
#define APS256XX_WRITE_REG_CMD 0xC0U /*!< Mode Register Write */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup APS256XX_Exported_Types APS256XX Exported Types
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
APS256XX_BURST_16_BYTES = APS256XX_MR8_BL_16_BYTES,
|
||||
APS256XX_BURST_32_BYTES = APS256XX_MR8_BL_32_BYTES,
|
||||
APS256XX_BURST_64_BYTES = APS256XX_MR8_BL_64_BYTES,
|
||||
APS256XX_BURST_2_KBYTES = APS256XX_MR8_BL_2K_BYTES
|
||||
} APS256XX_BurstLength_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
APS256XX_READ_LATENCY_3 = APS256XX_MR0_RLC_3,
|
||||
APS256XX_READ_LATENCY_4 = APS256XX_MR0_RLC_4,
|
||||
APS256XX_READ_LATENCY_5 = APS256XX_MR0_RLC_5,
|
||||
APS256XX_READ_LATENCY_6 = APS256XX_MR0_RLC_6,
|
||||
APS256XX_READ_LATENCY_7 = APS256XX_MR0_RLC_7
|
||||
} APS256XX_ReadLatencyCode_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
APS256XX_WRITE_LATENCY_3 = APS256XX_MR4_WLC_3,
|
||||
APS256XX_WRITE_LATENCY_4 = APS256XX_MR4_WLC_4,
|
||||
APS256XX_WRITE_LATENCY_5 = APS256XX_MR4_WLC_5,
|
||||
APS256XX_WRITE_LATENCY_6 = APS256XX_MR4_WLC_6,
|
||||
APS256XX_WRITE_LATENCY_7 = APS256XX_MR4_WLC_7
|
||||
} APS256XX_WriteLatencyCode_t;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup APS256XX_Exported_Macros APS256XX Exported Macros
|
||||
* @{
|
||||
*/
|
||||
#define APS256XX_READ_REG_LATENCY(rlc) ((((rlc) & APS256XX_MR0_READ_LATENCY_CODE) >> 2U) + 3U)
|
||||
|
||||
#define APS256XX_READ_LATENCY(rlc, type) ((((type) & APS256XX_MR0_LATENCY_TYPE) == 0U) ? \
|
||||
((((rlc) & APS256XX_MR0_READ_LATENCY_CODE) >> 2U) + 3U) : \
|
||||
(((((rlc) & APS256XX_MR0_READ_LATENCY_CODE) >> 2U) + 3U)*2U))
|
||||
|
||||
#define APS256XX_WRITE_LATENCY(wlc) ((((wlc) & APS256XX_MR4_WRITE_LATENCY_CODE) == 0U) ? 3U : \
|
||||
((((wlc) & APS256XX_MR4_WLC_7) != 0U) ? 7U : \
|
||||
((((wlc) & APS256XX_MR4_WLC_5) == 0U) ? 4U : \
|
||||
((((wlc) & APS256XX_MR4_WLC_4) == 0U) ? 5U : 6U))))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup APS256XX_Exported_Functions APS256XX Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/* Read/Write Array Commands **************************************************/
|
||||
int32_t APS256XX_Read(XSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t ReadAddr, uint32_t Size, uint32_t LatencyCode,
|
||||
uint32_t IOMode, uint32_t BurstType);
|
||||
int32_t APS256XX_Read_DMA(XSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t ReadAddr, uint32_t Size,
|
||||
uint32_t LatencyCode, uint32_t IOMode, uint32_t BurstType);
|
||||
int32_t APS256XX_Write(XSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t WriteAddr, uint32_t Size, uint32_t LatencyCode,
|
||||
uint32_t IOMode, uint32_t BurstType);
|
||||
int32_t APS256XX_Write_DMA(XSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t WriteAddr, uint32_t Size,
|
||||
uint32_t LatencyCode, uint32_t IOMode, uint32_t BurstType);
|
||||
int32_t APS256XX_EnableMemoryMappedMode(XSPI_HandleTypeDef *Ctx, uint32_t ReadLatencyCode, uint32_t WriteLatencyCode,
|
||||
uint32_t IOMode, uint32_t BurstType);
|
||||
|
||||
/* Register/Setting Commands **************************************************/
|
||||
int32_t APS256XX_ReadReg(XSPI_HandleTypeDef *Ctx, uint32_t Address, uint8_t *Value, uint32_t LatencyCode);
|
||||
int32_t APS256XX_WriteReg(XSPI_HandleTypeDef *Ctx, uint32_t Address, uint8_t Value);
|
||||
|
||||
/* ID Commands ****************************************************************/
|
||||
int32_t APS256XX_ReadID(XSPI_HandleTypeDef *Ctx, uint8_t *ID, uint32_t LatencyCode);
|
||||
|
||||
/* Power down Commands ********************************************************/
|
||||
int32_t APS256XX_EnterPowerDown(XSPI_HandleTypeDef *Ctx);
|
||||
int32_t APS256XX_LeavePowerDown(XSPI_HandleTypeDef *Ctx);
|
||||
|
||||
/* Reset Command **************************************************************/
|
||||
int32_t APS256XX_Reset(XSPI_HandleTypeDef *Ctx);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* APS256XX_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -0,0 +1,49 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file aps256xx_conf.h
|
||||
* @author MCD Application Team
|
||||
* @brief APS256XX 16bits-OSPI PSRAM memory configuration template file.
|
||||
* This file should be copied to the application folder and renamed
|
||||
* to aps256xx_conf.h
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef APS256XX_CONF_H
|
||||
#define APS256XX_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32xxxx_hal.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
#define CONF_HSPI_DS APS256XX_MR0_DS_HALF
|
||||
#define CONF_HSPI_PASR APS256XX_MR4_PASR_FULL
|
||||
#define CONF_HSPI_RF APS256XX_MR4_RF_4X
|
||||
|
||||
#define DEFAULT_READ_LATENCY_CODE APS256XX_READ_LATENCY_5
|
||||
#define DEFAULT_WRITE_LATENCY_CODE APS256XX_WRITE_LATENCY_5
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* APS256XX_CONF_H */
|
||||
Reference in new issue
Block a user