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Thomas Laduguie committed 2026-09-04 09:57:30 +02:00
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Drivers/STM32H7RSxx_HAL_Driver/.DS_Store
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Drivers/STM32H7RSxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
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Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal.h
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/**
******************************************************************************
* @file stm32h7rsxx_hal.h
* @author MCD Application Team
* @brief This file contains all the functions prototypes for the HAL
* module driver.
*
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7RSxx_HAL_H
#define STM32H7RSxx_HAL_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal_conf.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @addtogroup HAL
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup HAL_TICK_FREQ Tick Frequency
* @{
*/
/**
* @brief HAL Tick frequency
*/
typedef enum
{
HAL_TICK_FREQ_10HZ = 100U,
HAL_TICK_FREQ_100HZ = 10U,
HAL_TICK_FREQ_1KHZ = 1U,
HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
} HAL_TickFreqTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup REV_ID device revision ID
* @{
*/
#define REV_ID_A 0x1003U /*!< STM32H7Rx/Sx rev.A */
#define REV_ID_B 0x2000U /*!< STM32H7Rx/Sx rev.B */
/**
* @}
*/
/** @defgroup HAL_Exported_Constants HAL Exported Constants
* @{
*/
/**
* @brief STM32H7RSxx HAL Driver version number
*/
#define STM32H7RSXX_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */
#define STM32H7RSXX_HAL_VERSION_SUB1 (0x02UL) /*!< [23:16] sub1 version */
#define STM32H7RSXX_HAL_VERSION_SUB2 (0x01UL) /*!< [15:8] sub2 version */
#define STM32H7RSXX_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */
#define STM32H7RSXX_HAL_VERSION ((STM32H7RSXX_HAL_VERSION_MAIN << 24U)\
|(STM32H7RSXX_HAL_VERSION_SUB1 << 16U)\
|(STM32H7RSXX_HAL_VERSION_SUB2 << 8U)\
|(STM32H7RSXX_HAL_VERSION_RC))
/**
* @}
*/
/** @defgroup SBS_Exported_Constants SBS Exported Constants
* @{
*/
/** @defgroup SBS_HDPL_Value HDPL Value
* @{
*/
#define SBS_HDPL_VALUE_0 0x000000B4U /*!< Hide protection level 0 */
#define SBS_HDPL_VALUE_1 0x00000051U /*!< Hide protection level 1 */
#define SBS_HDPL_VALUE_2 0x0000008AU /*!< Hide protection level 2 */
#define SBS_HDPL_VALUE_3 0x0000006FU /*!< Hide protection level 3 */
/**
* @}
*/
/** @defgroup SBS_Timer_Break_Inputs Timer Break Inputs
* @{
*/
#define SBS_TIMER_BREAK_LOCK_PVD SBS_BKLOCKR_PVD_BL /*!< PVD break lock */
#define SBS_TIMER_BREAK_LOCK_FLASH SBS_BKLOCKR_FLASHECC_BL /*!< FLASH ECC error break lock */
#define SBS_TIMER_BREAK_LOCK_CORE SBS_BKLOCKR_CM7LCKUP_BL /*!< Cortex-M7 lockup break lock */
#define SBS_TIMER_BREAK_LOCK_BKPRAM SBS_BKLOCKR_BKRAMECC_BL /*!< Backup RAM ECC error break lock */
#define SBS_TIMER_BREAK_LOCK_DTCM SBS_BKLOCKR_DTCMECC_BL /*!< DTCM ECC error break lock */
#define SBS_TIMER_BREAK_LOCK_ITCM SBS_BKLOCKR_ITCMECC_BL /*!< ITCM ECC error break lock */
#define SBS_TIMER_BREAK_LOCK_AXISRAM3 SBS_BKLOCKR_ARAM3ECC_BL /*!< AXISRAM3 ECC error break lock */
#define SBS_TIMER_BREAK_LOCK_AXISRAM1 SBS_BKLOCKR_ARAM1ECC_BL /*!< AXISRAM1 ECC error break lock */
/**
* @}
*/
/** @defgroup SBS_FPU_Interrupts FPU Interrupts
* @{
*/
#define SBS_IT_FPU_IOC SBS_FPUIMR_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */
#define SBS_IT_FPU_DZC SBS_FPUIMR_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */
#define SBS_IT_FPU_UFC SBS_FPUIMR_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */
#define SBS_IT_FPU_OFC SBS_FPUIMR_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */
#define SBS_IT_FPU_IDC SBS_FPUIMR_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */
#define SBS_IT_FPU_IXC SBS_FPUIMR_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */
/**
* @}
*/
/** @defgroup SBS_Compensation_Cell_Selection Compensation Cell Selection
* @{
*/
#define SBS_IO_ANALOG_CELL SBS_CCCSR_COMP_EN /*!< Compensation cell for the I/O analog switches */
#define SBS_IO_XSPI1_CELL SBS_CCCSR_XSPI1_COMP_EN /*!< Compensation cell for the I/O of the XSPI1 */
#define SBS_IO_XSPI2_CELL SBS_CCCSR_XSPI2_COMP_EN /*!< Compensation cell for the I/O of the XSPI2 */
/**
* @}
*/
/** @defgroup SBS_Compensation_Cell_Ready_Selection Compensation Cell Ready Selection
* @{
*/
#define SBS_IO_ANALOG_CELL_READY SBS_CCCSR_COMP_RDY /*!< Ready flag of compensation cell for the I/O analog switches */
#define SBS_IO_XSPI1_CELL_READY SBS_CCCSR_XSPI1_COMP_RDY /*!< Ready flag of compensation cell for the I/O of the XSPI1 */
#define SBS_IO_XSPI2_CELL_READY SBS_CCCSR_XSPI2_COMP_RDY /*!< Ready flag of compensation cell for the I/O of the XSPI2 */
/**
* @}
*/
/** @defgroup SBS_IO_Compensation_Code_Config IO Compensation Code config
* @{
*/
#define SBS_IO_CELL_CODE 0UL /*!< Code from the cell */
#define SBS_IO_REGISTER_CODE 1UL /*!< Code from the values in the cell code register */
/**
* @}
*/
/** @defgroup SBS_IO_HSLV_Selection IO High Speed at Low Voltage Selection
* @{
*/
#define SBS_IO_ANALOG_HSLV SBS_CCCSR_IOHSLV /*!< High speed at low voltage for the I/O analog switches */
#define SBS_IO_XSPI1_HSLV SBS_CCCSR_XSPI1_IOHSLV /*!< High speed at low voltage for the I/O of the XSPI1 */
#define SBS_IO_XSPI2_HSLV SBS_CCCSR_XSPI2_IOHSLV /*!< High speed at low voltage for the I/O of the XSPI2 */
/**
* @}
*/
/** @defgroup SBS_Ethernet_PHY_Config Ethernet PHY config
* @{
*/
#define SBS_ETHERNET_PHY_GMII_OR_MII 0U /*!< GMII or MII */
#define SBS_ETHERNET_PHY_RMII SBS_PMCR_ETH_PHYSEL_2 /*!< RMII */
/**
* @}
*/
/** @defgroup SBS_ECC_AXISRAM_WS_Config ECC AXISRAMs Wait State when ECC=0 config
* @{
*/
#define SBS_AXISRAM_WS_0 0U /*!< 0 Wait state */
#define SBS_AXISRAM_WS_1 SBS_PMCR_AXISRAM_WS /*!< 1 Wait state */
/**
* @}
*/
/** @defgroup SBS_EXTI_Port EXTI Port configuration
* @{
*/
#define SBS_EXTI_PIN_PORTA 0x00UL /*!< Port A pin input of EXTI event detection */
#define SBS_EXTI_PIN_PORTB 0x01UL /*!< Port B pin input of EXTI event detection */
#define SBS_EXTI_PIN_PORTC 0x02UL /*!< Port C pin input of EXTI event detection */
#define SBS_EXTI_PIN_PORTD 0x03UL /*!< Port D pin input of EXTI event detection */
#define SBS_EXTI_PIN_PORTE 0x04UL /*!< Port E pin input of EXTI event detection */
#define SBS_EXTI_PIN_PORTF 0x05UL /*!< Port F pin input of EXTI event detection */
#define SBS_EXTI_PIN_PORTG 0x06UL /*!< Port G pin input of EXTI event detection */
#define SBS_EXTI_PIN_PORTH 0x07UL /*!< Port H pin input of EXTI event detection */
#define SBS_EXTI_PIN_PORTM 0x0CUL /*!< Port M pin input of EXTI event detection */
#define SBS_EXTI_PIN_PORTN 0x0DUL /*!< Port N pin input of EXTI event detection */
#define SBS_EXTI_PIN_PORTO 0x0EUL /*!< Port O pin input of EXTI event detection */
#define SBS_EXTI_PIN_PORTP 0x0FUL /*!< Port P pin input of EXTI event detection */
/**
* @}
*/
/** @defgroup AXIM_Exported_Constants AXIM Exported Constants
* @{
*/
/** @defgroup AXIM_ASIB_READ_ISSUING_CAP AXIM ASIBs Read Issuing Capability
* @{
*/
#define AXIM_ASIB_READ_ISS_NORMAL 0U /*!< Normal issuing capability */
#define AXIM_ASIB_READ_ISS_FORCE_TO_1 AXIM_ASIB_FNMOD_READ_ISS /*!< Force issuing capability to 1 */
/**
* @}
*/
/** @defgroup AXIM_ASIB_WRITE_ISSUING_CAP AXIM ASIBs Write Issuing Capability
* @{
*/
#define AXIM_ASIB_WRITE_ISS_NORMAL 0U /*!< Normal issuing capability */
#define AXIM_ASIB_WRITE_ISS_FORCE_TO_1 AXIM_ASIB_FNMOD_WRITE_ISS /*!< Force issuing capability to 1 */
/**
* @}
*/
/** @defgroup AXIM_AMIB_READ_ISSUING_CAP AXIM AMIBs Read Issuing Capability
* @{
*/
#define AXIM_AMIB_READ_ISS_NORMAL 0U /*!< Normal issuing capability */
#define AXIM_AMIB_READ_ISS_FORCE_TO_1 AXIM_AMIB_FNMOD_READ_ISS /*!< Force issuing capability to 1 */
/**
* @}
*/
/** @defgroup AXIM_AMIB_WRITE_ISSUING_CAP AXIM AMIBs Write Issuing Capability
* @{
*/
#define AXIM_AMIB_WRITE_ISS_NORMAL 0U /*!< Normal issuing capability */
#define AXIM_AMIB_WRITE_ISS_FORCE_TO_1 AXIM_AMIB_FNMOD_WRITE_ISS /*!< Force issuing capability to 1 */
/**
* @}
*/
/** @defgroup AXIM_AMIB_READ_ISSUING_BM_CAP AXIM AMIBs Read Issuing Bus Matrix Capability
* @{
*/
#define AXIM_AMIB_READ_ISS_BM_NORMAL 0U /*!< Normal issuing capability */
#define AXIM_AMIB_READ_ISS_BM_FORCE_TO_1 AXIM_AMIB_FNMOD_READ_ISS /*!< Force issuing capability to 1 */
/**
* @}
*/
/** @defgroup AXIM_AMIB_WRITE_ISSUING_BM_CAP AXIM AMIBs Write Issuing Bus Matrix Capability
* @{
*/
#define AXIM_AMIB_WRITE_ISS_BM_NORMAL 0U /*!< Normal issuing capability */
#define AXIM_AMIB_WRITE_ISS_BM_FORCE_TO_1 AXIM_AMIB_FNMOD_WRITE_ISS /*!< Force issuing capability to 1 */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
* @{
*/
/** @brief Freeze/Unfreeze Peripherals in Debug mode
*/
#define __HAL_DBGMCU_FREEZE_GPDMA0() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_0)
#define __HAL_DBGMCU_UNFREEZE_GPDMA0() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_0)
#define __HAL_DBGMCU_FREEZE_GPDMA1() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_1)
#define __HAL_DBGMCU_UNFREEZE_GPDMA1() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_1)
#define __HAL_DBGMCU_FREEZE_GPDMA2() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_2)
#define __HAL_DBGMCU_UNFREEZE_GPDMA2() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_2)
#define __HAL_DBGMCU_FREEZE_GPDMA3() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_3)
#define __HAL_DBGMCU_UNFREEZE_GPDMA3() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_3)
#define __HAL_DBGMCU_FREEZE_GPDMA4() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_4)
#define __HAL_DBGMCU_UNFREEZE_GPDMA4() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_4)
#define __HAL_DBGMCU_FREEZE_GPDMA5() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_5)
#define __HAL_DBGMCU_UNFREEZE_GPDMA5() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_5)
#define __HAL_DBGMCU_FREEZE_GPDMA6() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_6)
#define __HAL_DBGMCU_UNFREEZE_GPDMA6() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_6)
#define __HAL_DBGMCU_FREEZE_GPDMA7() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_7)
#define __HAL_DBGMCU_UNFREEZE_GPDMA7() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_7)
#define __HAL_DBGMCU_FREEZE_GPDMA8() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_8)
#define __HAL_DBGMCU_UNFREEZE_GPDMA8() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_8)
#define __HAL_DBGMCU_FREEZE_GPDMA9() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_9)
#define __HAL_DBGMCU_UNFREEZE_GPDMA9() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_9)
#define __HAL_DBGMCU_FREEZE_GPDMA10() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_10)
#define __HAL_DBGMCU_UNFREEZE_GPDMA10() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_10)
#define __HAL_DBGMCU_FREEZE_GPDMA11() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_11)
#define __HAL_DBGMCU_UNFREEZE_GPDMA11() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_11)
#define __HAL_DBGMCU_FREEZE_GPDMA12() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_12)
#define __HAL_DBGMCU_UNFREEZE_GPDMA12() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_12)
#define __HAL_DBGMCU_FREEZE_GPDMA13() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_13)
#define __HAL_DBGMCU_UNFREEZE_GPDMA13() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_13)
#define __HAL_DBGMCU_FREEZE_GPDMA14() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_14)
#define __HAL_DBGMCU_UNFREEZE_GPDMA14() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_14)
#define __HAL_DBGMCU_FREEZE_GPDMA15() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_15)
#define __HAL_DBGMCU_UNFREEZE_GPDMA15() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_15)
#define __HAL_DBGMCU_FREEZE_HPDMA0() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_0)
#define __HAL_DBGMCU_UNFREEZE_HPDMA0() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_0)
#define __HAL_DBGMCU_FREEZE_HPDMA1() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_1)
#define __HAL_DBGMCU_UNFREEZE_HPDMA1() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_1)
#define __HAL_DBGMCU_FREEZE_HPDMA2() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_2)
#define __HAL_DBGMCU_UNFREEZE_HPDMA2() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_2)
#define __HAL_DBGMCU_FREEZE_HPDMA3() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_3)
#define __HAL_DBGMCU_UNFREEZE_HPDMA3() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_3)
#define __HAL_DBGMCU_FREEZE_HPDMA4() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_4)
#define __HAL_DBGMCU_UNFREEZE_HPDMA4() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_4)
#define __HAL_DBGMCU_FREEZE_HPDMA5() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_5)
#define __HAL_DBGMCU_UNFREEZE_HPDMA5() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_5)
#define __HAL_DBGMCU_FREEZE_HPDMA6() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_6)
#define __HAL_DBGMCU_UNFREEZE_HPDMA6() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_6)
#define __HAL_DBGMCU_FREEZE_HPDMA7() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_7)
#define __HAL_DBGMCU_UNFREEZE_HPDMA7() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_7)
#define __HAL_DBGMCU_FREEZE_HPDMA8() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_8)
#define __HAL_DBGMCU_UNFREEZE_HPDMA8() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_8)
#define __HAL_DBGMCU_FREEZE_HPDMA9() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_9)
#define __HAL_DBGMCU_UNFREEZE_HPDMA9() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_9)
#define __HAL_DBGMCU_FREEZE_HPDMA10() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_10)
#define __HAL_DBGMCU_UNFREEZE_HPDMA10() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_10)
#define __HAL_DBGMCU_FREEZE_HPDMA11() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_11)
#define __HAL_DBGMCU_UNFREEZE_HPDMA11() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_11)
#define __HAL_DBGMCU_FREEZE_HPDMA12() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_12)
#define __HAL_DBGMCU_UNFREEZE_HPDMA12() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_12)
#define __HAL_DBGMCU_FREEZE_HPDMA13() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_13)
#define __HAL_DBGMCU_UNFREEZE_HPDMA13() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_13)
#define __HAL_DBGMCU_FREEZE_HPDMA14() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_14)
#define __HAL_DBGMCU_UNFREEZE_HPDMA14() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_14)
#define __HAL_DBGMCU_FREEZE_HPDMA15() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_15)
#define __HAL_DBGMCU_UNFREEZE_HPDMA15() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_15)
#define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_I2C1)
#define __HAL_DBGMCU_UNFREEZE_I2C1() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_I2C1)
#define __HAL_DBGMCU_FREEZE_I2C2() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_I2C2)
#define __HAL_DBGMCU_UNFREEZE_I2C2() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_I2C2)
#define __HAL_DBGMCU_FREEZE_I2C3() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_I2C3)
#define __HAL_DBGMCU_UNFREEZE_I2C3() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_I2C3)
#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM2)
#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM2)
#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM3)
#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM3)
#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM4)
#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM4)
#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM5)
#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM5)
#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM6)
#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM6)
#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM7)
#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM7)
#define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM9)
#define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM9)
#define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM12)
#define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM12)
#define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM13)
#define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM13)
#define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM14)
#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM14)
#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM1)
#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM1)
#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM15)
#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM15)
#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM16)
#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM16)
#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM17)
#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM17)
#define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_LPTIM1)
#define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_LPTIM1)
#define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_LPTIM2)
#define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_LPTIM2)
#define __HAL_DBGMCU_FREEZE_LPTIM3() SET_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_LPTIM3)
#define __HAL_DBGMCU_UNFREEZE_LPTIM3() CLEAR_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_LPTIM3)
#define __HAL_DBGMCU_FREEZE_LPTIM4() SET_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_LPTIM4)
#define __HAL_DBGMCU_UNFREEZE_LPTIM4() CLEAR_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_LPTIM4)
#define __HAL_DBGMCU_FREEZE_LPTIM5() SET_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_LPTIM5)
#define __HAL_DBGMCU_UNFREEZE_LPTIM5() CLEAR_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_LPTIM5)
#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_IWDG)
#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_IWDG)
#define __HAL_DBGMCU_FREEZE_PWM1() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_PWM1)
#define __HAL_DBGMCU_UNFREEZE_PWM1() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_PWM1)
#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_RTC)
#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_RTC)
#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_WWDG)
#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_WWDG)
/**
* @}
*/
/** @defgroup SBS_Exported_Macros SBS Exported Macros
* @{
*/
/** @brief Floating Point Unit interrupt enable/disable macros
* @param __INTERRUPT__ This parameter can be a value of @ref SBS_FPU_Interrupts
*/
#define __HAL_SBS_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do { \
assert_param(IS_SBS_FPU_INTERRUPT((__INTERRUPT__))); \
SET_BIT(SBS->FPUIMR, (__INTERRUPT__)); \
} while(0)
#define __HAL_SBS_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do { \
assert_param(IS_SBS_FPU_INTERRUPT((__INTERRUPT__))); \
CLEAR_BIT(SBS->FPUIMR, (__INTERRUPT__)); \
} while(0)
/** @brief Check SBS Memories Erase Status Flags.
* @retval The state of memory erase.
*/
#define __HAL_SBS_GET_MEMORIES_ERASE_STATUS() ((SBS->MESR) & (SBS_MESR_MEF))
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup VREFBUF_VoltageScale VREFBUF Voltage Scale
* @{
*/
#define VREFBUF_VOLTAGE_SCALE0 VREFBUF_CSR_VRS_OUT1 /*!< Voltage reference scale 0 (VREF_OUT1) */
#define VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_OUT2 /*!< Voltage reference scale 1 (VREF_OUT2) */
#define VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_OUT3 /*!< Voltage reference scale 2 (VREF_OUT3) */
#define VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_OUT4 /*!< Voltage reference scale 3 (VREF_OUT4) */
#define IS_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == VREFBUF_VOLTAGE_SCALE0) || \
((__SCALE__) == VREFBUF_VOLTAGE_SCALE1) || \
((__SCALE__) == VREFBUF_VOLTAGE_SCALE2) || \
((__SCALE__) == VREFBUF_VOLTAGE_SCALE3))
/**
* @}
*/
/** @defgroup VREFBUF_HighImpedance VREFBUF High Impedance
* @{
*/
#define VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
#define VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */
#define IS_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
((__VALUE__) == VREFBUF_HIGH_IMPEDANCE_ENABLE))
#define IS_VREFBUF_TRIMMING(__VALUE__) ((__VALUE__) <= VREFBUF_CCR_TRIM)
/**
* @}
*/
/** @defgroup FMC_SwapBankMapping_Config FMC SwapBankMapping Config
* @{
*/
#define FMC_SWAPBANK_MODE0 (0x00000000U) /*!< FMC memory default mapping is used */
#define FMC_SWAPBANK_MODE1 FMC_BCR1_BMAP_0 /*!< FMC SDRAM bank1 and NOR/SRAM/PSRAM bank are swapped */
#define IS_FMC_SWAPBANK_MODE(__MODE__) (((__MODE__) == FMC_SWAPBANK_MODE0) || \
((__MODE__) == FMC_SWAPBANK_MODE1))
/**
* @}
*/
/** @addtogroup SBS_Private_Macros
* @{
*/
#define IS_SBS_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SBS_IT_FPU_IOC) == SBS_IT_FPU_IOC) || \
(((__INTERRUPT__) & SBS_IT_FPU_DZC) == SBS_IT_FPU_DZC) || \
(((__INTERRUPT__) & SBS_IT_FPU_UFC) == SBS_IT_FPU_UFC) || \
(((__INTERRUPT__) & SBS_IT_FPU_OFC) == SBS_IT_FPU_OFC) || \
(((__INTERRUPT__) & SBS_IT_FPU_IDC) == SBS_IT_FPU_IDC) || \
(((__INTERRUPT__) & SBS_IT_FPU_IXC) == SBS_IT_FPU_IXC))
#define IS_SBS_HDPL(__LEVEL__) (((__LEVEL__) == SBS_HDPL_VALUE_0) || \
((__LEVEL__) == SBS_HDPL_VALUE_1) || \
((__LEVEL__) == SBS_HDPL_VALUE_2) || \
((__LEVEL__) == SBS_HDPL_VALUE_3))
#define IS_SBS_COMPENSATION_CELL(__CELL__) (((__CELL__) == SBS_IO_ANALOG_CELL) || \
((__CELL__) == SBS_IO_XSPI1_CELL) || \
((__CELL__) == SBS_IO_XSPI2_CELL))
#define IS_SBS_COMPENSATION_CELL_READY(__CELL__) (((__CELL__) == SBS_IO_ANALOG_CELL_READY) || \
((__CELL__) == SBS_IO_XSPI1_CELL_READY) || \
((__CELL__) == SBS_IO_XSPI2_CELL_READY))
#define IS_SBS_IOHSLV(__HSLV__) (((__HSLV__) == SBS_IO_ANALOG_HSLV) || \
((__HSLV__) == SBS_IO_XSPI1_HSLV) || \
((__HSLV__) == SBS_IO_XSPI2_HSLV))
#define IS_SBS_EXTI_INPUT(__INPUT__) ((__INPUT__) < 16U)
#define IS_SBS_EXTI_PIN(__PIN__) (((__PIN__) == SBS_EXTI_PIN_PORTA) || \
((__PIN__) == SBS_EXTI_PIN_PORTB) || \
((__PIN__) == SBS_EXTI_PIN_PORTC) || \
((__PIN__) == SBS_EXTI_PIN_PORTD) || \
((__PIN__) == SBS_EXTI_PIN_PORTE) || \
((__PIN__) == SBS_EXTI_PIN_PORTF) || \
((__PIN__) == SBS_EXTI_PIN_PORTG) || \
((__PIN__) == SBS_EXTI_PIN_PORTH) || \
((__PIN__) == SBS_EXTI_PIN_PORTM) || \
((__PIN__) == SBS_EXTI_PIN_PORTN) || \
((__PIN__) == SBS_EXTI_PIN_PORTO) || \
((__PIN__) == SBS_EXTI_PIN_PORTP))
/**
* @}
*/
/** @addtogroup AXIM_Private_Macros
* @{
*/
#define IS_AXIM_ASIB_READ_ISS(__ISS__) (((__ISS__) == AXIM_ASIB_READ_ISS_NORMAL) || \
((__ISS__) == AXIM_ASIB_READ_ISS_FORCE_TO_1))
#define IS_AXIM_ASIB_WRITE_ISS(__ISS__) (((__ISS__) == AXIM_ASIB_WRITE_ISS_NORMAL) || \
((__ISS__) == AXIM_ASIB_WRITE_ISS_FORCE_TO_1))
#define IS_AXIM_QOS(__QOS__) ((__QOS__) <= AXIM_ASIB_READQOS_AR_QOS)
#define IS_AXIM_AMIB_READ_ISS(__ISS__) (((__ISS__) == AXIM_AMIB_READ_ISS_NORMAL) || \
((__ISS__) == AXIM_AMIB_READ_ISS_FORCE_TO_1))
#define IS_AXIM_AMIB_WRITE_ISS(__ISS__) (((__ISS__) == AXIM_AMIB_WRITE_ISS_NORMAL) || \
((__ISS__) == AXIM_AMIB_WRITE_ISS_FORCE_TO_1))
#define IS_AXIM_AMIB_READ_ISS_BM(__ISS__) (((__ISS__) == AXIM_AMIB_READ_ISS_NORMAL) || \
((__ISS__) == AXIM_AMIB_READ_ISS_FORCE_TO_1))
#define IS_AXIM_AMIB_WRITE_ISS_BM(__ISS__) (((__ISS__) == AXIM_AMIB_WRITE_ISS_BM_NORMAL) || \
((__ISS__) == AXIM_AMIB_WRITE_ISS_BM_FORCE_TO_1))
/**
* @}
*/
/* Exported variables --------------------------------------------------------*/
/** @addtogroup HAL_Exported_Variables
* @{
*/
extern __IO uint32_t uwTick;
extern uint32_t uwTickPrio;
extern HAL_TickFreqTypeDef uwTickFreq;
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup HAL_Exported_Functions
* @{
*/
/** @addtogroup HAL_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_Init(void);
HAL_StatusTypeDef HAL_DeInit(void);
void HAL_MspInit(void);
void HAL_MspDeInit(void);
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group2
* @{
*/
/* Peripheral Control functions **********************************************/
void HAL_IncTick(void);
void HAL_Delay(uint32_t Delay);
uint32_t HAL_GetTick(void);
uint32_t HAL_GetTickPrio(void);
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
HAL_TickFreqTypeDef HAL_GetTickFreq(void);
void HAL_SuspendTick(void);
void HAL_ResumeTick(void);
uint32_t HAL_GetHalVersion(void);
uint32_t HAL_GetREVID(void);
uint32_t HAL_GetDEVID(void);
uint32_t HAL_GetUIDw0(void);
uint32_t HAL_GetUIDw1(void);
uint32_t HAL_GetUIDw2(void);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group3
* @{
*/
/* DBGMCU Peripheral Control functions ***************************************/
void HAL_DBGMCU_EnableDBGSleepMode(void);
void HAL_DBGMCU_DisableDBGSleepMode(void);
void HAL_DBGMCU_EnableDBGStopMode(void);
void HAL_DBGMCU_DisableDBGStopMode(void);
void HAL_DBGMCU_EnableDBGStandbyMode(void);
void HAL_DBGMCU_DisableDBGStandbyMode(void);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group4
* @{
*/
/* SBS Control functions *****************************************************/
uint32_t HAL_SBS_GetBootAddress(void);
void HAL_SBS_IncrementHDPLValue(void);
uint32_t HAL_SBS_GetHDPLValue(void);
void HAL_SBS_OpenAccessPort(void);
void HAL_SBS_OpenDebug(void);
HAL_StatusTypeDef HAL_SBS_ConfigDebugLevel(uint32_t Level);
uint32_t HAL_SBS_GetDebugLevel(void);
void HAL_SBS_UnlockDebugConfig(void);
void HAL_SBS_LockDebugConfig(void);
void HAL_SBS_ConfigRSSCommand(uint32_t Cmd);
uint32_t HAL_SBS_GetRSSCommand(void);
void HAL_SBS_EnableIOAnalogBooster(void);
void HAL_SBS_DisableIOAnalogBooster(void);
void HAL_SBS_EnableIOAnalogSwitchVdd(void);
void HAL_SBS_DisableIOAnalogSwitchVdd(void);
void HAL_SBS_ConfigEthernetPHY(uint32_t Config);
void HAL_SBS_ConfigAXISRAMWaitState(uint32_t Config);
void HAL_SBS_EnableCompensationCell(uint32_t Selection);
void HAL_SBS_DisableCompensationCell(uint32_t Selection);
uint32_t HAL_SBS_GetCompensationCellReadyStatus(uint32_t Selection);
void HAL_SBS_ConfigCompensationCell(uint32_t Selection, uint32_t Code, uint32_t NmosValue,
uint32_t PmosValue);
HAL_StatusTypeDef HAL_SBS_GetCompensationCell(uint32_t Selection, uint32_t *pCode, uint32_t *pNmosValue,
uint32_t *pPmosValue);
void HAL_SBS_EnableIOSpeedOptimize(uint32_t Selection);
void HAL_SBS_DisableIOSpeedOptimize(uint32_t Selection);
void HAL_SBS_ConfigTimerBreakInput(uint32_t Input);
uint32_t HAL_SBS_GetTimerBreakInputConfig(void);
void HAL_SBS_EXTIConfig(uint32_t Exti, uint32_t Port);
uint32_t HAL_SBS_GetEXTIConfig(uint32_t Exti);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group5
* @{
*/
/* VREFBUF Control functions *************************************************/
void HAL_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
void HAL_VREFBUF_HighImpedanceConfig(uint32_t Mode);
void HAL_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
HAL_StatusTypeDef HAL_VREFBUF_Enable(void);
void HAL_VREFBUF_Disable(void);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group6
* @{
*/
/* AXIM Configuration functions *************************************************/
void HAL_AXIM_ASIB_EnablePacking(AXIM_ASIB_TypeDef *AsibInstance);
void HAL_AXIM_ASIB_DisablePacking(AXIM_ASIB_TypeDef *AsibInstance);
void HAL_AXIM_ASIB_IssuingConfig(AXIM_ASIB_TypeDef *AsibInstance, uint32_t ReadIssuing,
uint32_t WriteIssuing);
void HAL_AXIM_ASIB_ReadQoSConfig(AXIM_ASIB_TypeDef *AsibInstance, uint32_t QosPriority);
void HAL_AXIM_ASIB_WriteQoSConfig(AXIM_ASIB_TypeDef *AsibInstance, uint32_t QosPriority);
void HAL_AXIM_AMIB_EnablePacking(AXIM_AMIB_TypeDef *AmibInstance);
void HAL_AXIM_AMIB_DisablePacking(AXIM_AMIB_TypeDef *AmibInstance);
void HAL_AXIM_AMIB_IssuingConfig(AXIM_AMIB_TypeDef *AmibInstance, uint32_t ReadIssuing,
uint32_t WriteIssuing);
void HAL_AXIM_AMIB_IssuingConfigBusMatrix(AXIM_AMIB_TypeDef *AmibInstance, uint32_t ReadIssuing,
uint32_t WriteIssuing);
void HAL_AXIM_AMIB_EnableLongBurst(AXIM_AMIB_TypeDef *AmibInstance);
void HAL_AXIM_AMIB_DisableLongBurst(AXIM_AMIB_TypeDef *AmibInstance);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group7
* @{
*/
/* FMC Configuration functions *************************************************/
void HAL_FMC_SetBankSwapConfig(uint32_t BankMapConfig);
uint32_t HAL_FMC_GetBankSwapConfig(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H7RSxx_HAL_H */
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_cortex.h
+413
View File
@@ -0,0 +1,413 @@
/**
******************************************************************************
* @file stm32h7rsxx_hal_cortex.h
* @author MCD Application Team
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7RSxx_HAL_CORTEX_H
#define STM32H7RSxx_HAL_CORTEX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal_def.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @defgroup CORTEX CORTEX
* @brief CORTEX HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
* @{
*/
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
* @brief MPU Region initialization structure
* @{
*/
typedef struct
{
uint8_t Enable; /*!< Specifies the status of the region.
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
uint8_t Number; /*!< Specifies the number of the region to protect.
This parameter can be a value of @ref CORTEX_MPU_Region_Number */
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect.
*/
uint8_t Size; /*!< Specifies the size of the region to protect.
This parameter can be a value of @ref CORTEX_MPU_Region_Size */
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
uint8_t TypeExtField; /*!< Specifies the TEX field level.
This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
uint8_t AccessPermission; /*!< Specifies the region access permission type.
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
uint8_t DisableExec; /*!< Specifies the instruction access status.
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
} MPU_Region_InitTypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
* @{
*/
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
* @{
*/
#define NVIC_PRIORITYGROUP_0 7U /*!< 0 bit for pre-emption priority,
4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1 6U /*!< 1 bit for pre-emption priority,
3 bits for subpriority */
#define NVIC_PRIORITYGROUP_2 5U /*!< 2 bits for pre-emption priority,
2 bits for subpriority */
#define NVIC_PRIORITYGROUP_3 4U /*!< 3 bits for pre-emption priority,
1 bit for subpriority */
#define NVIC_PRIORITYGROUP_4 3U /*!< 4 bits for pre-emption priority,
0 bit for subpriority */
/**
* @}
*/
/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
* @{
*/
#define SYSTICK_CLKSOURCE_HCLK_DIV8 0U
#define SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk
/**
* @}
*/
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
* @{
*/
#define MPU_HFNMI_PRIVDEF_NONE 0U
#define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
* @{
*/
#define MPU_REGION_ENABLE 1U
#define MPU_REGION_DISABLE 0U
/**
* @}
*/
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
* @{
*/
#define MPU_INSTRUCTION_ACCESS_ENABLE 0U
#define MPU_INSTRUCTION_ACCESS_DISABLE 1U
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
* @{
*/
#define MPU_ACCESS_NOT_SHAREABLE 0U
#define MPU_ACCESS_SHAREABLE 1U
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
* @{
*/
#define MPU_ACCESS_CACHEABLE 1U
#define MPU_ACCESS_NOT_CACHEABLE 0U
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
* @{
*/
#define MPU_ACCESS_BUFFERABLE 1U
#define MPU_ACCESS_NOT_BUFFERABLE 0U
/**
* @}
*/
/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels
* @{
*/
#define MPU_TEX_LEVEL0 0U
#define MPU_TEX_LEVEL1 1U
#define MPU_TEX_LEVEL2 2U
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
* @{
*
* @brief MPU region size encoding:
* Size (Bytes) = 2^(MPU_REGION_SIZE + 1),
* where MPU_REGION_SIZE represents one of the values defined below.
*/
#define MPU_REGION_SIZE_32B 0x04U /* 32 Bytes */
#define MPU_REGION_SIZE_64B 0x05U /* 64 Bytes */
#define MPU_REGION_SIZE_128B 0x06U /* 128 Bytes */
#define MPU_REGION_SIZE_256B 0x07U /* 256 Bytes */
#define MPU_REGION_SIZE_512B 0x08U /* 512 Bytes */
#define MPU_REGION_SIZE_1KB 0x09U /* 1 Kilobyte (1024 Bytes) */
#define MPU_REGION_SIZE_2KB 0x0AU /* 2 Kilobytes */
#define MPU_REGION_SIZE_4KB 0x0BU /* 4 Kilobytes */
#define MPU_REGION_SIZE_8KB 0x0CU /* 8 Kilobytes */
#define MPU_REGION_SIZE_16KB 0x0DU /* 16 Kilobytes */
#define MPU_REGION_SIZE_32KB 0x0EU /* 32 Kilobytes */
#define MPU_REGION_SIZE_64KB 0x0FU /* 64 Kilobytes */
#define MPU_REGION_SIZE_128KB 0x10U /* 128 Kilobytes */
#define MPU_REGION_SIZE_256KB 0x11U /* 256 Kilobytes */
#define MPU_REGION_SIZE_512KB 0x12U /* 512 Kilobytes */
#define MPU_REGION_SIZE_1MB 0x13U /* 1 Megabyte (1024 KB) */
#define MPU_REGION_SIZE_2MB 0x14U /* 2 Megabytes */
#define MPU_REGION_SIZE_4MB 0x15U /* 4 Megabytes */
#define MPU_REGION_SIZE_8MB 0x16U /* 8 Megabytes */
#define MPU_REGION_SIZE_16MB 0x17U /* 16 Megabytes */
#define MPU_REGION_SIZE_32MB 0x18U /* 32 Megabytes */
#define MPU_REGION_SIZE_64MB 0x19U /* 64 Megabytes */
#define MPU_REGION_SIZE_128MB 0x1AU /* 128 Megabytes */
#define MPU_REGION_SIZE_256MB 0x1BU /* 256 Megabytes */
#define MPU_REGION_SIZE_512MB 0x1CU /* 512 Megabytes */
#define MPU_REGION_SIZE_1GB 0x1DU /* 1 Gigabyte (1024 MB) */
#define MPU_REGION_SIZE_2GB 0x1EU /* 2 Gigabytes */
#define MPU_REGION_SIZE_4GB 0x1FU /* 4 Gigabytes (maximum region size) */
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
* @{
*/
#define MPU_REGION_NO_ACCESS 0U
#define MPU_REGION_PRIV_RW 1U
#define MPU_REGION_PRIV_RW_URO 2U
#define MPU_REGION_FULL_ACCESS 3U
#define MPU_REGION_PRIV_RO 5U
#define MPU_REGION_PRIV_RO_URO 6U
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
* @{
*/
#define MPU_REGION_NUMBER0 0U
#define MPU_REGION_NUMBER1 1U
#define MPU_REGION_NUMBER2 2U
#define MPU_REGION_NUMBER3 3U
#define MPU_REGION_NUMBER4 4U
#define MPU_REGION_NUMBER5 5U
#define MPU_REGION_NUMBER6 6U
#define MPU_REGION_NUMBER7 7U
#define MPU_REGION_NUMBER8 8U
#define MPU_REGION_NUMBER9 9U
#define MPU_REGION_NUMBER10 10U
#define MPU_REGION_NUMBER11 11U
#define MPU_REGION_NUMBER12 12U
#define MPU_REGION_NUMBER13 13U
#define MPU_REGION_NUMBER14 14U
#define MPU_REGION_NUMBER15 15U
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
* @{
*/
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
* @{
*/
/* Initialization and Configuration functions *****************************/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
void HAL_NVIC_SystemReset(void);
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
/**
* @}
*/
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
* @brief Cortex control functions
* @{
*/
/* Peripheral Control functions ***********************************************/
uint32_t HAL_NVIC_GetPriorityGrouping(void);
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority);
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
void HAL_SYSTICK_IRQHandler(void);
void HAL_SYSTICK_Callback(void);
void HAL_MPU_Enable(uint32_t MPU_Control);
void HAL_MPU_Disable(void);
void HAL_MPU_EnableRegion(uint32_t RegionNumber);
void HAL_MPU_DisableRegion(uint32_t RegionNumber);
void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *pMPU_RegionInit);
void HAL_CORTEX_ClearEvent(void);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
* @{
*/
#define IS_NVIC_PRIORITY_GROUP(__GROUP__) (((__GROUP__) == NVIC_PRIORITYGROUP_0) || \
((__GROUP__) == NVIC_PRIORITYGROUP_1) || \
((__GROUP__) == NVIC_PRIORITYGROUP_2) || \
((__GROUP__) == NVIC_PRIORITYGROUP_3) || \
((__GROUP__) == NVIC_PRIORITYGROUP_4))
#define IS_NVIC_PREEMPTION_PRIORITY(__PRIO__, __PRIOGRP__) (((__PRIO__) < (1uL << __NVIC_PRIO_BITS)) && \
((__PRIO__) < (0x1uL << (0x07u - __PRIOGRP__))))
#define IS_NVIC_SUB_PRIORITY(__PRIO__, __PRIOGRP__) \
((__PRIOGRP__ < (0x07u - __NVIC_PRIO_BITS)) ?\
((__PRIO__) < (1u)): \
((__PRIO__) < (0x1uL << (__PRIOGRP__ - (0x07u - __NVIC_PRIO_BITS)))))
#define IS_NVIC_DEVICE_IRQ(__IRQ__) ((__IRQ__) > SysTick_IRQn)
#define IS_NVIC_PRIO_INTERRUPT(__IT__) (((__IT__) > HardFault_IRQn) && ((__IT__) != DebugMonitor_IRQn))
#define IS_SYSTICK_CLK_SOURCE(__SOURCE__) (((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK) || \
((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK_DIV8))
#define IS_MPU_REGION_ENABLE(__STATE__) (((__STATE__) == MPU_REGION_ENABLE) || \
((__STATE__) == MPU_REGION_DISABLE))
#define IS_MPU_INSTRUCTION_ACCESS(__STATE__) (((__STATE__) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
((__STATE__) == MPU_INSTRUCTION_ACCESS_DISABLE))
#define IS_MPU_ACCESS_SHAREABLE(__STATE__) (((__STATE__) == MPU_ACCESS_SHAREABLE) || \
((__STATE__) == MPU_ACCESS_NOT_SHAREABLE))
#define IS_MPU_ACCESS_CACHEABLE(__STATE__) (((__STATE__) == MPU_ACCESS_CACHEABLE) || \
((__STATE__) == MPU_ACCESS_NOT_CACHEABLE))
#define IS_MPU_ACCESS_BUFFERABLE(__STATE__) (((__STATE__) == MPU_ACCESS_BUFFERABLE) || \
((__STATE__) == MPU_ACCESS_NOT_BUFFERABLE))
#define IS_MPU_TEX_LEVEL(__TYPE__) (((__TYPE__) == MPU_TEX_LEVEL0) || \
((__TYPE__) == MPU_TEX_LEVEL1) || \
((__TYPE__) == MPU_TEX_LEVEL2))
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(__TYPE__) (((__TYPE__) == MPU_REGION_NO_ACCESS) || \
((__TYPE__) == MPU_REGION_PRIV_RW) || \
((__TYPE__) == MPU_REGION_PRIV_RW_URO) || \
((__TYPE__) == MPU_REGION_FULL_ACCESS) || \
((__TYPE__) == MPU_REGION_PRIV_RO) || \
((__TYPE__) == MPU_REGION_PRIV_RO_URO))
#define IS_MPU_REGION_NUMBER(__NUMBER__) ((__NUMBER__) <= MPU_REGION_NUMBER15)
#define IS_MPU_REGION_SIZE(__SIZE__) (((__SIZE__) == MPU_REGION_SIZE_32B) || \
((__SIZE__) == MPU_REGION_SIZE_64B) || \
((__SIZE__) == MPU_REGION_SIZE_128B) || \
((__SIZE__) == MPU_REGION_SIZE_256B) || \
((__SIZE__) == MPU_REGION_SIZE_512B) || \
((__SIZE__) == MPU_REGION_SIZE_1KB) || \
((__SIZE__) == MPU_REGION_SIZE_2KB) || \
((__SIZE__) == MPU_REGION_SIZE_4KB) || \
((__SIZE__) == MPU_REGION_SIZE_8KB) || \
((__SIZE__) == MPU_REGION_SIZE_16KB) || \
((__SIZE__) == MPU_REGION_SIZE_32KB) || \
((__SIZE__) == MPU_REGION_SIZE_64KB) || \
((__SIZE__) == MPU_REGION_SIZE_128KB) || \
((__SIZE__) == MPU_REGION_SIZE_256KB) || \
((__SIZE__) == MPU_REGION_SIZE_512KB) || \
((__SIZE__) == MPU_REGION_SIZE_1MB) || \
((__SIZE__) == MPU_REGION_SIZE_2MB) || \
((__SIZE__) == MPU_REGION_SIZE_4MB) || \
((__SIZE__) == MPU_REGION_SIZE_8MB) || \
((__SIZE__) == MPU_REGION_SIZE_16MB) || \
((__SIZE__) == MPU_REGION_SIZE_32MB) || \
((__SIZE__) == MPU_REGION_SIZE_64MB) || \
((__SIZE__) == MPU_REGION_SIZE_128MB) || \
((__SIZE__) == MPU_REGION_SIZE_256MB) || \
((__SIZE__) == MPU_REGION_SIZE_512MB) || \
((__SIZE__) == MPU_REGION_SIZE_1GB) || \
((__SIZE__) == MPU_REGION_SIZE_2GB) || \
((__SIZE__) == MPU_REGION_SIZE_4GB))
#define IS_MPU_SUB_REGION_DISABLE(__SUBREGION__) ((__SUBREGION__) < (uint16_t)0x00FFU)
#define IS_MPU_ADDRESS_MULTIPLE_SIZE(__ADDRESS__, __SIZE__) (((__ADDRESS__) & ((1<<(__SIZE__+1U))- 1U)) == 0U)
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H7RSxx_HAL_CORTEX_H */
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_crc.h
+342
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/**
******************************************************************************
* @file stm32h7rsxx_hal_crc.h
* @author MCD Application Team
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7RSxx_HAL_CRC_H
#define STM32H7RSxx_HAL_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal_def.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @addtogroup CRC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CRC_Exported_Types CRC Exported Types
* @{
*/
/**
* @brief CRC HAL State Structure definition
*/
typedef enum
{
HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
} HAL_CRC_StateTypeDef;
/**
* @brief CRC Init Structure definition
*/
typedef struct
{
uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 +
X^4 + X^2+ X +1.
In that case, there is no need to set GeneratingPolynomial field.
If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and
CRCLength fields must be set. */
uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
0xFFFFFFFF value. In that case, there is no need to set InitValue field. If
otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
respectively equal to 7, 8, 16 or 32. This field is written in normal,
representation e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1
is written 0x65. No need to specify it if DefaultPolynomialUse is set to
DEFAULT_POLYNOMIAL_ENABLE. */
uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
Value can be either one of
@arg @ref CRC_POLYLENGTH_32B (32-bit CRC),
@arg @ref CRC_POLYLENGTH_16B (16-bit CRC),
@arg @ref CRC_POLYLENGTH_8B (8-bit CRC),
@arg @ref CRC_POLYLENGTH_7B (7-bit CRC). */
uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
is set to DEFAULT_INIT_VALUE_ENABLE. */
uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
Can be either one of the following values
@arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion
@arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D
becomes 0x58D43CB2
@arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion,
0x1A2B3C4D becomes 0xD458B23C
@arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D
becomes 0xB23CD458 */
uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
Can be either
@arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion,
@arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted
into 0x22CC4488 */
} CRC_InitTypeDef;
/**
* @brief CRC Handle Structure definition
*/
typedef struct
{
CRC_TypeDef *Instance; /*!< Register base address */
CRC_InitTypeDef Init; /*!< CRC configuration parameters */
HAL_LockTypeDef Lock; /*!< CRC Locking object */
__IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
Can be either
@arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes
(8-bit data)
@arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of
half-words (16-bit data)
@arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words
(32-bit data)
Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization
error must occur if InputBufferFormat is not one of the three values listed
above */
} CRC_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRC_Exported_Constants CRC Exported Constants
* @{
*/
/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial
* @{
*/
#define DEFAULT_CRC32_POLY 0x04C11DB7U /*!< X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */
/**
* @}
*/
/** @defgroup CRC_Default_InitValue Default CRC computation initialization value
* @{
*/
#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Initial CRC default value */
/**
* @}
*/
/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
* @{
*/
#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) /*!< Enable default generating polynomial 0x04C11DB7 */
#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /*!< Disable default generating polynomial 0x04C11DB7 */
/**
* @}
*/
/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used
* @{
*/
#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) /*!< Enable initial CRC default value */
#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) /*!< Disable initial CRC default value */
/**
* @}
*/
/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the peripheral
* @{
*/
#define CRC_POLYLENGTH_32B 0x00000000U /*!< Resort to a 32-bit long generating polynomial */
#define CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< Resort to a 16-bit long generating polynomial */
#define CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< Resort to a 8-bit long generating polynomial */
#define CRC_POLYLENGTH_7B CRC_CR_POLYSIZE /*!< Resort to a 7-bit long generating polynomial */
/**
* @}
*/
/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
* @{
*/
#define HAL_CRC_LENGTH_32B 32U /*!< 32-bit long CRC */
#define HAL_CRC_LENGTH_16B 16U /*!< 16-bit long CRC */
#define HAL_CRC_LENGTH_8B 8U /*!< 8-bit long CRC */
#define HAL_CRC_LENGTH_7B 7U /*!< 7-bit long CRC */
/**
* @}
*/
/** @defgroup CRC_Input_Buffer_Format Input Buffer Format
* @{
*/
/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
* an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
* to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
* the CRC APIs to provide a correct result */
#define CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U /*!< Undefined input data format */
#define CRC_INPUTDATA_FORMAT_BYTES 0x00000001U /*!< Input data in byte format */
#define CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U /*!< Input data in half-word format */
#define CRC_INPUTDATA_FORMAT_WORDS 0x00000003U /*!< Input data in word format */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup CRC_Exported_Macros CRC Exported Macros
* @{
*/
/** @brief Reset CRC handle state.
* @param __HANDLE__ CRC handle.
* @retval None
*/
#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
/**
* @brief Reset CRC Data Register.
* @param __HANDLE__ CRC handle
* @retval None
*/
#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
/**
* @brief Set CRC INIT non-default value
* @param __HANDLE__ CRC handle
* @param __INIT__ 32-bit initial value
* @retval None
*/
#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
/**
* @brief Store data in the Independent Data (ID) register.
* @param __HANDLE__ CRC handle
* @param __VALUE__ Value to be stored in the ID register
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
* @retval None
*/
#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
/**
* @brief Return the data stored in the Independent Data (ID) register.
* @param __HANDLE__ CRC handle
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
* @retval Value of the ID register
*/
#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @defgroup CRC_Private_Macros CRC Private Macros
* @{
*/
#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
#define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \
((LENGTH) == CRC_POLYLENGTH_16B) || \
((LENGTH) == CRC_POLYLENGTH_8B) || \
((LENGTH) == CRC_POLYLENGTH_7B))
#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \
((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
/**
* @}
*/
/* Include CRC HAL Extended module */
#include "stm32h7rsxx_hal_crc_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRC_Exported_Functions CRC Exported Functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
/**
* @}
*/
/* Peripheral Control functions ***********************************************/
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
* @{
*/
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
/**
* @}
*/
/* Peripheral State and Error functions ***************************************/
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
* @{
*/
HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H7RSxx_HAL_CRC_H */
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_crc_ex.h
+150
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/**
******************************************************************************
* @file stm32h7rsxx_hal_crc_ex.h
* @author MCD Application Team
* @brief Header file of CRC HAL extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7RSxx_HAL_CRC_EX_H
#define STM32H7RSxx_HAL_CRC_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal_def.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @addtogroup CRCEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
* @{
*/
/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
* @{
*/
#define CRC_INPUTDATA_INVERSION_NONE 0x00000000U /*!< No input data inversion */
#define CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion */
#define CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */
#define CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN /*!< Word-wise input data inversion */
/**
* @}
*/
/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
* @{
*/
#define CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U /*!< No output data inversion */
#define CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT /*!< Bit-wise output data inversion */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
* @{
*/
/**
* @brief Set CRC output reversal
* @param __HANDLE__ CRC handle
* @retval None
*/
#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
/**
* @brief Unset CRC output reversal
* @param __HANDLE__ CRC handle
* @retval None
*/
#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
/**
* @brief Set CRC non-default polynomial
* @param __HANDLE__ CRC handle
* @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
* @retval None
*/
#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @defgroup CRCEx_Private_Macros CRC Extended Private Macros
* @{
*/
#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
((MODE) == CRC_INPUTDATA_INVERSION_WORD))
#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CRCEx_Exported_Functions
* @{
*/
/** @addtogroup CRCEx_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H7RSxx_HAL_CRC_EX_H */
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_def.h
+199
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@@ -0,0 +1,199 @@
/**
******************************************************************************
* @file stm32h7rsxx_hal_def.h
* @author MCD Application Team
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
*
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7RSxx_HAL_DEF_H
#define STM32H7RSxx_HAL_DEF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx.h"
#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */
#include <math.h>
#include <stddef.h>
/* Exported types ------------------------------------------------------------*/
/**
* @brief HAL Status structures definition
*/
typedef enum
{
HAL_OK = 0x00,
HAL_ERROR = 0x01,
HAL_BUSY = 0x02,
HAL_TIMEOUT = 0x03
} HAL_StatusTypeDef;
/**
* @brief HAL Lock structures definition
*/
typedef enum
{
HAL_UNLOCKED = 0x00,
HAL_LOCKED = 0x01
} HAL_LockTypeDef;
/* Exported macros -----------------------------------------------------------*/
#if !defined(UNUSED)
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
#endif /* UNUSED */
#define HAL_MAX_DELAY 0xFFFFFFFFU
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
do{ \
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
(__DMA_HANDLE__).Parent = (__HANDLE__); \
} while(0)
/** @brief Reset the Handle's State field.
* @param __HANDLE__ specifies the Peripheral Handle.
* @note This macro can be used for the following purpose:
* - When the Handle is declared as local variable; before passing it as parameter
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
* to set to 0 the Handle's "State" field.
* Otherwise, "State" field may have any random value and the first time the function
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
* (i.e. HAL_PPP_MspInit() will not be executed).
* - When there is a need to reconfigure the low level hardware: instead of calling
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
* In this later function, when the Handle's "State" field is set to 0, it will execute the function
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
* @retval None
*/
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
#if (USE_RTOS == 1)
/* Reserved for future use */
#error " USE_RTOS should be 0 in the current HAL release "
#else
#define __HAL_LOCK(__HANDLE__) \
do{ \
if((__HANDLE__)->Lock == HAL_LOCKED) \
{ \
return HAL_BUSY; \
} \
else \
{ \
(__HANDLE__)->Lock = HAL_LOCKED; \
} \
}while (0)
#define __HAL_UNLOCK(__HANDLE__) \
do{ \
(__HANDLE__)->Lock = HAL_UNLOCKED; \
}while (0)
#endif /* USE_RTOS */
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
#ifndef __packed
#define __packed __attribute__((packed))
#endif /* packed */
#elif defined (__GNUC__) /* GNU Compiler */
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
#ifndef __packed
#define __packed __attribute__((__packed__))
#endif /* __packed */
#endif /* __GNUC__ */
/* Macro to get buffer 32-bytes aligned (aligned to cache line width) */
#define ALIGN_32BYTES(buf) buf __attribute__((aligned(32)))
/* Macro to get buffer 8-bytes aligned (aligned to double-word width) */
/* This alignment is required for double-word DMA transfers */
#define ALIGN_8BYTES(buf) buf __attribute__((aligned(8)))
/* Legacy macros to get variable 4-bytes aligned */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__((aligned(4)))
#endif /* __ALIGN_END */
/**
* @brief __RAM_FUNC definition
*/
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
/* ARM Compiler V6
---------------
RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module.
Using the 'Options for File' dialog you can simply change the 'Code / Const'
area of a module to a memory space in physical RAM.
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
dialog.
*/
#define __RAM_FUNC
#elif defined (__ICCARM__)
/* ICCARM Compiler
---------------
RAM functions are defined using a specific toolchain keyword "__ramfunc".
*/
#define __RAM_FUNC __ramfunc
#elif defined (__GNUC__)
/* GNU Compiler
------------
RAM functions are defined using a specific toolchain attribute
"__attribute__((section(".RamFunc")))".
*/
#define __RAM_FUNC __attribute__((section(".RamFunc")))
#endif /* __ARMCC_VERSION */
/**
* @brief __NOINLINE definition
*/
#if (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined (__GNUC__)
/* ARM V6 & GNU Compiler
---------------------
*/
#define __NOINLINE __attribute__((noinline))
#elif defined (__ICCARM__)
/* ICCARM Compiler
---------------
*/
#define __NOINLINE _Pragma("optimize = no_inline")
#endif /* __ARMCC_VERSION || __GNUC__ */
#ifdef __cplusplus
}
#endif
#endif /* STM32H7RSxx_HAL_DEF_H */
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_dma.h
+874
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/**
**********************************************************************************************************************
* @file stm32h7rsxx_hal_dma.h
* @author MCD Application Team
* @brief Header file of DMA HAL module.
**********************************************************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
**********************************************************************************************************************
*/
/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/
#ifndef STM32H7RSxx_HAL_DMA_H
#define STM32H7RSxx_HAL_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ----------------------------------------------------------------------------------------------------------*/
#include "stm32h7rsxx_hal_def.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @addtogroup DMA
* @{
*/
/* Exported types ----------------------------------------------------------------------------------------------------*/
/** @defgroup DMA_Exported_Types DMA Exported Types
* @brief DMA Exported Types
* @{
*/
/**
* @brief DMA Transfer Configuration Structure definition.
*/
typedef struct
{
uint32_t Request; /*!< Specifies the DMA channel request.
This parameter can be a value of @ref DMA_Request_Selection */
uint32_t BlkHWRequest; /*!< Specifies the Block hardware request mode for DMA channel.
Block Hardware request feature can be used only with dedicated peripherals.
This parameter can be a value of @ref DMA_Block_Request */
uint32_t Direction; /*!< Specifies the transfer direction for DMA channel.
This parameter can be a value of @ref DMA_Transfer_Direction */
uint32_t SrcInc; /*!< Specifies the source increment mode for the DMA channel.
This parameter can be a value of @ref DMA_Source_Increment_Mode */
uint32_t DestInc; /*!< Specifies the destination increment mode for the DMA channel.
This parameter can be a value of @ref DMA_Destination_Increment_Mode */
uint32_t SrcDataWidth; /*!< Specifies the source data width for the DMA channel.
This parameter can be a value of @ref DMA_Source_Data_Width */
uint32_t DestDataWidth; /*!< Specifies the destination data width for the DMA channel.
This parameter can be a value of @ref DMA_Destination_Data_Width */
uint32_t Priority; /*!< Specifies the priority level for the DMA channel.
This parameter can be a value of @ref DMA_Priority_Level */
uint32_t SrcBurstLength; /*!< Specifies the source burst length (number of beats within a burst) for the DMA
channel.
This parameter can be a value between 1 and 64 */
uint32_t DestBurstLength; /*!< Specifies the destination burst length (number of beats within a burst) for the
DMA channel.
This parameter can be a value between 1 and 64 */
uint32_t TransferAllocatedPort; /*!< Specifies the transfer allocated ports.
This parameter can be a combination of @ref DMA_Transfer_Allocated_Port */
uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel.
This parameter can be a value of @ref DMA_Transfer_Event_Mode */
uint32_t Mode; /*!< Specifies the transfer mode for the DMA channel.
This parameter can be a value of @ref DMA_Transfer_Mode */
} DMA_InitTypeDef;
/**
* @brief DMA Linked-List Configuration Structure Definition.
*/
typedef struct
{
uint32_t Priority; /*!< Specifies the priority level for the DMA channel.
This parameter can be a value of @ref DMA_Priority_Level */
uint32_t LinkStepMode; /*!< Specifies the link step mode for the DMA channel.
This parameter can be a value of @ref DMAEx_Link_Step_Mode */
uint32_t LinkAllocatedPort; /*!< Specifies the linked-list allocated port for the DMA channel.
This parameter can be a value of @ref DMAEx_Link_Allocated_Port */
uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel.
This parameter can be a value of @ref DMA_Transfer_Event_Mode */
uint32_t LinkedListMode; /*!< Specifies linked-list transfer mode for the DMA channel.
This parameter can be a value of @ref DMAEx_LinkedList_Mode */
} DMA_InitLinkedListTypeDef;
/**
* @brief HAL DMA State Enumeration Definition.
*/
typedef enum
{
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
HAL_DMA_STATE_ERROR = 0x03U, /*!< DMA error state */
HAL_DMA_STATE_ABORT = 0x04U, /*!< DMA Abort state */
HAL_DMA_STATE_SUSPEND = 0x05U, /*!< DMA Suspend state */
} HAL_DMA_StateTypeDef;
/**
* @brief HAL DMA Level Complete Enumeration Definition.
*/
typedef enum
{
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full channel transfer */
HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half channel transfer */
} HAL_DMA_LevelCompleteTypeDef;
/**
* @brief HAL DMA Callbacks IDs Enumeration Definition.
*/
typedef enum
{
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Complete transfer callback ID */
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half complete transfer callback ID */
HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error transfer callback ID */
HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort transfer callback ID */
HAL_DMA_XFER_SUSPEND_CB_ID = 0x04U, /*!< Suspend transfer callback ID */
HAL_DMA_XFER_ALL_CB_ID = 0x05U /*!< All callback ID */
} HAL_DMA_CallbackIDTypeDef;
/**
* @brief DMA handle Structure definition
*/
typedef struct __DMA_HandleTypeDef
{
DMA_Channel_TypeDef *Instance; /*!< Register the DMA channel base address */
DMA_InitTypeDef Init; /*!< DMA channel init parameters */
DMA_InitLinkedListTypeDef InitLinkedList; /*!< DMA channel linked-list init parameters */
HAL_LockTypeDef Lock; /*!< DMA locking object */
uint32_t Mode; /*!< DMA transfer mode */
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
__IO uint32_t ErrorCode; /*!< DMA error code */
void *Parent; /*!< Parent object state */
void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */
void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA half transfer complete callback */
void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */
void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Abort callback */
void (* XferSuspendCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Suspend callback */
struct __DMA_QListTypeDef *LinkedListQueue; /*!< DMA linked-list queue */
} DMA_HandleTypeDef;
/**
* @}
*/
/* Exported constants ------------------------------------------------------------------------------------------------*/
/** @defgroup DMA_Exported_Constants DMA Exported Constants
* @brief DMA Exported constants
* @{
*/
/** @defgroup DMA_Error_Codes DMA Error Codes
* @brief DMA Error Codes
* @{
*/
#define HAL_DMA_ERROR_NONE (0x0000U) /*!< No error */
#define HAL_DMA_ERROR_DTE (0x0001U) /*!< Data transfer error */
#define HAL_DMA_ERROR_ULE (0x0002U) /*!< Update linked-list item error */
#define HAL_DMA_ERROR_USE (0x0004U) /*!< User setting error */
#define HAL_DMA_ERROR_TO (0x0008U) /*!< Trigger overrun error */
#define HAL_DMA_ERROR_TIMEOUT (0x0010U) /*!< Timeout error */
#define HAL_DMA_ERROR_NO_XFER (0x0020U) /*!< No transfer ongoing error */
#define HAL_DMA_ERROR_BUSY (0x0040U) /*!< Busy error */
#define HAL_DMA_ERROR_INVALID_CALLBACK (0x0080U) /*!< Invalid callback error */
#define HAL_DMA_ERROR_NOT_SUPPORTED (0x0100U) /*!< Not supported mode */
/**
* @}
*/
/** @defgroup DMA_Interrupt_Enable_Definition DMA Interrupt Enable Definition
* @brief DMA Interrupt Enable Definition
* @{
*/
#define DMA_IT_TC DMA_CCR_TCIE /*!< Transfer complete interrupt */
#define DMA_IT_HT DMA_CCR_HTIE /*!< Half transfer complete interrupt */
#define DMA_IT_DTE DMA_CCR_DTEIE /*!< Data transfer error interrupt */
#define DMA_IT_ULE DMA_CCR_ULEIE /*!< Update linked-list item error interrupt */
#define DMA_IT_USE DMA_CCR_USEIE /*!< User eetting error interrupt */
#define DMA_IT_SUSP DMA_CCR_SUSPIE /*!< Completed suspension interrupt */
#define DMA_IT_TO DMA_CCR_TOIE /*!< Trigger overrun interrupt */
/**
* @}
*/
/** @defgroup DMA_Flag_Definition DMA Flag Definition
* @brief DMA Flag Definition
* @{
*/
#define DMA_FLAG_IDLE DMA_CSR_IDLEF /*!< Idle flag */
#define DMA_FLAG_TC DMA_CSR_TCF /*!< Transfer complete flag */
#define DMA_FLAG_HT DMA_CSR_HTF /*!< Half transfer complete flag */
#define DMA_FLAG_DTE DMA_CSR_DTEF /*!< Data transfer error flag */
#define DMA_FLAG_ULE DMA_CSR_ULEF /*!< Update linked-list item error flag */
#define DMA_FLAG_USE DMA_CSR_USEF /*!< User setting error flag */
#define DMA_FLAG_SUSP DMA_CSR_SUSPF /*!< Completed suspension flag */
#define DMA_FLAG_TO DMA_CSR_TOF /*!< Trigger overrun flag */
/**
* @}
*/
/** @defgroup DMA_Request_Selection DMA Request Selection
* @brief DMA Request Selection
* @{
*/
/* HPDMA1 requests */
#define HPDMA1_REQUEST_JPEG_RX 0U /*!< HPDMA1 HW request is JPEG_DMA_RX */
#define HPDMA1_REQUEST_JPEG_TX 1U /*!< HPDMA1 HW request is JPEG_DMA_TX */
#define HPDMA1_REQUEST_XSPI1 2U /*!< HPDMA1 HW request is XSPI1 */
#define HPDMA1_REQUEST_XSPI2 3U /*!< HPDMA1 HW request is XSPI2 */
#define HPDMA1_REQUEST_SPI3_RX 4U /*!< HPDMA1 HW request is SPI3_RX */
#define HPDMA1_REQUEST_SPI3_TX 5U /*!< HPDMA1 HW request is SPI3_TX */
#define HPDMA1_REQUEST_SPI4_RX 6U /*!< HPDMA1 HW request is SPI4_RX */
#define HPDMA1_REQUEST_SPI4_TX 7U /*!< HPDMA1 HW request is SPI4_TX */
#define HPDMA1_REQUEST_ADC1 8U /*!< HPDMA1 HW request is ADC1 */
#define HPDMA1_REQUEST_ADC2 9U /*!< HPDMA1 HW request is ADC2 */
#define HPDMA1_REQUEST_ADF1_FLT0 10U /*!< HPDMA1 HW request is ADF1_FLT0 */
#define HPDMA1_REQUEST_UART4_RX 11U /*!< HPDMA1 HW request is UART4_RX */
#define HPDMA1_REQUEST_UART4_TX 12U /*!< HPDMA1 HW request is UART4_TX */
#define HPDMA1_REQUEST_UART5_RX 13U /*!< HPDMA1 HW request is UART5_RX */
#define HPDMA1_REQUEST_UART5_TX 14U /*!< HPDMA1 HW request is UART5_TX */
#define HPDMA1_REQUEST_UART7_RX 15U /*!< HPDMA1 HW request is UART7_RX */
#define HPDMA1_REQUEST_UART7_TX 16U /*!< HPDMA1 HW request is UART7_TX */
#define HPDMA1_REQUEST_LPTIM2_IC1 17U /*!< HPDMA1 HW request is LPTIM2_IC1 */
#define HPDMA1_REQUEST_LPTIM2_IC2 18U /*!< HPDMA1 HW request is LPTIM2_IC2 */
#define HPDMA1_REQUEST_LPTIM2_UE 19U /*!< HPDMA1 HW request is LPTIM2_UE */
/* GPDMA1 requests */
#define GPDMA1_REQUEST_ADC1 0U /*!< GPDMA1 HW request is ADC1 */
#define GPDMA1_REQUEST_ADC2 1U /*!< GPDMA1 HW request is ADC2 */
#define GPDMA1_REQUEST_CRYP_IN 2U /*!< GPDMA1 HW request is CRYP_IN */
#define GPDMA1_REQUEST_CRYP_OUT 3U /*!< GPDMA1 HW request is CRYP_OUT */
#define GPDMA1_REQUEST_SAES_IN 4U /*!< GPDMA1 HW request is SAES_IN */
#define GPDMA1_REQUEST_SAES_OUT 5U /*!< GPDMA1 HW request is SAES_OUT */
#define GPDMA1_REQUEST_HASH_IN 6U /*!< GPDMA1 HW request is HASH_IN */
#define GPDMA1_REQUEST_TIM1_CH1 7U /*!< GPDMA1 HW request is TIM1_CH1 */
#define GPDMA1_REQUEST_TIM1_CH2 8U /*!< GPDMA1 HW request is TIM1_CH2 */
#define GPDMA1_REQUEST_TIM1_CH3 9U /*!< GPDMA1 HW request is TIM1_CH3 */
#define GPDMA1_REQUEST_TIM1_CH4 10U /*!< GPDMA1 HW request is TIM1_CH4 */
#define GPDMA1_REQUEST_TIM1_UP 11U /*!< GPDMA1 HW request is TIM1_UP */
#define GPDMA1_REQUEST_TIM1_TRIG 12U /*!< GPDMA1 HW request is TIM1_TRIG */
#define GPDMA1_REQUEST_TIM1_COM 13U /*!< GPDMA1 HW request is TIM1_COM */
#define GPDMA1_REQUEST_TIM2_CH1 14U /*!< GPDMA1 HW request is TIM2_CH1 */
#define GPDMA1_REQUEST_TIM2_CH2 15U /*!< GPDMA1 HW request is TIM2_CH2 */
#define GPDMA1_REQUEST_TIM2_CH3 16U /*!< GPDMA1 HW request is TIM2_CH3 */
#define GPDMA1_REQUEST_TIM2_CH4 17U /*!< GPDMA1 HW request is TIM2_CH4 */
#define GPDMA1_REQUEST_TIM2_UP 18U /*!< GPDMA1 HW request is TIM2_UP */
#define GPDMA1_REQUEST_TIM2_TRIG 19U /*!< GPDMA1 HW request is TIM2_TRIG */
#define GPDMA1_REQUEST_TIM3_CH1 20U /*!< GPDMA1 HW request is TIM3_CH1 */
#define GPDMA1_REQUEST_TIM3_CH2 21U /*!< GPDMA1 HW request is TIM3_CH2 */
#define GPDMA1_REQUEST_TIM3_CH3 22U /*!< GPDMA1 HW request is TIM3_CH3 */
#define GPDMA1_REQUEST_TIM3_CH4 23U /*!< GPDMA1 HW request is TIM3_CH4 */
#define GPDMA1_REQUEST_TIM3_UP 24U /*!< GPDMA1 HW request is TIM3_UP */
#define GPDMA1_REQUEST_TIM3_TRIG 25U /*!< GPDMA1 HW request is TIM3_TRIG */
#define GPDMA1_REQUEST_TIM4_CH1 26U /*!< GPDMA1 HW request is TIM4_CH1 */
#define GPDMA1_REQUEST_TIM4_CH2 27U /*!< GPDMA1 HW request is TIM4_CH2 */
#define GPDMA1_REQUEST_TIM4_CH3 28U /*!< GPDMA1 HW request is TIM4_CH3 */
#define GPDMA1_REQUEST_TIM4_CH4 29U /*!< GPDMA1 HW request is TIM4_CH4 */
#define GPDMA1_REQUEST_TIM4_UP 30U /*!< GPDMA1 HW request is TIM4_UP */
#define GPDMA1_REQUEST_TIM4_TRIG 31U /*!< GPDMA1 HW request is TIM4_TRIG */
#define GPDMA1_REQUEST_TIM5_CH1 32U /*!< GPDMA1 HW request is TIM5_CH1 */
#define GPDMA1_REQUEST_TIM5_CH2 33U /*!< GPDMA1 HW request is TIM5_CH2 */
#define GPDMA1_REQUEST_TIM5_CH3 34U /*!< GPDMA1 HW request is TIM5_CH3 */
#define GPDMA1_REQUEST_TIM5_CH4 35U /*!< GPDMA1 HW request is TIM5_CH4 */
#define GPDMA1_REQUEST_TIM5_UP 36U /*!< GPDMA1 HW request is TIM5_UP */
#define GPDMA1_REQUEST_TIM5_TRIG 37U /*!< GPDMA1 HW request is TIM5_TRIG */
#define GPDMA1_REQUEST_TIM6_UP 38U /*!< GPDMA1 HW request is TIM6_UP */
#define GPDMA1_REQUEST_TIM7_UP 39U /*!< GPDMA1 HW request is TIM7_UP */
#define GPDMA1_REQUEST_TIM15_CH1 40U /*!< GPDMA1 HW request is TIM15_CH1 */
#define GPDMA1_REQUEST_TIM15_CH2 41U /*!< GPDMA1 HW request is TIM15_CH2 */
#define GPDMA1_REQUEST_TIM15_UP 42U /*!< GPDMA1 HW request is TIM15_UP */
#define GPDMA1_REQUEST_TIM15_TRIG 43U /*!< GPDMA1 HW request is TIM15_TRIG */
#define GPDMA1_REQUEST_TIM15_COM 44U /*!< GPDMA1 HW request is TIM15_COM */
#define GPDMA1_REQUEST_TIM16_CH1 45U /*!< GPDMA1 HW request is TIM16_CH1 */
#define GPDMA1_REQUEST_TIM16_UP 46U /*!< GPDMA1 HW request is TIM16_UP */
#define GPDMA1_REQUEST_TIM16_COM 47U /*!< GPDMA1 HW request is TIM16_COM */
#define GPDMA1_REQUEST_TIM17_CH1 48U /*!< GPDMA1 HW request is TIM17_CH1 */
#define GPDMA1_REQUEST_TIM17_UP 49U /*!< GPDMA1 HW request is TIM17_UP */
#define GPDMA1_REQUEST_TIM17_COM 50U /*!< GPDMA1 HW request is TIM17_COM */
#define GPDMA1_REQUEST_SPI1_RX 51U /*!< GPDMA1 HW request is SPI1_RX */
#define GPDMA1_REQUEST_SPI1_TX 52U /*!< GPDMA1 HW request is SPI1_TX */
#define GPDMA1_REQUEST_SPI2_RX 53U /*!< GPDMA1 HW request is SPI2_RX */
#define GPDMA1_REQUEST_SPI2_TX 54U /*!< GPDMA1 HW request is SPI2_TX */
#define GPDMA1_REQUEST_SPI3_RX 55U /*!< GPDMA1 HW request is SPI3_RX */
#define GPDMA1_REQUEST_SPI3_TX 56U /*!< GPDMA1 HW request is SPI3_TX */
#define GPDMA1_REQUEST_SPI4_RX 57U /*!< GPDMA1 HW request is SPI4_RX */
#define GPDMA1_REQUEST_SPI4_TX 58U /*!< GPDMA1 HW request is SPI4_TX */
#define GPDMA1_REQUEST_SPI5_RX 59U /*!< GPDMA1 HW request is SPI5_RX */
#define GPDMA1_REQUEST_SPI5_TX 60U /*!< GPDMA1 HW request is SPI5_TX */
#define GPDMA1_REQUEST_SPI6_RX 61U /*!< GPDMA1 HW request is SPI6_RX */
#define GPDMA1_REQUEST_SPI6_TX 62U /*!< GPDMA1 HW request is SPI6_TX */
#define GPDMA1_REQUEST_SAI1_A 63U /*!< GPDMA1 HW request is SAI1_A */
#define GPDMA1_REQUEST_SAI1_B 64U /*!< GPDMA1 HW request is SAI1_B */
#define GPDMA1_REQUEST_SAI2_A 65U /*!< GPDMA1 HW request is SAI2_A */
#define GPDMA1_REQUEST_SAI2_B 66U /*!< GPDMA1 HW request is SAI2_B */
#define GPDMA1_REQUEST_I2C1_RX 67U /*!< GPDMA1 HW request is I2C1_RX */
#define GPDMA1_REQUEST_I2C1_TX 68U /*!< GPDMA1 HW request is I2C1_TX */
#define GPDMA1_REQUEST_I2C2_RX 69U /*!< GPDMA1 HW request is I2C2_RX */
#define GPDMA1_REQUEST_I2C2_TX 70U /*!< GPDMA1 HW request is I2C2_TX */
#define GPDMA1_REQUEST_I2C3_RX 71U /*!< GPDMA1 HW request is I2C3_RX */
#define GPDMA1_REQUEST_I2C3_TX 72U /*!< GPDMA1 HW request is I2C3_TX */
#define GPDMA1_REQUEST_USART1_RX 73U /*!< GPDMA1 HW request is USART1_RX */
#define GPDMA1_REQUEST_USART1_TX 74U /*!< GPDMA1 HW request is USART1_TX */
#define GPDMA1_REQUEST_USART2_RX 75U /*!< GPDMA1 HW request is USART2_RX */
#define GPDMA1_REQUEST_USART2_TX 76U /*!< GPDMA1 HW request is USART2_TX */
#define GPDMA1_REQUEST_USART3_RX 77U /*!< GPDMA1 HW request is USART3_RX */
#define GPDMA1_REQUEST_USART3_TX 78U /*!< GPDMA1 HW request is USART3_TX */
#define GPDMA1_REQUEST_UART4_RX 79U /*!< GPDMA1 HW request is UART4_RX */
#define GPDMA1_REQUEST_UART4_TX 80U /*!< GPDMA1 HW request is UART4_TX */
#define GPDMA1_REQUEST_UART5_RX 81U /*!< GPDMA1 HW request is UART5_RX */
#define GPDMA1_REQUEST_UART5_TX 82U /*!< GPDMA1 HW request is UART5_TX */
#define GPDMA1_REQUEST_UART7_RX 83U /*!< GPDMA1 HW request is UART7_RX */
#define GPDMA1_REQUEST_UART7_TX 84U /*!< GPDMA1 HW request is UART7_TX */
#define GPDMA1_REQUEST_UART8_RX 85U /*!< GPDMA1 HW request is UART8_RX */
#define GPDMA1_REQUEST_UART8_TX 86U /*!< GPDMA1 HW request is UART8_TX */
#define GPDMA1_REQUEST_CORDIC_READ 87U /*!< GPDMA1 HW request is CORDIC_READ */
#define GPDMA1_REQUEST_CORDIC_WRITE 88U /*!< GPDMA1 HW request is CORDIC_WRITE */
#define GPDMA1_REQUEST_LPTIM1_IC1 89U /*!< GPDMA1 HW request is LPTIM1_IC1 */
#define GPDMA1_REQUEST_LPTIM1_IC2 90U /*!< GPDMA1 HW request is LPTIM1_IC2 */
#define GPDMA1_REQUEST_LPTIM1_UE 91U /*!< GPDMA1 HW request is LPTIM1_UE */
#define GPDMA1_REQUEST_LPTIM2_IC1 92U /*!< GPDMA1 HW request is LPTIM2_IC1 */
#define GPDMA1_REQUEST_LPTIM2_IC2 93U /*!< GPDMA1 HW request is LPTIM2_IC2 */
#define GPDMA1_REQUEST_LPTIM2_UE 94U /*!< GPDMA1 HW request is LPTIM2_UE */
#define GPDMA1_REQUEST_SPDIF_RX_DT 95U /*!< GPDMA1 HW request is SPDIF_RX_DT */
#define GPDMA1_REQUEST_SPDIF_RX_CS 96U /*!< GPDMA1 HW request is SPDIF_RX_CS */
#define GPDMA1_REQUEST_ADF1_FLT0 97U /*!< GPDMA1 HW request is ADF1_FLT0 */
#define GPDMA1_REQUEST_UCPD1_TX 98U /*!< GPDMA1 HW request is UCPD1_TX */
#define GPDMA1_REQUEST_UCPD1_RX 99U /*!< GPDMA1 HW request is UCPD1_RX */
#define GPDMA1_REQUEST_PSSI 100U /*!< GPDMA1 HW request is PSSI */
#define GPDMA1_REQUEST_LPUART1_RX 101U /*!< GPDMA1 HW request is LPUART1_RX */
#define GPDMA1_REQUEST_LPUART1_TX 102U /*!< GPDMA1 HW request is LPUART1_TX */
#define GPDMA1_REQUEST_LPTIM3_IC1 103U /*!< GPDMA1 HW request is LPTIM3_IC1 */
#define GPDMA1_REQUEST_LPTIM3_IC2 104U /*!< GPDMA1 HW request is LPTIM3_IC2 */
#define GPDMA1_REQUEST_LPTIM3_UE 105U /*!< GPDMA1 HW request is LPTIM3_UE */
#define GPDMA1_REQUEST_I3C1_RX 106U /*!< GPDMA1 HW request is I3C1_RX */
#define GPDMA1_REQUEST_I3C1_TX 107U /*!< GPDMA1 HW request is I3C1_TX */
#define GPDMA1_REQUEST_I3C1_TC 108U /*!< GPDMA1 HW request is I3C1_TC */
#define GPDMA1_REQUEST_I3C1_RS 109U /*!< GPDMA1 HW request is I3C1_RS */
#define GPDMA1_MAX_REQUEST 109U
/* Software request */
#define DMA_REQUEST_SW DMA_CTR2_SWREQ /*!< DMA SW request */
/**
* @}
*/
/** @defgroup DMA_Block_Request DMA Block Request
* @brief DMA Block Request
* @{
*/
#define DMA_BREQ_SINGLE_BURST 0x00000000U /*!< Hardware request protocol at a single / burst level */
#define DMA_BREQ_BLOCK DMA_CTR2_BREQ /*!< Hardware request protocol at a block level */
/**
* @}
*/
/** @defgroup DMA_Transfer_Direction DMA Transfer Direction
* @brief DMA transfer direction
* @{
*/
#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
#define DMA_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */
#define DMA_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */
/**
* @}
*/
/** @defgroup DMA_Source_Increment_Mode DMA Source Increment Mode
* @brief DMA Source Increment Mode
* @{
*/
#define DMA_SINC_FIXED 0x00000000U /*!< Source fixed single / burst */
#define DMA_SINC_INCREMENTED DMA_CTR1_SINC /*!< Source incremented single / burst */
/**
* @}
*/
/** @defgroup DMA_Destination_Increment_Mode DMA Destination Increment Mode
* @brief DMA Destination Increment Mode
* @{
*/
#define DMA_DINC_FIXED 0x00000000U /*!< Destination fixed single / burst */
#define DMA_DINC_INCREMENTED DMA_CTR1_DINC /*!< Destination incremented single / burst */
/**
* @}
*/
/** @defgroup DMA_Source_Data_Width DMA Source Data Width
* @brief DMA Source Data Width
* @{
*/
#define DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source data width : Byte */
#define DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source data width : HalfWord */
#define DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source data width : Word */
#define DMA_SRC_DATAWIDTH_DOUBLEWORD DMA_CTR1_SDW_LOG2 /*!< Source data width : DoubleWord */
/**
* @}
*/
/** @defgroup DMA_Destination_Data_Width DMA destination Data Width
* @brief DMA destination Data Width
* @{
*/
#define DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination data width : Byte */
#define DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination data width : HalfWord */
#define DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination data width : Word */
#define DMA_DEST_DATAWIDTH_DOUBLEWORD DMA_CTR1_DDW_LOG2 /*!< Destination data width : DoubleWord */
/**
* @}
*/
/** @defgroup DMA_Priority_Level DMA Priority Level
* @brief DMA Priority Level
* @{
*/
#define DMA_LOW_PRIORITY_LOW_WEIGHT 0x00000000U /*!< Priority level : Low Priority, Low weight */
#define DMA_LOW_PRIORITY_MID_WEIGHT DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid weight */
#define DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High weight */
#define DMA_HIGH_PRIORITY DMA_CCR_PRIO /*!< Priority level : HIGH Priority */
/**
* @}
*/
/** @defgroup DMA_Transfer_Allocated_Port DMA Transfer Allocated Port
* @brief DMA Transfer Allocated Port
* @{
*/
#define DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source allocated Port 0 */
#define DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source allocated Port 1 */
#define DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination allocated Port 0 */
#define DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination allocated Port 1 */
/**
* @}
*/
/** @defgroup DMA_Transfer_Event_Mode DMA Transfer Event Mode
* @brief DMA Transfer Event Mode
* @{
*/
#define DMA_TCEM_BLOCK_TRANSFER 0x00000000U /*!< The TC event is generated at the end of each block and the
HT event is generated at the half of each block */
#define DMA_TCEM_REPEATED_BLOCK_TRANSFER DMA_CTR2_TCEM_0 /*!< The TC event is generated at the end of the repeated block
and the HT event is generated at the half of the repeated
block */
#define DMA_TCEM_EACH_LL_ITEM_TRANSFER DMA_CTR2_TCEM_1 /*!< The TC event is generated at the end of each linked-list
item and the HT event is generated at the half of each
linked-list item */
#define DMA_TCEM_LAST_LL_ITEM_TRANSFER DMA_CTR2_TCEM /*!< The TC event is generated at the end of the last
linked-list item and the HT event is generated at the half
of the last linked-list item */
/**
* @}
*/
/** @defgroup DMA_Transfer_Mode DMA Transfer Mode
* @brief DMA Transfer Mode
* @{
*/
#define DMA_NORMAL (0x00U) /*!< Normal DMA transfer */
#define DMA_PFCTRL DMA_CTR2_PFREQ /*!< HW request peripheral flow control mode */
/**
* @}
*/
/** @defgroup DMA_Channel_Attributes DMA Channel Attributes
* @brief DMA Channel Privilege Attribute
* @{
*/
#define DMA_CHANNEL_PRIV (DMA_CHANNEL_ATTR_PRIV_MASK | (1U<<DMA_CHANNEL_PRIV_VAL_POS)) /*!< Channel is privileged */
#define DMA_CHANNEL_NPRIV (DMA_CHANNEL_ATTR_PRIV_MASK) /*!< Channel is unprivileged */
#define DMA_CHANNEL_ATTRIBUTE_UNLOCKED (0x00U) /*!< Channel attribute is unlocked */
#define DMA_CHANNEL_ATTRIBUTE_LOCKED (0x01U) /*!< Channel attribute is locked */
/**
* @}
*/
/* Exported macro ----------------------------------------------------------------------------------------------------*/
/** @defgroup DMA_Exported_Macros DMA Exported Macros
* @brief DMA Exported Macros
* @{
*/
/** @brief Reset DMA handle state.
* @param __HANDLE__ : DMA handle.
* @retval None.
*/
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) \
((__HANDLE__)->State = HAL_DMA_STATE_RESET)
/**
* @brief Enable the specified DMA Channel.
* @param __HANDLE__ : DMA handle.
* @retval None
*/
#define __HAL_DMA_ENABLE(__HANDLE__) \
((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
/**
* @brief Disable the specified DMA Channel.
* @param __HANDLE__ : DMA handle.
* @retval None
*/
#define __HAL_DMA_DISABLE(__HANDLE__) \
((__HANDLE__)->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_RESET))
/**
* @brief Get the DMA channel pending flags.
* @param __HANDLE__ : DMA handle.
* @param __FLAG__ : Get the specified flag.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TC : Transfer Complete flag.
* @arg DMA_FLAG_HT : Half Transfer Complete flag.
* @arg DMA_FLAG_DTE : Data Transfer Error flag.
* @arg DMA_FLAG_ULE : Update linked-list Error flag.
* @arg DMA_FLAG_USE : User Setting Error flag.
* @arg DMA_FLAG_TO : Trigger Overrun flag.
* @arg DMA_FLAG_SUSP : Completed Suspension flag.
* @arg DMA_FLAG_IDLEF : Idle flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) \
((__HANDLE__)->Instance->CSR & (__FLAG__))
/**
* @brief Clear the DMA Channel pending flags.
* @param __HANDLE__ : DMA handle.
* @param __FLAG__ : Specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TC : Transfer Complete flag.
* @arg DMA_FLAG_HT : Half Transfer Complete flag.
* @arg DMA_FLAG_DTE : Data Transfer Error flag.
* @arg DMA_FLAG_ULE : Update Linked-List Error flag.
* @arg DMA_FLAG_USE : User Setting Error flag.
* @arg DMA_FLAG_TO : Trigger Overrun flag.
* @arg DMA_FLAG_SUSP : Completed Suspension flag.
* @retval None
*/
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
((__HANDLE__)->Instance->CFCR = (__FLAG__))
/**
* @brief Enable the specified DMA Channel interrupts.
* @param __HANDLE__ : DMA handle.
* @param __INTERRUPT__ : Specifies the DMA interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC : Transfer Complete interrupt.
* @arg DMA_IT_HT : Half Transfer Complete interrupt.
* @arg DMA_IT_DTE : Data Transfer Error interrupt.
* @arg DMA_IT_ULE : Update Linked-List Error interrupt.
* @arg DMA_IT_USE : User Setting Error interrupt.
* @arg DMA_IT_TO : Trigger Overrun interrupt.
* @arg DMA_IT_SUSP : Completed Suspension interrupt.
* @retval None
*/
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
/**
* @brief Disable the specified DMA Channel interrupts.
* @param __HANDLE__ : DMA handle.
* @param __INTERRUPT__ : specifies the DMA interrupt sources to be disabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC : Transfer Complete interrupt.
* @arg DMA_IT_HT : Half Transfer Complete interrupt.
* @arg DMA_IT_DTE : Data Transfer Error interrupt.
* @arg DMA_IT_ULE : Update Linked-List Error interrupt.
* @arg DMA_IT_USE : User Setting Error interrupt.
* @arg DMA_IT_TO : Trigger Overrun interrupt.
* @arg DMA_IT_SUSP : Completed Suspension interrupt.
* @retval None
*/
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
/**
* @brief Checks whether the specified DMA Channel interrupt is enabled or not.
* @param __HANDLE__ : DMA handle.
* @param __INTERRUPT__ : specifies the DMA interrupt source to check.
* @arg DMA_IT_TC : Transfer Complete interrupt.
* @arg DMA_IT_HT : Half Transfer Complete interrupt.
* @arg DMA_IT_DTE : Data Transfer Error interrupt.
* @arg DMA_IT_ULE : Update Linked-List Error interrupt.
* @arg DMA_IT_USE : User Setting Error interrupt.
* @arg DMA_IT_TO : Trigger Overrun interrupt.
* @arg DMA_IT_SUSP : Completed Suspension interrupt.
* @retval The state of DMA_IT (SET or RESET).
*/
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
(((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
/**
* @brief Writes the block number of bytes to be transferred from the source on the DMA Channel.
* @param __HANDLE__ : DMA handle.
* @param __COUNTER__ : Number of data bytes to be transferred from the source (from 0 to 65535).
*/
#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) \
MODIFY_REG((__HANDLE__)->Instance->CBR1, DMA_CBR1_BNDT, (__COUNTER__))
/**
* @brief Returns the number of remaining data bytes in the current DMA Channel transfer.
* @param __HANDLE__ : DMA handle.
* @retval The number of remaining data units in the current DMA Stream transfer.
*/
#define __HAL_DMA_GET_COUNTER(__HANDLE__) \
(((__HANDLE__)->Instance->CBR1) & DMA_CBR1_BNDT)
/**
* @}
*/
/* Include DMA HAL Extension module */
#include "stm32h7rsxx_hal_dma_ex.h"
/* Exported functions ------------------------------------------------------------------------------------------------*/
/** @defgroup DMA_Exported_Functions DMA Exported Functions
* @brief DMA Exported Functions
* @{
*/
/** @defgroup DMA_Exported_Functions_Group1 Initialization and De-Initialization Functions
* @brief Initialization and De-Initialization Functions
* @{
*/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma);
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma);
/**
* @}
*/
/** @defgroup DMA_Exported_Functions_Group2 I/O Operation Functions
* @brief I/O Operation Functions
* @{
*/
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *const hdma,
uint32_t SrcAddress,
uint32_t DstAddress,
uint32_t SrcDataSize);
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *const hdma,
uint32_t SrcAddress,
uint32_t DstAddress,
uint32_t SrcDataSize);
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *const hdma);
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *const hdma);
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *const hdma,
HAL_DMA_LevelCompleteTypeDef CompleteLevel,
uint32_t Timeout);
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma);
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma,
HAL_DMA_CallbackIDTypeDef CallbackID,
void (*const pCallback)(DMA_HandleTypeDef *const _hdma));
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma,
HAL_DMA_CallbackIDTypeDef CallbackID);
/**
* @}
*/
/** @defgroup DMA_Exported_Functions_Group3 State and Error Functions
* @brief State and Error Functions
* @{
*/
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef const *const hdma);
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma);
/**
* @}
*/
/** @defgroup DMA_Exported_Functions_Group4 DMA Attributes Functions
* @brief DMA Attributes Functions
* @{
*/
HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma,
uint32_t ChannelAttributes);
HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma,
uint32_t *const pChannelAttributes);
HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma);
HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma,
uint32_t *const pLockState);
/**
* @}
*/
/**
* @}
*/
/* Private constants -------------------------------------------------------------------------------------------------*/
/** @defgroup DMA_Private_Constants DMA Private Constants
* @brief DMA Private Constants
* @{
*/
#define HAL_TIMEOUT_DMA_ABORT (0x00000005U) /* DMA channel abort timeout 5 milli-second */
#define HAL_DMA_CHANNEL_START (0x00000050U) /* DMA channel offset */
#define HAL_DMA_CHANNEL_SIZE (0x00000080U) /* DMA channel size */
#define HAL_DMA_OFFSET_MASK (0x00000FFFU) /* DMA channel offset mask */
#define DMA_CHANNEL_ATTR_PRIV_MASK (0x01000000U) /* DMA channel privilege */
#define DMA_CHANNEL_PRIV_VAL_POS 0U
#define DMA_CHANNEL_BURST_MIN (0x00000001U) /* DMA channel minimum burst size */
#define DMA_CHANNEL_BURST_MAX (0x00000040U) /* DMA channel maximum burst size */
/**
* @}
*/
/* Private macros ----------------------------------------------------------------------------------------------------*/
/** @defgroup DMA_Private_Macros DMA Private Macros
* @brief DMA Private Macros
* @{
*/
#define GET_DMA_INSTANCE(__HANDLE__) \
((DMA_TypeDef *)((uint32_t)((__HANDLE__)->Instance) & (~HAL_DMA_OFFSET_MASK)))
#define GET_DMA_CHANNEL(__HANDLE__) \
((((uint32_t)((__HANDLE__)->Instance) & HAL_DMA_OFFSET_MASK) - HAL_DMA_CHANNEL_START) / HAL_DMA_CHANNEL_SIZE)
#define IS_DMA_MODE(MODE) \
(((MODE) == DMA_NORMAL) || \
((MODE) == DMA_PFCTRL))
#define IS_DMA_DIRECTION(DIRECTION) \
(((DIRECTION) == DMA_PERIPH_TO_MEMORY) || \
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
#define IS_DMA_LEVEL_COMPLETE(LEVEL) \
(((LEVEL) == HAL_DMA_FULL_TRANSFER) || \
((LEVEL) == HAL_DMA_HALF_TRANSFER))
#define IS_DMA_SOURCE_INC(INC) \
(((INC) == DMA_SINC_FIXED) || \
((INC) == DMA_SINC_INCREMENTED))
#define IS_DMA_DESTINATION_INC(INC) \
(((INC) == DMA_DINC_FIXED) || \
((INC) == DMA_DINC_INCREMENTED))
#define IS_DMA_SOURCE_DATA_WIDTH(WIDTH) \
(((WIDTH) == DMA_SRC_DATAWIDTH_BYTE) || \
((WIDTH) == DMA_SRC_DATAWIDTH_HALFWORD) || \
((WIDTH) == DMA_SRC_DATAWIDTH_WORD) || \
((WIDTH) == DMA_SRC_DATAWIDTH_DOUBLEWORD))
#define IS_DMA_DESTINATION_DATA_WIDTH(WIDTH) \
(((WIDTH) == DMA_DEST_DATAWIDTH_BYTE) || \
((WIDTH) == DMA_DEST_DATAWIDTH_HALFWORD) || \
((WIDTH) == DMA_DEST_DATAWIDTH_WORD) || \
((WIDTH) == DMA_DEST_DATAWIDTH_DOUBLEWORD))
#define IS_DMA_BURST_LENGTH(LENGTH) \
(((LENGTH) >= DMA_CHANNEL_BURST_MIN) && \
((LENGTH) <= DMA_CHANNEL_BURST_MAX))
#define IS_DMA_PRIORITY(PRIORITY) \
(((PRIORITY) == DMA_LOW_PRIORITY_LOW_WEIGHT) || \
((PRIORITY) == DMA_LOW_PRIORITY_MID_WEIGHT) || \
((PRIORITY) == DMA_LOW_PRIORITY_HIGH_WEIGHT) || \
((PRIORITY) == DMA_HIGH_PRIORITY))
#define IS_DMA_TRANSFER_ALLOCATED_PORT(ALLOCATED_PORT) \
(((ALLOCATED_PORT) & (~(DMA_CTR1_SAP | DMA_CTR1_DAP))) == 0U)
#define IS_DMA_REQUEST(REQUEST) \
(((REQUEST) == DMA_REQUEST_SW) || \
((REQUEST) <= GPDMA1_REQUEST_I3C1_RS))
#define IS_DMA_BLOCK_HW_REQUEST(MODE) \
(((MODE) == DMA_BREQ_SINGLE_BURST) || \
((MODE) == DMA_BREQ_BLOCK))
#define IS_DMA_TCEM_EVENT_MODE(MODE) \
(((MODE) == DMA_TCEM_BLOCK_TRANSFER) || \
((MODE) == DMA_TCEM_REPEATED_BLOCK_TRANSFER) || \
((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER) || \
((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER))
#define IS_DMA_BLOCK_SIZE(SIZE) \
(((SIZE) > 0U) && ((SIZE) <= DMA_CBR1_BNDT))
#define IS_DMA_GLOBAL_ACTIVE_FLAG(INSTANCE, GLOBAL_FLAG) \
(((INSTANCE)->MISR & (GLOBAL_FLAG)))
#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \
(((ATTRIBUTE) == DMA_CHANNEL_PRIV) || \
((ATTRIBUTE) == DMA_CHANNEL_NPRIV))
/**
* @}
*/
/* Private functions -------------------------------------------------------------------------------------------------*/
/** @defgroup DMA_Private_Functions DMA Private Functions
* @brief DMA Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H7RSxx_HAL_DMA_H */
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_dma2d.h
+715
View File
@@ -0,0 +1,715 @@
/**
******************************************************************************
* @file stm32h7rsxx_hal_dma2d.h
* @author MCD Application Team
* @brief Header file of DMA2D HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7RSxx_HAL_DMA2D_H
#define STM32H7RSxx_HAL_DMA2D_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal_def.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
#if defined (DMA2D)
/** @addtogroup DMA2D DMA2D
* @brief DMA2D HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DMA2D_Exported_Types DMA2D Exported Types
* @{
*/
#define MAX_DMA2D_LAYER 2U /*!< DMA2D maximum number of layers */
/**
* @brief DMA2D CLUT Structure definition
*/
typedef struct
{
uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/
uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode.
This parameter can be one value of @ref DMA2D_CLUT_CM. */
uint32_t Size; /*!< Configures the DMA2D CLUT size.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
} DMA2D_CLUTCfgTypeDef;
/**
* @brief DMA2D Init structure definition
*/
typedef struct
{
uint32_t Mode; /*!< Configures the DMA2D transfer mode.
This parameter can be one value of @ref DMA2D_Mode. */
uint32_t ColorMode; /*!< Configures the color format of the output image.
This parameter can be one value of @ref DMA2D_Output_Color_Mode. */
uint32_t OutputOffset; /*!< Specifies the Offset value.
This parameter must be a number between
Min_Data = 0x0000 and Max_Data = 0x3FFF. */
uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter.
This parameter can be one value of @ref DMA2D_Alpha_Inverted. */
uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR)
for the output pixel format converter.
This parameter can be one value of @ref DMA2D_RB_Swap. */
uint32_t BytesSwap; /*!< Select byte regular mode or bytes swap mode (two by two).
This parameter can be one value of @ref DMA2D_Bytes_Swap. */
uint32_t LineOffsetMode; /*!< Configures how is expressed the line offset for the foreground, background and output.
This parameter can be one value of @ref DMA2D_Line_Offset_Mode. */
} DMA2D_InitTypeDef;
/**
* @brief DMA2D Layer structure definition
*/
typedef struct
{
uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset.
This parameter must be a number between
Min_Data = 0x0000 and Max_Data = 0x3FFF. */
uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode.
This parameter can be one value of @ref DMA2D_Input_Color_Mode. */
uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode.
This parameter can be one value of @ref DMA2D_Alpha_Mode. */
uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value
in case of A8 or A4 color mode.
This parameter must be a number between Min_Data = 0x00
and Max_Data = 0xFF except for the color modes detailed below.
@note In case of A8 or A4 color mode (ARGB),
this parameter must be a number between
Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where
- InputAlpha[24:31] is the alpha value ALPHA[0:7]
- InputAlpha[16:23] is the red value RED[0:7]
- InputAlpha[8:15] is the green value GREEN[0:7]
- InputAlpha[0:7] is the blue value BLUE[0:7]. */
uint32_t AlphaInverted; /*!< Select regular or inverted alpha value.
This parameter can be one value of @ref DMA2D_Alpha_Inverted. */
uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR).
This parameter can be one value of @ref DMA2D_RB_Swap. */
uint32_t ChromaSubSampling; /*!< Configure the chroma sub-sampling mode for the YCbCr color mode
This parameter can be one value of @ref DMA2D_Chroma_Sub_Sampling */
} DMA2D_LayerCfgTypeDef;
/**
* @brief HAL DMA2D State structures definition
*/
typedef enum
{
HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */
HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */
HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */
} HAL_DMA2D_StateTypeDef;
/**
* @brief DMA2D handle Structure definition
*/
typedef struct __DMA2D_HandleTypeDef
{
DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */
DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */
void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer complete callback. */
void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer error callback. */
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
void (* LineEventCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D line event callback. */
void (* CLUTLoadingCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D CLUT loading completion callback */
void (* MspInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp Init callback. */
void (* MspDeInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp DeInit callback. */
#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
HAL_LockTypeDef Lock; /*!< DMA2D lock. */
__IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */
__IO uint32_t ErrorCode; /*!< DMA2D error code. */
} DMA2D_HandleTypeDef;
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
/**
* @brief HAL DMA2D Callback pointer definition
*/
typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointer to a DMA2D common callback function */
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants
* @{
*/
/** @defgroup DMA2D_Error_Code DMA2D Error Code
* @{
*/
#define HAL_DMA2D_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_DMA2D_ERROR_TE 0x00000001U /*!< Transfer error */
#define HAL_DMA2D_ERROR_CE 0x00000002U /*!< Configuration error */
#define HAL_DMA2D_ERROR_CAE 0x00000004U /*!< CLUT access error */
#define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
#define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid callback error */
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup DMA2D_Mode DMA2D Mode
* @{
*/
#define DMA2D_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */
#define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
#define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
#define DMA2D_R2M (DMA2D_CR_MODE_1 | DMA2D_CR_MODE_0) /*!< DMA2D register to memory transfer mode */
#define DMA2D_M2M_BLEND_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color FG */
#define DMA2D_M2M_BLEND_BG (DMA2D_CR_MODE_2 | DMA2D_CR_MODE_0) /*!< DMA2D memory to memory with blending transfer mode and fixed color BG */
/**
* @}
*/
/** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode
* @{
*/
#define DMA2D_OUTPUT_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D color mode */
#define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */
#define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */
#define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */
#define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */
/**
* @}
*/
/** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
* @{
*/
#define DMA2D_INPUT_ARGB8888 0x00000000U /*!< ARGB8888 color mode */
#define DMA2D_INPUT_RGB888 0x00000001U /*!< RGB888 color mode */
#define DMA2D_INPUT_RGB565 0x00000002U /*!< RGB565 color mode */
#define DMA2D_INPUT_ARGB1555 0x00000003U /*!< ARGB1555 color mode */
#define DMA2D_INPUT_ARGB4444 0x00000004U /*!< ARGB4444 color mode */
#define DMA2D_INPUT_L8 0x00000005U /*!< L8 color mode */
#define DMA2D_INPUT_AL44 0x00000006U /*!< AL44 color mode */
#define DMA2D_INPUT_AL88 0x00000007U /*!< AL88 color mode */
#define DMA2D_INPUT_L4 0x00000008U /*!< L4 color mode */
#define DMA2D_INPUT_A8 0x00000009U /*!< A8 color mode */
#define DMA2D_INPUT_A4 0x0000000AU /*!< A4 color mode */
#define DMA2D_INPUT_YCBCR 0x0000000BU /*!< YCbCr color mode */
/**
* @}
*/
/** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
* @{
*/
#define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */
#define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */
#define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value
with original alpha channel value */
/**
* @}
*/
/** @defgroup DMA2D_Alpha_Inverted DMA2D Alpha Inversion
* @{
*/
#define DMA2D_REGULAR_ALPHA 0x00000000U /*!< No modification of the alpha channel value */
#define DMA2D_INVERTED_ALPHA 0x00000001U /*!< Invert the alpha channel value */
/**
* @}
*/
/** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap
* @{
*/
#define DMA2D_RB_REGULAR 0x00000000U /*!< Select regular mode (RGB or ARGB) */
#define DMA2D_RB_SWAP 0x00000001U /*!< Select swap mode (BGR or ABGR) */
/**
* @}
*/
/** @defgroup DMA2D_Line_Offset_Mode DMA2D Line Offset Mode
* @{
*/
#define DMA2D_LOM_PIXELS 0x00000000U /*!< Line offsets expressed in pixels */
#define DMA2D_LOM_BYTES DMA2D_CR_LOM /*!< Line offsets expressed in bytes */
/**
* @}
*/
/** @defgroup DMA2D_Bytes_Swap DMA2D Bytes Swap
* @{
*/
#define DMA2D_BYTES_REGULAR 0x00000000U /*!< Bytes in regular order in output FIFO */
#define DMA2D_BYTES_SWAP DMA2D_OPFCCR_SB /*!< Bytes are swapped two by two in output FIFO */
/**
* @}
*/
/** @defgroup DMA2D_Chroma_Sub_Sampling DMA2D Chroma Sub Sampling
* @{
*/
#define DMA2D_NO_CSS 0x00000000U /*!< No chroma sub-sampling 4:4:4 */
#define DMA2D_CSS_422 0x00000001U /*!< chroma sub-sampling 4:2:2 */
#define DMA2D_CSS_420 0x00000002U /*!< chroma sub-sampling 4:2:0 */
/**
* @}
*/
/** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode
* @{
*/
#define DMA2D_CCM_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D CLUT color mode */
#define DMA2D_CCM_RGB888 0x00000001U /*!< RGB888 DMA2D CLUT color mode */
/**
* @}
*/
/** @defgroup DMA2D_Interrupts DMA2D Interrupts
* @{
*/
#define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
#define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */
#define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
#define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
#define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
#define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
/**
* @}
*/
/** @defgroup DMA2D_Flags DMA2D Flags
* @{
*/
#define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */
#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */
#define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
#define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
#define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
/**
* @}
*/
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
/**
* @brief HAL DMA2D common Callback ID enumeration definition
*/
typedef enum
{
HAL_DMA2D_MSPINIT_CB_ID = 0x00U, /*!< DMA2D MspInit callback ID */
HAL_DMA2D_MSPDEINIT_CB_ID = 0x01U, /*!< DMA2D MspDeInit callback ID */
HAL_DMA2D_TRANSFERCOMPLETE_CB_ID = 0x02U, /*!< DMA2D transfer complete callback ID */
HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */
HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */
HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */
} HAL_DMA2D_CallbackIDTypeDef;
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported macros ------------------------------------------------------------*/
/** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros
* @{
*/
/** @brief Reset DMA2D handle state
* @param __HANDLE__ specifies the DMA2D handle.
* @retval None
*/
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
}while(0)
#else
#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
/**
* @brief Enable the DMA2D.
* @param __HANDLE__ DMA2D handle
* @retval None.
*/
#define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
/* Interrupt & Flag management */
/**
* @brief Get the DMA2D pending flags.
* @param __HANDLE__ DMA2D handle
* @param __FLAG__ flag to check.
* This parameter can be any combination of the following values:
* @arg DMA2D_FLAG_CE: Configuration error flag
* @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
* @arg DMA2D_FLAG_CAE: CLUT access error flag
* @arg DMA2D_FLAG_TW: Transfer Watermark flag
* @arg DMA2D_FLAG_TC: Transfer complete flag
* @arg DMA2D_FLAG_TE: Transfer error flag
* @retval The state of FLAG.
*/
#define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
/**
* @brief Clear the DMA2D pending flags.
* @param __HANDLE__ DMA2D handle
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DMA2D_FLAG_CE: Configuration error flag
* @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
* @arg DMA2D_FLAG_CAE: CLUT access error flag
* @arg DMA2D_FLAG_TW: Transfer Watermark flag
* @arg DMA2D_FLAG_TC: Transfer complete flag
* @arg DMA2D_FLAG_TE: Transfer error flag
* @retval None
*/
#define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
/**
* @brief Enable the specified DMA2D interrupts.
* @param __HANDLE__ DMA2D handle
* @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg DMA2D_IT_CE: Configuration error interrupt mask
* @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
* @arg DMA2D_IT_CAE: CLUT access error interrupt mask
* @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
* @arg DMA2D_IT_TC: Transfer complete interrupt mask
* @arg DMA2D_IT_TE: Transfer error interrupt mask
* @retval None
*/
#define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
/**
* @brief Disable the specified DMA2D interrupts.
* @param __HANDLE__ DMA2D handle
* @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled.
* This parameter can be any combination of the following values:
* @arg DMA2D_IT_CE: Configuration error interrupt mask
* @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
* @arg DMA2D_IT_CAE: CLUT access error interrupt mask
* @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
* @arg DMA2D_IT_TC: Transfer complete interrupt mask
* @arg DMA2D_IT_TE: Transfer error interrupt mask
* @retval None
*/
#define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
/**
* @brief Check whether the specified DMA2D interrupt source is enabled or not.
* @param __HANDLE__ DMA2D handle
* @param __INTERRUPT__ specifies the DMA2D interrupt source to check.
* This parameter can be one of the following values:
* @arg DMA2D_IT_CE: Configuration error interrupt mask
* @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
* @arg DMA2D_IT_CAE: CLUT access error interrupt mask
* @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
* @arg DMA2D_IT_TC: Transfer complete interrupt mask
* @arg DMA2D_IT_TE: Transfer error interrupt mask
* @retval The state of INTERRUPT source.
*/
#define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions
* @{
*/
/** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions *******************************/
HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d);
void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d);
void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID,
pDMA2D_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions
* @{
*/
/* IO operation functions *******************************************************/
HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
uint32_t Height);
HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
uint32_t DstAddress, uint32_t Width, uint32_t Height);
HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
uint32_t Height);
HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
uint32_t DstAddress, uint32_t Width, uint32_t Height);
HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg,
uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg,
uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);
void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);
/**
* @}
*/
/** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
/* Peripheral Control functions *************************************************/
HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);
/**
* @}
*/
/** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
* @{
*/
/* Peripheral State functions ***************************************************/
HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(const DMA2D_HandleTypeDef *hdma2d);
uint32_t HAL_DMA2D_GetError(const DMA2D_HandleTypeDef *hdma2d);
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup DMA2D_Private_Constants DMA2D Private Constants
* @{
*/
/** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark
* @{
*/
#define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */
/**
* @}
*/
/** @defgroup DMA2D_Color_Value DMA2D Color Value
* @{
*/
#define DMA2D_COLOR_VALUE 0x000000FFU /*!< Color value mask */
/**
* @}
*/
/** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers
* @{
*/
#define DMA2D_MAX_LAYER 2U /*!< DMA2D maximum number of layers */
/**
* @}
*/
/** @defgroup DMA2D_Layers DMA2D Layers
* @{
*/
#define DMA2D_BACKGROUND_LAYER 0x00000000U /*!< DMA2D Background Layer (layer 0) */
#define DMA2D_FOREGROUND_LAYER 0x00000001U /*!< DMA2D Foreground Layer (layer 1) */
/**
* @}
*/
/** @defgroup DMA2D_Offset DMA2D Offset
* @{
*/
#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< maximum Line Offset */
/**
* @}
*/
/** @defgroup DMA2D_Size DMA2D Size
* @{
*/
#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D maximum number of pixels per line */
#define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D maximum number of lines */
/**
* @}
*/
/** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size
* @{
*/
#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U) /*!< DMA2D maximum CLUT size */
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup DMA2D_Private_Macros DMA2D Private Macros
* @{
*/
#define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER)\
|| ((LAYER) == DMA2D_FOREGROUND_LAYER))
#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M) || \
((MODE) == DMA2D_M2M_BLEND_FG) || ((MODE) == DMA2D_M2M_BLEND_BG))
#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || \
((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || \
((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE)
#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \
((INPUT_CM) == DMA2D_INPUT_RGB888) || \
((INPUT_CM) == DMA2D_INPUT_RGB565) || \
((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
((INPUT_CM) == DMA2D_INPUT_ARGB4444) || \
((INPUT_CM) == DMA2D_INPUT_L8) || \
((INPUT_CM) == DMA2D_INPUT_AL44) || \
((INPUT_CM) == DMA2D_INPUT_AL88) || \
((INPUT_CM) == DMA2D_INPUT_L4) || \
((INPUT_CM) == DMA2D_INPUT_A8) || \
((INPUT_CM) == DMA2D_INPUT_A4) || \
((INPUT_CM) == DMA2D_INPUT_YCBCR))
#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
((AlphaMode) == DMA2D_COMBINE_ALPHA))
#define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \
((Alpha_Inverted) == DMA2D_INVERTED_ALPHA))
#define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \
((RB_Swap) == DMA2D_RB_SWAP))
#define IS_DMA2D_LOM_MODE(LOM) (((LOM) == DMA2D_LOM_PIXELS) || \
((LOM) == DMA2D_LOM_BYTES))
#define IS_DMA2D_BYTES_SWAP(BYTES_SWAP) (((BYTES_SWAP) == DMA2D_BYTES_REGULAR) || \
((BYTES_SWAP) == DMA2D_BYTES_SWAP))
#define IS_DMA2D_CHROMA_SUB_SAMPLING(CSS) (((CSS) == DMA2D_NO_CSS) || \
((CSS) == DMA2D_CSS_422) || \
((CSS) == DMA2D_CSS_420))
#define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
/**
* @}
*/
/**
* @}
*/
#endif /* defined (DMA2D) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H7RSxx_HAL_DMA2D_H */
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_dma_ex.h
+719
View File
@@ -0,0 +1,719 @@
/**
**********************************************************************************************************************
* @file stm32h7rsxx_hal_dma_ex.h
* @author MCD Application Team
* @brief Header file of DMA HAL extension module.
**********************************************************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
**********************************************************************************************************************
*/
/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/
#ifndef STM32H7RSxx_HAL_DMA_EX_H
#define STM32H7RSxx_HAL_DMA_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ----------------------------------------------------------------------------------------------------------*/
#include "stm32h7rsxx_hal_def.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @addtogroup DMAEx
* @{
*/
/* Exported types ----------------------------------------------------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
* @brief DMAEx Exported types
* @{
*/
/**
* @brief DMAEx Data Handling Configuration Structure Definition.
*/
typedef struct
{
uint32_t DataExchange; /*!< Specifies the DMA channel data exchange mode.
This parameter can be a value of @ref DMAEx_Data_Exchange */
uint32_t DataAlignment; /*!< Specifies the DMA channel data padding and alignment mode
This parameter can be a value of @ref DMAEx_Data_Alignment */
} DMA_DataHandlingConfTypeDef;
/**
* @brief DMAEx Trigger Configuration Structure Definition.
*/
typedef struct
{
uint32_t TriggerMode; /*!< Specifies the DMA channel trigger mode.
This parameter can be a value of @ref DMAEx_Trigger_Mode */
uint32_t TriggerPolarity; /*!< Specifies the DMA channel trigger event polarity.
This parameter can be a value of @ref DMAEx_Trigger_Polarity */
uint32_t TriggerSelection; /*!< Specifies the DMA channel trigger event selection.
This parameter can be a value of @ref DMAEx_Trigger_Selection */
} DMA_TriggerConfTypeDef;
/**
* @brief DMAEx Repeated Block Configuration Structure Definition.
*/
typedef struct
{
uint32_t RepeatCount; /*!< Specifies the DMA channel repeat count (the number of repetitions of block).
This parameter can be a value between 1 and 2048 */
int32_t SrcAddrOffset; /*!< Specifies the DMA channel single/burst source address offset :
This parameter can be a value between -8191 and 8191.
* If source address offset > 0 => Increment the source address by offset from where
the last single/burst transfer ends.
* If source address offset < 0 => Decrement the source address by offset from where
the last single/burst transfer ends.
* If source address offset == 0 => The next single/burst source address starts from
where the last transfer ends */
int32_t DestAddrOffset; /*!< Specifies the DMA channel single/burst destination address offset signed value :
This parameter can be a value between -8191 and 8191.
* If destination address offset > 0 => Increment the destination address by offset
from where the last single/burst transfer ends.
* If destination address offset < 0 => Decrement the destination address by offset
from where the last single/burst transfer ends.
* If destination address offset == 0 => The next single/burst destination address
starts from where the last transfer ends. */
int32_t BlkSrcAddrOffset; /*!< Specifies the DMA channel block source address offset signed value :
This parameter can be a value between -65535 and 65535.
* If block source address offset > 0 => Increment the block source address by offset
from where the last block ends.
* If block source address offset < 0 => Decrement the next block source address by
offset from where the last block ends.
* If block source address offset == 0 => the next block source address starts from
where the last block ends */
int32_t BlkDestAddrOffset; /*!< Specifies the DMA channel block destination address offset signed value :
This parameter can be a value between -65535 and 65535.
* If block destination address offset > 0 => Increment the block destination address
by offset from where the last block ends.
* If block destination address offset < 0 => Decrement the next block destination
address by offset from where the last block ends.
* If block destination address offset == 0 => the next block destination address
starts from where the last block ends */
} DMA_RepeatBlockConfTypeDef;
/**
* @brief DMAEx Queue State Enumeration Definition.
*/
typedef enum
{
HAL_DMA_QUEUE_STATE_RESET = 0x00U, /*!< DMA queue empty */
HAL_DMA_QUEUE_STATE_READY = 0x01U, /*!< DMA queue ready for use */
HAL_DMA_QUEUE_STATE_BUSY = 0x02U /*!< DMA queue execution on going */
} HAL_DMA_QStateTypeDef;
/**
* @brief DMAEx Linked-List Node Configuration Structure Definition.
*/
typedef struct
{
uint32_t NodeType; /*!< Specifies the DMA channel node type.
This parameter can be a value of @ref DMAEx_Node_Type */
DMA_InitTypeDef Init; /*!< Specifies the DMA channel basic configuration */
DMA_DataHandlingConfTypeDef DataHandlingConfig; /*!< Specifies the DMA channel data handling channel configuration */
DMA_TriggerConfTypeDef TriggerConfig; /*!< Specifies the DMA channel trigger configuration */
DMA_RepeatBlockConfTypeDef RepeatBlockConfig; /*!< Specifies the DMA channel repeated block configuration */
uint32_t SrcAddress; /*!< Specifies the source memory address */
uint32_t DstAddress; /*!< Specifies the destination memory address */
uint32_t DataSize; /*!< Specifies the source data size in bytes */
} DMA_NodeConfTypeDef;
/**
* @brief DMAEx Linked-List Node Structure Definition.
*/
typedef struct
{
uint32_t LinkRegisters[8U]; /*!< Physical Node register description */
uint32_t NodeInfo; /*!< Node information */
} DMA_NodeTypeDef;
/**
* @brief DMAEx Linked-List Queue Structure Definition.
*/
typedef struct __DMA_QListTypeDef
{
DMA_NodeTypeDef *Head; /*!< Specifies the queue head node */
DMA_NodeTypeDef *FirstCircularNode; /*!< Specifies the queue first circular node */
uint32_t NodeNumber; /*!< Specifies the queue node number */
__IO HAL_DMA_QStateTypeDef State; /*!< Specifies the queue state */
__IO uint32_t ErrorCode; /*!< Specifies the queue error code */
__IO uint32_t Type; /*!< Specifies whether the queue is static or dynamic */
} DMA_QListTypeDef;
/**
* @}
*/
/* Exported constants ------------------------------------------------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
* @brief DMAEx Exported Constants
* @{
*/
/** @defgroup Queue_Error_Codes Queue Error Codes
* @brief Queue Error Codes
* @{
*/
#define HAL_DMA_QUEUE_ERROR_NONE (0x00U) /*!< No error */
#define HAL_DMA_QUEUE_ERROR_BUSY (0x01U) /*!< Error busy */
#define HAL_DMA_QUEUE_ERROR_EMPTY (0x02U) /*!< Error unallowed operation for empty queue */
#define HAL_DMA_QUEUE_ERROR_UNSUPPORTED (0x03U) /*!< Error unsupported feature */
#define HAL_DMA_QUEUE_ERROR_INVALIDTYPE (0x04U) /*!< Error incompatible node type or circular initialization
and queue circular types are incompatible */
#define HAL_DMA_QUEUE_ERROR_OUTOFRANGE (0x05U) /*!< Error out of range node memory */
#define HAL_DMA_QUEUE_ERROR_NOTFOUND (0x06U) /*!< Error node not found in queue */
/**
* @}
*/
/** @defgroup DMAEx_LinkedList_Mode DMAEx LinkedList Mode
* @brief DMAEx LinkedList Mode
* @{
*/
#define DMA_LINKEDLIST_NORMAL DMA_LINKEDLIST /*!< Linear linked-list DMA channel transfer */
#define DMA_LINKEDLIST_CIRCULAR (DMA_LINKEDLIST | (0x01U)) /*!< Circular linked-list DMA channel transfer */
/**
* @}
*/
/** @defgroup DMAEx_Data_Alignment DMAEx Data Alignment
* @brief DMAEx Data Alignment
* @{
*/
#define DMA_DATA_RIGHTALIGN_ZEROPADDED 0x00000000U /*!< If source data width < destination data width
=> Right aligned padded with 0 up to destination data
width */
#define DMA_DATA_RIGHTALIGN_LEFTTRUNC 0x00000000U /*!< If source data width > destination data width
=> Right aligned left Truncated down to destination
data width */
#define DMA_DATA_RIGHTALIGN_SIGNEXT DMA_CTR1_PAM_0 /*!< If source data width < destination data width
=> Right Aligned padded with sign extended up to
destination data width */
#define DMA_DATA_LEFTALIGN_RIGHTTRUNC DMA_CTR1_PAM_0 /*!< If source data width > destination data width
=> Left Aligned Right Truncated down to the
destination data width */
#define DMA_DATA_PACK DMA_CTR1_PAM_1 /*!< If source data width < destination data width
=> Packed at the destination data width */
#define DMA_DATA_UNPACK DMA_CTR1_PAM_1 /*!< If source data width > destination data width
=> Unpacked at the destination data width */
/**
* @}
*/
/** @defgroup DMAEx_Data_Exchange DMAEx Data Exchange
* @brief DMAEx Data Exchange
* @{
*/
#define DMA_EXCHANGE_NONE 0x00000000U /*!< No data exchange */
#define DMA_EXCHANGE_DEST_BYTE DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width is > Byte */
#define DMA_EXCHANGE_DEST_HALFWORD DMA_CTR1_DHX /*!< Destination Half-Word exchange when destination data width is > Half-Word */
#define DMA_EXCHANGE_SRC_BYTE DMA_CTR1_SBX /*!< Source Byte endianness exchange when source data width is word */
#define DMA_EXCHANGE_DEST_WORD DMA_CTR1_DWX /*!< Destination Word exchange when destination data width is > Word */
/**
* @}
*/
/** @defgroup DMAEx_Trigger_Polarity DMAEx Trigger Polarity
* @brief DMAEx Trigger Polarity
* @{
*/
#define DMA_TRIG_POLARITY_MASKED 0x00000000U /*!< No trigger of the selected DMA request. Masked trigger event */
#define DMA_TRIG_POLARITY_RISING DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising edge of the selected trigger event input */
#define DMA_TRIG_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling edge of the selected trigger event input */
/**
* @}
*/
/** @defgroup DMAEx_Trigger_Mode DMAEx Trigger Mode
* @brief DMAEx Trigger Mode
* @{
*/
#define DMA_TRIGM_BLOCK_TRANSFER 0x00000000U /*!< A block transfer is conditioned by (at least) one hit trigger */
#define DMA_TRIGM_REPEATED_BLOCK_TRANSFER DMA_CTR2_TRIGM_0 /*!< A repeated block transfer is conditioned by (at least) one hit trigger */
#define DMA_TRIGM_LLI_LINK_TRANSFER DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least) one hit trigger */
#define DMA_TRIGM_SINGLE_BURST_TRANSFER DMA_CTR2_TRIGM /*!< A single/burst transfer is conditioned by (at least) one hit trigger */
/**
* @}
*/
/** @defgroup DMAEx_Trigger_Selection DMAEx Trigger Selection
* @brief DMAEx Trigger Selection
* @{
*/
/* HPDMA1 triggers */
#define HPDMA1_TRIGGER_DCMIPP_EVT_FRAMEEND 0U /*!< HPDMA1 HW Trigger signal is DCMIPP_EVT_FRAMEEND */
#define HPDMA1_TRIGGER_DCMIPP_EVT_HSYNC 1U /*!< HPDMA1 HW Trigger signal is DCMIPP_EVT_HSYNC */
#define HPDMA1_TRIGGER_DCMIPP_EVT_LINEEND 2U /*!< HPDMA1 HW Trigger signal is DCMIPP_EVT_LINEEND */
#define HPDMA1_TRIGGER_DCMIPP_EVT_VSYNC 3U /*!< HPDMA1 HW Trigger signal is DCMIPP_EVT_VSYNC */
#define HPDMA1_TRIGGER_DMA2D_CTC_FLAG 4U /*!< HPDMA1 HW Trigger signal is DMA2D_CTC_FLAG */
#define HPDMA1_TRIGGER_DMA2D_TC_FLAG 5U /*!< HPDMA1 HW Trigger signal is DMA2D_TC_FLAG */
#define HPDMA1_TRIGGER_DMA2D_TW_FLAG 6U /*!< HPDMA1 HW Trigger signal is DMA2D_TW_FLAG */
#define HPDMA1_TRIGGER_JPEG_EOC_FLAG 7U /*!< HPDMA1 HW Trigger signal is JPEG_EOC_FLAG */
#define HPDMA1_TRIGGER_JPEG_IFNF_FLAG 8U /*!< HPDMA1 HW Trigger signal is JPEG_IFNF_FLAG */
#define HPDMA1_TRIGGER_JPEG_IFT_FLAG 9U /*!< HPDMA1 HW Trigger signal is JPEG_IFT_FLAG */
#define HPDMA1_TRIGGER_JPEG_OFNE_FLAG 10U /*!< HPDMA1 HW Trigger signal is JPEG_OFNE_FLAG */
#define HPDMA1_TRIGGER_JPEG_OFT_FLAG 11U /*!< HPDMA1 HW Trigger signal is JPEG_OFT_FLAG */
#define HPDMA1_TRIGGER_LCD 12U /*!< HPDMA1 HW Trigger signal is LCD */
#define HPDMA1_TRIGGER_GPU2D1_GP_FLAG0 13U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_FLAG0 */
#define HPDMA1_TRIGGER_GPU2D1_GP_FLAG1 14U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_FLAG1 */
#define HPDMA1_TRIGGER_GPU2D1_GP_FLAG2 15U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_FLAG2 */
#define HPDMA1_TRIGGER_GPU2D1_GP_FLAG3 16U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_FLAG3 */
#define HPDMA1_TRIGGER_GFXTIM_0_EVT_4 17U /*!< HPDMA1 HW Trigger signal is GFXTIM_0_EVT_4 */
#define HPDMA1_TRIGGER_GFXTIM_0_EVT_3 18U /*!< HPDMA1 HW Trigger signal is GFXTIM_0_EVT_3 */
#define HPDMA1_TRIGGER_GFXTIM_0_EVT_2 19U /*!< HPDMA1 HW Trigger signal is GFXTIM_0_EVT_2 */
#define HPDMA1_TRIGGER_GFXTIM_0_EVT_1 20U /*!< HPDMA1 HW Trigger signal is GFXTIM_0_EVT_1 */
#define HPDMA1_TRIGGER_GPDMA1_CH0_TCF 21U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */
#define HPDMA1_TRIGGER_GPDMA1_CH1_TCF 22U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */
#define HPDMA1_TRIGGER_GPDMA1_CH2_TCF 23U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */
#define HPDMA1_TRIGGER_GPDMA1_CH3_TCF 24U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */
#define HPDMA1_TRIGGER_GPDMA1_CH4_TCF 25U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */
#define HPDMA1_TRIGGER_GPDMA1_CH5_TCF 26U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */
#define HPDMA1_TRIGGER_GPDMA1_CH6_TCF 27U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */
#define HPDMA1_TRIGGER_GPDMA1_CH7_TCF 28U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */
#define HPDMA1_TRIGGER_GPDMA1_CH8_TCF 29U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH8_TCF */
#define HPDMA1_TRIGGER_GPDMA1_CH9_TCF 30U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH9_TCF */
#define HPDMA1_TRIGGER_GPDMA1_CH10_TCF 31U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH10_TCF */
#define HPDMA1_TRIGGER_GPDMA1_CH11_TCF 32U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH11_TCF */
#define HPDMA1_TRIGGER_GPDMA1_CH12_TCF 33U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */
#define HPDMA1_TRIGGER_GPDMA1_CH13_TCF 34U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */
#define HPDMA1_TRIGGER_GPDMA1_CH14_TCF 35U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH14_TCF */
#define HPDMA1_TRIGGER_GPDMA1_CH15_TCF 36U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH15_TCF */
#define HPDMA1_TRIGGER_HPDMA1_CH0_TCF 37U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH0_TCF */
#define HPDMA1_TRIGGER_HPDMA1_CH1_TCF 38U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH1_TCF */
#define HPDMA1_TRIGGER_HPDMA1_CH2_TCF 39U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH2_TCF */
#define HPDMA1_TRIGGER_HPDMA1_CH3_TCF 40U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH3_TCF */
#define HPDMA1_TRIGGER_HPDMA1_CH4_TCF 41U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH4_TCF */
#define HPDMA1_TRIGGER_HPDMA1_CH5_TCF 42U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH5_TCF */
#define HPDMA1_TRIGGER_HPDMA1_CH6_TCF 43U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH6_TCF */
#define HPDMA1_TRIGGER_HPDMA1_CH7_TCF 44U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH7_TCF */
#define HPDMA1_TRIGGER_HPDMA1_CH8_TCF 45U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH8_TCF */
#define HPDMA1_TRIGGER_HPDMA1_CH9_TCF 46U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH9_TCF */
#define HPDMA1_TRIGGER_HPDMA1_CH10_TCF 47U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH10_TCF */
#define HPDMA1_TRIGGER_HPDMA1_CH11_TCF 48U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH11_TCF */
#define HPDMA1_TRIGGER_HPDMA1_CH12_TCF 49U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH12_TCF */
#define HPDMA1_TRIGGER_HPDMA1_CH13_TCF 50U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH13_TCF */
#define HPDMA1_TRIGGER_HPDMA1_CH14_TCF 51U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH14_TCF */
#define HPDMA1_TRIGGER_HPDMA1_CH15_TCF 52U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH15_TCF */
/* GPDMA1 triggers */
#define GPDMA1_TRIGGER_HPDMA1_CH0_TCF 0U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH0_TCF */
#define GPDMA1_TRIGGER_HPDMA1_CH1_TCF 1U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH1_TCF */
#define GPDMA1_TRIGGER_HPDMA1_CH2_TCF 2U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH2_TCF */
#define GPDMA1_TRIGGER_HPDMA1_CH3_TCF 3U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH3_TCF */
#define GPDMA1_TRIGGER_HPDMA1_CH4_TCF 4U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH4_TCF */
#define GPDMA1_TRIGGER_HPDMA1_CH5_TCF 5U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH5_TCF */
#define GPDMA1_TRIGGER_HPDMA1_CH6_TCF 6U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH6_TCF */
#define GPDMA1_TRIGGER_HPDMA1_CH7_TCF 7U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH7_TCF */
#define GPDMA1_TRIGGER_HPDMA1_CH8_TCF 8U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH8_TCF */
#define GPDMA1_TRIGGER_HPDMA1_CH9_TCF 9U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH9_TCF */
#define GPDMA1_TRIGGER_HPDMA1_CH10_TCF 10U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH10_TCF */
#define GPDMA1_TRIGGER_HPDMA1_CH11_TCF 11U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH11_TCF */
#define GPDMA1_TRIGGER_HPDMA1_CH12_TCF 12U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH12_TCF */
#define GPDMA1_TRIGGER_HPDMA1_CH13_TCF 13U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH13_TCF */
#define GPDMA1_TRIGGER_HPDMA1_CH14_TCF 14U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH14_TCF */
#define GPDMA1_TRIGGER_HPDMA1_CH15_TCF 15U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH15_TCF */
#define GPDMA1_TRIGGER_LPTIM1_CH1 16U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH1 */
#define GPDMA1_TRIGGER_LPTIM1_CH2 17U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH2 */
#define GPDMA1_TRIGGER_LPTIM2_CH1 18U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1 */
#define GPDMA1_TRIGGER_LPTIM2_CH2 19U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */
#define GPDMA1_TRIGGER_LPTIM3_CH1 20U /*!< GPDMA1 HW Trigger signal is LPTIM3_CH1 */
#define GPDMA1_TRIGGER_LPTIM3_CH2 21U /*!< GPDMA1 HW Trigger signal is LPTIM3_CH2 */
#define GPDMA1_TRIGGER_LPTIM4_OUT 22U /*!< GPDMA1 HW Trigger signal is LPTIM4_OUT */
#define GPDMA1_TRIGGER_LPTIM5_OUT 23U /*!< GPDMA1 HW Trigger signal is LPTIM5_OUT */
#define GPDMA1_TRIGGER_EXTIT0_SYNC 24U /*!< GPDMA1 HW Trigger signal is EXTIT0_SYNC */
#define GPDMA1_TRIGGER_RTC_WKUP 25U /*!< GPDMA1 HW Trigger signal is RTC_WKUP */
#define GPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC 26U /*!< GPDMA1 HW Trigger signal is R_WUP_ASYNC */
#define GPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC 27U /*!< GPDMA1 HW Trigger signal is T_WUP_ASYNC */
#define GPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC 28U /*!< GPDMA1 HW Trigger signal is SPI6_OR_SPI6_AIT_SYNC */
#define GPDMA1_TRIGGER_GPDMA1_CH0_TCF 29U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH1_TCF 30U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH2_TCF 31U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH3_TCF 32U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH4_TCF 33U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH5_TCF 34U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH6_TCF 35U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH7_TCF 36U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH8_TCF 37U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH8_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH9_TCF 38U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH9_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH10_TCF 39U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH10_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH11_TCF 40U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH11_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH12_TCF 41U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH13_TCF 42U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH14_TCF 43U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH14_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH15_TCF 44U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH15_TCF */
#define GPDMA1_TRIGGER_TIM1_TRGO 45U /*!< GPDMA1 HW Trigger signal is TIM1_TRGO */
#define GPDMA1_TRIGGER_TIM1_TRGO2 46U /*!< GPDMA1 HW Trigger signal is TIM1_TRGO2 */
#define GPDMA1_TRIGGER_TIM2_TRGO 47U /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */
#define GPDMA1_TRIGGER_TIM3_TRGO 48U /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */
#define GPDMA1_TRIGGER_TIM4_TRGO 49U /*!< GPDMA1 HW Trigger signal is TIM4_TRGO */
#define GPDMA1_TRIGGER_TIM5_TRGO 50U /*!< GPDMA1 HW Trigger signal is TIM5_TRGO */
#define GPDMA1_TRIGGER_TIM6_TRGO 51U /*!< GPDMA1 HW Trigger signal is TIM6_TRGO */
#define GPDMA1_TRIGGER_TIM7_TRGO 52U /*!< GPDMA1 HW Trigger signal is TIM7_TRGO */
#define GPDMA1_TRIGGER_TIM9_TRGO 53U /*!< GPDMA1 HW Trigger signal is TIM9_TRGO */
#define GPDMA1_TRIGGER_TIM12_TRGO 54U /*!< GPDMA1 HW Trigger signal is TIM12_TRGO */
#define GPDMA1_TRIGGER_TIM15_TRGO 55U /*!< GPDMA1 HW Trigger signal is TIM15_TRGO */
#define GPDMA1_MAX_TRIGGER 55U
/**
* @}
*/
/** @defgroup DMAEx_Node_Type DMAEx Node Type
* @brief DMAEx Node Type
* @{
*/
#define DMA_GPDMA_LINEAR_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_LINEAR_ADDR) /*!< Defines the GPDMA linear addressing node type */
#define DMA_GPDMA_2D_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_2D_ADDR) /*!< Defines the GPDMA 2 dimension addressing node type */
#define DMA_HPDMA_LINEAR_NODE (DMA_CHANNEL_TYPE_HPDMA | DMA_CHANNEL_TYPE_LINEAR_ADDR) /*!< Defines the HPDMA linear addressing node type */
#define DMA_HPDMA_2D_NODE (DMA_CHANNEL_TYPE_HPDMA | DMA_CHANNEL_TYPE_2D_ADDR) /*!< Defines the HPDMA 2 dimension addressing node type */
/**
* @}
*/
/** @defgroup DMAEx_Link_Allocated_Port DMAEx Linked-List Allocated Port
* @brief DMAEx Linked-List Allocated Port
* @{
*/
#define DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Link allocated port 0 */
#define DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Link allocated port 1 */
/**
* @}
*/
/** @defgroup DMAEx_Link_Step_Mode DMAEx Link Step Mode
* @brief DMAEx Link Step Mode
* @{
*/
#define DMA_LSM_FULL_EXECUTION 0x00000000U /*!< Channel is executed for the full linked-list */
#define DMA_LSM_1LINK_EXECUTION DMA_CCR_LSM /*!< Channel is executed once for the current LLI */
/**
* @}
*/
/**
* @}
*/
/* Exported functions ------------------------------------------------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
* @brief DMAEx Exported functions
* @{
*/
/** @defgroup DMAEx_Exported_Functions_Group1 Linked-List Initialization and De-Initialization Functions
* @brief Linked-List Initialization and De-Initialization Functions
* @{
*/
HAL_StatusTypeDef HAL_DMAEx_List_Init(DMA_HandleTypeDef *const hdma);
HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma);
/**
* @}
*/
/** @defgroup DMAEx_Exported_Functions_Group2 Linked-List IO Operation Functions
* @brief Linked-List IO Operation Functions
* @{
*/
HAL_StatusTypeDef HAL_DMAEx_List_Start(DMA_HandleTypeDef *const hdma);
HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma);
/**
* @}
*/
/** @defgroup DMAEx_Exported_Functions_Group3 Linked-List Management Functions
* @brief Linked-List Management Functions
* @{
*/
HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig,
DMA_NodeTypeDef *const pNode);
HAL_StatusTypeDef HAL_DMAEx_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig,
DMA_NodeTypeDef const *const pNode);
HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList,
DMA_NodeTypeDef *const pPrevNode,
DMA_NodeTypeDef *const pNewNode);
HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList,
DMA_NodeTypeDef *const pNewNode);
HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList,
DMA_NodeTypeDef *const pNewNode);
HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode(DMA_QListTypeDef *const pQList,
DMA_NodeTypeDef *const pNode);
HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Head(DMA_QListTypeDef *const pQList);
HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Tail(DMA_QListTypeDef *const pQList);
HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList,
DMA_NodeTypeDef *const pOldNode,
DMA_NodeTypeDef *const pNewNode);
HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList,
DMA_NodeTypeDef *const pNewNode);
HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Tail(DMA_QListTypeDef *const pQList,
DMA_NodeTypeDef *const pNewNode);
HAL_StatusTypeDef HAL_DMAEx_List_ResetQ(DMA_QListTypeDef *const pQList);
HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList,
DMA_NodeTypeDef const *const pPrevNode,
DMA_QListTypeDef *const pDestQList);
HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList,
DMA_QListTypeDef *const pDestQList);
HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList,
DMA_QListTypeDef *const pDestQList);
HAL_StatusTypeDef HAL_DMAEx_List_SetCircularModeConfig(DMA_QListTypeDef *const pQList,
DMA_NodeTypeDef *const pFirstCircularNode);
HAL_StatusTypeDef HAL_DMAEx_List_SetCircularMode(DMA_QListTypeDef *const pQList);
HAL_StatusTypeDef HAL_DMAEx_List_ClearCircularMode(DMA_QListTypeDef *const pQList);
HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToDynamic(DMA_QListTypeDef *const pQList);
HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToStatic(DMA_QListTypeDef *const pQList);
HAL_StatusTypeDef HAL_DMAEx_List_LinkQ(DMA_HandleTypeDef *const hdma,
DMA_QListTypeDef *const pQList);
HAL_StatusTypeDef HAL_DMAEx_List_UnLinkQ(DMA_HandleTypeDef *const hdma);
/**
* @}
*/
/** @defgroup DMAEx_Exported_Functions_Group4 Data Handling, Repeated Block and Trigger Configuration Functions
* @brief Data Handling, Repeated Block and Trigger Configuration Functions
* @{
*/
HAL_StatusTypeDef HAL_DMAEx_ConfigDataHandling(DMA_HandleTypeDef *const hdma,
DMA_DataHandlingConfTypeDef const *const pConfigDataHandling);
HAL_StatusTypeDef HAL_DMAEx_ConfigTrigger(DMA_HandleTypeDef *const hdma,
DMA_TriggerConfTypeDef const *const pConfigTrigger);
HAL_StatusTypeDef HAL_DMAEx_ConfigRepeatBlock(DMA_HandleTypeDef *const hdma,
DMA_RepeatBlockConfTypeDef const *const pConfigRepeatBlock);
/**
* @}
*/
/** @defgroup DMAEx_Exported_Functions_Group5 Suspend and Resume Operation Functions
* @brief Suspend and Resume Operation Functions
* @{
*/
HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma);
HAL_StatusTypeDef HAL_DMAEx_Suspend_IT(DMA_HandleTypeDef *const hdma);
HAL_StatusTypeDef HAL_DMAEx_Resume(DMA_HandleTypeDef *const hdma);
/**
* @}
*/
/** @defgroup DMAEx_Exported_Functions_Group6 FIFO Status Function
* @brief FIFO Status Function
* @{
*/
uint32_t HAL_DMAEx_GetFifoLevel(DMA_HandleTypeDef const *const hdma);
/**
* @}
*/
/**
* @}
*/
/* Private types -----------------------------------------------------------------------------------------------------*/
/** @defgroup DMAEx_Private_Types DMAEx Private Types
* @brief DMAEx Private Types
* @{
*/
/**
* @brief DMA Node in Queue Information Structure Definition.
*/
typedef struct
{
uint32_t cllr_offset; /* CLLR register offset */
uint32_t previousnode_addr; /* Previous node address */
uint32_t currentnode_pos; /* Current node position */
uint32_t currentnode_addr; /* Current node address */
uint32_t nextnode_addr; /* Next node address */
} DMA_NodeInQInfoTypeDef;
/**
* @}
*/
/* Private constants -------------------------------------------------------------------------------------------------*/
/** @defgroup DMAEx_Private_Constants DMAEx Private Constants
* @brief DMAEx Private Constants
* @{
*/
#define DMA_LINKEDLIST (0x0080UL) /* DMA channel linked-list mode */
#define DMA_CHANNEL_TYPE_LINEAR_ADDR (0x0001UL) /* DMA channel linear addressing mode */
#define DMA_CHANNEL_TYPE_2D_ADDR (0x0002UL) /* DMA channel 2D addressing mode */
#define DMA_CHANNEL_TYPE_GPDMA (0x0020UL) /* GPDMA channel node */
#define DMA_CHANNEL_TYPE_HPDMA (0x0040UL) /* HPDMA channel node */
#define NODE_TYPE_MASK (0x00FFUL) /* DMA channel node type */
#define NODE_CLLR_IDX (0x0700UL) /* DMA channel node CLLR index mask */
#define NODE_CLLR_IDX_POS (0x0008UL) /* DMA channel node CLLR index position */
#define NODE_MAXIMUM_SIZE (0x0008UL) /* Amount of registers of the node */
#define NODE_STATIC_FORMAT (0x0000UL) /* DMA channel node static format */
#define NODE_DYNAMIC_FORMAT (0x0001UL) /* DMA channel node dynamic format */
#define UPDATE_CLLR_POSITION (0x0000UL) /* DMA channel update CLLR position */
#define UPDATE_CLLR_VALUE (0x0001UL) /* DMA channel update CLLR value */
#define LASTNODE_ISNOT_CIRCULAR (0x0000UL) /* Last node is not first circular node */
#define LASTNODE_IS_CIRCULAR (0x0001UL) /* Last node is first circular node */
#define QUEUE_TYPE_STATIC (0x0000UL) /* DMA channel static queue */
#define QUEUE_TYPE_DYNAMIC (0x0001UL) /* DMA channel dynamic queue */
#define NODE_CTR1_DEFAULT_OFFSET (0x0000UL) /* CTR1 default offset */
#define NODE_CTR2_DEFAULT_OFFSET (0x0001UL) /* CTR2 default offset */
#define NODE_CBR1_DEFAULT_OFFSET (0x0002UL) /* CBR1 default offset */
#define NODE_CSAR_DEFAULT_OFFSET (0x0003UL) /* CSAR default offset */
#define NODE_CDAR_DEFAULT_OFFSET (0x0004UL) /* CDAR default offset */
#define NODE_CTR3_DEFAULT_OFFSET (0x0005UL) /* CTR3 2D addressing default offset */
#define NODE_CBR2_DEFAULT_OFFSET (0x0006UL) /* CBR2 2D addressing default offset */
#define NODE_CLLR_2D_DEFAULT_OFFSET (0x0007UL) /* CLLR 2D addressing default offset */
#define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x0005UL) /* CLLR linear addressing default offset */
#define DMA_BURST_ADDR_OFFSET_MIN (-8192L) /* DMA burst minimum address offset */
#define DMA_BURST_ADDR_OFFSET_MAX (8192L) /* DMA burst maximum address offset */
#define DMA_BLOCK_ADDR_OFFSET_MIN (-65536L) /* DMA block minimum address offset */
#define DMA_BLOCK_ADDR_OFFSET_MAX (65536L) /* DMA block maximum address offset */
/**
* @}
*/
/* Private macros ----------------------------------------------------------------------------------------------------*/
/** @defgroup DMAEx_Private_Macros DMAEx Private Macros
* @brief DMAEx Private Macros
* @{
*/
#define IS_DMA_DATA_ALIGNMENT(ALIGNMENT) \
(((ALIGNMENT) == DMA_DATA_RIGHTALIGN_ZEROPADDED) || \
((ALIGNMENT) == DMA_DATA_RIGHTALIGN_SIGNEXT) || \
((ALIGNMENT) == DMA_DATA_PACK))
#define IS_DMA_DATA_EXCHANGE(EXCHANGE) \
(((EXCHANGE) & (~(DMA_EXCHANGE_SRC_BYTE | DMA_EXCHANGE_DEST_BYTE | DMA_EXCHANGE_DEST_HALFWORD | \
DMA_EXCHANGE_DEST_WORD))) == 0U)
#define IS_DMA_REPEAT_COUNT(COUNT) \
(((COUNT) > 0U) && ((COUNT) <= (DMA_CBR1_BRC >> DMA_CBR1_BRC_Pos)))
#define IS_DMA_BURST_ADDR_OFFSET(BURST_ADDR_OFFSET) \
(((BURST_ADDR_OFFSET) > DMA_BURST_ADDR_OFFSET_MIN) && \
((BURST_ADDR_OFFSET) < DMA_BURST_ADDR_OFFSET_MAX))
#define IS_DMA_BLOCK_ADDR_OFFSET(BLOCK_ADDR_OFFSET) \
(((BLOCK_ADDR_OFFSET) > DMA_BLOCK_ADDR_OFFSET_MIN) && \
((BLOCK_ADDR_OFFSET) < DMA_BLOCK_ADDR_OFFSET_MAX))
#define IS_DMA_LINK_ALLOCATED_PORT(LINK_ALLOCATED_PORT) \
(((LINK_ALLOCATED_PORT) & (~(DMA_CCR_LAP))) == 0U)
#define IS_DMA_LINK_STEP_MODE(MODE) \
(((MODE) == DMA_LSM_FULL_EXECUTION) || \
((MODE) == DMA_LSM_1LINK_EXECUTION))
#define IS_DMA_TRIGGER_MODE(MODE) \
(((MODE) == DMA_TRIGM_BLOCK_TRANSFER) || \
((MODE) == DMA_TRIGM_REPEATED_BLOCK_TRANSFER) || \
((MODE) == DMA_TRIGM_LLI_LINK_TRANSFER) || \
((MODE) == DMA_TRIGM_SINGLE_BURST_TRANSFER))
#define IS_DMA_TCEM_LINKEDLIST_EVENT_MODE(MODE) \
(((MODE) == DMA_TCEM_BLOCK_TRANSFER) || \
((MODE) == DMA_TCEM_REPEATED_BLOCK_TRANSFER) || \
((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER) || \
((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER))
#define IS_DMA_LINKEDLIST_MODE(MODE) \
(((MODE) == DMA_LINKEDLIST_NORMAL) || \
((MODE) == DMA_LINKEDLIST_CIRCULAR))
#define IS_DMA_TRIGGER_POLARITY(POLARITY) \
(((POLARITY) == DMA_TRIG_POLARITY_MASKED) || \
((POLARITY) == DMA_TRIG_POLARITY_RISING) || \
((POLARITY) == DMA_TRIG_POLARITY_FALLING))
#define IS_DMA_TRIGGER_SELECTION(TRIGGER) \
((TRIGGER) <= GPDMA1_TRIGGER_TIM15_TRGO)
#define IS_DMA_NODE_TYPE(TYPE) \
(((TYPE) == DMA_GPDMA_LINEAR_NODE) || \
((TYPE) == DMA_GPDMA_2D_NODE) || \
((TYPE) == DMA_HPDMA_LINEAR_NODE) || \
((TYPE) == DMA_HPDMA_2D_NODE))
/**
* @}
*/
/* Private functions -------------------------------------------------------------------------------------------------*/
/** @defgroup DMAEx_Private_Functions DMAEx Private Functions
* @brief DMAEx Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* STM32H7RSxx_HAL_DMA_EX_H */
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_exti.h
+347
View File
@@ -0,0 +1,347 @@
/**
******************************************************************************
* @file stm32h7rsxx_hal_exti.h
* @author MCD Application Team
* @brief Header file of EXTI HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7RSxx_HAL_EXTI_H
#define STM32H7RSxx_HAL_EXTI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal_def.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @defgroup EXTI EXTI
* @brief EXTI HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup EXTI_Exported_Types EXTI Exported Types
* @{
*/
typedef enum
{
HAL_EXTI_COMMON_CB_ID = 0x00U,
} EXTI_CallbackIDTypeDef;
/**
* @brief EXTI Handle structure definition
*/
typedef struct
{
uint32_t Line; /*!< Exti line number */
void (* PendingCallback)(void); /*!< Exti pending callback */
} EXTI_HandleTypeDef;
/**
* @brief EXTI Configuration structure definition
*/
typedef struct
{
uint32_t Line; /*!< The Exti line to be configured. This parameter
can be a value of @ref EXTI_Line */
uint32_t Mode; /*!< The Exit Mode to be configured for a core.
This parameter can be a combination of @ref EXTI_Mode */
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
can be a value of @ref EXTI_Trigger */
uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
This parameter is only possible for line 0 to 15. It
can be a value of @ref EXTI_GPIOSel */
} EXTI_ConfigTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
* @{
*/
/** @defgroup EXTI_Line EXTI Line
* @{
*/
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x11u)
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
#define EXTI_LINE_22 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x16u)
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u)
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu)
#define EXTI_LINE_29 (EXTI_RESERVED | EXTI_REG1 | 0x1Du)
#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Eu)
#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_34 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_35 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_37 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_38 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x07u)
#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x08u)
#define EXTI_LINE_41 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x09u)
#define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x0Au)
#define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x0Bu)
#define EXTI_LINE_44 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x0Cu)
#define EXTI_LINE_45 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x0Du)
#define EXTI_LINE_46 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x0Eu)
#define EXTI_LINE_47 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x0Fu)
#define EXTI_LINE_48 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x10u)
#define EXTI_LINE_49 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x11u)
#define EXTI_LINE_50 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x12u)
#define EXTI_LINE_51 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x13u)
#define EXTI_LINE_52 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x14u)
#define EXTI_LINE_53 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x15u)
#define EXTI_LINE_54 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x16u)
#define EXTI_LINE_55 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x17u)
#define EXTI_LINE_56 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x18u)
#define EXTI_LINE_57 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x19u)
#define EXTI_LINE_58 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x1Au)
#define EXTI_LINE_59 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x1Bu)
#define EXTI_LINE_77 (EXTI_DIRECT | EXTI_REG3 | EXTI_EVENT | 0x0Du)
/**
* @}
*/
/** @defgroup EXTI_Mode EXTI Mode
* @{
*/
#define EXTI_MODE_NONE 0x00000000u
#define EXTI_MODE_INTERRUPT 0x00000001u
#define EXTI_MODE_EVENT 0x00000002u
/**
* @}
*/
/** @defgroup EXTI_Trigger EXTI Trigger
* @{
*/
#define EXTI_TRIGGER_NONE 0x00000000u
#define EXTI_TRIGGER_RISING 0x00000001u
#define EXTI_TRIGGER_FALLING 0x00000002u
#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/**
* @}
*/
/** @defgroup EXTI_GPIOSel EXTI GPIOSel
* @brief
* @{
*/
#define EXTI_GPIOA 0x00000000u
#define EXTI_GPIOB 0x00000001u
#define EXTI_GPIOC 0x00000002u
#define EXTI_GPIOD 0x00000003u
#define EXTI_GPIOE 0x00000004u
#define EXTI_GPIOF 0x00000005u
#define EXTI_GPIOG 0x00000006u
#define EXTI_GPIOH 0x00000007u
#define EXTI_GPIOM 0x0000000Cu
#define EXTI_GPION 0x0000000Du
#define EXTI_GPIOO 0x0000000Eu
#define EXTI_GPIOP 0x0000000Fu
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
* @{
*/
/**
* @}
*/
/* Private constants --------------------------------------------------------*/
/** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{
*/
/**
* @brief EXTI Line property definition
*/
#define EXTI_PROPERTY_SHIFT 24u
#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT)
#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
/**
* @brief EXTI Event presence definition
*/
#define EXTI_EVENT_PRESENCE_SHIFT 28u
#define EXTI_EVENT (0x01uL << EXTI_EVENT_PRESENCE_SHIFT)
#define EXTI_EVENT_PRESENCE_MASK (EXTI_EVENT)
/**
* @brief EXTI Register and bit usage
*/
#define EXTI_REG_SHIFT 16u
#define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT)
#define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT)
#define EXTI_REG3 (0x02uL << EXTI_REG_SHIFT)
#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2 | EXTI_REG3)
#define EXTI_PIN_MASK 0x0000001Fu
/**
* @brief EXTI Mask for interrupt & event mode
*/
#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
/**
* @brief EXTI Mask for trigger possibilities
*/
#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/**
* @brief EXTI Line number
*/
#define EXTI_LINE_NB 78u
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup EXTI_Private_Macros EXTI Private Macros
* @{
*/
#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \
((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
(((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
(((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
((((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
(((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))) || \
(((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x0002000DUL)))
#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \
(((__LINE__) & ~EXTI_MODE_MASK) == 0x00u))
#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
#define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING)
#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOF) || \
((__PORT__) == EXTI_GPIOG) || \
((__PORT__) == EXTI_GPIOH) || \
((__PORT__) == EXTI_GPIOM) || \
((__PORT__) == EXTI_GPION) || \
((__PORT__) == EXTI_GPIOO) || \
((__PORT__) == EXTI_GPIOP))
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
* @brief EXTI Exported Functions
* @{
*/
/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
* @brief Configuration functions
* @{
*/
/* Configuration functions ****************************************************/
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti,const EXTI_ConfigTypeDef *pExtiConfig);
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti);
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
/**
* @}
*/
/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti);
uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge);
void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge);
void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H7RSxx_HAL_EXTI_H */
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_flash.h
+803
View File
@@ -0,0 +1,803 @@
/**
******************************************************************************
* @file stm32h7rsxx_hal_flash.h
* @author MCD Application Team
* @brief Header file of FLASH HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7RSxx_HAL_FLASH_H
#define STM32H7RSxx_HAL_FLASH_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal_def.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @addtogroup FLASH
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup FLASH_Exported_Types FLASH Exported Types
* @{
*/
/**
* @brief FLASH Erase structure definition
*/
typedef struct
{
uint32_t TypeErase; /*!< Mass erase or page erase.
This parameter can be a value of @ref FLASH_Type_Erase */
uint32_t Sector; /*!< Initial Flash sector to erase when sector erase is enabled
This parameter must be a value between 0 and (max number of sector - 1)
(eg : 15 for 128KB single bank) */
uint32_t NbSectors; /*!< Number of sectors to be erased.
This parameter must be a value between 1 and
(max number of sectors - value of initial page)*/
} FLASH_EraseInitTypeDef;
/**
* @brief FLASH Option Bytes Program structure definition
*/
#define FLASH_KEY_DATA_NB_REG (8U) /*!< 8 Key data registers */
typedef struct
{
uint32_t OptionType; /*!< Option byte to be configured.
This parameter can be a combination of the values of @ref FLASH_OB_TYPE */
uint32_t WRPState; /*!< Write protection activation or deactivation (used for OPTIONBYTE_WRP).
This parameter can be value of @ref FLASH_OB_WRP_STATE */
uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected (used for OPTIONBYTE_WRP).
The value of this parameter depend on device used within the same series */
uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
This parameter can be a combination of @ref FLASH_OB_USER_TYPE */
uint32_t USERConfig1; /*!< Value of the user option byte (used for OPTIONBYTE_USER).
This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEV,
@ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_nRST_STOP,
@ref FLASH_OB_USER_nRST_STDBY, @ref FLASH_OB_USER_XSPI1_HSLV,
@ref FLASH_OB_USER_XSPI2_HSLV, @ref FLASH_OB_USER_IWDG_STOP,
@ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_VDDIO_HSLV */
uint32_t USERConfig2; /*!< Value of the user option byte (used for OPTIONBYTE_USER).
This parameter can be a combination of @ref FLASH_OB_USER_ITCM_AXI_SHARE,
@ref FLASH_OB_USER_DTCM_AXI_SHARE, @ref FLASH_OB_USER_ECC_ON_SRAM,
@ref FLASH_OB_USER_I2C_NI3C */
uint32_t HDPStartPage; /*!< Start address that contains the first 256-byte block of HDP area (used for OPTIONBYTE_HDP).
This parameter must be a value between 0 or 0xFFF */
uint32_t HDPEndPage; /*!< End address that contains the last 256-byte block of HDP area (used for OPTIONBYTE_HDP).
This parameter must be a value between 0 or 0xFFF */
uint32_t NVState; /*!< Value of the non-volatile state (used for OPTIONBYTE_NV).
This parameter must be a value of @ref FLASH_OB_NVSTATE */
uint32_t ROTConfig; /*!< Value of the RoT status (only used for read configuration).
This parameter can be a combination of @ref FLASH_OB_ROT_OEM_PROVD,
@ref FLASH_OB_ROT_DBG_AUTH, @ref FLASH_OB_ROT_IROT_SELECT */
uint32_t EPOCH; /*!< Value of the epoch (only used for read configuration).
This parameter must be a value between 0x0 and 0xFFFFFF */
} FLASH_OBProgramInitTypeDef;
/**
* @brief FLASH handle Structure definition
*/
typedef struct
{
HAL_LockTypeDef Lock; /* FLASH locking object */
uint32_t ErrorCode; /* FLASH error code */
uint32_t ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT
context */
uint32_t Address; /* Internal variable to save address selected for program in IT context */
uint32_t Sector; /* Internal variable to define the current sector which is being erased in
IT context */
uint32_t NbSectorsToErase; /* Internal variable to save the remaining sectors to erase in IT context */
} FLASH_ProcessTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
* @{
*/
/** @defgroup FLASH_Flags FLASH Flags Definition
* @{
*/
#define FLASH_FLAG_EOP FLASH_ISR_EOPF /*!< FLASH End of program flag */
#define FLASH_FLAG_WRPERR FLASH_ISR_WRPERRF /*!< FLASH Write protection error flag */
#define FLASH_FLAG_PGSERR FLASH_ISR_PGSERRF /*!< FLASH Programming sequence error flag */
#define FLASH_FLAG_STRBERR FLASH_ISR_STRBERRF /*!< FLASH Strobe error flag */
#define FLASH_FLAG_OBLERR FLASH_ISR_OBLERRF /*!< FLASH Option byte loading error flag */
#define FLASH_FLAG_INCERR FLASH_ISR_INCERRF /*!< FLASH Inconsistency error flag */
#define FLASH_FLAG_RDSERR FLASH_ISR_RDSERRF /*!< FLASH Read security error flag */
#define FLASH_FLAG_SNECCERR FLASH_ISR_SNECCERRF /*!< FLASH ECC single error flag */
#define FLASH_FLAG_DBECCERR FLASH_ISR_DBECCERRF /*!< FLASH ECC double error flag */
#define FLASH_FLAG_CRCEND FLASH_ISR_CRCENDF /*!< FLASH CRC end of calculation flag */
#define FLASH_FLAG_CRCERR FLASH_ISR_CRCRDERRF /*!< FLASH CRC error flag */
#define FLASH_FLAG_KVERR FLASH_OPTISR_KVEF /*!< FLASH Key valid error flag */
#define FLASH_FLAG_KTERR FLASH_OPTISR_KTEF /*!< FLASH Key transfer error flag */
#define FLASH_FLAG_OPTERR FLASH_OPTISR_OPTERRF /*!< FLASH Options byte change error flag */
#define FLASH_FLAG_ISR_ERRORS (FLASH_FLAG_WRPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_STRBERR | \
FLASH_FLAG_OBLERR | FLASH_FLAG_INCERR | FLASH_FLAG_RDSERR | \
FLASH_FLAG_CRCERR)
#define FLASH_FLAG_ECC_ERRORS (FLASH_FLAG_SNECCERR | FLASH_FLAG_DBECCERR)
#define FLASH_FLAG_OPTISR_ERRORS (FLASH_FLAG_KVERR | FLASH_FLAG_KTERR | FLASH_FLAG_OPTERR)
#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_ISR_ERRORS | FLASH_FLAG_ECC_ERRORS | FLASH_FLAG_OPTISR_ERRORS)
#define FLASH_FLAG_ISR_FLAGS (FLASH_FLAG_ISR_ERRORS | FLASH_FLAG_ECC_ERRORS | FLASH_FLAG_EOP)
/**
* @}
*/
/** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition
* @brief FLASH Interrupt definition
* @{
*/
#define FLASH_IT_EOP FLASH_IER_EOPIE /*!< End of program interrupt source */
#define FLASH_IT_WRPERR FLASH_IER_WRPERRIE /*!< FLASH Write protection error interrupt source */
#define FLASH_IT_PGSERR FLASH_IER_PGSERRIE /*!< FLASH Programming sequence error interrupt source */
#define FLASH_IT_STRBERR FLASH_IER_STRBERRIE /*!< FLASH Strobe error interrupt source */
#define FLASH_IT_OBLERR FLASH_IER_OBLERRIE /*!< FLASH Option byte loading error interrupt source */
#define FLASH_IT_INCERR FLASH_IER_INCERRIE /*!< FLASH Inconsistency error interrupt source */
#define FLASH_IT_RDSERR FLASH_IER_RDSERRIE /*!< FLASH Read security error interrupt source */
#define FLASH_IT_SNECCERR FLASH_IER_SNECCERRIE /*!< FLASH ECC single error interrupt source */
#define FLASH_IT_DBECCERR FLASH_IER_DBECCERRIE /*!< FLASH ECC double error interrupt source */
#define FLASH_IT_CRCEND FLASH_IER_CRCENDIE /*!< FLASH CRC end of calculation interrupt source */
#define FLASH_IT_CRCERR FLASH_IER_CRCRDERRIE /*!< FLASH CRC error interrupt source */
#define FLASH_IT_KVERR FLASH_OPTCR_KVEIE /*!< FLASH Key valid error interrupt source */
#define FLASH_IT_KTERR FLASH_OPTCR_KTEIE /*!< FLASH Key transfer error interrupt source */
#define FLASH_IT_OPTERR FLASH_OPTCR_OPTERRIE /*!< FLASH Options byte change error interrupt source */
#define FLASH_IT_IER (FLASH_IT_EOP | FLASH_IT_WRPERR | FLASH_IT_PGSERR | FLASH_IT_STRBERR | \
FLASH_IT_OBLERR | FLASH_IT_INCERR | FLASH_IT_RDSERR | FLASH_IT_SNECCERR | \
FLASH_IT_DBECCERR | FLASH_IT_CRCEND | FLASH_IT_CRCERR)
#define FLASH_IT_OPTCR (FLASH_IT_KVERR | FLASH_IT_KTERR | FLASH_IT_OPTERR)
/**
* @}
*/
/** @defgroup FLASH_Error FLASH Error
* @{
*/
#define HAL_FLASH_ERROR_NONE 0x00000000U
#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR
#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR
#define HAL_FLASH_ERROR_STRB FLASH_FLAG_STRBERR
#define HAL_FLASH_ERROR_OBL FLASH_FLAG_OBLERR
#define HAL_FLASH_ERROR_INC FLASH_FLAG_INCERR
#define HAL_FLASH_ERROR_RDS FLASH_FLAG_RDSERR
#define HAL_FLASH_ERROR_SNECC FLASH_FLAG_SNECCERR
#define HAL_FLASH_ERROR_DBECC FLASH_FLAG_DBECCERR
#define HAL_FLASH_ERROR_CRC FLASH_FLAG_CRCERR
#define HAL_FLASH_ERROR_KV FLASH_FLAG_KVERR
#define HAL_FLASH_ERROR_KT FLASH_FLAG_KTERR
#define HAL_FLASH_ERROR_OPT FLASH_FLAG_OPTERR
/**
* @}
*/
/** @defgroup FLASH_Type_Erase FLASH Erase Type
* @{
*/
#define FLASH_TYPEERASE_SECTORS FLASH_CR_SER /*!< Sectors erase activation */
#define FLASH_TYPEERASE_MASSERASE FLASH_CR_BER /*!< Flash mass erase activation */
/**
* @}
*/
/** @defgroup FLASH_Type_Program FLASH Program Type
* @{
*/
#define FLASH_TYPEPROGRAM_BYTE (FLASH_CR_PG | FLASH_CR_FW) /*!< Program a byte (8-bit) at a specified address */
#define FLASH_TYPEPROGRAM_HALFWORD (FLASH_HALFWORD_MASK | FLASH_CR_PG | FLASH_CR_FW) /*!< Program a half-word (16-bit) at a specified address */
#define FLASH_TYPEPROGRAM_WORD (FLASH_WORD_MASK | FLASH_CR_PG | FLASH_CR_FW) /*!< Program a word (32-bit) at a specified address */
#define FLASH_TYPEPROGRAM_DOUBLEWORD (FLASH_DOUBLEWORD_MASK | FLASH_CR_PG | FLASH_CR_FW) /*!< Program a double-word (64-bit) at a specified address */
#define FLASH_TYPEPROGRAM_QUADWORD (FLASH_CR_PG) /*!< Program a quad-word (128-bit) at a specified address */
#define FLASH_TYPEPROGRAM_OTP_HALFWORD (FLASH_HALFWORD_MASK | FLASH_CR_PG_OTP | FLASH_CR_FW) /*!< Program a half-word (16-bit) at a OTP address */
#define FLASH_TYPEPROGRAM_OTP_WORD (FLASH_WORD_MASK | FLASH_CR_PG_OTP | FLASH_CR_FW) /*!< Program a word (32-bit) at a OTP address */
/**
* @}
*/
/** @defgroup FLASH_OB_TYPE FLASH Option Bytes Type
* @{
*/
#define OPTIONBYTE_WRP 0x00000001U /*!< WRP option byte configuration */
#define OPTIONBYTE_USER 0x00000002U /*!< User option byte configuration */
#define OPTIONBYTE_HDP 0x00000004U /*!< HDP option byte configuration */
#define OPTIONBYTE_NV 0x00000008U /*!< Non-Volatile State option byte configuration */
/**
* @}
*/
/** @defgroup FLASH_OB_WRP_STATE FLASH Option Bytes WRP State
* @{
*/
#define OB_WRPSTATE_DISABLE 0x00000000U /*!< Disable the write protection of the desired sectors */
#define OB_WRPSTATE_ENABLE 0x00000001U /*!< Enable the write protection of the desired sectors */
/**
* @}
*/
/** @defgroup FLASH_OB_USER_TYPE FLASH Option Bytes User Type
* @{
*/
#define OB_USER_BOR_LEV 0x00000001U /*!< Brownout level */
#define OB_USER_IWDG_SW 0x00000002U /*!< IWDG control mode */
#define OB_USER_NRST_STOP 0x00000004U /*!< Stop entry reset */
#define OB_USER_NRST_STDBY 0x00000008U /*!< Standby entry reset */
#define OB_USER_XSPI1_HSLV 0x00000010U /*!< XSPI1 High-speed at low voltage */
#define OB_USER_XSPI2_HSLV 0x00000020U /*!< XSPI2 High-speed at low voltage */
#define OB_USER_IWDG_STOP 0x00000040U /*!< IWDG Stop mode freeze */
#define OB_USER_IWDG_STDBY 0x00000080U /*!< IWDG Standby mode freeze */
#define OB_USER_VDDIO_HSLV 0x00000100U /*!< I/O High-speed at low voltage */
#define OB_USER_ITCM_AXI_SHARE 0x00000200U /*!< ITCM AXI share */
#define OB_USER_DTCM_AXI_SHARE 0x00000400U /*!< DTCM AXI share */
#define OB_USER_SRAM_ECC 0x00000800U /*!< ECC on SRAM */
#define OB_USER_I2C_NI3C 0x00001000U /*!< I2C Not I3C */
/**
* @}
*/
/** @defgroup FLASH_OB_USER_BOR_LEV FLASH Option Bytes User BOR Level
* @{
*/
#define OB_BOR_LEVEL_0 0x00000000U /*!< BOR OFF, POR/PDR reset threshold level is applied */
#define OB_BOR_LEVEL_1 FLASH_OBW1SRP_BOR_LEVEL_0 /*!< BOR Level 1, the threshold level is low (around 2.1 V) */
#define OB_BOR_LEVEL_2 FLASH_OBW1SRP_BOR_LEVEL_1 /*!< BOR Level 2, the threshold level is medium (around 2.4 V) */
#define OB_BOR_LEVEL_3 FLASH_OBW1SRP_BOR_LEVEL /*!< BOR Level 3, the threshold level is high (around 2.7 V) */
/**
* @}
*/
/** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG control mode
* @{
*/
#define OB_IWDG_HW 0x00000000U /*!< IWDG watchdog is controlled by hardware */
#define OB_IWDG_SW FLASH_OBW1SRP_IWDG_HW /*!< IWDG watchdog is controlled by software */
/**
* @}
*/
/** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User stop entry reset
* @{
*/
#define OB_STOP_RST 0x00000000U /*!< Reset generated when entering stop mode */
#define OB_STOP_NORST FLASH_OBW1SRP_NRST_STOP /*!< No reset generated when entering stop mode */
/**
* @}
*/
/** @defgroup FLASH_OB_USER_nRST_STDBY FLASH Option Bytes User standby entry reset
* @{
*/
#define OB_STANDBY_RST 0x00000000U /*!< Reset generated when entering standby mode */
#define OB_STANDBY_NORST FLASH_OBW1SRP_NRST_STBY /*!< No reset generated when entering standby mode */
/**
* @}
*/
/** @defgroup FLASH_OB_USER_XSPI1_HSLV FLASH Option Bytes User XSPI 1 High-Speed at Low-Voltage
* @{
*/
#define OB_XSPI1_HSLV_DISABLE 0x00000000U /*!< I/O speed optimization at low-voltage disabled */
#define OB_XSPI1_HSLV_ENABLE FLASH_OBW1SRP_XSPI1_HSLV /*!< I/O speed optimization at low-voltage feature allowed */
/**
* @}
*/
/** @defgroup FLASH_OB_USER_XSPI2_HSLV FLASH Option Bytes User XSPI 2 High-Speed at Low-Voltage
* @{
*/
#define OB_XSPI2_HSLV_DISABLE 0x00000000U /*!< I/O speed optimization at low-voltage disabled */
#define OB_XSPI2_HSLV_ENABLE FLASH_OBW1SRP_XSPI2_HSLV /*!< I/O speed optimization at low-voltage feature allowed */
/**
* @}
*/
/** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Stop Mode Freeze
* @{
*/
#define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Independent watchdog frozen in Stop mode */
#define OB_IWDG_STOP_RUN FLASH_OBW1SRP_IWDG_FZ_STOP /*!< Independent watchdog running in Stop mode */
/**
* @}
*/
/** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Standby Mode Freeze
* @{
*/
#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Independent watchdog frozen in Standby mode */
#define OB_IWDG_STDBY_RUN FLASH_OBW1SRP_IWDG_FZ_STBY /*!< Independent watchdog running in Standby mode */
/**
* @}
*/
/** @defgroup FLASH_OB_USER_VDDIO_HSLV FLASH Option Bytes User I/O High-Speed at Low-Voltage
* @{
*/
#define OB_VDDIO_HSLV_DISABLE 0x00000000U /*!< I/O speed optimization at low-voltage disabled */
#define OB_VDDIO_HSLV_ENABLE FLASH_OBW1SRP_VDDIO_HSLV /*!< I/O speed optimization at low-voltage feature allowed */
/**
* @}
*/
/** @defgroup FLASH_OB_USER_ITCM_AXI_SHARE FLASH Option Bytes User ITCM AXI share
* @{
*/
#define OB_ITCM_AXI_SHARE_0 0x00000000U
#define OB_ITCM_AXI_SHARE_1 FLASH_OBW2SRP_ITCM_AXI_SHARE_0
#define OB_ITCM_AXI_SHARE_2 FLASH_OBW2SRP_ITCM_AXI_SHARE_1
#define OB_ITCM_AXI_SHARE_3 (FLASH_OBW2SRP_ITCM_AXI_SHARE_0 | FLASH_OBW2SRP_ITCM_AXI_SHARE_1)
#define OB_ITCM_AXI_SHARE_4 FLASH_OBW2SRP_ITCM_AXI_SHARE_2
#define OB_ITCM_AXI_SHARE_5 (FLASH_OBW2SRP_ITCM_AXI_SHARE_2 | FLASH_OBW2SRP_ITCM_AXI_SHARE_0)
#define OB_ITCM_AXI_SHARE_6 (FLASH_OBW2SRP_ITCM_AXI_SHARE_2 | FLASH_OBW2SRP_ITCM_AXI_SHARE_1)
#define OB_ITCM_AXI_SHARE_7 FLASH_OBW2SRP_ITCM_AXI_SHARE
/**
* @}
*/
/** @defgroup FLASH_OB_USER_DTCM_AXI_SHARE FLASH Option Bytes User DTCM AXI share
* @{
*/
#define OB_DTCM_AXI_SHARE_0 0x00000000U
#define OB_DTCM_AXI_SHARE_1 FLASH_OBW2SRP_DTCM_AXI_SHARE_0
#define OB_DTCM_AXI_SHARE_2 FLASH_OBW2SRP_DTCM_AXI_SHARE_1
#define OB_DTCM_AXI_SHARE_3 (FLASH_OBW2SRP_DTCM_AXI_SHARE_0 | FLASH_OBW2SRP_DTCM_AXI_SHARE_1)
#define OB_DTCM_AXI_SHARE_4 FLASH_OBW2SRP_DTCM_AXI_SHARE_2
#define OB_DTCM_AXI_SHARE_5 (FLASH_OBW2SRP_DTCM_AXI_SHARE_2 | FLASH_OBW2SRP_DTCM_AXI_SHARE_0)
#define OB_DTCM_AXI_SHARE_6 (FLASH_OBW2SRP_DTCM_AXI_SHARE_2 | FLASH_OBW2SRP_DTCM_AXI_SHARE_1)
#define OB_DTCM_AXI_SHARE_7 FLASH_OBW2SRP_DTCM_AXI_SHARE
/**
* @}
*/
/** @defgroup FLASH_OB_USER_ECC_ON_SRAM FLASH Option Bytes User ECC on sRAM
* @{
*/
#define OB_AXISRAM_ECC_DISABLE 0x00000000U /*!< AXISRAM ECC check disable */
#define OB_AXISRAM_ECC_ENABLE FLASH_OBW2SRP_ECC_ON_SRAM /*!< AXISRAM ECC check enable */
/**
* @}
*/
/** @defgroup FLASH_OB_USER_I2C_NI3C FLASH Option Bytes User I2C Not I3C
* @{
*/
#define OB_I2C_NI3C_I2C FLASH_OBW2SRP_I2C_NI3C
#define OB_I2C_NI3C_I3C 0x00000000U
/**
* @}
*/
/** @defgroup FLASH_OB_NVSTATE FLASH Option Bytes Non-volatile state
* @{
*/
#define OB_NVSTATE_OPEN (uint8_t)0xB4
#define OB_NVSTATE_CLOSE (uint8_t)0x51
/**
* @}
*/
/** @defgroup FLASH_OB_ROT_OEM_PROVD FLASH Option Bytes Root-Of-Trust OEM Provisioned state
* @{
*/
#define OB_OEM_PROVD_ENABLE (0xB4UL << FLASH_ROTSR_OEM_PROVD_Pos) /*!< Device is in OEM provisioned state */
#define OB_OEM_PROVD_DEFAULT (0x6AUL << FLASH_ROTSR_OEM_PROVD_Pos) /*!< Device is not in OEM provisioned state (default value)*/
/**
* @}
*/
/** @defgroup FLASH_OB_ROT_DBG_AUTH FLASH Option Bytes Root-Of-Trust Debug authentication method
* @{
*/
#define OB_DBG_AUTH_LOCKED (0xB4UL << FLASH_ROTSR_DBG_AUTH_Pos) /*!< Locked device (no debug allowed) */
#define OB_DBG_AUTH_ECDSA_SIGN (0x51UL << FLASH_ROTSR_DBG_AUTH_Pos) /*!< Authentication method using ECDSA signature (NISTP256) */
#define OB_DBG_AUTH_PASSWORD (0x8AUL << FLASH_ROTSR_DBG_AUTH_Pos) /*!< Authentication method using password */
#define OB_DBG_AUTH_DEFAULT (0xFFUL << FLASH_ROTSR_DBG_AUTH_Pos) /*!< No authentication method selected (default value) */
/**
* @}
*/
/** @defgroup FLASH_OB_ROT_IROT_SELECT FLASH Option Bytes iRoT selection
* @{
*/
#define OB_IROT_SELECTION_ST (0xB4UL << FLASH_ROTSR_IROT_SELECT_Pos) /*!< ST iRoT is selected at boot */
#define OB_IROT_SELECTION_OEM (0x6AUL << FLASH_ROTSR_IROT_SELECT_Pos) /*!< OEM iRoT is selected at boot */
/**
* @}
*/
/** @defgroup FLASH_Latency FLASH Latency
* @{
*/
#define FLASH_LATENCY_0 0U /*!< FLASH Zero wait state */
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One wait state */
#define FLASH_LATENCY_2 (FLASH_ACR_LATENCY_1 | FLASH_ACR_WRHIGHFREQ_0) /*!< FLASH Two wait states */
#define FLASH_LATENCY_3 (FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0 | FLASH_ACR_WRHIGHFREQ_0) /*!< FLASH Three wait states */
#define FLASH_LATENCY_4 (FLASH_ACR_LATENCY_2 | FLASH_ACR_WRHIGHFREQ_1) /*!< FLASH Four wait states */
#define FLASH_LATENCY_5 (FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_0 | FLASH_ACR_WRHIGHFREQ_1) /*!< FLASH Five wait states */
#define FLASH_LATENCY_6 (FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_1 | FLASH_ACR_WRHIGHFREQ) /*!< FLASH Six wait state */
#define FLASH_LATENCY_7 (FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0 | FLASH_ACR_WRHIGHFREQ) /*!< FLASH Seven wait states */
/**
* @}
*/
/** @defgroup FLASH_Keys FLASH Keys
* @{
*/
#define FLASH_KEY1 0x45670123U /*!< Flash key1 */
#define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1
to unlock the FLASH registers access */
#define FLASH_OPT_KEY1 0x08192A3BU /*!< Flash option byte key1 */
#define FLASH_OPT_KEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPT_KEY1
to allow option bytes operations */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
* @brief macros to control FLASH features
* @{
*/
/**
* @brief Set the FLASH Latency.
* @param __LATENCY__ FLASH Latency
* This parameter can be one of the following values :
* @arg FLASH_LATENCY_0: FLASH Zero wait state
* @arg FLASH_LATENCY_1: FLASH One wait state
* @arg FLASH_LATENCY_2: FLASH Two wait states
* @arg FLASH_LATENCY_3: FLASH Three wait states
* @arg FLASH_LATENCY_4: FLASH Four wait states
* @arg FLASH_LATENCY_5: FLASH Five wait states
* @arg FLASH_LATENCY_6: FLASH Six wait states
* @arg FLASH_LATENCY_7: FLASH Seven wait states
* @retval None
*/
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, (FLASH_ACR_LATENCY |\
FLASH_ACR_WRHIGHFREQ), (__LATENCY__))
/**
* @brief Get the FLASH Latency.
* @retval FLASH Latency
* This return value can be one of the following values :
* @arg FLASH_LATENCY_0: FLASH Zero wait state
* @arg FLASH_LATENCY_1: FLASH One wait state
* @arg FLASH_LATENCY_2: FLASH Two wait states
* @arg FLASH_LATENCY_3: FLASH Three wait states
* @arg FLASH_LATENCY_4: FLASH Four wait states
* @arg FLASH_LATENCY_5: FLASH Five wait states
* @arg FLASH_LATENCY_6: FLASH Six wait states
* @arg FLASH_LATENCY_7: FLASH Seven wait states
*/
#define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, (FLASH_ACR_LATENCY | FLASH_ACR_WRHIGHFREQ))
/**
* @}
*/
/** @defgroup FLASH_Interrupt FLASH Interrupts Macros
* @brief macros to handle FLASH interrupts
* @{
*/
/**
* @brief Enable the specified FLASH interrupt.
* @param __INTERRUPT__ FLASH interrupt
* This parameter can be any combination of the following values:
* @arg FLASH_IT_EOP: End of program interrupt
* @arg FLASH_IT_WRPERR: Write protection error interrupt
* @arg FLASH_IT_PGSERR: Programming sequence error interrupt
* @arg FLASH_IT_STRBERR: Strobe error interrupt
* @arg FLASH_IT_OBLERR: Option byte loading error interrupt
* @arg FLASH_IT_INCERR: Inconsistency error interrupt
* @arg FLASH_IT_RDSERR: Read security error interrupt
* @arg FLASH_IT_SNECCERR: ECC single error interrupt
* @arg FLASH_IT_DBECCERR: ECC double error interrupt
* @arg FLASH_IT_CRCEND: CRC end of calculation interrupt
* @arg FLASH_IT_CRCERR: CRC error interrupt
* @arg FLASH_IT_KVERR: Key valid error interrupt
* @arg FLASH_IT_KTERR: Key transfer error interrupt
* @arg FLASH_IT_OPTERR: Options byte change error interrupt
* @retval none
*/
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_IER) != 0U)\
{ SET_BIT(FLASH->IER, ((__INTERRUPT__) & FLASH_IT_IER)); }\
if(((__INTERRUPT__) & FLASH_IT_OPTCR) != 0U)\
{ SET_BIT(FLASH->OPTCR, ((__INTERRUPT__) & FLASH_IT_OPTCR)); }\
} while(0)
/**
* @brief Disable the specified FLASH interrupt.
* @param __INTERRUPT__ FLASH interrupt
* This parameter can be any combination of the following values:
* @arg FLASH_IT_EOP: End of program interrupt
* @arg FLASH_IT_WRPERR: Write protection error interrupt
* @arg FLASH_IT_PGSERR: Programming sequence error interrupt
* @arg FLASH_IT_STRBERR: Strobe error interrupt
* @arg FLASH_IT_OBLERR: Option byte loading error interrupt
* @arg FLASH_IT_INCERR: Inconsistency error interrupt
* @arg FLASH_IT_RDSERR: Read security error interrupt
* @arg FLASH_IT_SNECCERR: ECC single error interrupt
* @arg FLASH_IT_DBECCERR: ECC double error interrupt
* @arg FLASH_IT_CRCEND: CRC end of calculation interrupt
* @arg FLASH_IT_CRCERR: CRC error interrupt
* @arg FLASH_IT_KVERR: Key valid error interrupt
* @arg FLASH_IT_KTERR: Key transfer error interrupt
* @arg FLASH_IT_OPTERR: Options byte change error interrupt
* @retval none
*/
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_IER) != 0U)\
{ CLEAR_BIT(FLASH->IER, ((__INTERRUPT__) & FLASH_IT_IER)); }\
if(((__INTERRUPT__) & FLASH_IT_OPTCR) != 0U)\
{ CLEAR_BIT(FLASH->OPTCR, ((__INTERRUPT__) & FLASH_IT_OPTCR)); }\
} while(0)
/**
* @brief Check whether the specified FLASH flag is set or not.
* @param __FLAG__ specifies the FLASH flag to check.
* This parameter can be one of the following values:
* @arg FLASH_FLAG_EOP: FLASH End of program flag
* @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
* @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
* @arg FLASH_FLAG_STRBERR: FLASH Strobe error flag
* @arg FLASH_FLAG_OBLERR: FLASH Option byte loading error flag
* @arg FLASH_FLAG_INCERR: FLASH Inconsistency error flag
* @arg FLASH_FLAG_RDSERR: FLASH Read security error flag
* @arg FLASH_FLAG_SNECCERR: FLASH ECC single error flag
* @arg FLASH_FLAG_DBECCERR: FLASH ECC double error flag
* @arg FLASH_FLAG_CRCEND: FLASH CRC end of calculation flag
* @arg FLASH_FLAG_CRCERR: FLASH CRC error flag
* @arg FLASH_FLAG_KVERR: FLASH Key valid error flag
* @arg FLASH_FLAG_KTERR: FLASH Key transfer error flag
* @arg FLASH_FLAG_OPTERR: FLASH Options byte change error flag
* @retval The new state of FLASH_FLAG (SET or RESET).
*/
#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & FLASH_FLAG_OPTISR_ERRORS) != 0U) ? \
(READ_BIT(FLASH->OPTISR, (__FLAG__)) == (__FLAG__)) : \
(READ_BIT(FLASH->ISR, (__FLAG__)) == (__FLAG__)))
/**
* @brief Clear the FLASH's pending flags.
* @param __FLAG__ specifies the FLASH flags to clear.
* This parameter can be any combination of the following values:
* @arg FLASH_FLAG_EOP: FLASH End of program flag
* @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
* @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
* @arg FLASH_FLAG_STRBERR: FLASH Strobe error flag
* @arg FLASH_FLAG_OBLERR: FLASH Option byte loading error flag
* @arg FLASH_FLAG_INCERR: FLASH Inconsistency error flag
* @arg FLASH_FLAG_RDSERR: FLASH Read security error flag
* @arg FLASH_FLAG_SNECCERR: FLASH ECC single error flag
* @arg FLASH_FLAG_DBECCERR: FLASH ECC double error flag
* @arg FLASH_FLAG_CRCEND: FLASH CRC end of calculation flag
* @arg FLASH_FLAG_CRCERR: FLASH CRC error flag
* @arg FLASH_FLAG_KVERR: FLASH Key valid error flag
* @arg FLASH_FLAG_KTERR: FLASH Key transfer error flag
* @arg FLASH_FLAG_OPTERR: FLASH Options byte change error flag
* @retval None
*/
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_OPTISR_ERRORS) != 0U)\
{ WRITE_REG(FLASH->OPTICR, ((__FLAG__) & FLASH_FLAG_OPTISR_ERRORS)); }\
if(((__FLAG__) & FLASH_FLAG_ISR_FLAGS) != 0U)\
{ WRITE_REG(FLASH->ICR, ((__FLAG__) & FLASH_FLAG_ISR_FLAGS)); }\
} while(0)
/**
* @}
*/
/* Include FLASH HAL Extended module */
#include "stm32h7rsxx_hal_flash_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup FLASH_Exported_Functions
* @{
*/
/* Program operation functions ***********************************************/
/** @addtogroup FLASH_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress);
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress);
/* FLASH IRQ handler method */
void HAL_FLASH_IRQHandler(void);
/* Callbacks in non blocking modes */
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
/**
* @}
*/
/* Peripheral Control functions **********************************************/
/** @addtogroup FLASH_Exported_Functions_Group2
* @{
*/
HAL_StatusTypeDef HAL_FLASH_Unlock(void);
HAL_StatusTypeDef HAL_FLASH_Lock(void);
/* Option bytes control */
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
/**
* @}
*/
/* Peripheral State functions ************************************************/
/** @addtogroup FLASH_Exported_Functions_Group3
* @{
*/
uint32_t HAL_FLASH_GetError(void);
/**
* @}
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @addtogroup FLASH_Private_Variables FLASH Private Variables
* @{
*/
extern FLASH_ProcessTypeDef pFlash;
/**
* @}
*/
/* Private constants --------------------------------------------------------*/
/** @defgroup FLASH_Private_Constants FLASH Private Constants
* @{
*/
#define FLASH_BANK_SIZE FLASH_SIZE
#define FLASH_SECTOR_NB 8U
#define FLASH_SECTOR_SIZE 0x2000UL /* 8 KB */
#define FLASH_HDP_BLOCK_NB 0x100U
#define FLASH_TIMEOUT_VALUE 1000U /* 1 s */
#define FLASH_BYTE_MASK 0x00000000U
#define FLASH_HALFWORD_MASK 0x40000000U
#define FLASH_WORD_MASK 0x80000000U
#define FLASH_DOUBLEWORD_MASK 0xC0000000U
#define FLASH_WORD_SIZE_MASK FLASH_DOUBLEWORD_MASK
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup FLASH_Private_Macros FLASH Private Macros
* @{
*/
#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) ||\
((VALUE) == FLASH_TYPEERASE_MASSERASE))
#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_BYTE) ||\
((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) ||\
((VALUE) == FLASH_TYPEPROGRAM_WORD) ||\
((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) ||\
((VALUE) == FLASH_TYPEPROGRAM_QUADWORD) ||\
((VALUE) == FLASH_TYPEPROGRAM_OTP_HALFWORD) ||\
((VALUE) == FLASH_TYPEPROGRAM_OTP_WORD))
#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE)))
#define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= OTP_AREA_BASE) && ((ADDRESS) < (OTP_AREA_BASE + OTP_SIZE)))
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) ((IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS)) || (IS_FLASH_OTP_ADDRESS(ADDRESS)))
#define IS_FLASH_SECTOR(SECTOR) ((SECTOR) < FLASH_SECTOR_NB)
#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP |\
OPTIONBYTE_USER | OPTIONBYTE_HDP | OPTIONBYTE_NV)))
#define IS_OB_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE))
#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= 0x1FFFU) && ((TYPE) != 0U))
#define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \
((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3))
#define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW))
#define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST))
#define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST))
#define IS_OB_USER_XSPI1_HSLV(VALUE) (((VALUE) == OB_XSPI1_HSLV_DISABLE) || ((VALUE) == OB_XSPI1_HSLV_ENABLE))
#define IS_OB_USER_XSPI2_HSLV(VALUE) (((VALUE) == OB_XSPI2_HSLV_DISABLE) || ((VALUE) == OB_XSPI2_HSLV_ENABLE))
#define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN))
#define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN))
#define IS_OB_USER_VDDIO_HSLV(VALUE) (((VALUE) == OB_VDDIO_HSLV_DISABLE) || ((VALUE) == OB_VDDIO_HSLV_ENABLE))
#define IS_OB_USER_ITCM_AXI_SHARE(VALUE) (((VALUE) == OB_ITCM_AXI_SHARE_0) || ((VALUE) == OB_ITCM_AXI_SHARE_1) || \
((VALUE) == OB_ITCM_AXI_SHARE_2) || ((VALUE) == OB_ITCM_AXI_SHARE_3) || \
((VALUE) == OB_ITCM_AXI_SHARE_4) || ((VALUE) == OB_ITCM_AXI_SHARE_5) || \
((VALUE) == OB_ITCM_AXI_SHARE_6) || ((VALUE) == OB_ITCM_AXI_SHARE_7))
#define IS_OB_USER_DTCM_AXI_SHARE(VALUE) (((VALUE) == OB_DTCM_AXI_SHARE_0) || ((VALUE) == OB_DTCM_AXI_SHARE_1) || \
((VALUE) == OB_DTCM_AXI_SHARE_2) || ((VALUE) == OB_DTCM_AXI_SHARE_3) || \
((VALUE) == OB_DTCM_AXI_SHARE_4) || ((VALUE) == OB_DTCM_AXI_SHARE_5) || \
((VALUE) == OB_DTCM_AXI_SHARE_6) || ((VALUE) == OB_DTCM_AXI_SHARE_7))
#define IS_OB_USER_AXISRAM_ECC(VALUE) (((VALUE) == OB_AXISRAM_ECC_ENABLE) || ((VALUE) == OB_AXISRAM_ECC_DISABLE))
#define IS_OB_USER_I2C_NI3C(VALUE) (((VALUE) == OB_I2C_NI3C_I2C) || ((VALUE) == OB_I2C_NI3C_I3C))
#define IS_OB_HDP_PAGE(PAGE) ((PAGE) < FLASH_HDP_BLOCK_NB)
#define IS_OB_NVSTATE(VALUE) (((VALUE) == OB_NVSTATE_OPEN) || ((VALUE) ==OB_NVSTATE_CLOSE))
#define IS_OB_ROT_TYPE(VALUE) ((VALUE) <= 0x7U)
#define IS_OB_OEM_PROVD(VALUE) ((VALUE) <= 0x000000FFU)
#define IS_OB_DBG_AUTH(VALUE) ((VALUE) <= 0x0000FF00U)
#define IS_OB_IROT_SELECT(VALUE) ((VALUE) <= 0xFF000000U)
#define IS_OB_EPOCH(VALUE) ((VALUE) <= 0xFFFFFFU)
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \
((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \
((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \
((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @addtogroup FLASH_Private_Functions
* @{
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H7RSxx_HAL_FLASH_H */
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_flash_ex.h
+262
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/**
******************************************************************************
* @file stm32h7rsxx_hal_flash_ex.h
* @author MCD Application Team
* @brief Header file of FLASH HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7RSxx_HAL_FLASH_EX_H
#define STM32H7RSxx_HAL_FLASH_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal_def.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @addtogroup FLASHEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @addtogroup FLASH_Exported_Types FLASH Exported Types
* @{
*/
/**
* @brief FLASH Erase structure definition
*/
typedef struct
{
uint32_t Index; /*!< Index of the key.
This parameter can be a value between 0 and 31 */
uint32_t Size; /*!< Size of the key.
This parameter must be a value of @ref FLASH_Key_Size */
uint32_t HDPLLevel; /*!< HDPL level of the key.
This parameter must be a value of @ref FLASH_KEY_Level */
} FLASH_KeyConfigTypeDef;
/**
* @brief FLASH CRC configuration structure definition
*/
typedef struct
{
uint32_t TypeCRC; /*!< CRC Selection Type.
This parameter can be a value of @ref FLASHEx_CRC_Selection_Type */
uint32_t BurstSize; /*!< CRC Burst Size.
This parameter can be a value of @ref FLASHEx_CRC_Burst_Size */
uint32_t Sector; /*!< Initial FLASH sector from which starts the CRC computation
This parameter must be a value between 0 and (max number of sector - 1)*/
uint32_t NbSectors; /*!< Number of sectors to be computed.
This parameter must be a value between 1 and
(max number of sectors - value of Initial sector)*/
uint32_t CRCStartAddr; /*!< CRC Start address.
This parameter must be a value between begin address and end address of a bank */
uint32_t CRCEndAddr; /*!< CRC End address.
This parameter must be a value between CRC Start address and end address of a bank */
} FLASH_CRCInitTypeDef;
/**
* @brief FLASH ECC information structure definition
*/
typedef struct
{
uint32_t Area; /*!< Area from which an ECC was detected.
This parameter can be a value of @ref FLASHEx_ECC_Area */
uint32_t Address; /*!< Flash address from which en ECC error was detected.
This parameter must be a value between begin address and end address of the Flash */
uint32_t MasterID; /*!< Master that initiated transfer on which error was detected
This parameter can be a value of @ref FLASHEx_ECC_Master */
} FLASH_EccInfoTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @addtogroup FLASHEx_Exported_Constants
* @{
*/
/** @defgroup FLASH_Key_Size FLASH Option Bytes Key Size
* @{
*/
#define FLASH_KEY_32_BITS 0x0000000U /*!< Key size is 32 bits */
#define FLASH_KEY_64_BITS FLASH_OBKCR_OBKSIZE_0 /*!< Key size is 64 bits */
#define FLASH_KEY_128_BITS FLASH_OBKCR_OBKSIZE_1 /*!< Key size is 128 bits */
#define FLASH_KEY_256_BITS FLASH_OBKCR_OBKSIZE /*!< Key size is 256 bits */
/**
* @}
*/
/** @defgroup FLASH_KEY_Level FLASH Option Bytes Key HDPL level
* @{
*/
#define FLASH_KEY_LEVEL_CURRENT 0x00000000U /*!< Key stored for the HDPL indicated in SBS_HDPLSR */
#define FLASH_KEY_LEVEL_NEXT FLASH_OBKCR_NEXTKL_0 /*!< Key stored for the HDPL indicated in SBS_HDPLSR + 1 */
#define FLASH_KEY_LEVEL_PLUS_TWO FLASH_OBKCR_NEXTKL_1 /*!< Key stored for the HDPL indicated in SBS_HDPLSR + 2 */
/**
* @}
*/
/** @defgroup FLASHEx_CRC_Selection_Type FLASH CRC Selection Type
* @{
*/
#define FLASH_CRC_ADDR 0x00000000U /*!< CRC selection type by address */
#define FLASH_CRC_SECTORS FLASH_CRCCR_CRC_BY_SECT /*!< CRC selection type by sectors */
#define FLASH_CRC_BANK (FLASH_CRCCR_ALL_SECT | FLASH_CRCCR_CRC_BY_SECT) /*!< CRC selection type all bank */
/**
* @}
*/
/** @defgroup FLASHEx_CRC_Burst_Size FLASH CRC Burst Size
* @{
*/
#define FLASH_CRC_BURST_SIZE_4 0x00000000U /*!< Every burst has a size of 4 Flash words (64 Bytes) */
#define FLASH_CRC_BURST_SIZE_16 FLASH_CRCCR_CRC_BURST_0 /*!< Every burst has a size of 16 Flash words (256 Bytes) */
#define FLASH_CRC_BURST_SIZE_64 FLASH_CRCCR_CRC_BURST_1 /*!< Every burst has a size of 64 Flash words (1 kByte) */
#define FLASH_CRC_BURST_SIZE_256 FLASH_CRCCR_CRC_BURST /*!< Every burst has a size of 256 Flash words (4 kBytes) */
/**
* @}
*/
/** @defgroup FLASHEx_ECC_Area FLASH ECC Area
* @{
*/
#define FLASH_ECC_AREA_USER_BANK1 0x00000000U /*!< FLASH bank 1 area */
#define FLASH_ECC_AREA_SYSTEM 0x00000001U /*!< System FLASH area */
#define FLASH_ECC_AREA_OTP 0x00000002U /*!< FLASH OTP area */
#define FLASH_ECC_AREA_READ_ONLY 0x00000004U /*!< FLASH Read-only area */
/**
* @}
*/
/** @defgroup FLASHEx_ECC_Master FLASH ECC Master
* @{
*/
#define FLASH_ECC_MASTER_CPU1 0x00000000U /*!< ECC error occurs on a CPU1 transaction */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup FLASHEx_Exported_Functions
* @{
*/
/* Extended Program operation functions *************************************/
/** @addtogroup FLASHEx_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_FLASHEx_Erase(const FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(const FLASH_EraseInitTypeDef *pEraseInit);
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(const FLASH_OBProgramInitTypeDef *pOBInit);
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
/**
* @}
*/
/** @addtogroup FLASHEx_Exported_Functions_Group2
* @{
*/
HAL_StatusTypeDef HAL_FLASHEx_OTPLockConfig(uint32_t OTPLBlock);
uint32_t HAL_FLASHEx_GetOTPLock(void);
HAL_StatusTypeDef HAL_FLASHEx_KeyConfig(const FLASH_KeyConfigTypeDef *pKeyConfig, const uint32_t *pKey);
HAL_StatusTypeDef HAL_FLASHEx_GetKey(const FLASH_KeyConfigTypeDef *pKeyConfig, uint32_t *pKey);
HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(const FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result);
/**
* @}
*/
/** @addtogroup FLASHEx_Exported_Functions_Group3
* @{
*/
void HAL_FLASHEx_EnableEccCorrectionInterrupt(void);
void HAL_FLASHEx_DisableEccCorrectionInterrupt(void);
void HAL_FLASHEx_EnableEccDetectionInterrupt(void);
void HAL_FLASHEx_DisableEccDetectionInterrupt(void);
void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData);
void HAL_FLASHEx_ECCD_IRQHandler(void);
void HAL_FLASHEx_EccDetectionCallback(void);
void HAL_FLASHEx_EccCorrectionCallback(void);
/**
* @}
*/
/**
* @}
*/
/* Private function ----------------------------------------------------------*/
/** @addtogroup FLASHEx_Private_Functions FLASHEx Private Functions
* @{
*/
void FLASH_SectorErase(uint32_t Sector);
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup FLASHEx_Private_Macros FLASH Private Macros
* @{
*/
#define IS_KEY_INDEX(VALUE) ((VALUE) < 0x20U)
#define IS_KEY_SIZE(VALUE) (((VALUE) == FLASH_KEY_32_BITS) || ((VALUE) == FLASH_KEY_64_BITS) || \
((VALUE) == FLASH_KEY_128_BITS) || ((VALUE) == FLASH_KEY_256_BITS))
#define IS_KEY_HDPL_LEVEL(VALUE) (((VALUE) == FLASH_KEY_LEVEL_CURRENT) || \
((VALUE) == FLASH_KEY_LEVEL_NEXT) || \
((VALUE) == FLASH_KEY_LEVEL_PLUS_TWO))
#define IS_OB_OTP_BLOCK(VALUE) ((VALUE) <= 0xFFFFU)
#define IS_FLASH_TYPE_CRC(VALUE) (((VALUE) == FLASH_CRC_ADDR) || ((VALUE) == FLASH_CRC_SECTORS) ||\
((VALUE) == FLASH_CRC_BANK))
#define IS_FLASH_BURST_SIZE_CRC(VALUE) (((VALUE) == FLASH_CRC_BURST_SIZE_4) || ((VALUE) == FLASH_CRC_BURST_SIZE_16) ||\
((VALUE) == FLASH_CRC_BURST_SIZE_64) || ((VALUE) == FLASH_CRC_BURST_SIZE_256))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H7RSxx_HAL_FLASH_EX_H */
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_gpio.h
+326
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/**
******************************************************************************
* @file stm32h7rsxx_hal_gpio.h
* @author MCD Application Team
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7RSxx_HAL_GPIO_H
#define STM32H7RSxx_HAL_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal_def.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @defgroup GPIO GPIO
* @brief GPIO HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Types GPIO Exported Types
* @{
*/
/**
* @brief GPIO Init structure definition
*/
typedef struct
{
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_pins */
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIO_mode */
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
This parameter can be a value of @ref GPIO_pull */
uint32_t Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIO_speed */
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
} GPIO_InitTypeDef;
/**
* @brief GPIO Bit SET and Bit RESET enumeration
*/
typedef enum
{
GPIO_PIN_RESET = 0U,
GPIO_PIN_SET
} GPIO_PinState;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
* @{
*/
/** @defgroup GPIO_pins GPIO pins
* @{
*/
#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define GPIO_PIN_ALL ((uint16_t)0xFFFF) /* All pins selected */
#define GPIO_PIN_MASK (0x0000FFFFu) /* PIN mask for assert test */
/**
* @}
*/
/** @defgroup GPIO_mode GPIO mode
* @brief GPIO Configuration Mode
* Elements values convention: 0x00WX00YZ
* - W : EXTI trigger detection on 3 bits
* - X : EXTI mode (IT or Event) on 2 bits
* - Y : Output type (Push Pull or Open Drain) on 1 bit
* - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
* @{
*/
#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */
#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */
#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */
#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */
#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */
#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */
#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */
#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */
#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */
#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
/** @defgroup GPIO_speed GPIO speed
* @brief GPIO Output Maximum frequency
* @{
*/
#define GPIO_SPEED_FREQ_LOW 0x00000000U /*!< Low speed */
#define GPIO_SPEED_FREQ_MEDIUM 0x00000001U /*!< Medium speed */
#define GPIO_SPEED_FREQ_HIGH 0x00000002U /*!< High speed */
#define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003U /*!< Very high speed */
/**
* @}
*/
/** @defgroup GPIO_pull GPIO pull
* @brief GPIO Pull-Up or Pull-Down Activation
* @{
*/
#define GPIO_NOPULL 0x00000000U /*!< No Pull-up or Pull-down activation */
#define GPIO_PULLUP 0x00000001U /*!< Pull-up activation */
#define GPIO_PULLDOWN 0x00000002U /*!< Pull-down activation */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
* @{
*/
/**
* @brief Check whether the specified EXTI line flag is set or not.
* @param __EXTI_LINE__ specifies the EXTI line flag to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
/**
* @brief Clear the EXTI's line pending flags.
* @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
/**
* @brief Check whether the specified EXTI line is asserted or not.
* @param __EXTI_LINE__ specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
/**
* @brief Clear the EXTI's line pending bits.
* @param __EXTI_LINE__ specifies the EXTI lines to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
/**
* @brief Generate a Software interrupt on selected EXTI line(s).
* @param __EXTI_LINE__ specifies the EXTI line to be set.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 = (__EXTI_LINE__))
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup GPIO_Private_Constants GPIO Private Constants
* @{
*/
#define GPIO_MODE_Pos 0U
#define GPIO_MODE (0x3UL << GPIO_MODE_Pos)
#define MODE_INPUT (0x0UL << GPIO_MODE_Pos)
#define MODE_OUTPUT (0x1UL << GPIO_MODE_Pos)
#define MODE_AF (0x2UL << GPIO_MODE_Pos)
#define MODE_ANALOG (0x3UL << GPIO_MODE_Pos)
#define OUTPUT_TYPE_Pos 4U
#define OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos)
#define OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos)
#define OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos)
#define EXTI_MODE_Pos 16U
#define EXTI_MODE (0x3UL << EXTI_MODE_Pos)
#define EXTI_IT (0x1UL << EXTI_MODE_Pos)
#define EXTI_EVT (0x2UL << EXTI_MODE_Pos)
#define TRIGGER_MODE_Pos 20U
#define TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos)
#define TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos)
#define TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos)
/**
* @}
*/
/** @defgroup GPIO_Private_Macros GPIO Private Macros
* @{
*/
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
(((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
#define IS_GPIO_COMMON_PIN(__RESETMASK__, __SETMASK__) \
(((uint32_t)(__RESETMASK__) & (uint32_t)(__SETMASK__)) == 0x00U)
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\
((__MODE__) == GPIO_MODE_AF_PP) ||\
((__MODE__) == GPIO_MODE_AF_OD) ||\
((__MODE__) == GPIO_MODE_IT_RISING) ||\
((__MODE__) == GPIO_MODE_IT_FALLING) ||\
((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\
((__MODE__) == GPIO_MODE_EVT_RISING) ||\
((__MODE__) == GPIO_MODE_EVT_FALLING) ||\
((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
((__MODE__) == GPIO_MODE_ANALOG))
#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\
((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\
((__SPEED__) == GPIO_SPEED_FREQ_HIGH) ||\
((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))
#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\
((__PULL__) == GPIO_PULLUP) || \
((__PULL__) == GPIO_PULLDOWN))
/**
* @}
*/
/* Include GPIO HAL Extended module */
#include "stm32h7rsxx_hal_gpio_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
* @brief GPIO Exported Functions
* @{
*/
/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
* @brief Initialization and Configuration functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init);
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
/**
* @}
*/
/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet);
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H7RSxx_HAL_GPIO_H */
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_gpio_ex.h
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/**
******************************************************************************
* @file stm32h7rsxx_hal_gpio_ex.h
* @author MCD Application Team
* @brief Header file of GPIO HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7RSxx_HAL_GPIO_EX_H
#define STM32H7RSxx_HAL_GPIO_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal_def.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @defgroup GPIOEx GPIOEx
* @brief GPIO Extended HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
* @{
*/
/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
* @{
*/
/**
* @brief AF 0 selection
*/
#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO (MCO1 and MCO2) Alternate Function mapping */
#define GPIO_AF0_JTAG ((uint8_t)0x00) /*!< JTAG Alternate Function mapping */
#define GPIO_AF0_SWD ((uint8_t)0x00) /*!< SWD Alternate Function mapping */
#define GPIO_AF0_RTC ((uint8_t)0x00) /*!< RCT_OUT Alternate Function mapping */
#define GPIO_AF0_TRACE ((uint8_t)0x00) /*!< TRACE Alternate Function mapping */
#define GPIO_AF0_PWR ((uint8_t)0x00) /*!< PWR Alternate Function mapping */
/**
* @brief AF 1 selection
*/
#define GPIO_AF1_ADF1 ((uint8_t)0x01) /*!< ADF1 Alternate Function mapping */
#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /*!< LPTIM1 Alternate Function mapping */
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */
#define GPIO_AF1_TIM16 ((uint8_t)0x01) /*!< TIM16 Alternate Function mapping */
#define GPIO_AF1_TIM17 ((uint8_t)0x01) /*!< TIM17 Alternate Function mapping */
/**
* @brief AF 2 selection
*/
#define GPIO_AF2_GFXTIM ((uint8_t)0x02) /*!< GFXTIM Alternate Function mapping */
#define GPIO_AF2_SAI1 ((uint8_t)0x02) /*!< SAI1 Alternate Function mapping */
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /*!< TIM3 Alternate Function mapping */
#define GPIO_AF2_TIM4 ((uint8_t)0x02) /*!< TIM4 Alternate Function mapping */
#define GPIO_AF2_TIM5 ((uint8_t)0x02) /*!< TIM5 Alternate Function mapping */
#define GPIO_AF2_TIM12 ((uint8_t)0x02) /*!< TIM12 Alternate Function mapping */
#define GPIO_AF2_TIM15 ((uint8_t)0x02) /*!< TIM15 Alternate Function mapping */
/**
* @brief AF 3 selection
*/
#define GPIO_AF3_ADF1 ((uint8_t)0x03) /*!< ADF1 Alternate Function mapping */
#define GPIO_AF3_LPTIM2 ((uint8_t)0x03) /*!< LPTIM2 Alternate Function mapping */
#define GPIO_AF3_LPTIM3 ((uint8_t)0x03) /*!< LPTIM3 Alternate Function mapping */
#define GPIO_AF3_LPTIM4 ((uint8_t)0x03) /*!< LPTIM4 Alternate Function mapping */
#define GPIO_AF3_LPTIM5 ((uint8_t)0x03) /*!< LPTIM5 Alternate Function mapping */
#define GPIO_AF3_LPUART1 ((uint8_t)0x03) /*!< LPUART1 Alternate Function mapping */
#define GPIO_AF3_TIM9 ((uint8_t)0x03) /*!< TIM9 Alternate Function mapping */
#define GPIO_AF3_USART3 ((uint8_t)0x03) /*!< USART3 Alternate Function mapping */
/**
* @brief AF 4 selection
*/
#define GPIO_AF4_CEC ((uint8_t)0x04) /*!< CEC Alternate Function mapping */
#define GPIO_AF4_DCMIPP ((uint8_t)0x04) /*!< DCMIPP Alternate Function mapping */
#define GPIO_AF4_ETH ((uint8_t)0x04) /*!< ETH Alternate Function mapping */
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /*!< I2C2 Alternate Function mapping */
#define GPIO_AF4_I2C3 ((uint8_t)0x04) /*!< I2C3 Alternate Function mapping */
#define GPIO_AF4_I3C1 ((uint8_t)0x04) /*!< I3C1 Alternate Function mapping */
#define GPIO_AF4_TIM15 ((uint8_t)0x04) /*!< TIM15 Alternate Function mapping */
#define GPIO_AF4_USART1 ((uint8_t)0x04) /*!< USART1 Alternate Function mapping */
/**
* @brief AF 5 selection
*/
#define GPIO_AF5_CEC ((uint8_t)0x05) /*!< CEC Alternate Function mapping */
#define GPIO_AF5_DCMIPP ((uint8_t)0x05) /*!< DCMIPP Alternate Function mapping */
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1/I2S1 Alternate Function mapping */
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2/I2S2 Alternate Function mapping */
#define GPIO_AF5_SPI3 ((uint8_t)0x05) /*!< SPI3/I2S3 Alternate Function mapping */
#define GPIO_AF5_SPI4 ((uint8_t)0x05) /*!< SPI4 Alternate Function mapping */
#define GPIO_AF5_SPI5 ((uint8_t)0x05) /*!< SPI5 Alternate Function mapping */
#define GPIO_AF5_SPI6 ((uint8_t)0x05) /*!< SPI6/I2S6 Alternate Function mapping */
/**
* @brief AF 6 selection
*/
#define GPIO_AF6_PSSI ((uint8_t)0x06) /*!< PSSI Alternate Function mapping */
#define GPIO_AF6_SAI1 ((uint8_t)0x06) /*!< SAI1 Alternate Function mapping */
#define GPIO_AF6_SDMMC1 ((uint8_t)0x06) /*!< SDMMC1 Alternate Function mapping */
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /*!< SPI3/I2S3 Alternate Function mapping */
#define GPIO_AF6_SPI4 ((uint8_t)0x06) /*!< SPI4 Alternate Function mapping */
#define GPIO_AF6_UART4 ((uint8_t)0x06) /*!< UART4 Alternate Function mapping */
#define GPIO_AF6_UCPD ((uint8_t)0x06) /*!< UCPD Alternate Function mapping */
/**
* @brief AF 7 selection
*/
#define GPIO_AF7_FMC ((uint8_t)0x07) /*!< FMC Alternate Function mapping */
#define GPIO_AF7_SDMMC1 ((uint8_t)0x07) /*!< SDMMC1 Alternate Function mapping */
#define GPIO_AF7_SPI2 ((uint8_t)0x07) /*!< SPI2/I2S2 Alternate Function mapping */
#define GPIO_AF7_SPI3 ((uint8_t)0x07) /*!< SPI3/I2S3 Alternate Function mapping */
#define GPIO_AF7_SPI6 ((uint8_t)0x07) /*!< SPI6/I2S6 Alternate Function mapping */
#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */
#define GPIO_AF7_USART2 ((uint8_t)0x07) /*!< USART2 Alternate Function mapping */
#define GPIO_AF7_USART3 ((uint8_t)0x07) /*!< USART3 Alternate Function mapping */
#define GPIO_AF7_UART7 ((uint8_t)0x07) /*!< UART7 Alternate Function mapping */
/**
* @brief AF 8 selection
*/
#define GPIO_AF8_GFXTIM ((uint8_t)0x08) /*!< GFXTIM Alternate Function mapping */
#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /*!< LPUART1 Alternate Function mapping */
#define GPIO_AF8_PSSI ((uint8_t)0x08) /*!< PSSI Alternate Function mapping */
#define GPIO_AF8_SAI2 ((uint8_t)0x08) /*!< SAI2 Alternate Function mapping */
#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /*!< SDMMC1 Alternate Function mapping */
#define GPIO_AF8_SPDIFRX ((uint8_t)0x08) /*!< SPDIFRX Alternate Function mapping */
#define GPIO_AF8_SPI6 ((uint8_t)0x08) /*!< SPI6/I2S6 Alternate Function mapping */
#define GPIO_AF8_UART4 ((uint8_t)0x08) /*!< UART4 Alternate Function mapping */
#define GPIO_AF8_UART5 ((uint8_t)0x08) /*!< UART5 Alternate Function mapping */
#define GPIO_AF8_UART8 ((uint8_t)0x08) /*!< UART8 Alternate Function mapping */
/**
* @brief AF 9 selection
*/
#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /*!< FDCAN1 Alternate Function mapping */
#define GPIO_AF9_FDCAN2 ((uint8_t)0x09) /*!< FDCAN2 Alternate Function mapping */
#define GPIO_AF9_FMC ((uint8_t)0x09) /*!< FMC Alternate Function mapping */
#define GPIO_AF9_XSPIM_P1 ((uint8_t)0x09) /*!< XSPIM Manager Port 1 Alternate Function mapping */
#define GPIO_AF9_XSPIM_P2 ((uint8_t)0x09) /*!< XSPIM Manager Port 2 Alternate Function mapping */
#define GPIO_AF9_PSSI ((uint8_t)0x09) /*!< PSSI Alternate Function mapping */
#define GPIO_AF9_SDMMC2 ((uint8_t)0x09) /*!< SDMMC2 Alternate Function mapping */
#define GPIO_AF9_SPDIFRX ((uint8_t)0x09) /*!< SPDIFRX Alternate Function mapping */
#define GPIO_AF9_SPI5 ((uint8_t)0x09) /*!< SPI5 Alternate Function mapping */
#define GPIO_AF9_TIM13 ((uint8_t)0x09) /*!< TIM13 Alternate Function mapping */
#define GPIO_AF9_TIM14 ((uint8_t)0x09) /*!< TIM14 Alternate Function mapping */
/**
* @brief AF 10 selection
*/
#define GPIO_AF10_CRS ((uint8_t)0x0A) /*!< CRS Alternate Function mapping */
#define GPIO_AF10_FMC ((uint8_t)0x0A) /*!< FMC Alternate Function mapping */
#define GPIO_AF10_LTDC ((uint8_t)0x0A) /*!< LTDC Alternate Function mapping */
#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /*!< OTG FS Alternate Function mapping */
#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /*!< OTG HS Alternate Function mapping */
#define GPIO_AF10_SAI2 ((uint8_t)0x0A) /*!< SAI2 Alternate Function mapping */
#define GPIO_AF10_SDMMC2 ((uint8_t)0x0A) /*!< SDMMC2 Alternate Function mapping */
#define GPIO_AF10_SPI1 ((uint8_t)0x0A) /*!< SPI1/I2S1 Alternate Function mapping */
/**
* @brief AF 11 selection
*/
#define GPIO_AF11_ETH ((uint8_t)0x0B) /*!< ETH Alternate Function mapping */
#define GPIO_AF11_LTDC ((uint8_t)0x0B) /*!< LTDC Alternate Function mapping */
#define GPIO_AF11_MDIOS ((uint8_t)0x0B) /*!< MDIOS Alternate Function mapping */
#define GPIO_AF11_SDMMC1 ((uint8_t)0x0B) /*!< SDMMC1 Alternate Function mapping */
#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /*!< SDMMC2 Alternate Function mapping */
#define GPIO_AF11_UART7 ((uint8_t)0x0B) /*!< UART7 Alternate Function mapping */
/**
* @brief AF 12 selection
*/
#define GPIO_AF12_FMC ((uint8_t)0x0C) /*!< FMC Alternate Function mapping */
#define GPIO_AF12_GFXTIM ((uint8_t)0x0C) /*!< GFXTIM Alternate Function mapping */
#define GPIO_AF12_LTDC ((uint8_t)0x0C) /*!< TIM1 Alternate Function mapping */
#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /*!< SDMMC1 Alternate Function mapping */
/**
* @brief AF 13 selection
*/
#define GPIO_AF13_DCMIPP ((uint8_t)0x0D) /*!< DCMIPP Alternate Function mapping */
#define GPIO_AF13_GFXTIM ((uint8_t)0x0D) /*!< GFXTIM Alternate Function mapping */
#define GPIO_AF13_LTDC ((uint8_t)0x0D) /*!< TIM1 Alternate Function mapping */
/**
* @brief AF 14 selection
*/
#define GPIO_AF14_FMC ((uint8_t)0x0E) /*!< FMC Alternate Function mapping */
#define GPIO_AF14_LTDC ((uint8_t)0x0E) /*!< LTDC Alternate Function mapping */
#define GPIO_AF14_MDIOS ((uint8_t)0x0E) /*!< MDIOS Alternate Function mapping */
#define GPIO_AF14_PSSI ((uint8_t)0x0E) /*!< PSSI Alternate Function mapping */
#define GPIO_AF14_TIM1 ((uint8_t)0x0E) /*!< TIM1 Alternate Function mapping */
#define GPIO_AF14_UART5 ((uint8_t)0x0E) /*!< UART5 Alternate Function mapping */
/**
* @brief AF 15 selection
*/
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
* @{
*/
/** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index
* @{
*/
#define GPIO_GET_INDEX(__GPIOx__) (((uint32_t )(__GPIOx__) & (~GPIOA_BASE)) >> 10)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H7RSxx_HAL_GPIO_EX_H */
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_gpu2d.h
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/**
******************************************************************************
* @file stm32h7rsxx_hal_gpu2d.h
* @author MCD Application Team
* @brief Header file of GPU2D HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7RSxx_HAL_GPU2D_H
#define STM32H7RSxx_HAL_GPU2D_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal_def.h"
#if defined (GPU2D)
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @defgroup GPU2D GPU2D
* @brief GPU2D HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup GPU2D_Exported_Types GPU2D Exported Types
* @{
*/
/**
* @brief HAL GPU2D State enumeration definition
*/
typedef enum
{
HAL_GPU2D_STATE_RESET = 0x00U, /*!< GPU2D not yet initialized or disabled */
HAL_GPU2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
HAL_GPU2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
HAL_GPU2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_GPU2D_STATE_ERROR = 0x04U
} HAL_GPU2D_StateTypeDef;
/**
* @brief GPU2D_TypeDef definition
*/
typedef uint32_t GPU2D_TypeDef;
/**
* @brief GPU2D handle Structure definition
*/
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
typedef struct __GPU2D_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
{
GPU2D_TypeDef Instance; /*!< GPU2D register base address. */
HAL_LockTypeDef Lock; /*!< GPU2D lock. */
__IO HAL_GPU2D_StateTypeDef State; /*!< GPU2D transfer state. */
__IO uint32_t ErrorCode; /*!< GPU2D error code. */
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
void (* CommandListCpltCallback)(struct __GPU2D_HandleTypeDef *hgpu2d, uint32_t CmdListID); /*!< GPU2D Command Complete Callback */
void (* MspInitCallback)(struct __GPU2D_HandleTypeDef *hgpu2d); /*!< GPU2D Msp Init callback */
void (* MspDeInitCallback)(struct __GPU2D_HandleTypeDef *hgpu2d); /*!< GPU2D Msp DeInit callback */
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
} GPU2D_HandleTypeDef;
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
/**
* @brief HAL GPU2D Callback ID enumeration definition
*/
typedef enum
{
HAL_GPU2D_MSPINIT_CB_ID = 0x00U, /*!< GPU2D MspInit callback ID */
HAL_GPU2D_MSPDEINIT_CB_ID = 0x01U, /*!< GPU2D MspDeInit callback ID */
} HAL_GPU2D_CallbackIDTypeDef;
/** @defgroup HAL_GPU2D_Callback_pointer_definition HAL GPU2D Callback pointer definition
* @brief HAL GPU2D Callback pointer definition
* @{
*/
typedef void (*pGPU2D_CallbackTypeDef)(GPU2D_HandleTypeDef *hgpu2d); /*!< pointer to an GPU2D Callback function */
typedef void (*pGPU2D_CommandListCpltCallbackTypeDef)(GPU2D_HandleTypeDef *hgpu2d, uint32_t CmdID); /*!< pointer to an GPU2D Command List Complete Callback function */
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPU2D_Exported_Constants GPU2D Exported Constants
* @{
*/
/** @defgroup GPU2D_Error_Code_definition GPU2D Error Code definition
* @brief GPU2D Error Code definition
* @{
*/
#define HAL_GPU2D_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_GPU2D_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
#define HAL_GPU2D_ERROR_INVALID_CALLBACK (0x00000002U) /*!< Invalid callback error */
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
/**
* @}
*/
/** @defgroup GPU2D_Interrupt_configuration_definition GPU2D Interrupt configuration definition
* @brief GPU2D Interrupt definition
* @{
*/
#define GPU2D_IT_CLC 0x00000001U /*!< Command List Complete Interrupt */
/**
* @}
*/
/** @defgroup GPU2D_Flag_definition GPU2D Flag definition
* @brief GPU2D Flags definition
* @{
*/
#define GPU2D_FLAG_CLC 0x00000001U /*!< Command List Complete Interrupt Flag */
/**
* @}
*/
/**
* @}
*/
/* Exported macros ------------------------------------------------------------*/
/** @defgroup GPU2D_Exported_Macros GPU2D Exported Macros
* @{
*/
/** @brief Reset GPU2D handle state
* @param __HANDLE__: specifies the GPU2D handle.
* @retval None
*/
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
#define __HAL_GPU2D_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_GPU2D_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
(__HANDLE__)->CommandListCpltCallback = NULL; \
} while(0)
#else /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 0 */
#define __HAL_GPU2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_GPU2D_STATE_RESET)
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
/* Interrupt & Flag management */
/**
* @brief Get the GPU2D pending flags.
* @param __HANDLE__: GPU2D handle
* @param __FLAG__: flag to check.
* This parameter can be one of the following values:
* @arg GPU2D_FLAG_CLC: Command List Complete interrupt mask
* @retval The state of FLAG.
*/
#define __HAL_GPU2D_GET_FLAG(__HANDLE__, __FLAG__) (READ_REG(*(__IO uint32_t *)((uint32_t)(__HANDLE__)->Instance\
+ GPU2D_ITCTRL)) & (__FLAG__))
/**
* @brief Clear the GPU2D pending flags.
* @param __HANDLE__: GPU2D handle
* @param __FLAG__: specifies the flag to clear.
* This parameter can be one of the following values:
* @arg GPU2D_FLAG_CLC: Command List Complete interrupt mask
* @retval None
*/
#define __HAL_GPU2D_CLEAR_FLAG(__HANDLE__, __FLAG__) do { \
__IO uint32_t *tmpreg = \
(__IO uint32_t *)((uint32_t)(__HANDLE__)->Instance\
+ GPU2D_ITCTRL); \
CLEAR_BIT(*tmpreg, __FLAG__); \
} while(0U)
/**
* @brief Check whether the specified GPU2D interrupt source is enabled or not.
* @param __HANDLE__: GPU2D handle
* @param __INTERRUPT__: specifies the GPU2D interrupt source to check.
* This parameter can be one of the following values:
* @arg GPU2D_IT_CLC: Command List Complete interrupt mask
* @retval The state of INTERRUPT source.
*/
#define __HAL_GPU2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_REG(*(__IO uint32_t *)\
((uint32_t)(__HANDLE__)->Instance\
+ GPU2D_ITCTRL)) & (__INTERRUPT__))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup GPU2D_Exported_Functions GPU2D Exported Functions
* @{
*/
/** @addtogroup GPU2D_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions *******************************/
HAL_StatusTypeDef HAL_GPU2D_Init(GPU2D_HandleTypeDef *hgpu2d);
HAL_StatusTypeDef HAL_GPU2D_DeInit(GPU2D_HandleTypeDef *hgpu2d);
void HAL_GPU2D_MspInit(GPU2D_HandleTypeDef *hgpu2d);
void HAL_GPU2D_MspDeInit(GPU2D_HandleTypeDef *hgpu2d);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_GPU2D_RegisterCallback(GPU2D_HandleTypeDef *hgpu2d, HAL_GPU2D_CallbackIDTypeDef CallbackID,
pGPU2D_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_GPU2D_UnRegisterCallback(GPU2D_HandleTypeDef *hgpu2d, HAL_GPU2D_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_GPU2D_RegisterCommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d,
pGPU2D_CommandListCpltCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_GPU2D_UnRegisterCommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d);
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
/**
* @}
*/
/** @addtogroup GPU2D_Exported_Functions_Group2 IO operation functions
* @{
*/
/* IO operation functions *******************************************************/
uint32_t HAL_GPU2D_ReadRegister(const GPU2D_HandleTypeDef *hgpu2d, uint32_t offset);
HAL_StatusTypeDef HAL_GPU2D_WriteRegister(GPU2D_HandleTypeDef *hgpu2d, uint32_t offset, uint32_t value);
void HAL_GPU2D_IRQHandler(GPU2D_HandleTypeDef *hgpu2d);
void HAL_GPU2D_ER_IRQHandler(GPU2D_HandleTypeDef *hgpu2d);
void HAL_GPU2D_CommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d, uint32_t CmdListID);
void HAL_GPU2D_ErrorCallback(GPU2D_HandleTypeDef *hgpu2d);
/**
* @}
*/
/** @addtogroup GPU2D_Exported_Functions_Group3 Peripheral State and Error functions
* @{
*/
/* Peripheral State functions ***************************************************/
HAL_GPU2D_StateTypeDef HAL_GPU2D_GetState(GPU2D_HandleTypeDef const *const hgpu2d);
uint32_t HAL_GPU2D_GetError(GPU2D_HandleTypeDef const *const hgpu2d);
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup GPU2D_Private_Constants GPU2D Private Constants
* @{
*/
#define GPU2D_ITCTRL (0x0F8U) /*!< GPU2D Interrupt Control Register Offset */
#define GPU2D_CLID (0x148U) /*!< GPU2D Last Command List Identifier Register Offset */
#define GPU2D_BREAKPOINT (0x080U) /*!< GPU2D Breakpoint Register Offset */
#define GPU2D_SYS_INTERRUPT (0xff8U) /*!< GPU2D System Interrupt Register Offset */
/** @defgroup GPU2D_Offset GPU2D Last Register Offset
* @{
*/
#define GPU2D_OFFSET 0x1000U /*!< Last GPU2D Register Offset */
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup GPU2D_Private_Macros GPU2D Private Macros
* @{
*/
#define IS_GPU2D_OFFSET(OFFSET) ((OFFSET) < GPU2D_OFFSET)
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (GPU2D) */
#ifdef __cplusplus
}
#endif
#endif /* STM32H7RSxx_HAL_GPU2D_H */
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_i2c.h
+842
View File
@@ -0,0 +1,842 @@
/**
******************************************************************************
* @file stm32h7rsxx_hal_i2c.h
* @author MCD Application Team
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7RSxx_HAL_I2C_H
#define STM32H7RSxx_HAL_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal_def.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @addtogroup I2C
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup I2C_Exported_Types I2C Exported Types
* @{
*/
/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
* @brief I2C Configuration Structure definition
* @{
*/
typedef struct
{
uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
This parameter calculated by referring to I2C initialization section
in Reference manual */
uint32_t OwnAddress1; /*!< Specifies the first device own address.
This parameter can be a 7-bit or 10-bit address. */
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
This parameter can be a value of @ref I2C_ADDRESSING_MODE */
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
This parameter can be a 7-bit address. */
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing
mode is selected.
This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
} I2C_InitTypeDef;
/**
* @}
*/
/** @defgroup HAL_state_structure_definition HAL state structure definition
* @brief HAL State structure definition
* @note HAL I2C State value coding follow below described bitmap :\n
* b7-b6 Error information\n
* 00 : No Error\n
* 01 : Abort (Abort user request on going)\n
* 10 : Timeout\n
* 11 : Error\n
* b5 Peripheral initialization status\n
* 0 : Reset (peripheral not initialized)\n
* 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
* b4 (not used)\n
* x : Should be set to 0\n
* b3\n
* 0 : Ready or Busy (No Listen mode ongoing)\n
* 1 : Listen (peripheral in Address Listen Mode)\n
* b2 Intrinsic process state\n
* 0 : Ready\n
* 1 : Busy (peripheral busy with some configuration or internal operations)\n
* b1 Rx state\n
* 0 : Ready (no Rx operation ongoing)\n
* 1 : Busy (Rx operation ongoing)\n
* b0 Tx state\n
* 0 : Ready (no Tx operation ongoing)\n
* 1 : Busy (Tx operation ongoing)
* @{
*/
typedef enum
{
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
process is ongoing */
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
process is ongoing */
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
} HAL_I2C_StateTypeDef;
/**
* @}
*/
/** @defgroup HAL_mode_structure_definition HAL mode structure definition
* @brief HAL Mode structure definition
* @note HAL I2C Mode value coding follow below described bitmap :\n
* b7 (not used)\n
* x : Should be set to 0\n
* b6\n
* 0 : None\n
* 1 : Memory (HAL I2C communication is in Memory Mode)\n
* b5\n
* 0 : None\n
* 1 : Slave (HAL I2C communication is in Slave Mode)\n
* b4\n
* 0 : None\n
* 1 : Master (HAL I2C communication is in Master Mode)\n
* b3-b2-b1-b0 (not used)\n
* xxxx : Should be set to 0000
* @{
*/
typedef enum
{
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
} HAL_I2C_ModeTypeDef;
/**
* @}
*/
/** @defgroup I2C_Error_Code_definition I2C Error Code definition
* @brief I2C Error Code definition
* @{
*/
#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */
#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */
#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */
#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
/**
* @}
*/
/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
* @brief I2C handle Structure definition
* @{
*/
typedef struct __I2C_HandleTypeDef
{
I2C_TypeDef *Instance; /*!< I2C registers base address */
I2C_InitTypeDef Init; /*!< I2C communication parameters */
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
uint16_t XferSize; /*!< I2C transfer size */
__IO uint16_t XferCount; /*!< I2C transfer counter */
__IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can
be a value of @ref I2C_XFEROPTIONS */
__IO uint32_t PreviousState; /*!< I2C communication Previous state */
HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
/*!< I2C transfer IRQ handler function pointer */
#if defined(HAL_DMA_MODULE_ENABLED)
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
#endif /*HAL_DMA_MODULE_ENABLED*/
HAL_LockTypeDef Lock; /*!< I2C locking object */
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
__IO uint32_t ErrorCode; /*!< I2C Error code */
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
__IO uint32_t Devaddress; /*!< I2C Target device address */
__IO uint32_t Memaddress; /*!< I2C Target memory address */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Master Tx Transfer completed callback */
void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Master Rx Transfer completed callback */
void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Slave Tx Transfer completed callback */
void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Slave Rx Transfer completed callback */
void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Listen Complete callback */
void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Memory Tx Transfer completed callback */
void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Memory Rx Transfer completed callback */
void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Error callback */
void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Abort callback */
void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
/*!< I2C Slave Address Match callback */
void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Msp Init callback */
void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Msp DeInit callback */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
} I2C_HandleTypeDef;
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
/**
* @brief HAL I2C Callback ID enumeration definition
*/
typedef enum
{
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */
HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */
HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */
HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */
HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */
HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */
HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */
HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */
HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */
HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */
} HAL_I2C_CallbackIDTypeDef;
/**
* @brief HAL I2C Callback pointer definition
*/
typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c);
/*!< pointer to an I2C callback function */
typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection,
uint16_t AddrMatchCode);
/*!< pointer to an I2C Address Match callback function */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2C_Exported_Constants I2C Exported Constants
* @{
*/
/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
* @{
*/
#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
/* List of XferOptions in usage of :
* 1- Restart condition in all use cases (direction change or not)
*/
#define I2C_OTHER_FRAME (0x000000AAU)
#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)
/**
* @}
*/
/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
* @{
*/
#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)
#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)
/**
* @}
*/
/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
* @{
*/
#define I2C_DUALADDRESS_DISABLE (0x00000000U)
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
/**
* @}
*/
/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
* @{
*/
#define I2C_OA2_NOMASK ((uint8_t)0x00U)
#define I2C_OA2_MASK01 ((uint8_t)0x01U)
#define I2C_OA2_MASK02 ((uint8_t)0x02U)
#define I2C_OA2_MASK03 ((uint8_t)0x03U)
#define I2C_OA2_MASK04 ((uint8_t)0x04U)
#define I2C_OA2_MASK05 ((uint8_t)0x05U)
#define I2C_OA2_MASK06 ((uint8_t)0x06U)
#define I2C_OA2_MASK07 ((uint8_t)0x07U)
/**
* @}
*/
/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
* @{
*/
#define I2C_GENERALCALL_DISABLE (0x00000000U)
#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
/**
* @}
*/
/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
* @{
*/
#define I2C_NOSTRETCH_DISABLE (0x00000000U)
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
/**
* @}
*/
/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
* @{
*/
#define I2C_MEMADD_SIZE_8BIT (0x00000001U)
#define I2C_MEMADD_SIZE_16BIT (0x00000002U)
/**
* @}
*/
/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
* @{
*/
#define I2C_DIRECTION_TRANSMIT (0x00000000U)
#define I2C_DIRECTION_RECEIVE (0x00000001U)
/**
* @}
*/
/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
* @{
*/
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define I2C_SOFTEND_MODE (0x00000000U)
/**
* @}
*/
/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
* @{
*/
#define I2C_NO_STARTSTOP (0x00000000U)
#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
/**
* @}
*/
/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
* @brief I2C Interrupt definition
* Elements values convention: 0xXXXXXXXX
* - XXXXXXXX : Interrupt control mask
* @{
*/
#define I2C_IT_ERRI I2C_CR1_ERRIE
#define I2C_IT_TCI I2C_CR1_TCIE
#define I2C_IT_STOPI I2C_CR1_STOPIE
#define I2C_IT_NACKI I2C_CR1_NACKIE
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
#define I2C_IT_RXI I2C_CR1_RXIE
#define I2C_IT_TXI I2C_CR1_TXIE
/**
* @}
*/
/** @defgroup I2C_Flag_definition I2C Flag definition
* @{
*/
#define I2C_FLAG_TXE I2C_ISR_TXE
#define I2C_FLAG_TXIS I2C_ISR_TXIS
#define I2C_FLAG_RXNE I2C_ISR_RXNE
#define I2C_FLAG_ADDR I2C_ISR_ADDR
#define I2C_FLAG_AF I2C_ISR_NACKF
#define I2C_FLAG_STOPF I2C_ISR_STOPF
#define I2C_FLAG_TC I2C_ISR_TC
#define I2C_FLAG_TCR I2C_ISR_TCR
#define I2C_FLAG_BERR I2C_ISR_BERR
#define I2C_FLAG_ARLO I2C_ISR_ARLO
#define I2C_FLAG_OVR I2C_ISR_OVR
#define I2C_FLAG_PECERR I2C_ISR_PECERR
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define I2C_FLAG_ALERT I2C_ISR_ALERT
#define I2C_FLAG_BUSY I2C_ISR_BUSY
#define I2C_FLAG_DIR I2C_ISR_DIR
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup I2C_Exported_Macros I2C Exported Macros
* @{
*/
/** @brief Reset I2C handle state.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_I2C_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/** @brief Enable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval None
*/
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
/** @brief Disable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the interrupt source to disable.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval None
*/
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
/** @brief Check whether the specified I2C interrupt source is enabled or not.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the I2C interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \
(__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified I2C flag is set or not.
* @param __HANDLE__ specifies the I2C Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref I2C_FLAG_TXE Transmit data register empty
* @arg @ref I2C_FLAG_TXIS Transmit interrupt status
* @arg @ref I2C_FLAG_RXNE Receive data register not empty
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
* @arg @ref I2C_FLAG_STOPF STOP detection flag
* @arg @ref I2C_FLAG_TC Transfer complete (master mode)
* @arg @ref I2C_FLAG_TCR Transfer complete reload
* @arg @ref I2C_FLAG_BERR Bus error
* @arg @ref I2C_FLAG_ARLO Arbitration lost
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
* @arg @ref I2C_FLAG_PECERR PEC error in reception
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref I2C_FLAG_ALERT SMBus alert
* @arg @ref I2C_FLAG_BUSY Bus busy
* @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)
*
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define I2C_FLAG_MASK (0x0001FFFFU)
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
(__FLAG__)) == (__FLAG__)) ? SET : RESET)
/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
* @param __HANDLE__ specifies the I2C Handle.
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg @ref I2C_FLAG_TXE Transmit data register empty
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
* @arg @ref I2C_FLAG_STOPF STOP detection flag
* @arg @ref I2C_FLAG_BERR Bus error
* @arg @ref I2C_FLAG_ARLO Arbitration lost
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
* @arg @ref I2C_FLAG_PECERR PEC error in reception
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref I2C_FLAG_ALERT SMBus alert
*
* @retval None
*/
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \
((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
((__HANDLE__)->Instance->ICR = (__FLAG__)))
/** @brief Enable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Disable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
/**
* @}
*/
/* Include I2C HAL Extended module */
#include "stm32h7rsxx_hal_i2c_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2C_Exported_Functions
* @{
*/
/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions******************************/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
pI2C_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* IO operation functions ****************************************************/
/******* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
uint32_t Timeout);
/******* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
#if defined(HAL_DMA_MODULE_ENABLED)
/******* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
#endif /*HAL_DMA_MODULE_ENABLED*/
/**
* @}
*/
/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
* @{
*/
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
* @{
*/
/* Peripheral State, Mode and Error functions *********************************/
HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c);
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c);
uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2C_Private_Constants I2C Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2C_Private_Macro I2C Private Macros
* @{
*/
#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
((MODE) == I2C_ADDRESSINGMODE_10BIT))
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
((ADDRESS) == I2C_DUALADDRESS_ENABLE))
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
((MASK) == I2C_OA2_MASK01) || \
((MASK) == I2C_OA2_MASK02) || \
((MASK) == I2C_OA2_MASK03) || \
((MASK) == I2C_OA2_MASK04) || \
((MASK) == I2C_OA2_MASK05) || \
((MASK) == I2C_OA2_MASK06) || \
((MASK) == I2C_OA2_MASK07))
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
((CALL) == I2C_GENERALCALL_ENABLE))
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
((STRETCH) == I2C_NOSTRETCH_ENABLE))
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
((SIZE) == I2C_MEMADD_SIZE_16BIT))
#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
((MODE) == I2C_AUTOEND_MODE) || \
((MODE) == I2C_SOFTEND_MODE))
#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
((REQUEST) == I2C_GENERATE_START_READ) || \
((REQUEST) == I2C_GENERATE_START_WRITE) || \
((REQUEST) == I2C_NO_STARTSTOP))
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
((REQUEST) == I2C_NEXT_FRAME) || \
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \
IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
(uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
I2C_CR2_RD_WRN)))
#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \
>> 16U))
#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \
>> 16U))
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
(uint16_t)(0xFF00U))) >> 8U)))
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
(~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
(I2C_CR2_ADD10) | (I2C_CR2_START) | \
(I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)))
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
/**
* @}
*/
/* Private Functions ---------------------------------------------------------*/
/** @defgroup I2C_Private_Functions I2C Private Functions
* @{
*/
/* Private functions are defined in stm32h7rsxx_hal_i2c.c file */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H7RSxx_HAL_I2C_H */
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_i2c_ex.h
+156
View File
@@ -0,0 +1,156 @@
/**
******************************************************************************
* @file stm32h7rsxx_hal_i2c_ex.h
* @author MCD Application Team
* @brief Header file of I2C HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7RSxx_HAL_I2C_EX_H
#define STM32H7RSxx_HAL_I2C_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal_def.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @addtogroup I2CEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
* @{
*/
/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
* @{
*/
#define I2C_ANALOGFILTER_ENABLE 0x00000000U
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
/**
* @}
*/
/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
* @{
*/
#define I2C_FASTMODEPLUS_ENABLE 0x00000000U /*!< Enable Fast Mode Plus */
#define I2C_FASTMODEPLUS_DISABLE 0x00000001U /*!< Disable Fast Mode Plus */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros
* @{
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
* @{
*/
/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
* @{
*/
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
/**
* @}
*/
/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
* @{
*/
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
* @{
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigFastModePlus(I2C_HandleTypeDef *hi2c, uint32_t FastModePlus);
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
* @{
*/
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
((FILTER) == I2C_ANALOGFILTER_DISABLE))
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define IS_I2C_FASTMODEPLUS(__CONFIG__) (((__CONFIG__) == (I2C_FASTMODEPLUS_ENABLE)) || \
((__CONFIG__) == (I2C_FASTMODEPLUS_DISABLE)))
/**
* @}
*/
/* Private Functions ---------------------------------------------------------*/
/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
* @{
*/
/* Private functions are defined in stm32h7rsxx_hal_i2c_ex.c file */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H7RSxx_HAL_I2C_EX_H */
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_i2s.h
+668
View File
@@ -0,0 +1,668 @@
/**
******************************************************************************
* @file stm32h7rsxx_hal_i2s.h
* @author MCD Application Team
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7RSxx_HAL_I2S_H
#define STM32H7RSxx_HAL_I2S_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal_def.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @addtogroup I2S
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup I2S_Exported_Types I2S Exported Types
* @{
*/
/**
* @brief I2S Init structure definition
*/
typedef struct
{
uint32_t Mode; /*!< Specifies the I2S operating mode.
This parameter can be a value of @ref I2S_Mode */
uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
This parameter can be a value of @ref I2S_Standard */
uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
This parameter can be a value of @ref I2S_Data_Format */
uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
This parameter can be a value of @ref I2S_MCLK_Output */
uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
This parameter can be a value of @ref I2S_Audio_Frequency */
uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
This parameter can be a value of @ref I2S_Clock_Polarity */
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref I2S_MSB_LSB_Transmission */
uint32_t WSInversion; /*!< Control the Word Select Inversion.
This parameter can be a value of @ref I2S_WSInversion */
uint32_t Data24BitAlignment; /*!< Specifies the Data Padding for 24 bits data length
This parameter can be a value of @ref I2S_Data_24Bit_Alignment */
uint32_t MasterKeepIOState; /*!< Control of Alternate function GPIOs state
This parameter can be a value of @ref I2S_Master_Keep_IO_State */
} I2S_InitTypeDef;
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_I2S_STATE_RESET = 0x00UL, /*!< I2S not yet initialized or disabled */
HAL_I2S_STATE_READY = 0x01UL, /*!< I2S initialized and ready for use */
HAL_I2S_STATE_BUSY = 0x02UL, /*!< I2S internal process is ongoing */
HAL_I2S_STATE_BUSY_TX = 0x03UL, /*!< Data Transmission process is ongoing */
HAL_I2S_STATE_BUSY_RX = 0x04UL, /*!< Data Reception process is ongoing */
HAL_I2S_STATE_BUSY_TX_RX = 0x05UL, /*!< Data Transmission and Reception process is ongoing */
HAL_I2S_STATE_TIMEOUT = 0x06UL, /*!< I2S timeout state */
HAL_I2S_STATE_ERROR = 0x07UL /*!< I2S error state */
} HAL_I2S_StateTypeDef;
/**
* @brief I2S handle Structure definition
*/
typedef struct __I2S_HandleTypeDef
{
SPI_TypeDef *Instance; /*!< I2S registers base address */
I2S_InitTypeDef Init; /*!< I2S communication parameters */
const uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
__IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
__IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
__IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
__IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
(This field is initialized at the
same value as transfer size at the
beginning of the transfer and
decremented when a sample is received
NbSamplesReceived = RxBufferSize-RxBufferCount) */
void (*RxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Rx ISR */
void (*TxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Tx ISR */
DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
__IO HAL_LockTypeDef Lock; /*!< I2S locking object */
__IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
__IO uint32_t ErrorCode; /*!< I2S Error code
This parameter can be a value of @ref I2S_Error */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Completed callback */
void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Completed callback */
void (* TxRxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S TxRx Completed callback */
void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Half Completed callback */
void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Half Completed callback */
void (* TxRxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S TxRx Half Completed callback */
void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Error callback */
void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp Init callback */
void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp DeInit callback */
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
} I2S_HandleTypeDef;
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
/**
* @brief HAL I2S Callback ID enumeration definition
*/
typedef enum
{
HAL_I2S_TX_COMPLETE_CB_ID = 0x00UL, /*!< I2S Tx Completed callback ID */
HAL_I2S_RX_COMPLETE_CB_ID = 0x01UL, /*!< I2S Rx Completed callback ID */
HAL_I2S_TX_RX_COMPLETE_CB_ID = 0x02UL, /*!< I2S TxRx Completed callback ID */
HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03UL, /*!< I2S Tx Half Completed callback ID */
HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04UL, /*!< I2S Rx Half Completed callback ID */
HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID = 0x05UL, /*!< I2S TxRx Half Completed callback ID */
HAL_I2S_ERROR_CB_ID = 0x06UL, /*!< I2S Error callback ID */
HAL_I2S_MSPINIT_CB_ID = 0x07UL, /*!< I2S Msp Init callback ID */
HAL_I2S_MSPDEINIT_CB_ID = 0x08UL /*!< I2S Msp DeInit callback ID */
} HAL_I2S_CallbackIDTypeDef;
/**
* @brief HAL I2S Callback pointer definition
*/
typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2S_Exported_Constants I2S Exported Constants
* @{
*/
/** @defgroup I2S_Error I2S Error
* @{
*/
#define HAL_I2S_ERROR_NONE (0x00000000UL) /*!< No error */
#define HAL_I2S_ERROR_TIMEOUT (0x00000001UL) /*!< Timeout error */
#define HAL_I2S_ERROR_OVR (0x00000002UL) /*!< OVR error */
#define HAL_I2S_ERROR_UDR (0x00000004UL) /*!< UDR error */
#define HAL_I2S_ERROR_DMA (0x00000008UL) /*!< DMA transfer error */
#define HAL_I2S_ERROR_PRESCALER (0x00000010UL) /*!< Prescaler Calculation error */
#define HAL_I2S_ERROR_FRE (0x00000020UL) /*!< FRE error */
#define HAL_I2S_ERROR_NO_OGT (0x00000040UL) /*!< No On Going Transfer error */
#define HAL_I2S_ERROR_NOT_SUPPORTED (0x00000080UL) /*!< Requested operation not supported */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000100UL) /*!< Invalid Callback error */
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup I2S_Mode I2S Mode
* @{
*/
#define I2S_MODE_SLAVE_TX (0x00000000UL)
#define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
#define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
#define I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)
#define I2S_MODE_SLAVE_FULLDUPLEX (SPI_I2SCFGR_I2SCFG_2)
#define I2S_MODE_MASTER_FULLDUPLEX (SPI_I2SCFGR_I2SCFG_2 | SPI_I2SCFGR_I2SCFG_0)
/**
* @}
*/
/** @defgroup I2S_Standard I2S Standard
* @{
*/
#define I2S_STANDARD_PHILIPS (0x00000000UL)
#define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
#define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
#define I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)
#define I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)
/**
* @}
*/
/** @defgroup I2S_Data_Format I2S Data Format
* @{
*/
#define I2S_DATAFORMAT_16B (0x00000000UL)
#define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
#define I2S_DATAFORMAT_24B (SPI_I2SCFGR_DATLEN_0)
#define I2S_DATAFORMAT_32B (SPI_I2SCFGR_DATLEN_1)
/**
* @}
*/
/** @defgroup I2S_MCLK_Output I2S MCLK Output
* @{
*/
#define I2S_MCLKOUTPUT_ENABLE (SPI_I2SCFGR_MCKOE)
#define I2S_MCLKOUTPUT_DISABLE (0x00000000UL)
/**
* @}
*/
/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
* @{
*/
#define I2S_AUDIOFREQ_192K (192000UL)
#define I2S_AUDIOFREQ_96K (96000UL)
#define I2S_AUDIOFREQ_48K (48000UL)
#define I2S_AUDIOFREQ_44K (44100UL)
#define I2S_AUDIOFREQ_32K (32000UL)
#define I2S_AUDIOFREQ_22K (22050UL)
#define I2S_AUDIOFREQ_16K (16000UL)
#define I2S_AUDIOFREQ_11K (11025UL)
#define I2S_AUDIOFREQ_8K (8000UL)
#define I2S_AUDIOFREQ_DEFAULT (2UL)
/**
* @}
*/
/** @defgroup I2S_Clock_Polarity I2S FullDuplex Mode
* @{
*/
#define I2S_CPOL_LOW (0x00000000UL)
#define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)
/**
* @}
*/
/** @defgroup I2S_MSB_LSB_Transmission I2S MSB LSB Transmission
* @{
*/
#define I2S_FIRSTBIT_MSB (0x00000000UL)
#define I2S_FIRSTBIT_LSB SPI_CFG2_LSBFRST
/**
* @}
*/
/** @defgroup I2S_WSInversion I2S Word Select Inversion
* @{
*/
#define I2S_WS_INVERSION_DISABLE (0x00000000UL)
#define I2S_WS_INVERSION_ENABLE SPI_I2SCFGR_WSINV
/**
* @}
*/
/** @defgroup I2S_Data_24Bit_Alignment Data Padding 24Bit
* @{
*/
#define I2S_DATA_24BIT_ALIGNMENT_RIGHT (0x00000000UL)
#define I2S_DATA_24BIT_ALIGNMENT_LEFT SPI_I2SCFGR_DATFMT
/**
* @}
*/
/** @defgroup I2S_Master_Keep_IO_State Keep IO State
* @{
*/
#define I2S_MASTER_KEEP_IO_STATE_DISABLE (0x00000000U)
#define I2S_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR
/**
* @}
*/
/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
* @{
*/
#define I2S_IT_RXP SPI_IER_RXPIE
#define I2S_IT_TXP SPI_IER_TXPIE
#define I2S_IT_DXP SPI_IER_DXPIE
#define I2S_IT_UDR SPI_IER_UDRIE
#define I2S_IT_OVR SPI_IER_OVRIE
#define I2S_IT_FRE SPI_IER_TIFREIE
#define I2S_IT_ERR (SPI_IER_UDRIE | SPI_IER_OVRIE | SPI_IER_TIFREIE)
/**
* @}
*/
/** @defgroup I2S_Flags_Definition I2S Flags Definition
* @{
*/
#define I2S_FLAG_RXP SPI_SR_RXP /* I2S status flag : Rx-Packet available flag */
#define I2S_FLAG_TXP SPI_SR_TXP /* I2S status flag : Tx-Packet space available flag */
#define I2S_FLAG_DXP SPI_SR_DXP /* I2S status flag : Dx-Packet space available flag */
#define I2S_FLAG_UDR SPI_SR_UDR /* I2S Error flag : Underrun flag */
#define I2S_FLAG_OVR SPI_SR_OVR /* I2S Error flag : Overrun flag */
#define I2S_FLAG_FRE SPI_SR_TIFRE /* I2S Error flag : TI mode frame format error flag */
#define I2S_FLAG_MASK (SPI_SR_RXP | SPI_SR_TXP | SPI_SR_DXP |SPI_SR_UDR | SPI_SR_OVR | SPI_SR_TIFRE)
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup I2S_Exported_macros I2S Exported Macros
* @{
*/
/** @brief Reset I2S handle state
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_I2S_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/** @brief Enable the specified SPI peripheral (in I2S mode).
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE))
/** @brief Disable the specified SPI peripheral (in I2S mode).
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE))
/** @brief Enable the specified I2S interrupts.
* @param __HANDLE__ specifies the I2S Handle.
* This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg I2S_IT_RXP : Rx-Packet available interrupt
* @arg I2S_IT_TXP : Tx-Packet space available interrupt
* @arg I2S_IT_UDR : Underrun interrupt
* @arg I2S_IT_OVR : Overrun interrupt
* @arg I2S_IT_FRE : TI mode frame format error interrupt
* @arg I2S_IT_ERR : Error interrupt enable
* @retval None
*/
#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
/** @brief Disable the specified I2S interrupts.
* @param __HANDLE__ specifies the I2S Handle.
* This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg I2S_IT_RXP : Rx-Packet available interrupt
* @arg I2S_IT_TXP : Tx-Packet space available interrupt
* @arg I2S_IT_UDR : Underrun interrupt
* @arg I2S_IT_OVR : Overrun interrupt
* @arg I2S_IT_FRE : TI mode frame format error interrupt
* @arg I2S_IT_ERR : Error interrupt enable
* @retval None
*/
#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
/** @brief Check if the specified I2S interrupt source is enabled or disabled.
* @param __HANDLE__ specifies the I2S Handle.
* This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.
* @param __INTERRUPT__ specifies the I2S interrupt source to check.
* This parameter can be one of the following values:
* @arg I2S_IT_RXP : Rx-Packet available interrupt
* @arg I2S_IT_TXP : Tx-Packet space available interrupt
* @arg I2S_IT_DXP : Tx-Packet space available interrupt
* @arg I2S_IT_UDR : Underrun interrupt
* @arg I2S_IT_OVR : Overrun interrupt
* @arg I2S_IT_FRE : TI mode frame format error interrupt
* @arg I2S_IT_ERR : Error interrupt enable
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified I2S flag is set or not.
* @param __HANDLE__ specifies the I2S Handle.
* This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg I2S_FLAG_RXP : Rx-Packet available flag
* @arg I2S_FLAG_TXP : Tx-Packet space available flag
* @arg I2S_FLAG_UDR : Underrun flag
* @arg I2S_FLAG_OVR : Overrun flag
* @arg I2S_FLAG_FRE : TI mode frame format error flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clear the I2S OVR pending flag.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
/** @brief Clear the I2S UDR pending flag.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
/** @brief Clear the I2S FRE pending flag.
* @param __HANDLE__: specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_CLEAR_TIFREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2S_Exported_Functions
* @{
*/
/** @addtogroup I2S_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s);
void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
pI2S_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup I2S_Exported_Functions_Group2
* @{
*/
/* I/O operation functions ***************************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData,
uint16_t Size, uint32_t Timeout);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData,
uint16_t Size);
void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
/* IO Swap feature */
HAL_StatusTypeDef HAL_I2S_EnableIOSwap(I2S_HandleTypeDef *hi2s);
HAL_StatusTypeDef HAL_I2S_DisableIOSwap(I2S_HandleTypeDef *hi2s);
uint32_t HAL_I2S_IsEnabledIOSwap(const I2S_HandleTypeDef *hi2s);
/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
/**
* @}
*/
/** @addtogroup I2S_Exported_Functions_Group3
* @{
*/
/* Peripheral Control and State functions ************************************/
HAL_I2S_StateTypeDef HAL_I2S_GetState(const I2S_HandleTypeDef *hi2s);
uint32_t HAL_I2S_GetError(const I2S_HandleTypeDef *hi2s);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2S_Private_Constants I2S Private Constants
* @{
*/
/**
* @}
*/
/* Private Functions ---------------------------------------------------------*/
/** @defgroup I2S_Private_Functions I2S Private Functions
* @{
*/
/* Private functions are defined in stm32h7xx_hal_i2S.c file */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2S_Private_Macros I2S Private Macros
* @{
*/
/** @brief Check whether the specified SPI flag is set or not.
* @param __SR__ copy of I2S SR register.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg I2S_FLAG_RXP : Rx-Packet available flag
* @arg I2S_FLAG_TXP : Tx-Packet space available flag
* @arg I2S_FLAG_UDR : Underrun flag
* @arg I2S_FLAG_OVR : Overrun flag
* @arg I2S_FLAG_FRE : TI mode frame format error flag
* @retval SET or RESET.
*/
#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\
& ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK))\
? SET : RESET)
/** @brief Check whether the specified SPI Interrupt is set or not.
* @param __IER__ copy of I2S IER register.
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
* This parameter can be one of the following values:
* @arg I2S_IT_RXP : Rx-Packet available interrupt
* @arg I2S_IT_TXP : Tx-Packet space available interrupt
* @arg I2S_IT_UDR : Underrun interrupt
* @arg I2S_IT_OVR : Overrun interrupt
* @arg I2S_IT_FRE : TI mode frame format error interrupt
* @arg I2S_IT_ERR : Error interrupt enable
* @retval SET or RESET.
*/
#define I2S_CHECK_IT_SOURCE(__IER__, __INTERRUPT__) ((((__IER__)\
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks if I2S Mode parameter is in allowed range.
* @param __MODE__ specifies the I2S Mode.
* This parameter can be a value of @ref I2S_Mode
* @retval None
*/
#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \
((__MODE__) == I2S_MODE_SLAVE_RX) || \
((__MODE__) == I2S_MODE_MASTER_TX) || \
((__MODE__) == I2S_MODE_MASTER_RX) || \
((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX) || \
((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX))
#define IS_I2S_MASTER(__MODE__) (((__MODE__) == I2S_MODE_MASTER_TX) || \
((__MODE__) == I2S_MODE_MASTER_RX) || \
((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX))
#define IS_I2S_SLAVE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \
((__MODE__) == I2S_MODE_SLAVE_RX) || \
((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX))
#define IS_I2S_FULLDUPLEX(__MODE__) (((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX) || \
((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX))
#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \
((__STANDARD__) == I2S_STANDARD_MSB) || \
((__STANDARD__) == I2S_STANDARD_LSB) || \
((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
((__STANDARD__) == I2S_STANDARD_PCM_LONG))
#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \
((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \
((__FORMAT__) == I2S_DATAFORMAT_24B) || \
((__FORMAT__) == I2S_DATAFORMAT_32B))
#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \
((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
((__CPOL__) == I2S_CPOL_HIGH))
#define IS_I2S_FIRST_BIT(__BIT__) (((__BIT__) == I2S_FIRSTBIT_MSB) || \
((__BIT__) == I2S_FIRSTBIT_LSB))
#define IS_I2S_WS_INVERSION(__WSINV__) (((__WSINV__) == I2S_WS_INVERSION_DISABLE) || \
((__WSINV__) == I2S_WS_INVERSION_ENABLE))
#define IS_I2S_DATA_24BIT_ALIGNMENT(__ALIGNMENT__) (((__ALIGNMENT__) == I2S_DATA_24BIT_ALIGNMENT_RIGHT) || \
((__ALIGNMENT__) == I2S_DATA_24BIT_ALIGNMENT_LEFT))
#define IS_I2S_MASTER_KEEP_IO_STATE(__AFCNTR__) (((__AFCNTR__) == I2S_MASTER_KEEP_IO_STATE_DISABLE) || \
((__AFCNTR__) == I2S_MASTER_KEEP_IO_STATE_ENABLE))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H7RSxx_HAL_I2S_H */
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_i2s_ex.h
+26
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@@ -0,0 +1,26 @@
/**
******************************************************************************
* @file stm32h7rsxx_hal_i2s_ex.h
* @author MCD Application Team
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/**
******************************************************************************
===== I2S FULL DUPLEX FEATURE =====
I2S Full Duplex APIs are available in stm32h7rsxx_hal_i2s.c/.h
******************************************************************************
*/
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_icache.h
+216
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/**
******************************************************************************
* @file stm32h7rsxx_hal_icache.h
* @author MCD Application Team
* @brief Header file of ICACHE HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion ------------------------------------*/
#ifndef STM32H7RSxx_HAL_ICACHE_H
#define STM32H7RSxx_HAL_ICACHE_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes -----------------------------------------------------------------*/
#include "stm32h7rsxx_hal_def.h"
#if defined(ICACHE)
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @addtogroup ICACHE
* @{
*/
/* Exported types -----------------------------------------------------------*/
/* Exported constants -------------------------------------------------------*/
/** @defgroup ICACHE_Exported_Constants ICACHE Exported Constants
* @{
*/
/** @defgroup ICACHE_WaysSelection Ways selection
* @{
*/
#define ICACHE_1WAY 0UL /*!< 1-way cache (direct mapped cache) */
#define ICACHE_4WAYS ICACHE_CR_WAYSEL /*!< 4-ways set associative cache (default) */
/**
* @}
*/
/** @defgroup ICACHE_Monitor_Type Monitor type
* @{
*/
#define ICACHE_MONITOR_HIT_MISS (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< Hit & Miss monitoring */
#define ICACHE_MONITOR_HIT ICACHE_CR_HITMEN /*!< Hit monitoring */
#define ICACHE_MONITOR_MISS ICACHE_CR_MISSMEN /*!< Miss monitoring */
/**
* @}
*/
/** @defgroup ICACHE_Interrupts Interrupts
* @{
*/
#define ICACHE_IT_BUSYEND ICACHE_IER_BSYENDIE /*!< Busy end interrupt */
#define ICACHE_IT_ERROR ICACHE_IER_ERRIE /*!< Cache error interrupt */
/**
* @}
*/
/** @defgroup ICACHE_Flags Flags
* @{
*/
#define ICACHE_FLAG_BUSY ICACHE_SR_BUSYF /*!< Busy flag */
#define ICACHE_FLAG_BUSYEND ICACHE_SR_BSYENDF /*!< Busy end flag */
#define ICACHE_FLAG_ERROR ICACHE_SR_ERRF /*!< Cache error flag */
/**
* @}
*/
/**
* @}
*/
/* Exported macros ----------------------------------------------------------*/
/** @defgroup ICACHE_Exported_Macros ICACHE Exported Macros
* @{
*/
/** @defgroup ICACHE_Flags_Interrupts_Management Flags and Interrupts Management
* @brief macros to manage the specified ICACHE flags and interrupts.
* @{
*/
/** @brief Enable ICACHE interrupts.
* @param __INTERRUPT__ specifies the ICACHE interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg @ref ICACHE_IT_BUSYEND Busy end interrupt
* @arg @ref ICACHE_IT_ERROR Cache error interrupt
*/
#define __HAL_ICACHE_ENABLE_IT(__INTERRUPT__) SET_BIT(ICACHE->IER, (__INTERRUPT__))
/** @brief Disable ICACHE interrupts.
* @param __INTERRUPT__ specifies the ICACHE interrupt sources to be disabled.
* This parameter can be any combination of the following values:
* @arg @ref ICACHE_IT_BUSYEND Busy end interrupt
* @arg @ref ICACHE_IT_ERROR Cache error interrupt
*/
#define __HAL_ICACHE_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(ICACHE->IER, (__INTERRUPT__))
/** @brief Check whether the specified ICACHE interrupt source is enabled or not.
* @param __INTERRUPT__ specifies the ICACHE interrupt source to check.
* This parameter can be any combination of the following values:
* @arg @ref ICACHE_IT_BUSYEND Busy end interrupt
* @arg @ref ICACHE_IT_ERROR Cache error interrupt
* @retval The state of __INTERRUPT__ (0 or 1).
*/
#define __HAL_ICACHE_GET_IT_SOURCE(__INTERRUPT__) \
((READ_BIT(ICACHE->IER, (__INTERRUPT__)) == (__INTERRUPT__)) ? 1U : 0U)
/** @brief Check whether the selected ICACHE flag is set or not.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref ICACHE_FLAG_BUSY Busy flag
* @arg @ref ICACHE_FLAG_BUSYEND Busy end flag
* @arg @ref ICACHE_FLAG_ERROR Cache error flag
* @retval The state of __FLAG__ (0 or 1).
*/
#define __HAL_ICACHE_GET_FLAG(__FLAG__) ((READ_BIT(ICACHE->SR, (__FLAG__)) != 0U) ? 1U : 0U)
/** @brief Clear the selected ICACHE flags.
* @param __FLAG__ specifies the ICACHE flags to clear.
* This parameter can be any combination of the following values:
* @arg @ref ICACHE_FLAG_BUSYEND Busy end flag
* @arg @ref ICACHE_FLAG_ERROR Cache error flag
*/
#define __HAL_ICACHE_CLEAR_FLAG(__FLAG__) WRITE_REG(ICACHE->FCR, (__FLAG__))
/**
* @}
*/
/**
* @}
*/
/* Exported functions -------------------------------------------------------*/
/** @addtogroup ICACHE_Exported_Functions
* @{
*/
/** @addtogroup ICACHE_Exported_Functions_Group1
* @brief Initialization and control functions
* @{
*/
/* Peripheral Control functions **********************************************/
HAL_StatusTypeDef HAL_ICACHE_Enable(void);
HAL_StatusTypeDef HAL_ICACHE_Disable(void);
uint32_t HAL_ICACHE_IsEnabled(void);
HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode);
HAL_StatusTypeDef HAL_ICACHE_DeInit(void);
/******* Invalidate in blocking mode (Polling) */
HAL_StatusTypeDef HAL_ICACHE_Invalidate(void);
/******* Invalidate in non-blocking mode (Interrupt) */
HAL_StatusTypeDef HAL_ICACHE_Invalidate_IT(void);
/******* Wait for Invalidate complete in blocking mode (Polling) */
HAL_StatusTypeDef HAL_ICACHE_WaitForInvalidateComplete(void);
/******* Performance instruction cache monitoring functions */
HAL_StatusTypeDef HAL_ICACHE_Monitor_Start(uint32_t MonitorType);
HAL_StatusTypeDef HAL_ICACHE_Monitor_Stop(uint32_t MonitorType);
HAL_StatusTypeDef HAL_ICACHE_Monitor_Reset(uint32_t MonitorType);
uint32_t HAL_ICACHE_Monitor_GetHitValue(void);
uint32_t HAL_ICACHE_Monitor_GetMissValue(void);
/**
* @}
*/
/** @addtogroup ICACHE_Exported_Functions_Group2
* @brief IRQ and callback functions
* @{
*/
/******* IRQHandler and Callbacks used in non-blocking mode (Interrupt) */
void HAL_ICACHE_IRQHandler(void);
void HAL_ICACHE_InvalidateCompleteCallback(void);
void HAL_ICACHE_ErrorCallback(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* ICACHE */
#ifdef __cplusplus
}
#endif
#endif /* STM32H7RSxx_HAL_ICACHE_H */
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_jpeg.h
+654
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/**
******************************************************************************
* @file stm32h7rsxx_hal_jpeg.h
* @author MCD Application Team
* @brief Header file of JPEG HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7RSxx_HAL_JPEG_H
#define STM32H7RSxx_HAL_JPEG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal_def.h"
#if defined (JPEG)
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @addtogroup JPEG
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup JPEG_Exported_Types JPEG Exported Types
* @{
*/
/** @defgroup JPEG_Configuration_Structure_definition JPEG Configuration for encoding Structure definition
* @brief JPEG encoding configuration Structure definition
* @{
*/
typedef struct
{
uint32_t ColorSpace; /*!< Image Color space : gray-scale, YCBCR, RGB or CMYK
This parameter can be a value of @ref JPEG_ColorSpace */
uint32_t ChromaSubsampling; /*!< Chroma Subsampling in case of YCBCR or CMYK color space, 0-> 4:4:4 , 1-> 4:2:2, 2 -> 4:1:1, 3 -> 4:2:0
This parameter can be a value of @ref JPEG_ChromaSubsampling */
uint32_t ImageHeight; /*!< Image height : number of lines */
uint32_t ImageWidth; /*!< Image width : number of pixels per line */
uint32_t ImageQuality; /*!< Quality of the JPEG encoding : from 1 to 100 */
} JPEG_ConfTypeDef;
/**
* @}
*/
/** @defgroup HAL_JPEG_state_structure_definition HAL JPEG state structure definition
* @brief HAL JPEG State structure definition
* @{
*/
typedef enum
{
HAL_JPEG_STATE_RESET = 0x00U, /*!< JPEG not yet initialized or disabled */
HAL_JPEG_STATE_READY = 0x01U, /*!< JPEG initialized and ready for use */
HAL_JPEG_STATE_BUSY = 0x02U, /*!< JPEG internal processing is ongoing */
HAL_JPEG_STATE_BUSY_ENCODING = 0x03U, /*!< JPEG encoding processing is ongoing */
HAL_JPEG_STATE_BUSY_DECODING = 0x04U, /*!< JPEG decoding processing is ongoing */
HAL_JPEG_STATE_TIMEOUT = 0x05U, /*!< JPEG timeout state */
HAL_JPEG_STATE_ERROR = 0x06U /*!< JPEG error state */
} HAL_JPEG_STATETypeDef;
/**
* @}
*/
/** @defgroup JPEG_handle_Structure_definition JPEG handle Structure definition
* @brief JPEG handle Structure definition
* @{
*/
#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
typedef struct __JPEG_HandleTypeDef
#else
typedef struct
#endif /* (USE_HAL_JPEG_REGISTER_CALLBACKS) */
{
JPEG_TypeDef *Instance; /*!< JPEG peripheral register base address */
JPEG_ConfTypeDef Conf; /*!< Current JPEG encoding/decoding parameters */
uint8_t *pJpegInBuffPtr; /*!< Pointer to JPEG processing (encoding, decoding,...) input buffer */
uint8_t *pJpegOutBuffPtr; /*!< Pointer to JPEG processing (encoding, decoding,...) output buffer */
__IO uint32_t JpegInCount; /*!< Internal Counter of input data */
__IO uint32_t JpegOutCount; /*!< Internal Counter of output data */
uint32_t InDataLength; /*!< Input Buffer Length in Bytes */
uint32_t OutDataLength; /*!< Output Buffer Length in Bytes */
DMA_HandleTypeDef *hdmain; /*!< JPEG In DMA handle parameters */
DMA_HandleTypeDef *hdmaout; /*!< JPEG Out DMA handle parameters */
uint8_t CustomQuanTable; /*!< If set to 1 specify that user customized quantization tables are used */
uint8_t *QuantTable0; /*!< Basic Quantization Table for component 0 */
uint8_t *QuantTable1; /*!< Basic Quantization Table for component 1 */
uint8_t *QuantTable2; /*!< Basic Quantization Table for component 2 */
uint8_t *QuantTable3; /*!< Basic Quantization Table for component 3 */
HAL_LockTypeDef Lock; /*!< JPEG locking object */
__IO HAL_JPEG_STATETypeDef State; /*!< JPEG peripheral state */
__IO uint32_t ErrorCode; /*!< JPEG Error code */
__IO uint32_t Context; /*!< JPEG Internal context */
#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
void (*InfoReadyCallback)(struct __JPEG_HandleTypeDef *hjpeg,
JPEG_ConfTypeDef *pInfo); /*!< JPEG Info ready callback */
void (*EncodeCpltCallback)(struct __JPEG_HandleTypeDef
*hjpeg); /*!< JPEG Encode complete callback */
void (*DecodeCpltCallback)(struct __JPEG_HandleTypeDef
*hjpeg); /*!< JPEG Decode complete callback */
void (*ErrorCallback)(struct __JPEG_HandleTypeDef
*hjpeg); /*!< JPEG Error callback */
void (*GetDataCallback)(struct __JPEG_HandleTypeDef *hjpeg,
uint32_t NbDecodedData); /*!< JPEG Get Data callback */
void (*DataReadyCallback)(struct __JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut,
uint32_t OutDataLength); /*!< JPEG Data ready callback */
void (* MspInitCallback)(struct __JPEG_HandleTypeDef *hjpeg); /*!< JPEG Msp Init callback */
void (* MspDeInitCallback)(struct __JPEG_HandleTypeDef
*hjpeg); /*!< JPEG Msp DeInit callback */
#endif /* (USE_HAL_JPEG_REGISTER_CALLBACKS) */
} JPEG_HandleTypeDef;
/**
* @}
*/
#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
/** @defgroup HAL_JPEG_Callback_ID_enumeration_definition HAL JPEG Callback ID enumeration definition
* @brief HAL JPEG Callback ID enumeration definition
* @{
*/
typedef enum
{
HAL_JPEG_ENCODE_CPLT_CB_ID = 0x01U, /*!< JPEG Encode Complete callback ID */
HAL_JPEG_DECODE_CPLT_CB_ID = 0x02U, /*!< JPEG Decode Complete callback ID */
HAL_JPEG_ERROR_CB_ID = 0x03U, /*!< JPEG Error callback ID */
HAL_JPEG_MSPINIT_CB_ID = 0x04U, /*!< JPEG MspInit callback ID */
HAL_JPEG_MSPDEINIT_CB_ID = 0x05U /*!< JPEG MspDeInit callback ID */
} HAL_JPEG_CallbackIDTypeDef;
/**
* @}
*/
/** @defgroup HAL_JPEG_Callback_pointer_definition HAL JPEG Callback pointer definition
* @brief HAL JPEG Callback pointer definition
* @{
*/
typedef void (*pJPEG_CallbackTypeDef)(JPEG_HandleTypeDef *hjpeg); /*!< pointer to a common JPEG callback function */
typedef void (*pJPEG_InfoReadyCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg,
JPEG_ConfTypeDef *pInfo); /*!< pointer to an Info ready JPEG callback function */
typedef void (*pJPEG_GetDataCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg,
uint32_t NbDecodedData); /*!< pointer to a Get data JPEG callback function */
typedef void (*pJPEG_DataReadyCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut,
uint32_t OutDataLength); /*!< pointer to a Data ready JPEG callback function */
/**
* @}
*/
#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup JPEG_Exported_Constants JPEG Exported Constants
* @{
*/
/** @defgroup JPEG_Error_Code_definition JPEG Error Code definition
* @brief JPEG Error Code definition
* @{
*/
#define HAL_JPEG_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_JPEG_ERROR_HUFF_TABLE ((uint32_t)0x00000001U) /*!< HUffman Table programming error */
#define HAL_JPEG_ERROR_QUANT_TABLE ((uint32_t)0x00000002U) /*!< Quantization Table programming error */
#define HAL_JPEG_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */
#define HAL_JPEG_ERROR_TIMEOUT ((uint32_t)0x00000008U) /*!< Timeout error */
#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
#define HAL_JPEG_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U) /*!< Invalid Callback error */
#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup JPEG_Quantization_Table_Size JPEG Quantization Table Size
* @brief JPEG Quantization Table Size
* @{
*/
#define JPEG_QUANT_TABLE_SIZE ((uint32_t)64U) /*!< JPEG Quantization Table Size in bytes */
/**
* @}
*/
/** @defgroup JPEG_ColorSpace JPEG ColorSpace
* @brief JPEG Color Space
* @{
*/
#define JPEG_GRAYSCALE_COLORSPACE ((uint32_t)0x00000000U)
#define JPEG_YCBCR_COLORSPACE JPEG_CONFR1_COLORSPACE_0
#define JPEG_CMYK_COLORSPACE JPEG_CONFR1_COLORSPACE
/**
* @}
*/
/** @defgroup JPEG_ChromaSubsampling JPEG Chrominance Sampling
* @brief JPEG Chrominance Sampling
* @{
*/
#define JPEG_444_SUBSAMPLING ((uint32_t)0x00000000U) /*!< Chroma Subsampling 4:4:4 */
#define JPEG_420_SUBSAMPLING ((uint32_t)0x00000001U) /*!< Chroma Subsampling 4:2:0 */
#define JPEG_422_SUBSAMPLING ((uint32_t)0x00000002U) /*!< Chroma Subsampling 4:2:2 */
/**
* @}
*/
/** @defgroup JPEG_ImageQuality JPEG Image Quality
* @brief JPEG Min and Max Image Quality
* @{
*/
#define JPEG_IMAGE_QUALITY_MIN ((uint32_t)1U) /*!< Minimum JPEG quality */
#define JPEG_IMAGE_QUALITY_MAX ((uint32_t)100U) /*!< Maximum JPEG quality */
/**
* @}
*/
/** @defgroup JPEG_Interrupt_configuration_definition JPEG Interrupt configuration definition
* @brief JPEG Interrupt definition
* @{
*/
#define JPEG_IT_IFT ((uint32_t)JPEG_CR_IFTIE) /*!< Input FIFO Threshold Interrupt */
#define JPEG_IT_IFNF ((uint32_t)JPEG_CR_IFNFIE) /*!< Input FIFO Not Full Interrupt */
#define JPEG_IT_OFT ((uint32_t)JPEG_CR_OFTIE) /*!< Output FIFO Threshold Interrupt */
#define JPEG_IT_OFNE ((uint32_t)JPEG_CR_OFTIE) /*!< Output FIFO Not Empty Interrupt */
#define JPEG_IT_EOC ((uint32_t)JPEG_CR_EOCIE) /*!< End of Conversion Interrupt */
#define JPEG_IT_HPD ((uint32_t)JPEG_CR_HPDIE) /*!< Header Parsing Done Interrupt */
/**
* @}
*/
/** @defgroup JPEG_Flag_definition JPEG Flag definition
* @brief JPEG Flags definition
* @{
*/
#define JPEG_FLAG_IFTF ((uint32_t)JPEG_SR_IFTF) /*!< Input FIFO is not full and is below its threshold flag */
#define JPEG_FLAG_IFNFF ((uint32_t)JPEG_SR_IFNFF) /*!< Input FIFO Not Full Flag, a data can be written */
#define JPEG_FLAG_OFTF ((uint32_t)JPEG_SR_OFTF) /*!< Output FIFO is not empty and has reach its threshold */
#define JPEG_FLAG_OFNEF ((uint32_t)JPEG_SR_OFNEF) /*!< Output FIFO is not empty, a data is available */
#define JPEG_FLAG_EOCF ((uint32_t)JPEG_SR_EOCF) /*!< JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
#define JPEG_FLAG_HPDF ((uint32_t)JPEG_SR_HPDF) /*!< JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
#define JPEG_FLAG_COF ((uint32_t)JPEG_SR_COF) /*!< JPEG Codec operation on going flag*/
#define JPEG_FLAG_ALL ((uint32_t)0x000000FEU) /*!< JPEG Codec All previous flag*/
/**
* @}
*/
/** @defgroup JPEG_PROCESS_PAUSE_RESUME_definition JPEG Process Pause Resume definition
* @brief JPEG process pause, resume definition
* @{
*/
#define JPEG_PAUSE_RESUME_INPUT ((uint32_t)0x00000001U) /*!< Pause/Resume Input FIFO Xfer*/
#define JPEG_PAUSE_RESUME_OUTPUT ((uint32_t)0x00000002U) /*!< Pause/Resume Output FIFO Xfer*/
#define JPEG_PAUSE_RESUME_INPUT_OUTPUT ((uint32_t)0x00000003U) /*!< Pause/Resume Input and Output FIFO Xfer*/
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup JPEG_Exported_Macros JPEG Exported Macros
* @{
*/
/** @brief Reset JPEG handle state
* @param __HANDLE__ specifies the JPEG handle.
* @retval None
*/
#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
#define __HAL_JPEG_RESET_HANDLE_STATE(__HANDLE__) do{\
(__HANDLE__)->State = HAL_JPEG_STATE_RESET;\
(__HANDLE__)->MspInitCallback = NULL;\
(__HANDLE__)->MspDeInitCallback = NULL;\
}while(0)
#else
#define __HAL_JPEG_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_JPEG_STATE_RESET)
#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
/**
* @brief Enable the JPEG peripheral.
* @param __HANDLE__ specifies the JPEG handle.
* @retval None
*/
#define __HAL_JPEG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= JPEG_CR_JCEN)
/**
* @brief Disable the JPEG peripheral.
* @param __HANDLE__ specifies the JPEG handle.
* @retval None
*/
#define __HAL_JPEG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~JPEG_CR_JCEN)
/**
* @brief Check the specified JPEG status flag.
* @param __HANDLE__ specifies the JPEG handle.
* @param __FLAG__ specifies the flag to check
* This parameter can be one of the following values:
* @arg JPEG_FLAG_IFTF : The input FIFO is not full and is below its threshold flag
* @arg JPEG_FLAG_IFNFF : The input FIFO Not Full Flag, a data can be written
* @arg JPEG_FLAG_OFTF : The output FIFO is not empty and has reach its threshold
* @arg JPEG_FLAG_OFNEF : The output FIFO is not empty, a data is available
* @arg JPEG_FLAG_EOCF : JPEG Codec core has finished the encoding or the decoding process
* and than last data has been sent to the output FIFO
* @arg JPEG_FLAG_HPDF : JPEG Codec has finished the parsing of the headers
* and the internal registers have been updated
* @arg JPEG_FLAG_COF : JPEG Codec operation on going flag
*
* @retval __HAL_JPEG_GET_FLAG : returns The new state of __FLAG__ (TRUE or FALSE)
*/
#define __HAL_JPEG_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)))
/**
* @brief Clear the specified JPEG status flag.
* @param __HANDLE__ specifies the JPEG handle.
* @param __FLAG__ specifies the flag to clear
* This parameter can be one of the following values:
* @arg JPEG_FLAG_EOCF : JPEG Codec core has finished the encoding or the decoding process
* and than last data has been sent to the output FIFO
* @arg JPEG_FLAG_HPDF : JPEG Codec has finished the parsing of the headers
* @retval None
*/
#define __HAL_JPEG_CLEAR_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->CFR |= ((__FLAG__) &\
(JPEG_FLAG_EOCF | JPEG_FLAG_HPDF))))
/**
* @brief Enable Interrupt.
* @param __HANDLE__ specifies the JPEG handle.
* @param __INTERRUPT__ specifies the interrupt to enable
* This parameter can be one of the following values:
* @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt
* @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt
* @arg JPEG_IT_OFT : Output FIFO Threshold Interrupt
* @arg JPEG_IT_OFNE : Output FIFO Not empty Interrupt
* @arg JPEG_IT_EOC : End of Conversion Interrupt
* @arg JPEG_IT_HPD : Header Parsing Done Interrupt
*
* @retval No return
*/
#define __HAL_JPEG_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__) )
/**
* @brief Disable Interrupt.
* @param __HANDLE__ specifies the JPEG handle.
* @param __INTERRUPT__ specifies the interrupt to disable
* This parameter can be one of the following values:
* @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt
* @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt
* @arg JPEG_IT_OFT : Output FIFO Threshold Interrupt
* @arg JPEG_IT_OFNE : Output FIFO Not empty Interrupt
* @arg JPEG_IT_EOC : End of Conversion Interrupt
* @arg JPEG_IT_HPD : Header Parsing Done Interrupt
*
* @note To disable an IT we must use MODIFY_REG macro to avoid writing "1" to the FIFO flush bits
* located in the same IT enable register (CR register).
* @retval No return
*/
#define __HAL_JPEG_DISABLE_IT(__HANDLE__,__INTERRUPT__) MODIFY_REG((__HANDLE__)->Instance->CR, (__INTERRUPT__), 0UL)
/**
* @brief Get Interrupt state.
* @param __HANDLE__ specifies the JPEG handle.
* @param __INTERRUPT__ specifies the interrupt to check
* This parameter can be one of the following values:
* @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt
* @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt
* @arg JPEG_IT_OFT : Output FIFO Threshold Interrupt
* @arg JPEG_IT_OFNE : Output FIFO Not empty Interrupt
* @arg JPEG_IT_EOC : End of Conversion Interrupt
* @arg JPEG_IT_HPD : Header Parsing Done Interrupt
*
* @retval returns The new state of __INTERRUPT__ (Enabled or disabled)
*/
#define __HAL_JPEG_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup JPEG_Exported_Functions
* @{
*/
/** @addtogroup JPEG_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_JPEG_Init(JPEG_HandleTypeDef *hjpeg);
HAL_StatusTypeDef HAL_JPEG_DeInit(JPEG_HandleTypeDef *hjpeg);
void HAL_JPEG_MspInit(JPEG_HandleTypeDef *hjpeg);
void HAL_JPEG_MspDeInit(JPEG_HandleTypeDef *hjpeg);
#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_JPEG_RegisterCallback(JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID,
pJPEG_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_JPEG_UnRegisterCallback(JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_JPEG_RegisterInfoReadyCallback(JPEG_HandleTypeDef *hjpeg,
pJPEG_InfoReadyCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_JPEG_UnRegisterInfoReadyCallback(JPEG_HandleTypeDef *hjpeg);
HAL_StatusTypeDef HAL_JPEG_RegisterGetDataCallback(JPEG_HandleTypeDef *hjpeg, pJPEG_GetDataCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_JPEG_UnRegisterGetDataCallback(JPEG_HandleTypeDef *hjpeg);
HAL_StatusTypeDef HAL_JPEG_RegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg,
pJPEG_DataReadyCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_JPEG_UnRegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg);
#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup JPEG_Exported_Functions_Group2
* @{
*/
/* Encoding/Decoding Configuration functions ********************************/
HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, const JPEG_ConfTypeDef *pConf);
HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo);
HAL_StatusTypeDef HAL_JPEG_EnableHeaderParsing(JPEG_HandleTypeDef *hjpeg);
HAL_StatusTypeDef HAL_JPEG_DisableHeaderParsing(JPEG_HandleTypeDef *hjpeg);
HAL_StatusTypeDef HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1,
uint8_t *QTable2, uint8_t *QTable3);
/**
* @}
*/
/** @addtogroup JPEG_Exported_Functions_Group3
* @{
*/
/* JPEG processing functions **************************************/
HAL_StatusTypeDef HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength,
uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout);
HAL_StatusTypeDef HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength,
uint8_t *pDataOutMCU, uint32_t OutDataLength, uint32_t Timeout);
HAL_StatusTypeDef HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength,
uint8_t *pDataOut, uint32_t OutDataLength);
HAL_StatusTypeDef HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength,
uint8_t *pDataOutMCU, uint32_t OutDataLength);
HAL_StatusTypeDef HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength,
uint8_t *pDataOut, uint32_t OutDataLength);
HAL_StatusTypeDef HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength,
uint8_t *pDataOutMCU, uint32_t OutDataLength);
HAL_StatusTypeDef HAL_JPEG_Pause(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection);
HAL_StatusTypeDef HAL_JPEG_Resume(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection);
void HAL_JPEG_ConfigInputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength);
void HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength);
HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg);
/**
* @}
*/
/** @addtogroup JPEG_Exported_Functions_Group4
* @{
*/
/* JPEG Decode/Encode callback functions ********************************************************/
void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo);
void HAL_JPEG_EncodeCpltCallback(JPEG_HandleTypeDef *hjpeg);
void HAL_JPEG_DecodeCpltCallback(JPEG_HandleTypeDef *hjpeg);
void HAL_JPEG_ErrorCallback(JPEG_HandleTypeDef *hjpeg);
void HAL_JPEG_GetDataCallback(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData);
void HAL_JPEG_DataReadyCallback(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength);
/**
* @}
*/
/** @addtogroup JPEG_Exported_Functions_Group5
* @{
*/
/* JPEG IRQ handler management ******************************************************/
void HAL_JPEG_IRQHandler(JPEG_HandleTypeDef *hjpeg);
/**
* @}
*/
/** @addtogroup JPEG_Exported_Functions_Group6
* @{
*/
/* Peripheral State and Error functions ************************************************/
HAL_JPEG_STATETypeDef HAL_JPEG_GetState(const JPEG_HandleTypeDef *hjpeg);
uint32_t HAL_JPEG_GetError(const JPEG_HandleTypeDef *hjpeg);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/** @defgroup JPEG_Private_Types JPEG Private Types
* @{
*/
/**
* @}
*/
/* Private defines -----------------------------------------------------------*/
/** @defgroup JPEG_Private_Defines JPEG Private Defines
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup JPEG_Private_Variables JPEG Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup JPEG_Private_Constants JPEG Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup JPEG_Private_Macros JPEG Private Macros
* @{
*/
#define IS_JPEG_CHROMASUBSAMPLING(SUBSAMPLING) (((SUBSAMPLING) == JPEG_444_SUBSAMPLING) || \
((SUBSAMPLING) == JPEG_420_SUBSAMPLING) || \
((SUBSAMPLING) == JPEG_422_SUBSAMPLING))
#define IS_JPEG_IMAGE_QUALITY(NUMBER) (((NUMBER) >= JPEG_IMAGE_QUALITY_MIN) && ((NUMBER) <= JPEG_IMAGE_QUALITY_MAX))
#define IS_JPEG_COLORSPACE(COLORSPACE) (((COLORSPACE) == JPEG_GRAYSCALE_COLORSPACE) || \
((COLORSPACE) == JPEG_YCBCR_COLORSPACE) || \
((COLORSPACE) == JPEG_CMYK_COLORSPACE))
#define IS_JPEG_PAUSE_RESUME_STATE(VALUE) (((VALUE) == JPEG_PAUSE_RESUME_INPUT) || \
((VALUE) == JPEG_PAUSE_RESUME_OUTPUT)|| \
((VALUE) == JPEG_PAUSE_RESUME_INPUT_OUTPUT))
/**
* @}
*/
/* Private functions prototypes ----------------------------------------------*/
/** @defgroup JPEG_Private_Functions_Prototypes JPEG Private Functions Prototypes
* @{
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup JPEG_Private_Functions JPEG Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* JPEG */
#ifdef __cplusplus
}
#endif
#endif /* STM32H7RSxx_HAL_JPEG_H */
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_ltdc.h
+720
View File
@@ -0,0 +1,720 @@
/**
******************************************************************************
* @file stm32h7rsxx_hal_ltdc.h
* @author MCD Application Team
* @brief Header file of LTDC HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7RSxx_HAL_LTDC_H
#define STM32H7RSxx_HAL_LTDC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal_def.h"
#if defined (LTDC)
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @defgroup LTDC LTDC
* @brief LTDC HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup LTDC_Exported_Types LTDC Exported Types
* @{
*/
#define MAX_LAYER 2U
/**
* @brief LTDC color structure definition
*/
typedef struct
{
uint8_t Blue; /*!< Configures the blue value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
uint8_t Green; /*!< Configures the green value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
uint8_t Red; /*!< Configures the red value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
uint8_t Reserved; /*!< Reserved 0xFF */
} LTDC_ColorTypeDef;
/**
* @brief LTDC Init structure definition
*/
typedef struct
{
uint32_t HSPolarity; /*!< configures the horizontal synchronization polarity.
This parameter can be one value of @ref LTDC_HS_POLARITY */
uint32_t VSPolarity; /*!< configures the vertical synchronization polarity.
This parameter can be one value of @ref LTDC_VS_POLARITY */
uint32_t DEPolarity; /*!< configures the data enable polarity.
This parameter can be one of value of @ref LTDC_DE_POLARITY */
uint32_t PCPolarity; /*!< configures the pixel clock polarity.
This parameter can be one of value of @ref LTDC_PC_POLARITY */
uint32_t HorizontalSync; /*!< configures the number of Horizontal synchronization width.
This parameter must be a number between
Min_Data = 0x000 and Max_Data = 0xFFF. */
uint32_t VerticalSync; /*!< configures the number of Vertical synchronization height.
This parameter must be a number between
Min_Data = 0x000 and Max_Data = 0x7FF. */
uint32_t AccumulatedHBP; /*!< configures the accumulated horizontal back porch width.
This parameter must be a number between
Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */
uint32_t AccumulatedVBP; /*!< configures the accumulated vertical back porch height.
This parameter must be a number between
Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */
uint32_t AccumulatedActiveW; /*!< configures the accumulated active width.
This parameter must be a number between
Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */
uint32_t AccumulatedActiveH; /*!< configures the accumulated active height.
This parameter must be a number between
Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */
uint32_t TotalWidth; /*!< configures the total width.
This parameter must be a number between
Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */
uint32_t TotalHeigh; /*!< configures the total height.
This parameter must be a number between
Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */
LTDC_ColorTypeDef Backcolor; /*!< Configures the background color. */
} LTDC_InitTypeDef;
/**
* @brief LTDC Layer structure definition
*/
typedef struct
{
uint32_t WindowX0; /*!< Configures the Window Horizontal Start Position.
This parameter must be a number between
Min_Data = 0x000 and Max_Data = 0xFFF. */
uint32_t WindowX1; /*!< Configures the Window Horizontal Stop Position.
This parameter must be a number between
Min_Data = 0x000 and Max_Data = 0xFFF. */
uint32_t WindowY0; /*!< Configures the Window vertical Start Position.
This parameter must be a number between
Min_Data = 0x000 and Max_Data = 0x7FF. */
uint32_t WindowY1; /*!< Configures the Window vertical Stop Position.
This parameter must be a number between
Min_Data = 0x0000 and Max_Data = 0x7FF. */
uint32_t PixelFormat; /*!< Specifies the pixel format.
This parameter can be one of value of @ref LTDC_Pixelformat */
uint32_t Alpha; /*!< Specifies the constant alpha used for blending.
This parameter must be a number between
Min_Data = 0x00 and Max_Data = 0xFF. */
uint32_t Alpha0; /*!< Configures the default alpha value.
This parameter must be a number between
Min_Data = 0x00 and Max_Data = 0xFF. */
uint32_t BlendingFactor1; /*!< Select the blending factor 1.
This parameter can be one of value of @ref LTDC_BlendingFactor1 */
uint32_t BlendingFactor2; /*!< Select the blending factor 2.
This parameter can be one of value of @ref LTDC_BlendingFactor2 */
uint32_t FBStartAdress; /*!< Configures the color frame buffer address */
uint32_t ImageWidth; /*!< Configures the color frame buffer line length.
This parameter must be a number between
Min_Data = 0x0000 and Max_Data = 0x1FFF. */
uint32_t ImageHeight; /*!< Specifies the number of line in frame buffer.
This parameter must be a number between
Min_Data = 0x000 and Max_Data = 0x7FF. */
LTDC_ColorTypeDef Backcolor; /*!< Configures the layer background color. */
} LTDC_LayerCfgTypeDef;
/**
* @brief HAL LTDC State structures definition
*/
typedef enum
{
HAL_LTDC_STATE_RESET = 0x00U, /*!< LTDC not yet initialized or disabled */
HAL_LTDC_STATE_READY = 0x01U, /*!< LTDC initialized and ready for use */
HAL_LTDC_STATE_BUSY = 0x02U, /*!< LTDC internal process is ongoing */
HAL_LTDC_STATE_TIMEOUT = 0x03U, /*!< LTDC Timeout state */
HAL_LTDC_STATE_ERROR = 0x04U /*!< LTDC state error */
} HAL_LTDC_StateTypeDef;
/**
* @brief LTDC handle Structure definition
*/
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
typedef struct __LTDC_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
{
LTDC_TypeDef *Instance; /*!< LTDC Register base address */
LTDC_InitTypeDef Init; /*!< LTDC parameters */
LTDC_LayerCfgTypeDef LayerCfg[MAX_LAYER]; /*!< LTDC Layers parameters */
HAL_LockTypeDef Lock; /*!< LTDC Lock */
__IO HAL_LTDC_StateTypeDef State; /*!< LTDC state */
__IO uint32_t ErrorCode; /*!< LTDC Error code */
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
void (* LineEventCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Line Event Callback */
void (* ReloadEventCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Reload Event Callback */
void (* ErrorCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Error Callback */
void (* MspInitCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Msp Init callback */
void (* MspDeInitCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Msp DeInit callback */
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
} LTDC_HandleTypeDef;
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/**
* @brief HAL LTDC Callback ID enumeration definition
*/
typedef enum
{
HAL_LTDC_MSPINIT_CB_ID = 0x00U, /*!< LTDC MspInit callback ID */
HAL_LTDC_MSPDEINIT_CB_ID = 0x01U, /*!< LTDC MspDeInit callback ID */
HAL_LTDC_LINE_EVENT_CB_ID = 0x02U, /*!< LTDC Line Event Callback ID */
HAL_LTDC_RELOAD_EVENT_CB_ID = 0x03U, /*!< LTDC Reload Callback ID */
HAL_LTDC_ERROR_CB_ID = 0x04U /*!< LTDC Error Callback ID */
} HAL_LTDC_CallbackIDTypeDef;
/**
* @brief HAL LTDC Callback pointer definition
*/
typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer to an LTDC callback function */
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup LTDC_Exported_Constants LTDC Exported Constants
* @{
*/
/** @defgroup LTDC_Error_Code LTDC Error Code
* @{
*/
#define HAL_LTDC_ERROR_NONE 0x00000000U /*!< LTDC No error */
#define HAL_LTDC_ERROR_TE 0x00000001U /*!< LTDC Transfer error */
#define HAL_LTDC_ERROR_FU 0x00000002U /*!< LTDC FIFO Underrun */
#define HAL_LTDC_ERROR_TIMEOUT 0x00000020U /*!< LTDC Timeout error */
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
#define HAL_LTDC_ERROR_INVALID_CALLBACK 0x00000040U /*!< LTDC Invalid Callback error */
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup LTDC_Layer LTDC Layer
* @{
*/
#define LTDC_LAYER_1 0x00000000U /*!< LTDC Layer 1 */
#define LTDC_LAYER_2 0x00000001U /*!< LTDC Layer 2 */
/**
* @}
*/
/** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY
* @{
*/
#define LTDC_HSPOLARITY_AL 0x00000000U /*!< Horizontal Synchronization is active low. */
#define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */
/**
* @}
*/
/** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY
* @{
*/
#define LTDC_VSPOLARITY_AL 0x00000000U /*!< Vertical Synchronization is active low. */
#define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */
/**
* @}
*/
/** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY
* @{
*/
#define LTDC_DEPOLARITY_AL 0x00000000U /*!< Data Enable, is active low. */
#define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */
/**
* @}
*/
/** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY
* @{
*/
#define LTDC_PCPOLARITY_IPC 0x00000000U /*!< input pixel clock. */
#define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */
/**
* @}
*/
/** @defgroup LTDC_SYNC LTDC SYNC
* @{
*/
#define LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16U) /*!< Horizontal synchronization width. */
#define LTDC_VERTICALSYNC LTDC_SSCR_VSH /*!< Vertical synchronization height. */
/**
* @}
*/
/** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR
* @{
*/
#define LTDC_COLOR 0x000000FFU /*!< Color mask */
/**
* @}
*/
/** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1
* @{
*/
#define LTDC_BLENDING_FACTOR1_CA 0x00000400U /*!< Blending factor : Cte Alpha */
#define LTDC_BLENDING_FACTOR1_PAxCA 0x00000600U /*!< Blending factor : Cte Alpha x Pixel Alpha*/
/**
* @}
*/
/** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2
* @{
*/
#define LTDC_BLENDING_FACTOR2_CA 0x00000005U /*!< Blending factor : Cte Alpha */
#define LTDC_BLENDING_FACTOR2_PAxCA 0x00000007U /*!< Blending factor : Cte Alpha x Pixel Alpha*/
/**
* @}
*/
/** @defgroup LTDC_Pixelformat LTDC Pixel format
* @{
*/
#define LTDC_PIXEL_FORMAT_ARGB8888 0x00000000U /*!< ARGB8888 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_RGB888 0x00000001U /*!< RGB888 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_RGB565 0x00000002U /*!< RGB565 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_ARGB1555 0x00000003U /*!< ARGB1555 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_ARGB4444 0x00000004U /*!< ARGB4444 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_L8 0x00000005U /*!< L8 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_AL44 0x00000006U /*!< AL44 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_AL88 0x00000007U /*!< AL88 LTDC pixel format */
/**
* @}
*/
/** @defgroup LTDC_Alpha LTDC Alpha
* @{
*/
#define LTDC_ALPHA LTDC_LxCACR_CONSTA /*!< LTDC Constant Alpha mask */
/**
* @}
*/
/** @defgroup LTDC_LAYER_Config LTDC LAYER Config
* @{
*/
#define LTDC_STOPPOSITION (LTDC_LxWHPCR_WHSPPOS >> 16U) /*!< LTDC Layer stop position */
#define LTDC_STARTPOSITION LTDC_LxWHPCR_WHSTPOS /*!< LTDC Layer start position */
#define LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL /*!< LTDC Layer Line length */
#define LTDC_LINE_NUMBER LTDC_LxCFBLNR_CFBLNBR /*!< LTDC Layer Line number */
/**
* @}
*/
/** @defgroup LTDC_Interrupts LTDC Interrupts
* @{
*/
#define LTDC_IT_LI LTDC_IER_LIE /*!< LTDC Line Interrupt */
#define LTDC_IT_FU LTDC_IER_FUIE /*!< LTDC FIFO Underrun Interrupt */
#define LTDC_IT_TE LTDC_IER_TERRIE /*!< LTDC Transfer Error Interrupt */
#define LTDC_IT_RR LTDC_IER_RRIE /*!< LTDC Register Reload Interrupt */
/**
* @}
*/
/** @defgroup LTDC_Flags LTDC Flags
* @{
*/
#define LTDC_FLAG_LI LTDC_ISR_LIF /*!< LTDC Line Interrupt Flag */
#define LTDC_FLAG_FU LTDC_ISR_FUIF /*!< LTDC FIFO Underrun interrupt Flag */
#define LTDC_FLAG_TE LTDC_ISR_TERRIF /*!< LTDC Transfer Error interrupt Flag */
#define LTDC_FLAG_RR LTDC_ISR_RRIF /*!< LTDC Register Reload interrupt Flag */
/**
* @}
*/
/** @defgroup LTDC_Reload_Type LTDC Reload Type
* @{
*/
#define LTDC_RELOAD_IMMEDIATE LTDC_SRCR_IMR /*!< Immediate Reload */
#define LTDC_RELOAD_VERTICAL_BLANKING LTDC_SRCR_VBR /*!< Vertical Blanking Reload */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup LTDC_Exported_Macros LTDC Exported Macros
* @{
*/
/** @brief Reset LTDC handle state.
* @param __HANDLE__ LTDC handle
* @retval None
*/
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_LTDC_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET)
#endif /*USE_HAL_LTDC_REGISTER_CALLBACKS */
/**
* @brief Enable the LTDC.
* @param __HANDLE__ LTDC handle
* @retval None.
*/
#define __HAL_LTDC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN)
/**
* @brief Disable the LTDC.
* @param __HANDLE__ LTDC handle
* @retval None.
*/
#define __HAL_LTDC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN))
/**
* @brief Enable the LTDC Layer.
* @param __HANDLE__ LTDC handle
* @param __LAYER__ Specify the layer to be enabled.
* This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
* @retval None.
*/
#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR\
|= (uint32_t)LTDC_LxCR_LEN)
/**
* @brief Disable the LTDC Layer.
* @param __HANDLE__ LTDC handle
* @param __LAYER__ Specify the layer to be disabled.
* This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
* @retval None.
*/
#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR\
&= ~(uint32_t)LTDC_LxCR_LEN)
/**
* @brief Reload immediately all LTDC Layers.
* @param __HANDLE__ LTDC handle
* @retval None.
*/
#define __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR)
/**
* @brief Reload during vertical blanking period all LTDC Layers.
* @param __HANDLE__ LTDC handle
* @retval None.
*/
#define __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_VBR)
/* Interrupt & Flag management */
/**
* @brief Get the LTDC pending flags.
* @param __HANDLE__ LTDC handle
* @param __FLAG__ Get the specified flag.
* This parameter can be any combination of the following values:
* @arg LTDC_FLAG_LI: Line Interrupt flag
* @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
* @arg LTDC_FLAG_TE: Transfer Error interrupt flag
* @arg LTDC_FLAG_RR: Register Reload Interrupt Flag
* @retval The state of FLAG (SET or RESET).
*/
#define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
/**
* @brief Clears the LTDC pending flags.
* @param __HANDLE__ LTDC handle
* @param __FLAG__ Specify the flag to clear.
* This parameter can be any combination of the following values:
* @arg LTDC_FLAG_LI: Line Interrupt flag
* @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
* @arg LTDC_FLAG_TE: Transfer Error interrupt flag
* @arg LTDC_FLAG_RR: Register Reload Interrupt Flag
* @retval None
*/
#define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
/**
* @brief Enables the specified LTDC interrupts.
* @param __HANDLE__ LTDC handle
* @param __INTERRUPT__ Specify the LTDC interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg LTDC_IT_LI: Line Interrupt flag
* @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
* @arg LTDC_IT_TE: Transfer Error interrupt flag
* @arg LTDC_IT_RR: Register Reload Interrupt Flag
* @retval None
*/
#define __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
/**
* @brief Disables the specified LTDC interrupts.
* @param __HANDLE__ LTDC handle
* @param __INTERRUPT__ Specify the LTDC interrupt sources to be disabled.
* This parameter can be any combination of the following values:
* @arg LTDC_IT_LI: Line Interrupt flag
* @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
* @arg LTDC_IT_TE: Transfer Error interrupt flag
* @arg LTDC_IT_RR: Register Reload Interrupt Flag
* @retval None
*/
#define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
/**
* @brief Check whether the specified LTDC interrupt has occurred or not.
* @param __HANDLE__ LTDC handle
* @param __INTERRUPT__ Specify the LTDC interrupt source to check.
* This parameter can be one of the following values:
* @arg LTDC_IT_LI: Line Interrupt flag
* @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
* @arg LTDC_IT_TE: Transfer Error interrupt flag
* @arg LTDC_IT_RR: Register Reload Interrupt Flag
* @retval The state of INTERRUPT (SET or RESET).
*/
#define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
/**
* @}
*/
/* Include LTDC HAL Extension module */
#include "stm32h7rsxx_hal_ltdc_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup LTDC_Exported_Functions
* @{
*/
/** @addtogroup LTDC_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc);
HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc);
void HAL_LTDC_MspInit(LTDC_HandleTypeDef *hltdc);
void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc);
void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc);
void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc);
void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID,
pLTDC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup LTDC_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc);
/**
* @}
*/
/** @addtogroup LTDC_Exported_Functions_Group3
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, const uint32_t *pCLUT, uint32_t CLUTSize,
uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line);
HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc);
HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc);
HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType);
HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg,
uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize,
uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0,
uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
/**
* @}
*/
/** @addtogroup LTDC_Exported_Functions_Group4
* @{
*/
/* Peripheral State functions *************************************************/
HAL_LTDC_StateTypeDef HAL_LTDC_GetState(const LTDC_HandleTypeDef *hltdc);
uint32_t HAL_LTDC_GetError(const LTDC_HandleTypeDef *hltdc);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup LTDC_Private_Macros LTDC Private Macros
* @{
*/
#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(\
((uint32_t)((__HANDLE__)->Instance))\
+ 0x84U + (0x80U*(__LAYER__)))))
#define IS_LTDC_LAYER(__LAYER__) ((__LAYER__) < MAX_LAYER)
#define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL)\
|| ((__HSPOL__) == LTDC_HSPOLARITY_AH))
#define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL)\
|| ((__VSPOL__) == LTDC_VSPOLARITY_AH))
#define IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL)\
|| ((__DEPOL__) == LTDC_DEPOLARITY_AH))
#define IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC)\
|| ((__PCPOL__) == LTDC_PCPOLARITY_IIPC))
#define IS_LTDC_HSYNC(__HSYNC__) ((__HSYNC__) <= LTDC_HORIZONTALSYNC)
#define IS_LTDC_VSYNC(__VSYNC__) ((__VSYNC__) <= LTDC_VERTICALSYNC)
#define IS_LTDC_AHBP(__AHBP__) ((__AHBP__) <= LTDC_HORIZONTALSYNC)
#define IS_LTDC_AVBP(__AVBP__) ((__AVBP__) <= LTDC_VERTICALSYNC)
#define IS_LTDC_AAW(__AAW__) ((__AAW__) <= LTDC_HORIZONTALSYNC)
#define IS_LTDC_AAH(__AAH__) ((__AAH__) <= LTDC_VERTICALSYNC)
#define IS_LTDC_TOTALW(__TOTALW__) ((__TOTALW__) <= LTDC_HORIZONTALSYNC)
#define IS_LTDC_TOTALH(__TOTALH__) ((__TOTALH__) <= LTDC_VERTICALSYNC)
#define IS_LTDC_BLUEVALUE(__BBLUE__) ((__BBLUE__) <= LTDC_COLOR)
#define IS_LTDC_GREENVALUE(__BGREEN__) ((__BGREEN__) <= LTDC_COLOR)
#define IS_LTDC_REDVALUE(__BRED__) ((__BRED__) <= LTDC_COLOR)
#define IS_LTDC_BLENDING_FACTOR1(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_CA) || \
((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_PAxCA))
#define IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_CA) || \
((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_PAxCA))
#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__) (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || \
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888) || \
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565) || \
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || \
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8) || \
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44) || \
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88))
#define IS_LTDC_ALPHA(__ALPHA__) ((__ALPHA__) <= LTDC_ALPHA)
#define IS_LTDC_HCONFIGST(__HCONFIGST__) ((__HCONFIGST__) <= LTDC_STARTPOSITION)
#define IS_LTDC_HCONFIGSP(__HCONFIGSP__) ((__HCONFIGSP__) <= LTDC_STOPPOSITION)
#define IS_LTDC_VCONFIGST(__VCONFIGST__) ((__VCONFIGST__) <= LTDC_STARTPOSITION)
#define IS_LTDC_VCONFIGSP(__VCONFIGSP__) ((__VCONFIGSP__) <= LTDC_STOPPOSITION)
#define IS_LTDC_CFBP(__CFBP__) ((__CFBP__) <= LTDC_COLOR_FRAME_BUFFER)
#define IS_LTDC_CFBLL(__CFBLL__) ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER)
#define IS_LTDC_CFBLNBR(__CFBLNBR__) ((__CFBLNBR__) <= LTDC_LINE_NUMBER)
#define IS_LTDC_LIPOS(__LIPOS__) ((__LIPOS__) <= 0x7FFU)
#define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || \
((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup LTDC_Private_Functions LTDC Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* LTDC */
#ifdef __cplusplus
}
#endif
#endif /* STM32H7RSxx_HAL_LTDC_H */
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_ltdc_ex.h
+87
View File
@@ -0,0 +1,87 @@
/**
******************************************************************************
* @file stm32h7rsxx_hal_ltdc_ex.h
* @author MCD Application Team
* @brief Header file of LTDC HAL Extension module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7RSxx_HAL_LTDC_EX_H
#define STM32H7RSxx_HAL_LTDC_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal_def.h"
#if defined(HAL_LTDC_MODULE_ENABLED) && defined(HAL_DSI_MODULE_ENABLED)
#if defined (LTDC) && defined (DSI)
#include "stm32h7rsxx_hal_dsi.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @addtogroup LTDCEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup LTDCEx_Exported_Functions
* @{
*/
/** @addtogroup LTDCEx_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg);
HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#endif /* LTDC && DSI */
#endif /* HAL_LTCD_MODULE_ENABLED && HAL_DSI_MODULE_ENABLED */
#ifdef __cplusplus
}
#endif
#endif /* STM32H7RSxx_HAL_LTDC_EX_H */
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_mdf.h
+781
View File
@@ -0,0 +1,781 @@
/**
******************************************************************************
* @file stm32h7rsxx_hal_mdf.h
* @author MCD Application Team
* @brief Header file of MDF HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7RSxx_HAL_MDF_H
#define STM32H7RSxx_HAL_MDF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal_def.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @addtogroup MDF
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup MDF_Exported_Types MDF Exported Types
* @{
*/
/**
* @brief HAL MDF states definition
*/
typedef enum
{
HAL_MDF_STATE_RESET = 0x00U, /*!< MDF not initialized */
HAL_MDF_STATE_READY = 0x01U, /*!< MDF initialized and ready for use */
HAL_MDF_STATE_ACQUISITION = 0x02U, /*!< MDF acquisition in progress */
HAL_MDF_STATE_ERROR = 0xFFU /*!< MDF state error */
} HAL_MDF_StateTypeDef;
/**
* @brief MDF clock trigger structure definition
*/
typedef struct
{
FunctionalState Activation; /*!< Output clock trigger enable/disable */
uint32_t Source; /*!< Output clock trigger source.
This parameter can be a value of @ref MDF_ClockTriggerSource */
uint32_t Edge; /*!< Output clock trigger edge.
This parameter can be a value of @ref MDF_ClockTriggerEdge */
} MDF_ClockTriggerTypeDef;
/**
* @brief MDF output clock structure definition
*/
typedef struct
{
FunctionalState Activation; /*!< Output clock enable/disable */
uint32_t Pins; /*!< Output clock pins.
This parameter can be a value of @ref MDF_OuputClockPins */
uint32_t Divider; /*!< Output clock divider.
This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
MDF_ClockTriggerTypeDef Trigger; /*!< Output clock trigger parameters */
} MDF_OutputClockTypeDef;
/**
* @brief MDF common parameters structure definition
*/
typedef struct
{
uint32_t ProcClockDivider; /*!< Processing clock divider.
This parameter must be a number between Min_Data = 1
and Max_Data = 128 */
MDF_OutputClockTypeDef OutputClock; /*!< Output clock parameters */
} MDF_CommonParamTypeDef;
/**
* @brief MDF serial interface structure definition
*/
typedef struct
{
FunctionalState Activation; /*!< Serial interface enable/disable */
uint32_t Mode; /*!< Serial interface mode.
This parameter can be a value of @ref MDF_SitfMode */
uint32_t ClockSource; /*!< Serial interface clock source.
This parameter can be a value of @ref MDF_SitfClockSource */
uint32_t Threshold; /*!< SPI threshold for clock absence detection or Manchester symbol threshold.
This parameter must be a number between Min_Data = 4 and Max_Data = 31 */
} MDF_SerialInterfaceTypeDef;
/**
* @brief MDF init structure definition
*/
typedef struct
{
MDF_CommonParamTypeDef CommonParam; /*!< MDF common parameters */
MDF_SerialInterfaceTypeDef SerialInterface; /*!< MDF serial interface parameters */
uint32_t FilterBistream; /*!< MDF filter bitstream selection.
This parameter can be a value of @ref MDF_FilterBitstream */
} MDF_InitTypeDef;
/**
* @brief MDF handle structure definition
*/
#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
typedef struct __MDF_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
{
MDF_Filter_TypeDef *Instance; /*!< MDF instance */
MDF_InitTypeDef Init; /*!< MDF init parameters */
DMA_HandleTypeDef *hdma; /*!< Pointer on DMA handler for acquisitions */
__IO HAL_MDF_StateTypeDef State; /*!< MDF state */
__IO uint32_t ErrorCode; /*!< MDF error code */
#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
void (*AcqCpltCallback)(struct __MDF_HandleTypeDef *hmdf); /*!< MDF acquisition complete callback */
void (*AcqHalfCpltCallback)(struct __MDF_HandleTypeDef *hmdf); /*!< MDF acquisition half complete callback */
void (*SndLvCallback)(struct __MDF_HandleTypeDef *hmdf,
uint32_t SoundLevel,
uint32_t AmbientNoise); /*!< MDF sound level callback */
void (*SadCallback)(struct __MDF_HandleTypeDef *hmdf); /*!< MDF sound activity detector callback */
void (*ErrorCallback)(struct __MDF_HandleTypeDef *hmdf); /*!< MDF error callback */
void (*MspInitCallback)(struct __MDF_HandleTypeDef *hmdf); /*!< MDF MSP init callback */
void (*MspDeInitCallback)(struct __MDF_HandleTypeDef *hmdf); /*!< MDF MSP de-init callback */
#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
} MDF_HandleTypeDef;
#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
/**
* @brief MDF callback ID enumeration definition
*/
typedef enum
{
HAL_MDF_ACQ_COMPLETE_CB_ID = 0x01U, /*!< MDF acquisition complete callback ID */
HAL_MDF_ACQ_HALFCOMPLETE_CB_ID = 0x02U, /*!< MDF acquisition half complete callback ID */
HAL_MDF_SNDLVL_CB_ID = 0x03U, /*!< MDF sound level callback ID */
HAL_MDF_SAD_CB_ID = 0x04U, /*!< MDF sound activity detector callback ID */
HAL_MDF_ERROR_CB_ID = 0x05U, /*!< MDF error callback ID */
HAL_MDF_MSPINIT_CB_ID = 0x06U, /*!< MDF MSP init callback ID */
HAL_MDF_MSPDEINIT_CB_ID = 0x07U /*!< MDF MSP de-init callback ID */
} HAL_MDF_CallbackIDTypeDef;
/**
* @brief MDF callback pointers definition
*/
typedef void (*pMDF_CallbackTypeDef)(MDF_HandleTypeDef *hmdf);
typedef void (*pMDF_SndLvlCallbackTypeDef)(MDF_HandleTypeDef *hmdf, uint32_t SoundLevel, uint32_t AmbientNoise);
#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
/**
* @brief MDF reshape filter structure definition
*/
typedef struct
{
FunctionalState Activation; /*!< Reshape filter enable/disable */
uint32_t DecimationRatio; /*!< Reshape filter decimation ratio.
This parameter can be a value of @ref MDF_ReshapeDecimationRatio */
} MDF_ReshapeFilterTypeDef;
/**
* @brief MDF high pass filter structure definition
*/
typedef struct
{
FunctionalState Activation; /*!< High pass filter enable/disable */
uint32_t CutOffFrequency; /*!< High pass filter cut-off frequency.
This parameter can be a value of @ref MDF_HighPassCutOffFreq */
} MDF_HighPassFilterTypeDef;
/**
* @brief MDF sound activity structure definition
*/
typedef struct
{
FunctionalState Activation; /*!< Sound activity detector enable/disable */
uint32_t Mode; /*!< Sound activity detector mode.
This parameter can be a value of @ref MDF_SadMode */
uint32_t FrameSize; /*!< Size of one frame to compute short-term signal level.
This parameter can be a value of @ref MDF_SadFrameSize */
FunctionalState Hysteresis; /*!< Hysteresis enable/disable.
@note This parameter is not used if Mode is set
to MDF_SAD_AMBIENT_NOISE_ESTIMATOR */
uint32_t SoundTriggerEvent; /*!< Sound trigger event configuration.
This parameter can be a value of @ref MDF_SadSoundTriggerEvent */
uint32_t DataMemoryTransfer; /*!< Data memory transfer mode.
This parameter can be a value of @ref MDF_SadDataMemoryTransfer */
uint32_t MinNoiseLevel; /*!< Minimum noise level.
This parameter must be a number between Min_Data = 0
and Max_Data = 8191 */
uint32_t HangoverWindow; /*!< Hangover time window in frames.
This parameter can be a value of @ref MDF_SadHangoverWindow */
uint32_t LearningFrames; /*!< Number of learning frames for the first estimation of noise level.
This parameter can be a value of @ref MDF_SadLearningFrames */
uint32_t AmbientNoiseSlope; /*!< Ambient noise slope control.
This parameter must be a number between Min_Data = 0 and Max_Data = 7.
@note This parameter is not used if Mode is set
to MDF_SAD_SOUND_DETECTOR */
uint32_t SignalNoiseThreshold; /*!< Signal to noise threshold.
This parameter can be a value of @ref MDF_SadSignalNoiseThreshold */
FunctionalState SoundLevelInterrupt; /*!< Sound level interrupt enable/disable.
@note This interrupt is mainly used for debug purpose */
} MDF_SoundActivityTypeDef;
/**
* @brief MDF filter trigger structure definition
*/
typedef struct
{
uint32_t Source; /*!< Filter trigger source.
This parameter can be a value of @ref MDF_FilterTriggerSource */
uint32_t Edge; /*!< Filter trigger edge.
This parameter can be a value of @ref MDF_FilterTriggerEdge */
} MDF_FilterTriggerTypeDef;
/**
* @brief MDF filter configuration structure definition
*/
typedef struct
{
uint32_t DataSource; /*!< Filter data source.
This parameter can be a value of @ref MDF_DataSource */
uint32_t Delay; /*!< Delay to apply on data source in number of samples.
This parameter must be a number between Min_Data = 0
and Max_Data = 127 */
uint32_t CicMode; /*!< CIC filter mode.
This parameter can be a value of @ref MDF_CicMode */
uint32_t DecimationRatio; /*!< Filter decimation ratio.
This parameter must be a number between Min_Data = 2
and Max_Data = 512 */
int32_t Gain; /*!< Filter gain in step of around 3db (from -48db to 72dB).
This parameter must be a number between Min_Data = -16
and Max_Data = 24 */
MDF_ReshapeFilterTypeDef ReshapeFilter; /*!< Reshape filter configuration */
MDF_HighPassFilterTypeDef HighPassFilter; /*!< High pass filter configuration */
MDF_SoundActivityTypeDef SoundActivity; /*!< Sound activity detector configuration */
uint32_t AcquisitionMode; /*!< Filter acquisition mode.
This parameter can be a value of @ref MDF_AcquisitionMode */
uint32_t FifoThreshold; /*!< Filter RXFIFO threshold.
This parameter can be a value of @ref MDF_FifoThreshold */
uint32_t DiscardSamples; /*!< Number of samples to discard after filter enable.
This parameter must be a number between Min_Data = 0
and Max_Data = 255 */
MDF_FilterTriggerTypeDef Trigger; /*!< Filter trigger configuration.
@note This parameter is not used if AcquisitionMode is set
to MDF_MODE_ASYNC_CONT or MDF_MODE_ASYNC_SINGLE */
} MDF_FilterConfigTypeDef;
/**
* @brief MDF DMA configuration structure definition
*/
typedef struct
{
uint32_t Address; /*!< DMA destination address */
uint32_t DataLength; /*!< Length of data to transfer in bytes */
FunctionalState MsbOnly; /*!< Transfer only the 16MSB of the acquistion data */
} MDF_DmaConfigTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup MDF_Exported_Constants MDF Exported Constants
* @{
*/
/** @defgroup MDF_ErrorCode MDF error code
* @{
*/
#define MDF_ERROR_NONE 0x00000000U /*!< No error */
#define MDF_ERROR_ACQUISITION_OVERFLOW 0x00000001U /*!< Overflow occurs during acquisition */
#define MDF_ERROR_RSF_OVERRUN 0x00000002U /*!< Overrun occurs on reshape filter */
#define MDF_ERROR_CLOCK_ABSENCE 0x00000004U /*!< Clock absence detection occurs */
#define MDF_ERROR_SATURATION 0x00000010U /*!< Saturation detection occurs */
#define MDF_ERROR_DMA 0x00000040U /*!< DMA error occurs */
#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
#define MDF_ERROR_INVALID_CALLBACK 0x00000080U /*!< Invalid callback error occurs */
#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup MDF_ClockTriggerSource MDF output clock trigger source
* @{
*/
#define MDF_CLOCK_TRIG_TRGO 0x00000000U
#define MDF_CLOCK_TRIG_EXTI15 MDF_CKGCR_TRGSRC_1
/**
* @}
*/
/** @defgroup MDF_ClockTriggerEdge MDF output clock trigger edge
* @{
*/
#define MDF_CLOCK_TRIG_RISING_EDGE 0x00000000U /*!< Rising edge */
#define MDF_CLOCK_TRIG_FALLING_EDGE MDF_CKGCR_TRGSENS /*!< Falling edge */
/**
* @}
*/
/** @defgroup MDF_OuputClockPins MDF output clock pins
* @{
*/
#define MDF_OUTPUT_CLOCK_0 MDF_CKGCR_CCK0DIR /*!< MDF_CCK0 is used as output clock */
#define MDF_OUTPUT_CLOCK_1 MDF_CKGCR_CCK1DIR /*!< MDF_CCK1 is used as output clock */
#define MDF_OUTPUT_CLOCK_ALL (MDF_CKGCR_CCK0DIR | \
MDF_CKGCR_CCK1DIR) /*!< MDF_CCK0 and MDF_CCK1 are used as output clock */
/**
* @}
*/
/** @defgroup MDF_SitfMode MDF serial interface mode
* @{
*/
#define MDF_SITF_LF_MASTER_SPI_MODE 0x00000000U /*!< Low frequency master SPI mode */
#define MDF_SITF_NORMAL_SPI_MODE MDF_SITFCR_SITFMOD_0 /*!< Normal SPI mode */
#define MDF_SITF_MANCHESTER_FALLING_MODE MDF_SITFCR_SITFMOD_1 /*!< Manchester mode rising edge logic 0
and falling edge logic 1 */
#define MDF_SITF_MANCHESTER_RISING_MODE MDF_SITFCR_SITFMOD /*!< Manchester mode rising edge logic 1
and falling edge logic 0 */
/**
* @}
*/
/** @defgroup MDF_SitfClockSource MDF serial interface clock source
* @{
*/
#define MDF_SITF_CCK0_SOURCE 0x00000000U /*!< Common clock 0 source */
#define MDF_SITF_CCK1_SOURCE MDF_SITFCR_SCKSRC_0 /*!< Common clock 1 source */
/**
* @}
*/
/** @defgroup MDF_FilterBitstream MDF filter bitstream
* @{
*/
#define MDF_BITSTREAM0_RISING 0x00000000U
#define MDF_BITSTREAM0_FALLING MDF_BSMXCR_BSSEL_0
/**
* @}
*/
/** @defgroup MDF_ReshapeDecimationRatio MDF reshape filter decimation ratio
* @{
*/
#define MDF_RSF_DECIMATION_RATIO_4 0x00000000U /*!< Reshape filter decimation ratio is 4 */
#define MDF_RSF_DECIMATION_RATIO_1 MDF_DFLTRSFR_RSFLTD /*!< Reshape filter decimation ratio is 1 */
/**
* @}
*/
/** @defgroup MDF_HighPassCutOffFreq MDF high pass filter cut-off frequency
* @{
*/
#define MDF_HPF_CUTOFF_0_000625FPCM 0x00000000U /*!< Cut-off frequency of 0.000625xFpcm */
#define MDF_HPF_CUTOFF_0_00125FPCM MDF_DFLTRSFR_HPFC_0 /*!< Cut-off frequency of 0.00125xFpcm */
#define MDF_HPF_CUTOFF_0_0025FPCM MDF_DFLTRSFR_HPFC_1 /*!< Cut-off frequency of 0.0025xFpcm */
#define MDF_HPF_CUTOFF_0_0095FPCM MDF_DFLTRSFR_HPFC /*!< Cut-off frequency of 0.0095xFpcm */
/**
* @}
*/
/** @defgroup MDF_SadMode MDF sound activity detector mode
* @{
*/
#define MDF_SAD_VOICE_ACTIVITY_DETECTOR 0x00000000U /*!< Voice activity detector */
#define MDF_SAD_SOUND_DETECTOR MDF_SADCR_SADMOD_0 /*!< Sound detector */
#define MDF_SAD_AMBIENT_NOISE_DETECTOR MDF_SADCR_SADMOD /*!< Ambient noise detector */
/**
* @}
*/
/** @defgroup MDF_SadFrameSize MDF sound activity detector frame size
* @{
*/
#define MDF_SAD_8_PCM_SAMPLES 0x00000000U /*!< Frame size of 8 PCM samples */
#define MDF_SAD_16_PCM_SAMPLES MDF_SADCR_FRSIZE_0 /*!< Frame size of 16 PCM samples */
#define MDF_SAD_32_PCM_SAMPLES MDF_SADCR_FRSIZE_1 /*!< Frame size of 32 PCM samples */
#define MDF_SAD_64_PCM_SAMPLES (MDF_SADCR_FRSIZE_0 | MDF_SADCR_FRSIZE_1) /*!< Frame size of 64 PCM samples */
#define MDF_SAD_128_PCM_SAMPLES MDF_SADCR_FRSIZE_2 /*!< Frame size of 128 PCM samples */
#define MDF_SAD_256_PCM_SAMPLES (MDF_SADCR_FRSIZE_0 | MDF_SADCR_FRSIZE_2) /*!< Frame size of 256 PCM samples */
#define MDF_SAD_512_PCM_SAMPLES MDF_SADCR_FRSIZE /*!< Frame size of 512 PCM samples */
/**
* @}
*/
/** @defgroup MDF_SadSoundTriggerEvent MDF sound activity detector trigger event
* @{
*/
#define MDF_SAD_ENTER_DETECT 0x00000000U /*!< Event when SAD enters in detect state */
#define MDF_SAD_ENTER_EXIT_DETECT MDF_SADCR_DETCFG /*!< Event when SAD enters or exits from detect state */
/**
* @}
*/
/** @defgroup MDF_SadDataMemoryTransfer MDF sound activity detector data memory transfer mode
* @{
*/
#define MDF_SAD_NO_MEMORY_TRANSFER 0x00000000U /*!< No memory transfer */
#define MDF_SAD_MEMORY_TRANSFER_IN_DETECT MDF_SADCR_DATCAP_0 /*!< Memory transfer only in detect state */
#define MDF_SAD_MEMORY_TRANSFER_ALWAYS MDF_SADCR_DATCAP /*!< Memory transfer always */
/**
* @}
*/
/** @defgroup MDF_SadHangoverWindow MDF sound activity detector data hangover time window
* @{
*/
#define MDF_SAD_HANGOVER_4_FRAMES 0x00000000U /*!< Hangover window of 4 frames */
#define MDF_SAD_HANGOVER_8_FRAMES MDF_SADCFGR_HGOVR_0 /*!< Hangover window of 8 frames */
#define MDF_SAD_HANGOVER_16_FRAMES MDF_SADCFGR_HGOVR_1 /*!< Hangover window of 16 frames */
#define MDF_SAD_HANGOVER_32_FRAMES (MDF_SADCFGR_HGOVR_0 | \
MDF_SADCFGR_HGOVR_1) /*!< Hangover window of 32 frames */
#define MDF_SAD_HANGOVER_64_FRAMES MDF_SADCFGR_HGOVR_2 /*!< Hangover window of 64 frames */
#define MDF_SAD_HANGOVER_128_FRAMES (MDF_SADCFGR_HGOVR_0 | \
MDF_SADCFGR_HGOVR_2) /*!< Hangover window of 128 frames */
#define MDF_SAD_HANGOVER_256_FRAMES (MDF_SADCFGR_HGOVR_1 | \
MDF_SADCFGR_HGOVR_2) /*!< Hangover window of 256 frames */
#define MDF_SAD_HANGOVER_512_FRAMES (MDF_SADCFGR_HGOVR_0 | \
MDF_SADCFGR_HGOVR_1 | \
MDF_SADCFGR_HGOVR_2) /*!< Hangover window of 512 frames */
/**
* @}
*/
/** @defgroup MDF_SadLearningFrames MDF sound activity detector data learning frames
* @{
*/
#define MDF_SAD_LEARNING_2_FRAMES 0x00000000U /*!< 2 learning frames */
#define MDF_SAD_LEARNING_4_FRAMES MDF_SADCFGR_LFRNB_0 /*!< 4 learning frames */
#define MDF_SAD_LEARNING_8_FRAMES MDF_SADCFGR_LFRNB_1 /*!< 8 learning frames */
#define MDF_SAD_LEARNING_16_FRAMES (MDF_SADCFGR_LFRNB_0 | MDF_SADCFGR_LFRNB_1) /*!< 16 learning frames */
#define MDF_SAD_LEARNING_32_FRAMES MDF_SADCFGR_LFRNB /*!< 32 learning frames */
/**
* @}
*/
/** @defgroup MDF_SadSignalNoiseThreshold MDF sound activity detector data signal to noise threshold
* @{
*/
#define MDF_SAD_SIGNAL_NOISE_3_5DB 0x00000000U /*!< Signal to noise threshold is 3.5dB */
#define MDF_SAD_SIGNAL_NOISE_6DB MDF_SADCFGR_SNTHR_0 /*!< Signal to noise threshold is 6dB */
#define MDF_SAD_SIGNAL_NOISE_9_5DB MDF_SADCFGR_SNTHR_1 /*!< Signal to noise threshold is 9.5dB */
#define MDF_SAD_SIGNAL_NOISE_12DB (MDF_SADCFGR_SNTHR_0 | \
MDF_SADCFGR_SNTHR_1) /*!< Signal to noise threshold is 12dB */
#define MDF_SAD_SIGNAL_NOISE_15_6DB MDF_SADCFGR_SNTHR_2 /*!< Signal to noise threshold is 15.6dB */
#define MDF_SAD_SIGNAL_NOISE_18DB (MDF_SADCFGR_SNTHR_0 | \
MDF_SADCFGR_SNTHR_2) /*!< Signal to noise threshold is 18dB */
#define MDF_SAD_SIGNAL_NOISE_21_6DB (MDF_SADCFGR_SNTHR_1 | \
MDF_SADCFGR_SNTHR_2) /*!< Signal to noise threshold is 21.6dB */
#define MDF_SAD_SIGNAL_NOISE_24_1DB (MDF_SADCFGR_SNTHR_0 | \
MDF_SADCFGR_SNTHR_1 | \
MDF_SADCFGR_SNTHR_2) /*!< Signal to noise threshold is 24.1dB */
#define MDF_SAD_SIGNAL_NOISE_27_6DB MDF_SADCFGR_SNTHR_3 /*!< Signal to noise threshold is 27.6dB */
#define MDF_SAD_SIGNAL_NOISE_30_1DB (MDF_SADCFGR_SNTHR_0 | \
MDF_SADCFGR_SNTHR_3) /*!< Signal to noise threshold is 30.1dB */
/**
* @}
*/
/** @defgroup MDF_FilterTriggerSource MDF filter trigger source
* @{
*/
#define MDF_FILTER_TRIG_TRGO 0x00000000U
#define MDF_FILTER_TRIG_EXTI15 MDF_DFLTCR_TRGSRC_1
/**
* @}
*/
/** @defgroup MDF_FilterTriggerEdge MDF filter trigger edge
* @{
*/
#define MDF_FILTER_TRIG_RISING_EDGE 0x00000000U /*!< Rising edge */
#define MDF_FILTER_TRIG_FALLING_EDGE MDF_DFLTCR_TRGSENS /*!< Falling edge */
/**
* @}
*/
/** @defgroup MDF_DataSource MDF data source
* @{
*/
#define MDF_DATA_SOURCE_BSMX 0x00000000U /*!< Data from bitstream matrix */
#define MDF_DATA_SOURCE_ADCITF1 MDF_DFLTCICR_DATSRC_1 /*!< Data from ADC interface 1 */
#define MDF_DATA_SOURCE_ADCITF2 MDF_DFLTCICR_DATSRC /*!< Data from ADC interface 2 */
/**
* @}
*/
/** @defgroup MDF_CicMode MDF CIC mode
* @{
*/
#define MDF_ONE_FILTER_SINC4 MDF_DFLTCICR_CICMOD_2 /*!< One filter in Sinc4 order */
#define MDF_ONE_FILTER_SINC5 (MDF_DFLTCICR_CICMOD_0 | \
MDF_DFLTCICR_CICMOD_2) /*!< One filter in Sinc5 order */
/**
* @}
*/
/** @defgroup MDF_AcquisitionMode MDF acquisition mode
* @{
*/
#define MDF_MODE_ASYNC_CONT 0x00000000U /*!< Asynchronous, continuous acquisition mode */
#define MDF_MODE_ASYNC_SINGLE MDF_DFLTCR_ACQMOD_0 /*!< Asynchronous, single-shot acquisition mode.
@note Not available with SAD usage */
#define MDF_MODE_SYNC_CONT MDF_DFLTCR_ACQMOD_1 /*!< Synchronous, continuous acquisition mode */
#define MDF_MODE_SYNC_SINGLE (MDF_DFLTCR_ACQMOD_0 | \
MDF_DFLTCR_ACQMOD_1) /*!< Synchronous, single-shot acquisition mode.
@note Not available with SAD usage */
#define MDF_MODE_WINDOW_CONT MDF_DFLTCR_ACQMOD_2 /*!< Window, continuous acquisition mode.
@note Not available with SAD usage */
/**
* @}
*/
/** @defgroup MDF_FifoThreshold MDF RXFIFO threshold
* @{
*/
#define MDF_FIFO_THRESHOLD_NOT_EMPTY 0x00000000U /*!< Event generated when RXFIFO is not empty */
#define MDF_FIFO_THRESHOLD_HALF_FULL MDF_DFLTCR_FTH /*!< Event generated when RXFIFO is half_full */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup MDF_Exported_Macros MDF Exported Macros
* @{
*/
/** @brief Reset MDF handle state.
* @param __HANDLE__ MDF handle.
* @retval None
*/
#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
#define __HAL_MDF_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_MDF_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
#define __HAL_MDF_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MDF_STATE_RESET)
#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup MDF_Exported_Functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
/** @addtogroup MDF_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_MDF_Init(MDF_HandleTypeDef *hmdf);
HAL_StatusTypeDef HAL_MDF_DeInit(MDF_HandleTypeDef *hmdf);
void HAL_MDF_MspInit(MDF_HandleTypeDef *hmdf);
void HAL_MDF_MspDeInit(MDF_HandleTypeDef *hmdf);
#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_MDF_RegisterCallback(MDF_HandleTypeDef *hmdf,
HAL_MDF_CallbackIDTypeDef CallbackID,
pMDF_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_MDF_UnRegisterCallback(MDF_HandleTypeDef *hmdf,
HAL_MDF_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_MDF_RegisterSndLvlCallback(MDF_HandleTypeDef *hmdf,
pMDF_SndLvlCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_MDF_UnRegisterSndLvlCallback(MDF_HandleTypeDef *hmdf);
#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
/**
* @}
*/
/* Acquisition functions *****************************************************/
/** @addtogroup MDF_Exported_Functions_Group2
* @{
*/
HAL_StatusTypeDef HAL_MDF_AcqStart(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig);
HAL_StatusTypeDef HAL_MDF_PollForAcq(MDF_HandleTypeDef *hmdf, uint32_t Timeout);
HAL_StatusTypeDef HAL_MDF_GetAcqValue(const MDF_HandleTypeDef *hmdf, int32_t *pValue);
HAL_StatusTypeDef HAL_MDF_AcqStop(MDF_HandleTypeDef *hmdf);
HAL_StatusTypeDef HAL_MDF_AcqStart_IT(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig);
HAL_StatusTypeDef HAL_MDF_AcqStop_IT(MDF_HandleTypeDef *hmdf);
HAL_StatusTypeDef HAL_MDF_AcqStart_DMA(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig,
const MDF_DmaConfigTypeDef *pDmaConfig);
HAL_StatusTypeDef HAL_MDF_AcqStop_DMA(MDF_HandleTypeDef *hmdf);
HAL_StatusTypeDef HAL_MDF_GenerateTrgo(const MDF_HandleTypeDef *hmdf);
HAL_StatusTypeDef HAL_MDF_SetDelay(MDF_HandleTypeDef *hmdf, uint32_t Delay);
HAL_StatusTypeDef HAL_MDF_GetDelay(const MDF_HandleTypeDef *hmdf, uint32_t *pDelay);
HAL_StatusTypeDef HAL_MDF_SetGain(MDF_HandleTypeDef *hmdf, int32_t Gain);
HAL_StatusTypeDef HAL_MDF_GetGain(const MDF_HandleTypeDef *hmdf, int32_t *pGain);
HAL_StatusTypeDef HAL_MDF_PollForSndLvl(MDF_HandleTypeDef *hmdf, uint32_t Timeout, uint32_t *pSoundLevel,
uint32_t *pAmbientNoise);
HAL_StatusTypeDef HAL_MDF_PollForSad(MDF_HandleTypeDef *hmdf, uint32_t Timeout);
void HAL_MDF_AcqCpltCallback(MDF_HandleTypeDef *hmdf);
void HAL_MDF_AcqHalfCpltCallback(MDF_HandleTypeDef *hmdf);
void HAL_MDF_SndLvlCallback(MDF_HandleTypeDef *hmdf, uint32_t SoundLevel, uint32_t AmbientNoise);
void HAL_MDF_SadCallback(MDF_HandleTypeDef *hmdf);
/**
* @}
*/
/* Clock absence detection functions *****************************************/
/** @addtogroup MDF_Exported_Functions_Group3
* @{
*/
HAL_StatusTypeDef HAL_MDF_PollForCkab(MDF_HandleTypeDef *hmdf, uint32_t Timeout);
HAL_StatusTypeDef HAL_MDF_CkabStart_IT(MDF_HandleTypeDef *hmdf);
HAL_StatusTypeDef HAL_MDF_CkabStop_IT(MDF_HandleTypeDef *hmdf);
/**
* @}
*/
/* Generic functions *********************************************************/
/** @addtogroup MDF_Exported_Functions_Group4
* @{
*/
void HAL_MDF_IRQHandler(MDF_HandleTypeDef *hmdf);
void HAL_MDF_ErrorCallback(MDF_HandleTypeDef *hmdf);
HAL_MDF_StateTypeDef HAL_MDF_GetState(const MDF_HandleTypeDef *hmdf);
uint32_t HAL_MDF_GetError(const MDF_HandleTypeDef *hmdf);
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup MDF_Private_Macros MDF Private Macros
* @{
*/
#define IS_MDF_FILTER_BITSTREAM(PARAM) (((PARAM) == MDF_BITSTREAM0_RISING) || \
((PARAM) == MDF_BITSTREAM0_FALLING))
#define IS_MDF_PROC_CLOCK_DIVIDER(PARAM) ((1U <= (PARAM)) && ((PARAM) <= 128U))
#define IS_MDF_OUTPUT_CLOCK_PINS(PARAM) (((PARAM) == MDF_OUTPUT_CLOCK_0) || \
((PARAM) == MDF_OUTPUT_CLOCK_1) || \
((PARAM) == MDF_OUTPUT_CLOCK_ALL))
#define IS_MDF_OUTPUT_CLOCK_DIVIDER(PARAM) ((1U <= (PARAM)) && ((PARAM) <= 16U))
#define IS_MDF_OUTPUT_CLOCK_TRIGGER_SOURCE(PARAM) (((PARAM) == MDF_CLOCK_TRIG_TRGO) || \
((PARAM) == MDF_CLOCK_TRIG_EXTI15))
#define IS_MDF_OUTPUT_CLOCK_TRIGGER_EDGE(PARAM) (((PARAM) == MDF_CLOCK_TRIG_RISING_EDGE) || \
((PARAM) == MDF_CLOCK_TRIG_FALLING_EDGE))
#define IS_MDF_SITF_MODE(PARAM) (((PARAM) == MDF_SITF_LF_MASTER_SPI_MODE) || \
((PARAM) == MDF_SITF_NORMAL_SPI_MODE) || \
((PARAM) == MDF_SITF_MANCHESTER_FALLING_MODE) || \
((PARAM) == MDF_SITF_MANCHESTER_RISING_MODE))
#define IS_MDF_SITF_CLOCK_SOURCE(PARAM) (((PARAM) == MDF_SITF_CCK0_SOURCE) || \
((PARAM) == MDF_SITF_CCK1_SOURCE))
#define IS_MDF_SITF_THRESHOLD(PARAM) ((4U <= (PARAM)) && ((PARAM) <= 31U))
#define IS_MDF_CIC_MODE(PARAM) (((PARAM) == MDF_ONE_FILTER_SINC4) || \
((PARAM) == MDF_ONE_FILTER_SINC5))
#define IS_MDF_ACQUISITION_MODE(PARAM) (((PARAM) == MDF_MODE_ASYNC_CONT) || \
((PARAM) == MDF_MODE_ASYNC_SINGLE) || \
((PARAM) == MDF_MODE_SYNC_CONT) || \
((PARAM) == MDF_MODE_SYNC_SINGLE) || \
((PARAM) == MDF_MODE_WINDOW_CONT))
#define IS_MDF_DISCARD_SAMPLES(PARAM) ((PARAM) <= 255U)
#define IS_MDF_FIFO_THRESHOLD(PARAM) (((PARAM) == MDF_FIFO_THRESHOLD_NOT_EMPTY) || \
((PARAM) == MDF_FIFO_THRESHOLD_HALF_FULL))
#define IS_MDF_TRIGGER_SOURCE(PARAM) (((PARAM) == MDF_FILTER_TRIG_TRGO) || \
((PARAM) == MDF_FILTER_TRIG_EXTI15))
#define IS_MDF_TRIGGER_EDGE(PARAM) (((PARAM) == MDF_FILTER_TRIG_RISING_EDGE) || \
((PARAM) == MDF_FILTER_TRIG_FALLING_EDGE))
#define IS_MDF_DATA_SOURCE(PARAM) (((PARAM) == MDF_DATA_SOURCE_BSMX) || \
((PARAM) == MDF_DATA_SOURCE_ADCITF1) || \
((PARAM) == MDF_DATA_SOURCE_ADCITF2))
#define IS_MDF_DECIMATION_RATIO(PARAM) ((2U <= (PARAM)) && ((PARAM) <= 512U))
#define IS_MDF_GAIN(PARAM) ((-16 <= (PARAM)) && ((PARAM) <= 24))
#define IS_MDF_DELAY(PARAM) ((PARAM) <= 127U)
#define IS_MDF_RSF_DECIMATION_RATIO(PARAM) (((PARAM) == MDF_RSF_DECIMATION_RATIO_4) || \
((PARAM) == MDF_RSF_DECIMATION_RATIO_1))
#define IS_MDF_HPF_CUTOFF_FREQ(PARAM) (((PARAM) == MDF_HPF_CUTOFF_0_000625FPCM) || \
((PARAM) == MDF_HPF_CUTOFF_0_00125FPCM) || \
((PARAM) == MDF_HPF_CUTOFF_0_0025FPCM) || \
((PARAM) == MDF_HPF_CUTOFF_0_0095FPCM))
#define IS_MDF_SAD_MODE(PARAM) (((PARAM) == MDF_SAD_VOICE_ACTIVITY_DETECTOR) || \
((PARAM) == MDF_SAD_SOUND_DETECTOR) || \
((PARAM) == MDF_SAD_AMBIENT_NOISE_DETECTOR))
#define IS_MDF_SAD_FRAME_SIZE(PARAM) (((PARAM) == MDF_SAD_8_PCM_SAMPLES) || \
((PARAM) == MDF_SAD_16_PCM_SAMPLES) || \
((PARAM) == MDF_SAD_32_PCM_SAMPLES) || \
((PARAM) == MDF_SAD_64_PCM_SAMPLES) || \
((PARAM) == MDF_SAD_128_PCM_SAMPLES) || \
((PARAM) == MDF_SAD_256_PCM_SAMPLES) || \
((PARAM) == MDF_SAD_512_PCM_SAMPLES))
#define IS_MDF_SAD_SOUND_TRIGGER(PARAM) (((PARAM) == MDF_SAD_ENTER_DETECT) || \
((PARAM) == MDF_SAD_ENTER_EXIT_DETECT))
#define IS_MDF_SAD_DATA_MEMORY_TRANSFER(PARAM) (((PARAM) == MDF_SAD_NO_MEMORY_TRANSFER) || \
((PARAM) == MDF_SAD_MEMORY_TRANSFER_IN_DETECT) || \
((PARAM) == MDF_SAD_MEMORY_TRANSFER_ALWAYS))
#define IS_MDF_SAD_MIN_NOISE_LEVEL(PARAM) ((PARAM) <= 8191U)
#define IS_MDF_SAD_HANGOVER_WINDOW(PARAM) (((PARAM) == MDF_SAD_HANGOVER_4_FRAMES) || \
((PARAM) == MDF_SAD_HANGOVER_8_FRAMES) || \
((PARAM) == MDF_SAD_HANGOVER_16_FRAMES) || \
((PARAM) == MDF_SAD_HANGOVER_32_FRAMES) || \
((PARAM) == MDF_SAD_HANGOVER_64_FRAMES) || \
((PARAM) == MDF_SAD_HANGOVER_128_FRAMES) || \
((PARAM) == MDF_SAD_HANGOVER_256_FRAMES) || \
((PARAM) == MDF_SAD_HANGOVER_512_FRAMES))
#define IS_MDF_SAD_LEARNING_FRAMES(PARAM) (((PARAM) == MDF_SAD_LEARNING_2_FRAMES) || \
((PARAM) == MDF_SAD_LEARNING_4_FRAMES) || \
((PARAM) == MDF_SAD_LEARNING_8_FRAMES) || \
((PARAM) == MDF_SAD_LEARNING_16_FRAMES) || \
((PARAM) == MDF_SAD_LEARNING_32_FRAMES))
#define IS_MDF_SAD_AMBIENT_NOISE_SLOPE(PARAM) ((PARAM) <= 7U)
#define IS_MDF_SAD_SIGNAL_NOISE_THRESHOLD(PARAM) (((PARAM) == MDF_SAD_SIGNAL_NOISE_3_5DB) || \
((PARAM) == MDF_SAD_SIGNAL_NOISE_6DB) || \
((PARAM) == MDF_SAD_SIGNAL_NOISE_9_5DB) || \
((PARAM) == MDF_SAD_SIGNAL_NOISE_12DB) || \
((PARAM) == MDF_SAD_SIGNAL_NOISE_15_6DB) || \
((PARAM) == MDF_SAD_SIGNAL_NOISE_18DB) || \
((PARAM) == MDF_SAD_SIGNAL_NOISE_21_6DB) || \
((PARAM) == MDF_SAD_SIGNAL_NOISE_24_1DB) || \
((PARAM) == MDF_SAD_SIGNAL_NOISE_27_6DB) || \
((PARAM) == MDF_SAD_SIGNAL_NOISE_30_1DB))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H7RSxx_HAL_MDF_H */
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_pwr.h
+589
View File
@@ -0,0 +1,589 @@
/**
******************************************************************************
* @file stm32h7rsxx_hal_pwr.h
* @author MCD Application Team
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7RSxx_HAL_PWR_H
#define STM32H7RSxx_HAL_PWR_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal_def.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @addtogroup PWR
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup PWR_Exported_Types PWR Exported Types
* @{
*/
/**
* @brief PWR PVD configuration structure definition
*/
typedef struct
{
uint32_t PVDLevel; /*!< Specifies the PVD detection level.
This parameter can be a value of
@ref PWR_PVD_Detection_Level. */
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref PWR_PVD_Mode. */
} PWR_PVDTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PWR_Exported_Constants PWR Exported Constants
* @{
*/
/** @defgroup PWR_WakeUp_Pins PWR Wake-Up Pins
* @{
*/
/* High level and No pull (default configuration) */
#define PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4 /*!< Wakeup pin 4 (with high level polarity) */
#define PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3 /*!< Wakeup pin 3 (with high level polarity) */
#define PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2 /*!< Wakeup pin 2 (with high level polarity) */
#define PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1 /*!< Wakeup pin 1 (with high level polarity) */
/* High level and No pull */
#define PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN4 /*!< Wakeup pin 4 (with high level polarity) */
#define PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN3 /*!< Wakeup pin 3 (with high level polarity) */
#define PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN2 /*!< Wakeup pin 2 (with high level polarity) */
#define PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN1 /*!< Wakeup pin 1 (with high level polarity) */
/* Low level and No pull */
#define PWR_WAKEUP_PIN4_LOW (PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4) /*!< Wakeup pin 4 (with low level polarity) */
#define PWR_WAKEUP_PIN3_LOW (PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3) /*!< Wakeup pin 3 (with low level polarity) */
#define PWR_WAKEUP_PIN2_LOW (PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2) /*!< Wakeup pin 2 (with low level polarity) */
#define PWR_WAKEUP_PIN1_LOW (PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1) /*!< Wakeup pin 1 (with low level polarity) */
/**
* @}
*/
/** @defgroup PWR_PVD_Detection_Level PWR PVD detection level
* @{
*/
#define PWR_PVDLEVEL_1 (0x00000000U) /*!< Programmable voltage detector level 1 selection : 1V95 */
#define PWR_PVDLEVEL_2 PWR_CR1_PLS_0 /*!< Programmable voltage detector level 2 selection : 2V1 */
#define PWR_PVDLEVEL_3 PWR_CR1_PLS_1 /*!< Programmable voltage detector level 3 selection : 2V25 */
#define PWR_PVDLEVEL_4 (PWR_CR1_PLS_1 | PWR_CR1_PLS_0) /*!< Programmable voltage detector level 4 selection : 2V4 */
#define PWR_PVDLEVEL_5 PWR_CR1_PLS_2 /*!< Programmable voltage detector level 5 selection : 2V55 */
#define PWR_PVDLEVEL_6 (PWR_CR1_PLS_2 | PWR_CR1_PLS_0) /*!< Programmable voltage detector level 6 selection : 2V7 */
#define PWR_PVDLEVEL_7 (PWR_CR1_PLS_2 | PWR_CR1_PLS_1) /*!< Programmable voltage detector level 7 selection : 2V85 */
#define PWR_PVDLEVEL_EXT_VOL (PWR_CR1_PLS_2 | PWR_CR1_PLS_1 | PWR_CR1_PLS_0) /*!< External input analog voltage (Compare internally to VREF) */
/**
* @}
*/
/** @defgroup PWR_PVD_Mode PWR PVD Mode
* @{
*/
#define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< Basic mode is used */
#define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< Interrupt Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< Interrupt Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< Interrupt Mode with Rising/Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
/** @defgroup PWR_Regulator_state_in_LP_mode PWR Regulator state in SLEEP/STOP mode
* @{
*/
/* define for interface compatibility purpose */
#define PWR_MAINREGULATOR_ON (0x0U)
/**
* @}
*/
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
* @{
*/
#define PWR_SLEEPENTRY_WFI (0x01U)
#define PWR_SLEEPENTRY_WFE (0x02U)
#define PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR (0x03U)
/**
* @}
*/
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
* @{
*/
#define PWR_STOPENTRY_WFI (0x01U)
#define PWR_STOPENTRY_WFE (0x02U)
#define PWR_STOPENTRY_WFE_NO_EVT_CLEAR (0x03U)
/**
* @}
*/
/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
* @{
*/
#define PWR_REGULATOR_VOLTAGE_SCALE0 PWR_CSR4_VOS /*!< Voltage scaling range 0 (highest frequency) */
#define PWR_REGULATOR_VOLTAGE_SCALE1 (0U) /*!< Voltage scaling range 1 (lowest power) */
/**
* @}
*/
/** @defgroup PWR_Flag PWR Status Flags
* Elements values convention: 0000 0XXX XXXY YYYYb
* - Y YYYY : Flag position in the XXX register (5 bits)
* - XXX XXX : Status register (6 bits)
* - 000001: SR1 register
* - 000010: CSR1 register
* - 000100: CSR2 register
* - 001000: CSR3 register
* - 010000: CSR4 register
* - 100000: WKUPCR register
* The only exception is PWR_FLAG_WU, encompassing all
* wake-up flags and set to PWR_SR1_WUF.
* @{
*/
/* SR1 */
#define PWR_FLAG_AVDO (0x002DU) /*!< Analog voltage detector output on VDDA */
#define PWR_FLAG_PVDO (0x0024U) /*!< Programmable voltage detect output */
#define PWR_FLAG_ACTVOSRDY (0x0021U) /*!< Voltage levels ready bit for currently used ACTVOS and SDHILEVEL */
#define PWR_FLAG_ACTVOS (0x0020U) /*!< Programmable voltage detect output */
/* CSR1 */
#define PWR_FLAG_TEMPH (0x0057U) /*!< Temperature level monitoring versus high threshold */
#define PWR_FLAG_TEMPL (0x0056U) /*!< Temperature level monitoring versus low threshold */
#define PWR_FLAG_VBATH (0x0055U) /*!< VBAT level monitoring versus high threshold */
#define PWR_FLAG_VBATL (0x0054U) /*!< VBAT level monitoring versus low threshold */
#define PWR_FLAG_BRRDY (0x0050U) /*!< Backup regulator ready */
/* CSR2 */
#define PWR_FLAG_USB33RDY (0x009AU) /*!< USB supply ready */
#define PWR_FLAG_SDEXTRDY (0x0090U) /*!< SMPS step-down converter external supply ready */
/* CSR3 */
#define PWR_FLAG_SBF (0x0109U) /*!< System Standby flag */
#define PWR_FLAG_STOPF (0x0108U) /*!< System Stop flag */
/* CSR4 */
#define PWR_FLAG_VOSRDY (0x0201U) /*!< VOS Ready bit for VCORE voltage scaling output selection */
/* WKUPCR & WKUPFR */
#define PWR_FLAG_WUF1 (0x0400U) /*!< Wakeup event on wakeup pin 1 */
#define PWR_FLAG_WUF2 (0x0401U) /*!< Wakeup event on wakeup pin 2 */
#define PWR_FLAG_WUF3 (0x0402U) /*!< Wakeup event on wakeup pin 3 */
#define PWR_FLAG_WUF4 (0x0403U) /*!< Wakeup event on wakeup pin 4 */
#define PWR_FLAG_WUF_ALL (0x0404U) /*!< Wakeup flag all */
/**
* @}
*/
/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask
* @{
*/
#define PWR_EWUP_MASK (0x00FF0F0FU)
/**
* @}
*/
/** @defgroup PWR_Flag_WUP PWR Flag WakeUp
* @{
*/
#define PWR_FLAG_WKUP1 PWR_WKUPCR_WKUPC1
#define PWR_FLAG_WKUP2 PWR_WKUPCR_WKUPC2
#define PWR_FLAG_WKUP3 PWR_WKUPCR_WKUPC3
#define PWR_FLAG_WKUP4 PWR_WKUPCR_WKUPC4
#define PWR_FLAG_WKUP PWR_WKUPCR_WKUPC
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup PWR_Exported_Macro PWR Exported Macro
* @{
*/
/** @brief Check whether or not a specific PWR flag is set.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg PWR_FLAG_ACTVOS: This flag indicates that the regulator voltage
* scaling output selection is ready.
* @arg PWR_FLAG_ACTVOSRDY: This flag indicates that the regulator voltage
* scaling output selection is ready.
* @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD
* is enabled by the HAL_PWR_EnablePVD()function.
* The PVD is stopped by STANDBY mode. For this reason,
* this bit is equal to 0 after STANDBY or reset until the
* PVDE bit is set.
* @arg PWR_FLAG_AVDO: AVD Output. This flag is valid only if AVD is enabled
* by the HAL_PWREx_EnableAVD() function. The AVD is stopped by Standby mode.
* For this reason, this bit is equal to 0 after Standby or reset
* until the AVDE bit is set.
* @arg PWR_FLAG_BRRDY : Backup regulator ready flag. This bit is not reset
* when the device wakes up from Standby mode or by a system reset
* or power reset.
* @arg PWR_FLAG_VBATL: This flag indicates if the VBAT level is above
* the low monitoring threshold.
* @arg PWR_FLAG_VBATH: This flag indicates if the VBAT level is above
* the high monitoring threshold.
* @arg PWR_FLAG_TEMPL This flag indicates if the temperature level is above
* the low monitoring threshold.
* @arg PWR_FLAG_TEMPH: This flag indicates if the temperature level is above
* the high monitoring threshold.
* @arg PWR_FLAG_SDEXTRDY: This flag indicates if the external supply
* from the SMPS step-down converter is ready.
* @arg PWR_FLAG_USB33RDY: This flag indicates if the USB supply is ready.
* @arg PWR_FLAG_STOPF: STOP mode flag
* @arg PWR_FLAG_SBF: Standby mode flag
* @arg PWR_FLAG_VOSRDY When an internal regulator is used, this bit indicates
* that all the features allowed by the selected VOS can be used.
* @arg PWR_FLAG_WUF1: This flag indicates a wakeup event was
* received from WKUP1 pin.
* @arg PWR_FLAG_WUF2: This flag indicates a wakeup event was
* received from WKUP2 pin.
* @arg PWR_FLAG_WUF3: This flag indicates a wakeup event was
* received from WKUP3 pin.
* @arg PWR_FLAG_WUF4: This flag indicates a wakeup event was
* received from WKUP4 pin.
* @retval The (__FLAG__) state (TRUE or FALSE).
*/
#define __HAL_PWR_GET_FLAG(__FLAG__) ( \
((__FLAG__) == PWR_FLAG_ACTVOS) ? ((PWR->SR1 & PWR_SR1_ACTVOS) == PWR_SR1_ACTVOS) : \
((__FLAG__) == PWR_FLAG_ACTVOSRDY)? ((PWR->SR1 & PWR_SR1_ACTVOSRDY) == PWR_SR1_ACTVOSRDY) : \
((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->SR1 & PWR_SR1_PVDO) == PWR_SR1_PVDO) : \
((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->SR1 & PWR_SR1_AVDO) == PWR_SR1_AVDO) : \
((__FLAG__) == PWR_FLAG_BRRDY) ? ((PWR->CSR1 & PWR_CSR1_BRRDY) == PWR_CSR1_BRRDY) : \
((__FLAG__) == PWR_FLAG_VBATL) ? ((PWR->CSR1 & PWR_CSR1_VBATL) == PWR_CSR1_VBATL) : \
((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CSR1 & PWR_CSR1_VBATH) == PWR_CSR1_VBATH) : \
((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CSR1 & PWR_CSR1_TEMPL) == PWR_CSR1_TEMPL) : \
((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CSR1 & PWR_CSR1_TEMPH) == PWR_CSR1_TEMPH) : \
((__FLAG__) == PWR_FLAG_SDEXTRDY) ? ((PWR->CSR2 & PWR_CSR2_SDEXTRDY) == PWR_CSR2_SDEXTRDY) : \
((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CSR2 & PWR_CSR2_USB33RDY) == PWR_CSR2_USB33RDY) : \
((__FLAG__) == PWR_FLAG_STOPF) ? ((PWR->CSR3 & PWR_CSR3_STOPF) == PWR_CSR3_STOPF) : \
((__FLAG__) == PWR_FLAG_SBF) ? ((PWR->CSR3 & PWR_CSR3_SBF) == PWR_CSR3_SBF) : \
((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->CSR4 & PWR_CSR4_VOSRDY) == PWR_CSR4_VOSRDY) : \
((__FLAG__) == PWR_FLAG_WUF1) ? ((PWR->WKUPFR & PWR_WKUPFR_WKUPF1) == PWR_WKUPFR_WKUPF1) : \
((__FLAG__) == PWR_FLAG_WUF2) ? ((PWR->WKUPFR & PWR_WKUPFR_WKUPF2) == PWR_WKUPFR_WKUPF2) : \
((__FLAG__) == PWR_FLAG_WUF3) ? ((PWR->WKUPFR & PWR_WKUPFR_WKUPF3) == PWR_WKUPFR_WKUPF3) : \
((PWR->WKUPFR & PWR_WKUPFR_WKUPF4) == PWR_WKUPFR_WKUPF4))
/** @brief Clear PWR flags.
* @param __FLAG__: specifies the flag to clear.
* This parameter can be one of the following values:
* @arg PWR_FLAG_STOPF : Stop flag.
* Indicates that the device was resumed from Stop mode.
* @arg PWR_FLAG_SBF : Standby flag.
* Indicates that the device was resumed from Standby mode.
* @arg PWR_FLAG_WUF1 : Wakeup flag 1.
* Indicates that a wakeup event was received from the WKUP line 1.
* @arg PWR_FLAG_WUF2 : Wakeup flag 2.
* Indicates that a wakeup event was received from the WKUP line 2.
* @arg PWR_FLAG_WUF3 : Wakeup flag 3.
* Indicates that a wakeup event was received from the WKUP line 3.
* @arg PWR_FLAG_WUF4 : Wakeup flag 4.
* Indicates that a wakeup event was received from the WKUP line 4.
* @arg PWR_FLAG_WUF_ALL: All Wakeup flags.
* @retval None.
*/
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( \
((__FLAG__) == PWR_FLAG_STOPF) ? (SET_BIT(PWR->CSR3, PWR_CSR3_CSSF)) : \
((__FLAG__) == PWR_FLAG_SBF) ? (SET_BIT(PWR->CSR3, PWR_CSR3_CSSF)) : \
((__FLAG__) == PWR_FLAG_WUF1) ? (SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC1)) : \
((__FLAG__) == PWR_FLAG_WUF2) ? (SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC2)) : \
((__FLAG__) == PWR_FLAG_WUF3) ? (SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC3)) : \
((__FLAG__) == PWR_FLAG_WUF4) ? (SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC4)) : \
(SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC)))
/** @brief Check PWR wake up flags are set or not.
* @param __FLAG__: specifies the wake up flag to check.
* This parameter can be one of the following values:
* @arg PWR_FLAG_WKUP1 : This parameter gets Wake up line 1 flag.
* @arg PWR_FLAG_WKUP2 : This parameter gets Wake up line 2 flag.
* @arg PWR_FLAG_WKUP3 : This parameter gets Wake up line 3 flag.
* @arg PWR_FLAG_WKUP4 : This parameter gets Wake up line 4 flag.
* @arg PWR_FLAG_WKUP : This parameter gets Wake up lines 1 to 4 flags.
* @retval The (__FLAG__) state (TRUE or FALSE).
*/
#define __HAL_PWR_GET_WAKEUPFLAG(__FLAG__) ((PWR->WKUPFR & (__FLAG__)) ? 0 : 1)
/** @brief Clear CPU PWR wake up flags.
* @param __FLAG__ : Specifies the wake up flag to be cleared.
* This parameter can be one of the following values :
* @arg PWR_FLAG_WKUP1 : This parameter clears Wake up line 1 flag.
* @arg PWR_FLAG_WKUP2 : This parameter clears Wake up line 2 flag.
* @arg PWR_FLAG_WKUP3 : This parameter clears Wake up line 3 flag.
* @arg PWR_FLAG_WKUP4 : This parameter clears Wake up line 4 flag.
* @arg PWR_FLAG_WKUP : This parameter clears Wake up lines 1 to 4 flags.
* @retval None.
*/
#define __HAL_PWR_CLEAR_WAKEUPFLAG(__FLAG__) SET_BIT(PWR->WKUPCR, (__FLAG__))
/**
* @brief Enable the PVD Extended Interrupt Line.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
/**
* @brief Disable the PVD Extended Interrupt Line.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
/**
* @brief Enable the PVD Event Line.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
/**
* @brief Disable the PVD Event Line.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
/**
* @brief Enable the PVD Extended Interrupt Rising Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
/**
* @brief Disable the PVD Extended Interrupt Rising Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
/**
* @brief Enable the PVD Extended Interrupt Falling Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
/**
* @brief Disable the PVD Extended Interrupt Falling Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
/**
* @brief Enable the PVD Extended Interrupt Rising & Falling Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
do \
{ \
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \
} while(0);
/**
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
do \
{ \
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
} while(0);
/**
* @brief Check whether the specified PVD EXTI interrupt flag is set or not.
* @retval EXTI PVD Line Status.
*/
#define __HAL_PWR_PVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)
/**
* @brief Clear the PVD EXTI flag.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD)
/**
* @brief Generates a Software interrupt on PVD EXTI line.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
/**
* @}
*/
/* Include PWR HAL Extension module */
#include "stm32h7rsxx_hal_pwr_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PWR_Exported_Functions PWR Exported Functions
* @{
*/
/** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
void HAL_PWR_DeInit(void);
void HAL_PWR_EnableBkUpAccess(void);
void HAL_PWR_DisableBkUpAccess(void);
/**
* @}
*/
/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control Functions
* @{
*/
/* Peripheral Control Functions **********************************************/
/* PVD configuration */
void HAL_PWR_ConfigPVD(const PWR_PVDTypeDef *sConfigPVD);
void HAL_PWR_EnablePVD(void);
void HAL_PWR_DisablePVD(void);
/* WakeUp pins configuration */
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
/* Low Power modes entry */
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
void HAL_PWR_EnterSTANDBYMode(void);
/* Cortex System Control functions *******************************************/
void HAL_PWR_EnableSleepOnExit(void);
void HAL_PWR_DisableSleepOnExit(void);
void HAL_PWR_EnableSEVOnPend(void);
void HAL_PWR_DisableSEVOnPend(void);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup PWR_Private_Constants PWR Private Constants
* @{
*/
/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
* @{
*/
#define PWR_EXTI_LINE_PVD EXTI_IMR1_IM16 /*!< External interrupt line 16 connected to the PVD EXTI Line */
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup PWR_Private_Macros PWR Private Macros
* @{
*/
/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
* @{
*/
/* Check PVD level parameter */
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_1) ||\
((LEVEL) == PWR_PVDLEVEL_2) ||\
((LEVEL) == PWR_PVDLEVEL_3) ||\
((LEVEL) == PWR_PVDLEVEL_4) ||\
((LEVEL) == PWR_PVDLEVEL_5) ||\
((LEVEL) == PWR_PVDLEVEL_6) ||\
((LEVEL) == PWR_PVDLEVEL_7) ||\
((LEVEL) == PWR_PVDLEVEL_EXT_VOL))
/* Check PVD mode parameter */
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING) ||\
((MODE) == PWR_PVD_MODE_IT_FALLING) ||\
((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\
((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\
((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\
((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) ||\
((MODE) == PWR_PVD_MODE_NORMAL))
/* Check low power regulator parameter */
#define IS_PWR_REGULATOR(REGULATOR) ((REGULATOR) == PWR_MAINREGULATOR_ON)
/* Check low power mode entry parameter */
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) ||\
((ENTRY) == PWR_SLEEPENTRY_WFE) ||\
((ENTRY) == PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR))
/* Check low power mode entry parameter */
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) ||\
((ENTRY) == PWR_STOPENTRY_WFE) ||\
((ENTRY) == PWR_STOPENTRY_WFE_NO_EVT_CLEAR))
/* Check voltage scale level parameter */
#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE0) || \
((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1))
/* Check wake up pin parameter */
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) ||\
((PIN) == PWR_WAKEUP_PIN2) ||\
((PIN) == PWR_WAKEUP_PIN3) ||\
((PIN) == PWR_WAKEUP_PIN4) ||\
((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\
((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\
((PIN) == PWR_WAKEUP_PIN3_HIGH) ||\
((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\
((PIN) == PWR_WAKEUP_PIN1_LOW) ||\
((PIN) == PWR_WAKEUP_PIN2_LOW) ||\
((PIN) == PWR_WAKEUP_PIN3_LOW) ||\
((PIN) == PWR_WAKEUP_PIN4_LOW))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* STM32H7RSxx_HAL_PWR_H */
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_pwr_ex.h
+610
View File
@@ -0,0 +1,610 @@
/**
******************************************************************************
* @file stm32h7rsxx_hal_pwr_ex.h
* @author MCD Application Team
* @brief Header file of PWR HAL Extension module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7RSxx_HAL_PWR_EX_H
#define STM32H7RSxx_HAL_PWR_EX_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal_def.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @addtogroup PWREx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup PWREx_Exported_Types PWREx Exported Types
* @{
*/
/**
* @brief PWREx AVD configuration structure definition
*/
typedef struct
{
uint32_t AVDLevel; /*!< Specifies the AVD detection level.
This parameter can be a value of @ref PWREx_AVD_detection_level */
uint32_t Mode; /*!< Specifies the EXTI operating mode for the AVD event.
This parameter can be a value of @ref PWREx_AVD_Mode. */
} PWREx_AVDTypeDef;
/**
* @brief PWREx Wakeup pin configuration structure definition
*/
typedef struct
{
uint32_t WakeUpPin; /*!< Specifies the Wake-Up pin to be enabled.
This parameter can be a value of @ref PWR_WakeUp_Pins */
uint32_t PinPolarity; /*!< Specifies the Wake-Up pin polarity.
This parameter can be a value of @ref PWREx_PIN_Polarity */
uint32_t PinPull; /*!< Specifies the Wake-Up pin pull.
This parameter can be a value of @ref PWREx_PIN_Pull */
} PWREx_WakeupPinTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
* @{
*/
/** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration
* @{
*/
#define PWR_PIN_POLARITY_HIGH (0x0U)
#define PWR_PIN_POLARITY_LOW (0x1U)
/**
* @}
*/
/** @defgroup PWREx_PIN_Pull PWREx Pin Pull configuration
* @{
*/
#define PWR_PIN_NO_PULL (0x0U)
#define PWR_PIN_PULL_UP (0x1U)
#define PWR_PIN_PULL_DOWN (0x2U)
/**
* @}
*/
/** @defgroup PWREx_Wakeup_Pins_Flags PWREx Wakeup Pins Flags.
* @{
*/
#define PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1 /*!< Wakeup flag on PA0 */
#define PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2 /*!< Wakeup flag on PA2 */
#define PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3 /*!< Wakeup flag on PC13 */
#define PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4 /*!< Wakeup flag on PC1 */
#define PWR_WAKEUP_FLAG_ALL (PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 |\
PWR_WKUPFR_WKUPF3 | PWR_WKUPFR_WKUPF4)
/**
* @}
*/
/** @defgroup PWREx_Supply_configuration PWREx Supply configuration
* @{
*/
#define PWR_LDO_SUPPLY PWR_CSR2_LDOEN /*!< Core domains are supplied from the LDO */
#define PWR_EXTERNAL_SOURCE_SUPPLY PWR_CSR2_BYPASS /*!< The SMPS disabled and the LDO Bypass. The Core domains are supplied from an external source */
#define PWR_DIRECT_SMPS_SUPPLY PWR_CSR2_SDEN /*!< Core domains are supplied from the SMPS only */
#define PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CSR2_SDHILEVEL | PWR_CSR2_SDEN | PWR_CSR2_LDOEN) /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains */
#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CSR2_SDHILEVEL | PWR_CSR2_SMPSEXTHP | PWR_CSR2_SDEN | PWR_CSR2_LDOEN) /*!< The SMPS 1.8V output supplies external circuits and the LDO. The Core domains are supplied from the LDO */
#define PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CSR2_SDHILEVEL | PWR_CSR2_SMPSEXTHP | PWR_CSR2_SDEN | PWR_CSR2_BYPASS) /*!< The SMPS 1.8V output supplies external source which supplies the Core domains */
#define PWR_SUPPLY_CONFIG_MASK (PWR_CSR2_SDHILEVEL | PWR_CSR2_SMPSEXTHP | \
PWR_CSR2_SDEN | PWR_CSR2_LDOEN | PWR_CSR2_BYPASS)
/**
* @}
*/
/** @defgroup PWREx_AVD_detection_level PWREx AVD detection level
* @{
*/
#define PWR_AVDLEVEL_1 (0x0U) /*!< Analog voltage detector level 1 : 1V7 */
#define PWR_AVDLEVEL_2 PWR_CR1_ALS_0 /*!< Analog voltage detector level 2 : 2V1 */
#define PWR_AVDLEVEL_3 PWR_CR1_ALS_1 /*!< Analog voltage detector level 3 : 2V5 */
#define PWR_AVDLEVEL_4 (PWR_CR1_ALS_1 | PWR_CR1_ALS_0) /*!< Analog voltage detector level 4 : 2V8 */
/**
* @}
*/
/** @defgroup PWREx_AVD_Mode PWREx AVD Mode
* @{
*/
#define PWR_AVD_MODE_NORMAL (0x00000000U) /*!< Basic mode is used */
#define PWR_AVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */
#define PWR_AVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */
#define PWR_AVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define PWR_AVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */
#define PWR_AVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */
#define PWR_AVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale
* @{
*/
#define PWR_REGULATOR_STOP_VOLTAGE_SCALE3 PWR_CR1_SVOS /*!< System Stop mode voltage scaling range 3 (highest frequency) */
#define PWR_REGULATOR_STOP_VOLTAGE_SCALE5 (0x0U) /*!< System Stop mode voltage scaling range 5 (lowest power) */
/**
* @}
*/
/** @defgroup PWREx_VBAT_Battery_Charging_Resistor PWR battery charging resistor selection
* @{
*/
#define PWR_BATTERY_CHARGING_RESISTOR_5 (0x0U) /*!< VBAT charging through a 5 kOhms resistor */
#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CSR2_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */
/**
* @}
*/
/** @defgroup PWREx_VBAT_Thresholds PWREx VBAT Thresholds
* @{
*/
#define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD (0x0U)
#define PWR_VBAT_BELOW_LOW_THRESHOLD PWR_CSR1_VBATL
#define PWR_VBAT_ABOVE_HIGH_THRESHOLD PWR_CSR1_VBATH
/**
* @}
*/
/** @defgroup PWREx_TEMP_Thresholds PWREx Temperature Thresholds
* @{
*/
#define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD (0x00000000U)
#define PWR_TEMP_BELOW_LOW_THRESHOLD PWR_CSR1_TEMPL
#define PWR_TEMP_ABOVE_HIGH_THRESHOLD PWR_CSR1_TEMPH
/**
* @}
*/
/** @defgroup PWREx_CAPACITOR_Port PWREx Capacitor Port
* @{
*/
#define PWR_CAPACITOR_PORT1 PWR_CSR2_XSPICAP1
#define PWR_CAPACITOR_PORT2 PWR_CSR2_XSPICAP2
/**
* @}
*/
/** @defgroup PWREx_CAPACITOR_Value PWREx Capacitor Value
* @{
*/
#define PWR_CAPACITOR_OFF (0x0U)
#define PWR_CAPACITOR_ONE_THIRD_CAPACITANCE PWR_CSR2_XSPICAP1_0
#define PWR_CAPACITOR_TWO_THIRD_CAPACITANCE PWR_CSR2_XSPICAP1_1
#define PWR_CAPACITOR_FULL_CAPACITANCE PWR_CSR2_XSPICAP1
/**
* @}
*/
/** @defgroup PWREx_AVD_EXTI_Line PWREx AVD EXTI Line 16
* @{
*/
#define PWR_EXTI_LINE_AVD EXTI_IMR1_IM16 /*!< External interrupt line 16 connected to the AVD EXTI Line */
/**
* @}
*/
/** @defgroup PWREx_GPIO_PullUp_Port PWR Extended GPIO Pull-Up Port
* @{
*/
#define PWR_GPIO_PULLUP_PORT_N (0x00U) /*!< GPIO port N */
#define PWR_GPIO_PULLUP_PORT_O (0x01U) /*!< GPIO port O */
/**
* @}
*/
/** @defgroup PWREx_GPIO_PullDown_Port PWR Extended GPIO Pull-Down Port
* @{
*/
#define PWR_GPIO_PULLDOWN_PORT_N (0x00U) /*!< GPIO port N */
#define PWR_GPIO_PULLDOWN_PORT_O (0x01U) /*!< GPIO port O */
#define PWR_GPIO_PULLDOWN_PORT_P (0x02U) /*!< GPIO port P */
/**
* @}
*/
/** @defgroup PWREx_GPIO_PullUp_Pin_Mask PWR Extended GPIO Pull-Up Pin Mask
* @{
*/
#define PWR_GPIO_N_PULLUP_PIN_1 (0x0002U) /*!< GPIO N pin 1 */
#define PWR_GPIO_N_PULLUP_PIN_6 (0x0040U) /*!< GPIO N pin 6 */
#define PWR_GPIO_N_PULLUP_PIN_12 (0x1000U) /*!< GPIO N pin 12 */
#define PWR_GPIO_O_PULLUP_PIN_0 (0x0001U) /*!< GPIO O pin 0 */
#define PWR_GPIO_O_PULLUP_PIN_1 (0x0002U) /*!< GPIO O pin 1 */
#define PWR_GPIO_O_PULLUP_PIN_4 (0x0010U) /*!< GPIO O pin 4 */
/**
* @}
*/
/** @defgroup PWREx_GPIO_PullDown_Pin_Mask PWR Extended GPIO Pull-Down Pin Mask
* @{
*/
#define PWR_GPIO_N_PULLDOWN_PIN_0 (0x0001U) /*!< GPIO N pin 0 */
#define PWR_GPIO_N_PULLDOWN_PIN_1 (0x0002U) /*!< GPIO N pin 1 */
#define PWR_GPIO_N_PULLDOWN_PIN_2_5 (0x0004U) /*!< GPIO N pin 2 to 5 */
#define PWR_GPIO_N_PULLDOWN_PIN_6 (0x0040U) /*!< GPIO N pin 6 */
#define PWR_GPIO_N_PULLDOWN_PIN_8_11 (0x0100U) /*!< GPIO N pin 8 to 11 */
#define PWR_GPIO_N_PULLDOWN_PIN_12 (0x1000U) /*!< GPIO N pin 12 */
#define PWR_GPIO_O_PULLDOWN_PIN_0 (0x0001U) /*!< GPIO O pin 0 */
#define PWR_GPIO_O_PULLDOWN_PIN_1 (0x0002U) /*!< GPIO O pin 1 */
#define PWR_GPIO_O_PULLDOWN_PIN_2 (0x0004U) /*!< GPIO O pin 2 */
#define PWR_GPIO_O_PULLDOWN_PIN_3 (0x0008U) /*!< GPIO O pin 3 */
#define PWR_GPIO_O_PULLDOWN_PIN_4 (0x0010U) /*!< GPIO O pin 4 */
#define PWR_GPIO_P_PULLDOWN_PIN_0_3 (0x0001U) /*!< GPIO P pin 0 to 3 */
#define PWR_GPIO_P_PULLDOWN_PIN_4_7 (0x0010U) /*!< GPIO P pin 4 to 7 */
#define PWR_GPIO_P_PULLDOWN_PIN_8_11 (0x0100U) /*!< GPIO P pin 8 to 11 */
#define PWR_GPIO_P_PULLDOWN_PIN_12_15 (0x1000U) /*!< GPIO P pin 12 to 15 */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup PWREx_Exported_Macro PWREx Exported Macro
* @{
*/
/**
* @brief Enable the AVD EXTI Line 16.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
/**
* @brief Disable the AVD EXTI Line 16
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
/**
* @brief Enable event on AVD EXTI Line 16.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
/**
* @brief Disable event on AVD EXTI Line 16.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
/**
* @brief Enable the AVD Extended Interrupt Rising Trigger.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
/**
* @brief Disable the AVD Extended Interrupt Rising Trigger.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
/**
* @brief Enable the AVD Extended Interrupt Falling Trigger.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
/**
* @brief Disable the AVD Extended Interrupt Falling Trigger.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
/**
* @brief Enable the AVD Extended Interrupt Rising and Falling Trigger.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE(); \
__HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE(); \
} while(0);
/**
* @brief Disable the AVD Extended Interrupt Rising & Falling Trigger.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE(); \
} while(0);
/**
* @brief Check whether the specified AVD EXTI interrupt flag is set or not.
* @retval EXTI AVD Line Status.
*/
#define __HAL_PWR_AVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL)
/**
* @brief Clear the AVD EXTI flag.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_AVD)
/**
* @brief Generates a Software interrupt on AVD EXTI line.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVD)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
* @{
*/
/** @addtogroup PWREx_Exported_Functions_Group1 Power Supply Control Functions
* @{
*/
/* Power supply control functions */
HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource);
uint32_t HAL_PWREx_GetSupplyConfig(void);
/* Power voltage scaling functions */
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
uint32_t HAL_PWREx_GetVoltageRange(void);
HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling);
uint32_t HAL_PWREx_GetStopModeVoltageRange(void);
/**
* @}
*/
/** @addtogroup PWREx_Exported_Functions_Group2 Low Power Control Functions
* @{
*/
/* Flash low power control functions */
void HAL_PWREx_EnableFlashPowerDown(void);
void HAL_PWREx_DisableFlashPowerDown(void);
/* Wakeup Pins control functions */
void HAL_PWREx_EnableWakeUpPin(const PWREx_WakeupPinTypeDef *sPinParams);
void HAL_PWREx_DisableWakeUpPin(uint32_t WakeUpPin);
uint32_t HAL_PWREx_GetWakeupFlag(uint32_t WakeUpFlag);
HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag);
/* Power Wakeup PIN IRQ Handler */
void HAL_PWREx_WAKEUP_PIN_IRQHandler(void);
void HAL_PWREx_WKUP1_Callback(void);
void HAL_PWREx_WKUP2_Callback(void);
void HAL_PWREx_WKUP3_Callback(void);
void HAL_PWREx_WKUP4_Callback(void);
/**
* @}
*/
/** @addtogroup PWREx_Exported_Functions_Group3 Peripherals Control Functions
* @{
*/
/* Backup regulator control functions */
HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
/* USB regulator control functions */
void HAL_PWREx_EnableUSBReg(void);
void HAL_PWREx_DisableUSBReg(void);
HAL_StatusTypeDef HAL_PWREx_EnableUSBVoltageDetector(void);
HAL_StatusTypeDef HAL_PWREx_DisableUSBVoltageDetector(void);
void HAL_PWREx_EnableUSBHSregulator(void);
void HAL_PWREx_DisableUSBHSregulator(void);
/* USB regulator control functions */
void HAL_PWREx_EnableUCPDStandbyMode(void);
void HAL_PWREx_DisableUCPDStandbyMode(void);
void HAL_PWREx_EnableUCPDDeadBattery(void);
void HAL_PWREx_DisableUCPDDeadBattery(void);
/* Battery control functions */
void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue);
void HAL_PWREx_DisableBatteryCharging(void);
/* Analog Booster functions */
void HAL_PWREx_EnableAnalogBooster(void);
void HAL_PWREx_DisableAnalogBooster(void);
/* XSPIM_P1 functions */
void HAL_PWREx_EnableXSPIM1(void);
void HAL_PWREx_DisableXSPIM1(void);
/* XSPIM_P2 functions */
void HAL_PWREx_EnableXSPIM2(void);
void HAL_PWREx_DisableXSPIM2(void);
/* PORT capacitor control functions */
void HAL_PWREx_ConfigXSPIPortCap(uint32_t PortCapacitor, uint32_t PortCapacitorSetting);
uint32_t HAL_PWREx_GetConfigXSPIPortCap(uint32_t PortCapacitor);
/**
* @}
*/
/** @addtogroup PWREx_Exported_Functions_Group4 Power Monitoring functions
* @{
*/
/* Power VBAT/Temperature monitoring functions */
void HAL_PWREx_EnableMonitoring(void);
void HAL_PWREx_DisableMonitoring(void);
uint32_t HAL_PWREx_GetTemperatureLevel(void);
uint32_t HAL_PWREx_GetVBATLevel(void);
/* Power AVD configuration functions */
void HAL_PWREx_ConfigAVD(const PWREx_AVDTypeDef *sConfigAVD);
void HAL_PWREx_EnableAVD(void);
void HAL_PWREx_DisableAVD(void);
/* Power PVD/AVD IRQ Handler */
void HAL_PWREx_PVD_AVD_IRQHandler(void);
void HAL_PWREx_PVD_AVD_Callback(void);
/**
* @}
*/
/** @addtogroup PWREx_Exported_Functions_Group5 I/O Pull-Up Pull-Down Configuration Functions
* @{
*/
/* GPIO Pull-up Pull-down configuration functions */
void HAL_PWREx_EnablePullUpPullDownConfig(void);
void HAL_PWREx_DisablePullUpPullDownConfig(void);
/* GPIO Pull control functions */
HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin);
HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin);
HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin);
HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup PWREx_Private_Macros PWREx Private Macros
* @{
*/
/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
* @{
*/
/* Check PWR regulator configuration parameter */
#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\
((PWR_SOURCE) == PWR_DIRECT_SMPS_SUPPLY) ||\
((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_LDO) ||\
((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||\
((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT) ||\
((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))
/* Check PWR regulator configuration in STOP mode parameter */
#define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_STOP_VOLTAGE_SCALE3) ||\
((VOLTAGE) == PWR_REGULATOR_STOP_VOLTAGE_SCALE5))
/* Check wake up pin polarity parameter */
#define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) ||\
((POLARITY) == PWR_PIN_POLARITY_LOW))
/* Check wake up pin pull configuration parameter */
#define IS_PWR_WAKEUP_PIN_PULL(PULL) (((PULL) == PWR_PIN_NO_PULL) ||\
((PULL) == PWR_PIN_PULL_UP) ||\
((PULL) == PWR_PIN_PULL_DOWN))
/* Check wake up flag parameter */
#define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\
((FLAG) == PWR_WAKEUP_FLAG2) ||\
((FLAG) == PWR_WAKEUP_FLAG3) ||\
((FLAG) == PWR_WAKEUP_FLAG4) ||\
((FLAG) == PWR_WAKEUP_FLAG_ALL))
/* Check wake up flag parameter */
#define IS_PWR_AVD_LEVEL(LEVEL) (((LEVEL) == PWR_AVDLEVEL_1) ||\
((LEVEL) == PWR_AVDLEVEL_2) ||\
((LEVEL) == PWR_AVDLEVEL_3) ||\
((LEVEL) == PWR_AVDLEVEL_4))
/* Check AVD mode parameter */
#define IS_PWR_AVD_MODE(MODE) (((MODE) == PWR_AVD_MODE_IT_RISING) ||\
((MODE) == PWR_AVD_MODE_IT_FALLING) ||\
((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) ||\
((MODE) == PWR_AVD_MODE_EVENT_RISING) ||\
((MODE) == PWR_AVD_MODE_EVENT_FALLING) ||\
((MODE) == PWR_AVD_MODE_NORMAL) ||\
((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING))
/* Check resistor battery parameter */
#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
/* Check the capacitor port parameter */
#define IS_PWR_CAPACITOR(PORT) (((PORT) == PWR_CAPACITOR_PORT1) || \
((PORT) == PWR_CAPACITOR_PORT2))
/* Check the capacitor port setting parameter */
#define IS_PWR_CAPACITOR_SETTING(SETTING) (((SETTING) == PWR_CAPACITOR_OFF) || \
((SETTING) == PWR_CAPACITOR_ONE_THIRD_CAPACITANCE) || \
((SETTING) == PWR_CAPACITOR_TWO_THIRD_CAPACITANCE) || \
((SETTING) == PWR_CAPACITOR_FULL_CAPACITANCE))
/* Check GPIO Pull-Up Port parameter */
#define IS_PWR_GPIO_PULLPUP_PORT(GPIO_PORT) (((GPIO_PORT) == PWR_GPIO_PULLUP_PORT_N) ||\
((GPIO_PORT) == PWR_GPIO_PULLUP_PORT_O))
/* Check GPIO Pull-Down Port parameter */
#define IS_PWR_GPIO_PULLDOWN_PORT(GPIO_PORT) (((GPIO_PORT) == PWR_GPIO_PULLDOWN_PORT_N) ||\
((GPIO_PORT) == PWR_GPIO_PULLDOWN_PORT_O) ||\
((GPIO_PORT) == PWR_GPIO_PULLDOWN_PORT_P))
/* GPIO pin mask check macro */
#define IS_PWR_GPIO_PIN_MASK(BIT_MASK) ((((BIT_MASK) & GPIO_PIN_MASK) != 0U) && ((BIT_MASK) <= GPIO_PIN_MASK))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* STM32H7RSxx_HAL_PWR_EX_H */
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_rcc.h
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Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_rcc_ex.h
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Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_smbus.h
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/**
******************************************************************************
* @file stm32h7rsxx_hal_smbus.h
* @author MCD Application Team
* @brief Header file of SMBUS HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7RSxx_HAL_SMBUS_H
#define STM32H7RSxx_HAL_SMBUS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal_def.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @addtogroup SMBUS
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup SMBUS_Exported_Types SMBUS Exported Types
* @{
*/
/** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
* @brief SMBUS Configuration Structure definition
* @{
*/
typedef struct
{
uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value.
This parameter calculated by referring to SMBUS initialization section
in Reference manual */
uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
This parameter can be a value of @ref SMBUS_Analog_Filter */
uint32_t OwnAddress1; /*!< Specifies the first device own address.
This parameter can be a 7-bit address. */
uint32_t AddressingMode; /*!< Specifies addressing mode selected.
This parameter can be a value of @ref SMBUS_addressing_mode */
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
This parameter can be a value of @ref SMBUS_dual_addressing_mode */
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
This parameter can be a 7-bit address. */
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address
if dual addressing mode is selected
This parameter can be a value of @ref SMBUS_own_address2_masks. */
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
This parameter can be a value of @ref SMBUS_nostretch_mode */
uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected.
This parameter can be a value of @ref SMBUS_packet_error_check_mode */
uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected.
This parameter can be a value of @ref SMBUS_peripheral_mode */
uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
(Enable bits and different timeout values)
This parameter calculated by referring to SMBUS initialization section
in Reference manual */
} SMBUS_InitTypeDef;
/**
* @}
*/
/** @defgroup HAL_state_definition HAL state definition
* @brief HAL State definition
* @{
*/
#define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */
#define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */
#define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */
#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */
#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */
#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */
#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
/**
* @}
*/
/** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
* @brief SMBUS Error Code definition
* @{
*/
#define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */
#define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */
#define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */
#define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */
#define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */
#define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */
#define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */
#define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
#define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
/**
* @}
*/
/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
* @brief SMBUS handle Structure definition
* @{
*/
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
typedef struct __SMBUS_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
{
I2C_TypeDef *Instance; /*!< SMBUS registers base address */
SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */
uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */
uint16_t XferSize; /*!< SMBUS transfer size */
__IO uint16_t XferCount; /*!< SMBUS transfer counter */
__IO uint32_t XferOptions; /*!< SMBUS transfer options */
__IO uint32_t PreviousState; /*!< SMBUS communication Previous state */
HAL_LockTypeDef Lock; /*!< SMBUS locking object */
__IO uint32_t State; /*!< SMBUS communication state */
__IO uint32_t ErrorCode; /*!< SMBUS Error code */
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
/*!< SMBUS Master Tx Transfer completed callback */
void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
/*!< SMBUS Master Rx Transfer completed callback */
void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
/*!< SMBUS Slave Tx Transfer completed callback */
void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
/*!< SMBUS Slave Rx Transfer completed callback */
void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
/*!< SMBUS Listen Complete callback */
void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
/*!< SMBUS Error callback */
void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
/*!< SMBUS Slave Address Match callback */
void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
/*!< SMBUS Msp Init callback */
void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
/*!< SMBUS Msp DeInit callback */
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
} SMBUS_HandleTypeDef;
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
/**
* @brief HAL SMBUS Callback ID enumeration definition
*/
typedef enum
{
HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< SMBUS Master Tx Transfer completed callback ID */
HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< SMBUS Master Rx Transfer completed callback ID */
HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< SMBUS Slave Tx Transfer completed callback ID */
HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< SMBUS Slave Rx Transfer completed callback ID */
HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< SMBUS Listen Complete callback ID */
HAL_SMBUS_ERROR_CB_ID = 0x05U, /*!< SMBUS Error callback ID */
HAL_SMBUS_MSPINIT_CB_ID = 0x06U, /*!< SMBUS Msp Init callback ID */
HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U /*!< SMBUS Msp DeInit callback ID */
} HAL_SMBUS_CallbackIDTypeDef;
/**
* @brief HAL SMBUS Callback pointer definition
*/
typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus);
/*!< pointer to an SMBUS callback function */
typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection,
uint16_t AddrMatchCode);
/*!< pointer to an SMBUS Address Match callback function */
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
* @{
*/
/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
* @{
*/
#define SMBUS_ANALOGFILTER_ENABLE (0x00000000U)
#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
/**
* @}
*/
/** @defgroup SMBUS_addressing_mode SMBUS addressing mode
* @{
*/
#define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
/**
* @}
*/
/** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
* @{
*/
#define SMBUS_DUALADDRESS_DISABLE (0x00000000U)
#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
/**
* @}
*/
/** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks
* @{
*/
#define SMBUS_OA2_NOMASK ((uint8_t)0x00U)
#define SMBUS_OA2_MASK01 ((uint8_t)0x01U)
#define SMBUS_OA2_MASK02 ((uint8_t)0x02U)
#define SMBUS_OA2_MASK03 ((uint8_t)0x03U)
#define SMBUS_OA2_MASK04 ((uint8_t)0x04U)
#define SMBUS_OA2_MASK05 ((uint8_t)0x05U)
#define SMBUS_OA2_MASK06 ((uint8_t)0x06U)
#define SMBUS_OA2_MASK07 ((uint8_t)0x07U)
/**
* @}
*/
/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
* @{
*/
#define SMBUS_GENERALCALL_DISABLE (0x00000000U)
#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN
/**
* @}
*/
/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
* @{
*/
#define SMBUS_NOSTRETCH_DISABLE (0x00000000U)
#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
/**
* @}
*/
/** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
* @{
*/
#define SMBUS_PEC_DISABLE (0x00000000U)
#define SMBUS_PEC_ENABLE I2C_CR1_PECEN
/**
* @}
*/
/** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
* @{
*/
#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN
#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)
#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN
/**
* @}
*/
/** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
* @{
*/
#define SMBUS_SOFTEND_MODE (0x00000000U)
#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD
#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
/**
* @}
*/
/** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
* @{
*/
#define SMBUS_NO_STARTSTOP (0x00000000U)
#define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
/**
* @}
*/
/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
* @{
*/
/* List of XferOptions in usage of :
* 1- Restart condition when direction change
* 2- No Restart condition in other use cases
*/
#define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE
#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE))
#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
/* List of XferOptions in usage of :
* 1- Restart condition in all use cases (direction change or not)
*/
#define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
#define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
#define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
#define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)
/**
* @}
*/
/** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
* @brief SMBUS Interrupt definition
* Elements values convention: 0xXXXXXXXX
* - XXXXXXXX : Interrupt control mask
* @{
*/
#define SMBUS_IT_ERRI I2C_CR1_ERRIE
#define SMBUS_IT_TCI I2C_CR1_TCIE
#define SMBUS_IT_STOPI I2C_CR1_STOPIE
#define SMBUS_IT_NACKI I2C_CR1_NACKIE
#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE
#define SMBUS_IT_RXI I2C_CR1_RXIE
#define SMBUS_IT_TXI I2C_CR1_TXIE
#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | \
SMBUS_IT_NACKI | SMBUS_IT_TXI)
#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | \
SMBUS_IT_RXI)
#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)
#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
/**
* @}
*/
/** @defgroup SMBUS_Flag_definition SMBUS Flag definition
* @brief Flag definition
* Elements values convention: 0xXXXXYYYY
* - XXXXXXXX : Flag mask
* @{
*/
#define SMBUS_FLAG_TXE I2C_ISR_TXE
#define SMBUS_FLAG_TXIS I2C_ISR_TXIS
#define SMBUS_FLAG_RXNE I2C_ISR_RXNE
#define SMBUS_FLAG_ADDR I2C_ISR_ADDR
#define SMBUS_FLAG_AF I2C_ISR_NACKF
#define SMBUS_FLAG_STOPF I2C_ISR_STOPF
#define SMBUS_FLAG_TC I2C_ISR_TC
#define SMBUS_FLAG_TCR I2C_ISR_TCR
#define SMBUS_FLAG_BERR I2C_ISR_BERR
#define SMBUS_FLAG_ARLO I2C_ISR_ARLO
#define SMBUS_FLAG_OVR I2C_ISR_OVR
#define SMBUS_FLAG_PECERR I2C_ISR_PECERR
#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define SMBUS_FLAG_ALERT I2C_ISR_ALERT
#define SMBUS_FLAG_BUSY I2C_ISR_BUSY
#define SMBUS_FLAG_DIR I2C_ISR_DIR
/**
* @}
*/
/**
* @}
*/
/* Exported macros ------------------------------------------------------------*/
/** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
* @{
*/
/** @brief Reset SMBUS handle state.
* @param __HANDLE__ specifies the SMBUS Handle.
* @retval None
*/
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
/** @brief Enable the specified SMBUS interrupts.
* @param __HANDLE__ specifies the SMBUS Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable.
* This parameter can be one of the following values:
* @arg @ref SMBUS_IT_ERRI Errors interrupt enable
* @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
* @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
* @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
* @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
* @arg @ref SMBUS_IT_RXI RX interrupt enable
* @arg @ref SMBUS_IT_TXI TX interrupt enable
*
* @retval None
*/
#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
/** @brief Disable the specified SMBUS interrupts.
* @param __HANDLE__ specifies the SMBUS Handle.
* @param __INTERRUPT__ specifies the interrupt source to disable.
* This parameter can be one of the following values:
* @arg @ref SMBUS_IT_ERRI Errors interrupt enable
* @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
* @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
* @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
* @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
* @arg @ref SMBUS_IT_RXI RX interrupt enable
* @arg @ref SMBUS_IT_TXI TX interrupt enable
*
* @retval None
*/
#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
/** @brief Check whether the specified SMBUS interrupt source is enabled or not.
* @param __HANDLE__ specifies the SMBUS Handle.
* @param __INTERRUPT__ specifies the SMBUS interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref SMBUS_IT_ERRI Errors interrupt enable
* @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
* @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
* @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
* @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
* @arg @ref SMBUS_IT_RXI RX interrupt enable
* @arg @ref SMBUS_IT_TXI TX interrupt enable
*
* @retval The new state of __IT__ (SET or RESET).
*/
#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified SMBUS flag is set or not.
* @param __HANDLE__ specifies the SMBUS Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref SMBUS_FLAG_TXE Transmit data register empty
* @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status
* @arg @ref SMBUS_FLAG_RXNE Receive data register not empty
* @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
* @arg @ref SMBUS_FLAG_AF NACK received flag
* @arg @ref SMBUS_FLAG_STOPF STOP detection flag
* @arg @ref SMBUS_FLAG_TC Transfer complete (master mode)
* @arg @ref SMBUS_FLAG_TCR Transfer complete reload
* @arg @ref SMBUS_FLAG_BERR Bus error
* @arg @ref SMBUS_FLAG_ARLO Arbitration lost
* @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
* @arg @ref SMBUS_FLAG_PECERR PEC error in reception
* @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref SMBUS_FLAG_ALERT SMBus alert
* @arg @ref SMBUS_FLAG_BUSY Bus busy
* @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode)
*
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define SMBUS_FLAG_MASK (0x0001FFFFU)
#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \
(((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
/** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
* @param __HANDLE__ specifies the SMBUS Handle.
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg @ref SMBUS_FLAG_TXE Transmit data register empty
* @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
* @arg @ref SMBUS_FLAG_AF NACK received flag
* @arg @ref SMBUS_FLAG_STOPF STOP detection flag
* @arg @ref SMBUS_FLAG_BERR Bus error
* @arg @ref SMBUS_FLAG_ARLO Arbitration lost
* @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
* @arg @ref SMBUS_FLAG_PECERR PEC error in reception
* @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref SMBUS_FLAG_ALERT SMBus alert
*
* @retval None
*/
#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == SMBUS_FLAG_TXE) ? \
((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
((__HANDLE__)->Instance->ICR = (__FLAG__)))
/** @brief Enable the specified SMBUS peripheral.
* @param __HANDLE__ specifies the SMBUS Handle.
* @retval None
*/
#define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Disable the specified SMBUS peripheral.
* @param __HANDLE__ specifies the SMBUS Handle.
* @retval None
*/
#define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
* @param __HANDLE__ specifies the SMBUS Handle.
* @retval None
*/
#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup SMBUS_Private_Macro SMBUS Private Macros
* @{
*/
#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
#define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define IS_SMBUS_ADDRESSING_MODE(MODE) ((MODE) == SMBUS_ADDRESSINGMODE_7BIT)
#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \
((MASK) == SMBUS_OA2_MASK01) || \
((MASK) == SMBUS_OA2_MASK02) || \
((MASK) == SMBUS_OA2_MASK03) || \
((MASK) == SMBUS_OA2_MASK04) || \
((MASK) == SMBUS_OA2_MASK05) || \
((MASK) == SMBUS_OA2_MASK06) || \
((MASK) == SMBUS_OA2_MASK07))
#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
((CALL) == SMBUS_GENERALCALL_ENABLE))
#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \
((PEC) == SMBUS_PEC_ENABLE))
#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
((MODE) == SMBUS_AUTOEND_MODE) || \
((MODE) == SMBUS_SOFTEND_MODE) || \
((MODE) == SMBUS_SENDPEC_MODE) || \
((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | \
SMBUS_RELOAD_MODE )))
#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \
((REQUEST) == SMBUS_GENERATE_START_READ) || \
((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
((REQUEST) == SMBUS_NO_STARTSTOP))
#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
((REQUEST) == SMBUS_FIRST_FRAME) || \
((REQUEST) == SMBUS_NEXT_FRAME) || \
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \
((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \
((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \
(uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | \
I2C_CR1_PECEN)))
#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
(uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
I2C_CR2_RD_WRN)))
#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
(~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & \
(I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \
(I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
#define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
#define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
#define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
#define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
#define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
/**
* @}
*/
/* Include SMBUS HAL Extended module */
#include "stm32h7rsxx_hal_smbus_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
* @{
*/
/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter);
HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus,
HAL_SMBUS_CallbackIDTypeDef CallbackID,
pSMBUS_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus,
HAL_SMBUS_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus,
pSMBUS_AddrCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus);
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* IO operation functions *****************************************************/
/** @addtogroup Blocking_mode_Polling Blocking mode Polling
* @{
*/
/******* Blocking mode: Polling */
HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials,
uint32_t Timeout);
/**
* @}
*/
/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
* @{
*/
/******* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
/**
* @}
*/
/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
* @{
*/
/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
/**
* @}
*/
/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
* @{
*/
/* Peripheral State and Errors functions **************************************************/
uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus);
uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus);
/**
* @}
*/
/**
* @}
*/
/* Private Functions ---------------------------------------------------------*/
/** @defgroup SMBUS_Private_Functions SMBUS Private Functions
* @{
*/
/* Private functions are defined in stm32h7rsxx_hal_smbus.c file */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H7RSxx_HAL_SMBUS_H */
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_smbus_ex.h
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/**
******************************************************************************
* @file stm32h7rsxx_hal_smbus_ex.h
* @author MCD Application Team
* @brief Header file of SMBUS HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7RSxx_HAL_SMBUS_EX_H
#define STM32H7RSxx_HAL_SMBUS_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal_def.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @addtogroup SMBUSEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SMBUSEx_Exported_Constants SMBUS Extended Exported Constants
* @{
*/
/** @defgroup SMBUSEx_FastModePlus SMBUS Extended Fast Mode Plus
* @{
*/
#define SMBUS_FASTMODEPLUS_ENABLE 0x00000000U /*!< Enable Fast Mode Plus */
#define SMBUS_FASTMODEPLUS_DISABLE 0x00000001U /*!< Disable Fast Mode Plus */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SMBUSEx_Exported_Macros SMBUS Extended Exported Macros
* @{
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions
* @{
*/
/** @addtogroup SMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions
* @{
*/
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus);
/**
* @}
*/
/** @addtogroup SMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions
* @{
*/
HAL_StatusTypeDef HAL_SMBUSEx_ConfigFastModePlus(SMBUS_HandleTypeDef *hsmbus, uint32_t FastModePlus);
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup SMBUSEx_Private_Constants SMBUS Extended Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup SMBUSEx_Private_Macro SMBUS Extended Private Macros
* @{
*/
#define IS_SMBUS_FASTMODEPLUS(__CONFIG__) (((__CONFIG__) == (SMBUS_FASTMODEPLUS_ENABLE)) || \
((__CONFIG__) == (SMBUS_FASTMODEPLUS_DISABLE)))
/**
* @}
*/
/* Private Functions ---------------------------------------------------------*/
/** @defgroup SMBUSEx_Private_Functions SMBUS Extended Private Functions
* @{
*/
/* Private functions are defined in stm32h7rsxx_hal_smbus_ex.c file */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H7RSxx_HAL_SMBUS_EX_H */
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_tim.h
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Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_tim_ex.h
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Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_uart.h
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Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_uart_ex.h
+409
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/**
******************************************************************************
* @file stm32h7rsxx_hal_uart_ex.h
* @author MCD Application Team
* @brief Header file of UART HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7RSxx_HAL_UART_EX_H
#define STM32H7RSxx_HAL_UART_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal_def.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @addtogroup UARTEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
* @{
*/
/**
* @brief UART wake up from stop mode parameters
*/
typedef struct
{
uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).
This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
be filled up. */
uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.
This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */
uint8_t Address; /*!< UART/USART node address (7-bit long max). */
} UART_WakeUpTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
* @{
*/
/** @defgroup UARTEx_Word_Length UARTEx Word Length
* @{
*/
#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */
#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */
#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */
/**
* @}
*/
/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
* @{
*/
#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */
#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */
/**
* @}
*/
/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode
* @brief UART FIFO mode
* @{
*/
#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */
/**
* @}
*/
/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level
* @brief UART TXFIFO threshold level
* @{
*/
#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TX FIFO reaches 1/8 of its depth */
#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TX FIFO reaches 1/4 of its depth */
#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TX FIFO reaches 1/2 of its depth */
#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */
#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TX FIFO reaches 7/8 of its depth */
#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty */
/**
* @}
*/
/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level
* @brief UART RXFIFO threshold level
* @{
*/
#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RX FIFO reaches 1/8 of its depth */
#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RX FIFO reaches 1/4 of its depth */
#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RX FIFO reaches 1/2 of its depth */
#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */
#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RX FIFO reaches 7/8 of its depth */
#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup UARTEx_Exported_Functions
* @{
*/
/** @addtogroup UARTEx_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
uint32_t DeassertionTime);
/**
* @}
*/
/** @addtogroup UARTEx_Exported_Functions_Group2
* @{
*/
void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart);
void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart);
/**
* @}
*/
/** @addtogroup UARTEx_Exported_Functions_Group3
* @{
*/
/* Peripheral Control functions **********************************************/
HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
uint32_t Timeout);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
#if defined(HAL_DMA_MODULE_ENABLED)
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
#endif /* HAL_DMA_MODULE_ENABLED */
HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart);
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
* @{
*/
/** @brief Report the UART clock source.
* @param __HANDLE__ specifies the UART Handle.
* @param __CLOCKSOURCE__ output variable.
* @retval UART clocking source, written in __CLOCKSOURCE__.
*/
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_PLL2Q: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2Q; \
break; \
case RCC_USART1CLKSOURCE_PLL3Q: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3Q; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if(((__HANDLE__)->Instance == USART2) || \
((__HANDLE__)->Instance == USART3) || \
((__HANDLE__)->Instance == UART4) || \
((__HANDLE__)->Instance == UART5) || \
((__HANDLE__)->Instance == UART7) || \
((__HANDLE__)->Instance == UART8)) \
{ \
switch(__HAL_RCC_GET_USART234578_SOURCE()) \
{ \
case RCC_USART234578CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART234578CLKSOURCE_PLL2Q: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2Q; \
break; \
case RCC_USART234578CLKSOURCE_PLL3Q: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3Q; \
break; \
case RCC_USART234578CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART234578CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
break; \
case RCC_USART234578CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == LPUART1) \
{ \
switch(__HAL_RCC_GET_LPUART1_SOURCE()) \
{ \
case RCC_LPUART1CLKSOURCE_PCLK4: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK4; \
break; \
case RCC_LPUART1CLKSOURCE_PLL2Q: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2Q; \
break; \
case RCC_LPUART1CLKSOURCE_PLL3Q: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3Q; \
break; \
case RCC_LPUART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_LPUART1CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
break; \
case RCC_LPUART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
/** @brief Report the UART mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.
* @note If PCE = 1, the parity bit is not included in the data extracted
* by the reception API().
* This masking operation is not carried out in the case of
* DMA transfers.
* @param __HANDLE__ specifies the UART Handle.
* @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
*/
#define UART_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x01FFU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x007FU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x007FU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x003FU ; \
} \
} \
else \
{ \
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
/**
* @brief Ensure that UART frame length is valid.
* @param __LENGTH__ UART frame length.
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
*/
#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
((__LENGTH__) == UART_WORDLENGTH_8B) || \
((__LENGTH__) == UART_WORDLENGTH_9B))
/**
* @brief Ensure that UART wake-up address length is valid.
* @param __ADDRESS__ UART wake-up address length.
* @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
*/
#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
/**
* @brief Ensure that UART TXFIFO threshold level is valid.
* @param __THRESHOLD__ UART TXFIFO threshold level.
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
*/
#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))
/**
* @brief Ensure that UART RXFIFO threshold level is valid.
* @param __THRESHOLD__ UART RXFIFO threshold level.
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
*/
#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H7RSxx_HAL_UART_EX_H */
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_xspi.h
+1275
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File diff suppressed because it is too large. Load diff
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_bus.h
+2734
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File diff suppressed because it is too large. Load diff
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_cortex.h
+714
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@@ -0,0 +1,714 @@
/**
******************************************************************************
* @file stm32h7rsxx_ll_cortex.h
* @author MCD Application Team
* @brief Header file of CORTEX LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The LL CORTEX driver contains a set of generic APIs that can be
used by user:
(+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
functions
(+) Low power mode configuration (SCB register of Cortex-MCU)
(+) API to access to MCU info (CPUID register)
(+) API to enable fault handler (SHCSR accesses)
(+) API to enable and disable the MPU
(+) API to configure the region of MPU
(+) API to configure the attributes region of MPU
@endverbatim
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7RSxx_LL_CORTEX_H
#define STM32H7RSxx_LL_CORTEX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx.h"
/** @addtogroup STM32H7RSxx_LL_Driver
* @{
*/
/** @defgroup CORTEX_LL CORTEX
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CORTEX_LL_Exported_Constants CORTEX LL Exported Constants
* @{
*/
/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK CORTEX LL SYSTICK Clock Source
* @{
*/
#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0U /*!< AHB clock divided by 8 selected as SysTick
clock source */
#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick
clock source */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_FAULT CORTEX LL Handler Fault type
* @{
*/
#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF CORTEX LL MPU HFNMI and PRIVILEGED Access control
* @{
*/
#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U /*!< Disable NMI and privileged SW access */
#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_REGION CORTEX LL MPU Region Number
* @{
*/
#define LL_MPU_REGION_NUMBER0 0U /*!< REGION Number 0 */
#define LL_MPU_REGION_NUMBER1 1U /*!< REGION Number 1 */
#define LL_MPU_REGION_NUMBER2 2U /*!< REGION Number 2 */
#define LL_MPU_REGION_NUMBER3 3U /*!< REGION Number 3 */
#define LL_MPU_REGION_NUMBER4 4U /*!< REGION Number 4 */
#define LL_MPU_REGION_NUMBER5 5U /*!< REGION Number 5 */
#define LL_MPU_REGION_NUMBER6 6U /*!< REGION Number 6 */
#define LL_MPU_REGION_NUMBER7 7U /*!< REGION Number 7 */
#define LL_MPU_REGION_NUMBER8 8U /*!< REGION Number 8 */
#define LL_MPU_REGION_NUMBER9 9U /*!< REGION Number 9 */
#define LL_MPU_REGION_NUMBER10 10U /*!< REGION Number 10 */
#define LL_MPU_REGION_NUMBER11 11U /*!< REGION Number 11 */
#define LL_MPU_REGION_NUMBER12 12U /*!< REGION Number 12 */
#define LL_MPU_REGION_NUMBER13 13U /*!< REGION Number 13 */
#define LL_MPU_REGION_NUMBER14 14U /*!< REGION Number 14 */
#define LL_MPU_REGION_NUMBER15 15U /*!< REGION Number 15 */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_REGION_SIZE CORTEX LL MPU Region Size
* @{
*/
#define LL_MPU_REGION_SIZE_32B (0x04UL << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_64B (0x05UL << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_128B (0x06UL << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_256B (0x07UL << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_512B (0x08UL << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_1KB (0x09UL << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_2KB (0x0AUL << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_4KB (0x0BUL << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_8KB (0x0CUL << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_16KB (0x0DUL << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_32KB (0x0EUL << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_64KB (0x0FUL << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_128KB (0x10UL << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_256KB (0x11UL << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_512KB (0x12UL << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_1MB (0x13UL << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_2MB (0x14UL << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_4MB (0x15UL << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_8MB (0x16UL << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_16MB (0x17UL << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_32MB (0x18UL << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_64MB (0x19UL << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_128MB (0x1AUL << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_256MB (0x1BUL << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_512MB (0x1CUL << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_1GB (0x1DUL << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_2GB (0x1EUL << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_4GB (0x1FUL << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES CORTEX LL MPU Region Privileges
* @{
*/
#define LL_MPU_REGION_NO_ACCESS (0U << MPU_RASR_AP_Pos) /*!< No access*/
#define LL_MPU_REGION_PRIV_RW (1U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
#define LL_MPU_REGION_PRIV_RW_URO (2U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
#define LL_MPU_REGION_FULL_ACCESS (3U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
#define LL_MPU_REGION_PRIV_RO (5U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
#define LL_MPU_REGION_PRIV_RO_URO (6U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_TEX CORTEX LL MPU TEX Level
* @{
*/
#define LL_MPU_TEX_LEVEL0 (0U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
#define LL_MPU_TEX_LEVEL1 (1U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
#define LL_MPU_TEX_LEVEL2 (2U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS CORTEX LL MPU Instruction Access
* @{
*/
#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0U /*!< Instruction fetches enabled */
#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS CORTEX LL MPU Shareable Access
* @{
*/
#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
#define LL_MPU_ACCESS_NOT_SHAREABLE 0U /*!< Not Shareable memory attribute */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS CORTEX LL MPU Cacheable Access
* @{
*/
#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
#define LL_MPU_ACCESS_NOT_CACHEABLE 0U /*!< Not Cacheable memory attribute */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS CORTEX LL MPU Bufferable Access
* @{
*/
#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
#define LL_MPU_ACCESS_NOT_BUFFERABLE 0U /*!< Not Bufferable memory attribute */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CORTEX_LL_Exported_Functions CORTEX LL Exported Functions
* @{
*/
/** @defgroup CORTEX_LL_EF_SYSTICK CORTEX LL SYSTICK
* @brief CORTEX SYSTICK LL module driver
* @{
*/
/**
* @brief This function checks if the Systick counter flag is active or not.
* @note It can be used in timeout function on application side.
* @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
{
return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
}
/**
* @brief Configures the SysTick clock source
* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
* @retval None
*/
__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
{
MODIFY_REG(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK, Source);
}
/**
* @brief Get the SysTick clock source
* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
*/
__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
{
return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
}
/**
* @brief Enable SysTick exception request
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
* @retval None
*/
__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
{
SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
}
/**
* @brief Disable SysTick exception request
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
* @retval None
*/
__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
{
CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
}
/**
* @brief Checks if the SYSTICK interrupt is enabled or disabled.
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
{
return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE CORTEX LL LOW POWER MODE
* @{
*/
/**
* @brief Processor uses sleep as its low power mode
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableSleep(void)
{
/* Clear SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
}
/**
* @brief Processor uses deep sleep as its low power mode
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
{
/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
}
/**
* @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
* @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
* empty main application.
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
{
/* Set SLEEPONEXIT bit of Cortex System Control Register */
SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
}
/**
* @brief Do not sleep when returning to Thread mode.
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
* @retval None
*/
__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
{
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
}
/**
* @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
* processor.
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
{
/* Set SEVEONPEND bit of Cortex System Control Register */
SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
}
/**
* @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
* excluded
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
* @retval None
*/
__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
{
/* Clear SEVEONPEND bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
}
/**
* @brief Clear pending events.
* @retval None
*/
__STATIC_INLINE void LL_LPM_ClearEvent(void)
{
__SEV();
__WFE();
}
/**
* @}
*/
/** @defgroup CORTEX_LL_EF_HANDLER CORTEX LL HANDLER
* @{
*/
/**
* @brief Enable a fault in System handler control register (SHCSR)
* @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_EnableFault\n
* SCB_SHCSR BUSFAULTENA LL_HANDLER_EnableFault\n
* SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
* @param Fault This parameter can be a combination of the following values:
* @arg @ref LL_HANDLER_FAULT_USG
* @arg @ref LL_HANDLER_FAULT_BUS
* @arg @ref LL_HANDLER_FAULT_MEM
* @retval None
*/
__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
{
/* Enable the system handler fault */
SET_BIT(SCB->SHCSR, Fault);
}
/**
* @brief Disable a fault in System handler control register (SHCSR)
* @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_DisableFault\n
* SCB_SHCSR BUSFAULTENA LL_HANDLER_DisableFault\n
* SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
* @param Fault This parameter can be a combination of the following values:
* @arg @ref LL_HANDLER_FAULT_USG
* @arg @ref LL_HANDLER_FAULT_BUS
* @arg @ref LL_HANDLER_FAULT_MEM
* @retval None
*/
__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
{
/* Disable the system handler fault */
CLEAR_BIT(SCB->SHCSR, Fault);
}
/**
* @}
*/
/** @defgroup CORTEX_LL_EF_MCU_INFO CORTEX LL MCU INFO
* @{
*/
/**
* @brief Get Implementer code
* @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
* @retval Value should be equal to 0x41 for ARM
*/
__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
}
/**
* @brief Get Variant number (The r value in the rnpn product revision identifier)
* @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
* @retval Value between 0 and 255 (0x0: revision 0)
*/
__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
}
/**
* @brief Get Architecture version
* @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture
* @retval Value should be equal to 0xF for Cortex-M7
*/
__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
}
/**
* @brief Get Part number
* @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
* @retval Value should be equal to 0xC27 for Cortex-M7
*/
__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
}
/**
* @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
* @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
* @retval Value between 0 and 255 (0x1: patch 1)
*/
__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
}
/**
* @}
*/
/** @defgroup CORTEX_LL_EF_MPU CORTEX LL MPU
* @{
*/
/**
* @brief Enable MPU with input options
* @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
* @param MPU_Control This parameter can be one of the following values:
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
* @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
* @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
* @retval None
*/
__STATIC_INLINE void LL_MPU_Enable(uint32_t MPU_Control)
{
__DMB(); /* Force any outstanding transfers to complete before enabling MPU */
/* Enable the MPU*/
WRITE_REG(MPU->CTRL, (MPU_Control | MPU_CTRL_ENABLE_Msk));
/* Ensure MPU settings take effects */
__DSB();
__ISB();
}
/**
* @brief Disable MPU
* @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
* @retval None
*/
__STATIC_INLINE void LL_MPU_Disable(void)
{
/* Make sure outstanding transfers are done */
__DMB();
/* Disable the MPU and clear the control register */
WRITE_REG(MPU->CTRL, 0U);
}
/**
* @brief Check if MPU is enabled or not
* @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
{
return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
}
/**
* @brief Enable a MPU region
* @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @arg @ref LL_MPU_REGION_NUMBER8
* @arg @ref LL_MPU_REGION_NUMBER9
* @arg @ref LL_MPU_REGION_NUMBER10
* @arg @ref LL_MPU_REGION_NUMBER11
* @arg @ref LL_MPU_REGION_NUMBER12
* @arg @ref LL_MPU_REGION_NUMBER13
* @arg @ref LL_MPU_REGION_NUMBER14
* @arg @ref LL_MPU_REGION_NUMBER15
* @retval None
*/
__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Enable the MPU region */
SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
}
/**
* @brief Check if MPU region is enabled or not
* @rmtoll MPU_RNR ENABLE LL_MPU_IsEnabled_Region
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @arg @ref LL_MPU_REGION_NUMBER8
* @arg @ref LL_MPU_REGION_NUMBER9
* @arg @ref LL_MPU_REGION_NUMBER10
* @arg @ref LL_MPU_REGION_NUMBER11
* @arg @ref LL_MPU_REGION_NUMBER12
* @arg @ref LL_MPU_REGION_NUMBER13
* @arg @ref LL_MPU_REGION_NUMBER14
* @arg @ref LL_MPU_REGION_NUMBER15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_MPU_IsEnabled_Region(uint32_t Region)
{
/* Set region index */
WRITE_REG(MPU->RNR, Region);
/* Return MPU region status */
return ((READ_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk) == (MPU_RASR_ENABLE_Msk)) ? 1UL : 0UL);
}
/**
* @brief Configure and enable a MPU region
* @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
* MPU_RBAR REGION LL_MPU_ConfigRegion\n
* MPU_RBAR ADDR LL_MPU_ConfigRegion\n
* MPU_RASR XN LL_MPU_ConfigRegion\n
* MPU_RASR AP LL_MPU_ConfigRegion\n
* MPU_RASR S LL_MPU_ConfigRegion\n
* MPU_RASR C LL_MPU_ConfigRegion\n
* MPU_RASR B LL_MPU_ConfigRegion\n
* MPU_RASR SIZE LL_MPU_ConfigRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @arg @ref LL_MPU_REGION_NUMBER8
* @arg @ref LL_MPU_REGION_NUMBER9
* @arg @ref LL_MPU_REGION_NUMBER10
* @arg @ref LL_MPU_REGION_NUMBER11
* @arg @ref LL_MPU_REGION_NUMBER12
* @arg @ref LL_MPU_REGION_NUMBER13
* @arg @ref LL_MPU_REGION_NUMBER14
* @arg @ref LL_MPU_REGION_NUMBER15
* @param Address Value of region base address
* @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
* @param Attributes This parameter can be a combination of the following values:
* @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B
* or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
* or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB
* or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
* or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB
* or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
* or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB
* or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
* or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB
* or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
* or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
* @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO
* or @ref LL_MPU_REGION_FULL_ACCESS or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
* @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2
* @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
* @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
* @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
* @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
* @retval None
*/
__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address,
uint32_t Attributes)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Set base address */
WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
/* Configure MPU */
WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));
}
/**
* @brief Disable a MPU region
* @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
* MPU_RASR ENABLE LL_MPU_DisableRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @arg @ref LL_MPU_REGION_NUMBER8
* @arg @ref LL_MPU_REGION_NUMBER9
* @arg @ref LL_MPU_REGION_NUMBER10
* @arg @ref LL_MPU_REGION_NUMBER11
* @arg @ref LL_MPU_REGION_NUMBER12
* @arg @ref LL_MPU_REGION_NUMBER13
* @arg @ref LL_MPU_REGION_NUMBER14
* @arg @ref LL_MPU_REGION_NUMBER15
* @retval None
*/
__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Disable the MPU region */
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H7RSxx_LL_CORTEX_H */
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_crc.h
+461
View File
@@ -0,0 +1,461 @@
/**
******************************************************************************
* @file stm32h7rsxx_ll_crc.h
* @author MCD Application Team
* @brief Header file of CRC LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7RSxx_LL_CRC_H
#define STM32H7RSxx_LL_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx.h"
/** @addtogroup STM32H7RSxx_LL_Driver
* @{
*/
#if defined(CRC)
/** @defgroup CRC_LL CRC
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
* @{
*/
/** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length
* @{
*/
#define LL_CRC_POLYLENGTH_32B 0x00000000U /*!< 32 bits Polynomial size */
#define LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< 16 bits Polynomial size */
#define LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< 8 bits Polynomial size */
#define LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0) /*!< 7 bits Polynomial size */
/**
* @}
*/
/** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse
* @{
*/
#define LL_CRC_INDATA_REVERSE_NONE 0x00000000U /*!< Input Data bit order not affected */
#define LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0 /*!< Input Data bit reversal done by byte */
#define LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1 /*!< Input Data bit reversal done by half-word */
#define LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0) /*!< Input Data bit reversal done by word */
/**
* @}
*/
/** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse
* @{
*/
#define LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U /*!< Output Data bit order not affected */
#define LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT /*!< Output Data bit reversal done by bit */
/**
* @}
*/
/** @defgroup CRC_LL_EC_Default_Polynomial_Value Default CRC generating polynomial value
* @brief Normal representation of this polynomial value is
* X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .
* @{
*/
#define LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U /*!< Default CRC generating polynomial value */
/**
* @}
*/
/** @defgroup CRC_LL_EC_Default_InitValue Default CRC computation initialization value
* @{
*/
#define LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Default CRC computation initialization value */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
* @{
*/
/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in CRC register
* @param __INSTANCE__ CRC Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
/**
* @brief Read a value in CRC register
* @param __INSTANCE__ CRC Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
* @{
*/
/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
* @{
*/
/**
* @brief Reset the CRC calculation unit.
* @note If Programmable Initial CRC value feature
* is available, also set the Data Register to the value stored in the
* CRC_INIT register, otherwise, reset Data Register to its default value.
* @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit
* @param CRCx CRC Instance
* @retval None
*/
__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
{
SET_BIT(CRCx->CR, CRC_CR_RESET);
}
/**
* @brief Configure size of the polynomial.
* @rmtoll CR POLYSIZE LL_CRC_SetPolynomialSize
* @param CRCx CRC Instance
* @param PolySize This parameter can be one of the following values:
* @arg @ref LL_CRC_POLYLENGTH_32B
* @arg @ref LL_CRC_POLYLENGTH_16B
* @arg @ref LL_CRC_POLYLENGTH_8B
* @arg @ref LL_CRC_POLYLENGTH_7B
* @retval None
*/
__STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySize)
{
MODIFY_REG(CRCx->CR, CRC_CR_POLYSIZE, PolySize);
}
/**
* @brief Return size of the polynomial.
* @rmtoll CR POLYSIZE LL_CRC_GetPolynomialSize
* @param CRCx CRC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRC_POLYLENGTH_32B
* @arg @ref LL_CRC_POLYLENGTH_16B
* @arg @ref LL_CRC_POLYLENGTH_8B
* @arg @ref LL_CRC_POLYLENGTH_7B
*/
__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE));
}
/**
* @brief Configure the reversal of the bit order of the input data
* @rmtoll CR REV_IN LL_CRC_SetInputDataReverseMode
* @param CRCx CRC Instance
* @param ReverseMode This parameter can be one of the following values:
* @arg @ref LL_CRC_INDATA_REVERSE_NONE
* @arg @ref LL_CRC_INDATA_REVERSE_BYTE
* @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
* @arg @ref LL_CRC_INDATA_REVERSE_WORD
* @retval None
*/
__STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
{
MODIFY_REG(CRCx->CR, CRC_CR_REV_IN, ReverseMode);
}
/**
* @brief Return type of reversal for input data bit order
* @rmtoll CR REV_IN LL_CRC_GetInputDataReverseMode
* @param CRCx CRC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRC_INDATA_REVERSE_NONE
* @arg @ref LL_CRC_INDATA_REVERSE_BYTE
* @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
* @arg @ref LL_CRC_INDATA_REVERSE_WORD
*/
__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN));
}
/**
* @brief Configure the reversal of the bit order of the Output data
* @rmtoll CR REV_OUT LL_CRC_SetOutputDataReverseMode
* @param CRCx CRC Instance
* @param ReverseMode This parameter can be one of the following values:
* @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
* @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
* @retval None
*/
__STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
{
MODIFY_REG(CRCx->CR, CRC_CR_REV_OUT, ReverseMode);
}
/**
* @brief Return type of reversal of the bit order of the Output data
* @rmtoll CR REV_OUT LL_CRC_GetOutputDataReverseMode
* @param CRCx CRC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
* @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
*/
__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT));
}
/**
* @brief Initialize the Programmable initial CRC value.
* @note If the CRC size is less than 32 bits, the least significant bits
* are used to write the correct value
* @note LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter.
* @rmtoll INIT INIT LL_CRC_SetInitialData
* @param CRCx CRC Instance
* @param InitCrc Value to be programmed in Programmable initial CRC value register
* @retval None
*/
__STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc)
{
WRITE_REG(CRCx->INIT, InitCrc);
}
/**
* @brief Return current Initial CRC value.
* @note If the CRC size is less than 32 bits, the least significant bits
* are used to read the correct value
* @rmtoll INIT INIT LL_CRC_GetInitialData
* @param CRCx CRC Instance
* @retval Value programmed in Programmable initial CRC value register
*/
__STATIC_INLINE uint32_t LL_CRC_GetInitialData(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->INIT));
}
/**
* @brief Initialize the Programmable polynomial value
* (coefficients of the polynomial to be used for CRC calculation).
* @note LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter.
* @note Please check Reference Manual and existing Errata Sheets,
* regarding possible limitations for Polynomial values usage.
* For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
* @rmtoll POL POL LL_CRC_SetPolynomialCoef
* @param CRCx CRC Instance
* @param PolynomCoef Value to be programmed in Programmable Polynomial value register
* @retval None
*/
__STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t PolynomCoef)
{
WRITE_REG(CRCx->POL, PolynomCoef);
}
/**
* @brief Return current Programmable polynomial value
* @note Please check Reference Manual and existing Errata Sheets,
* regarding possible limitations for Polynomial values usage.
* For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
* @rmtoll POL POL LL_CRC_GetPolynomialCoef
* @param CRCx CRC Instance
* @retval Value programmed in Programmable Polynomial value register
*/
__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->POL));
}
/**
* @}
*/
/** @defgroup CRC_LL_EF_Data_Management Data_Management
* @{
*/
/**
* @brief Write given 32-bit data to the CRC calculator
* @rmtoll DR DR LL_CRC_FeedData32
* @param CRCx CRC Instance
* @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
* @retval None
*/
__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
{
WRITE_REG(CRCx->DR, InData);
}
/**
* @brief Write given 16-bit data to the CRC calculator
* @rmtoll DR DR LL_CRC_FeedData16
* @param CRCx CRC Instance
* @param InData 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF
* @retval None
*/
__STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData)
{
__IO uint16_t *pReg;
pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR); /* Derogation MisraC2012 R.11.5 */
*pReg = InData;
}
/**
* @brief Write given 8-bit data to the CRC calculator
* @rmtoll DR DR LL_CRC_FeedData8
* @param CRCx CRC Instance
* @param InData 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData)
{
*(uint8_t __IO *)(&CRCx->DR) = (uint8_t) InData;
}
/**
* @brief Return current CRC calculation result. 32 bits value is returned.
* @rmtoll DR DR LL_CRC_ReadData32
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
*/
__STATIC_INLINE uint32_t LL_CRC_ReadData32(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->DR));
}
/**
* @brief Return current CRC calculation result. 16 bits value is returned.
* @note This function is expected to be used in a 16 bits CRC polynomial size context.
* @rmtoll DR DR LL_CRC_ReadData16
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (16 bits).
*/
__STATIC_INLINE uint16_t LL_CRC_ReadData16(const CRC_TypeDef *CRCx)
{
return (uint16_t)READ_REG(CRCx->DR);
}
/**
* @brief Return current CRC calculation result. 8 bits value is returned.
* @note This function is expected to be used in a 8 bits CRC polynomial size context.
* @rmtoll DR DR LL_CRC_ReadData8
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (8 bits).
*/
__STATIC_INLINE uint8_t LL_CRC_ReadData8(const CRC_TypeDef *CRCx)
{
return (uint8_t)READ_REG(CRCx->DR);
}
/**
* @brief Return current CRC calculation result. 7 bits value is returned.
* @note This function is expected to be used in a 7 bits CRC polynomial size context.
* @rmtoll DR DR LL_CRC_ReadData7
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (7 bits).
*/
__STATIC_INLINE uint8_t LL_CRC_ReadData7(const CRC_TypeDef *CRCx)
{
return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU);
}
/**
* @brief Return data stored in the Independent Data(IDR) register.
* @note This register can be used as a temporary storage location for one 32-bit long data.
* @rmtoll IDR IDR LL_CRC_Read_IDR
* @param CRCx CRC Instance
* @retval Value stored in CRC_IDR register (General-purpose 32-bit data register).
*/
__STATIC_INLINE uint32_t LL_CRC_Read_IDR(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->IDR));
}
/**
* @brief Store data in the Independent Data(IDR) register.
* @note This register can be used as a temporary storage location for one 32-bit long data.
* @rmtoll IDR IDR LL_CRC_Write_IDR
* @param CRCx CRC Instance
* @param InData value to be stored in CRC_IDR register (32-bit) between Min_Data=0 and Max_Data=0xFFFFFFFF
* @retval None
*/
__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
{
*((uint32_t __IO *)(&CRCx->IDR)) = (uint32_t) InData;
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(CRC) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H7RSxx_LL_CRC_H */
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_crs.h
+786
View File
@@ -0,0 +1,786 @@
/**
******************************************************************************
* @file stm32h7rsxx_ll_crs.h
* @author MCD Application Team
* @brief Header file of CRS LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7RSxx_LL_CRS_H
#define STM32H7RSxx_LL_CRS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx.h"
/** @addtogroup STM32H7RSxx_LL_Driver
* @{
*/
#if defined(CRS)
/** @defgroup CRS_LL CRS
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
* @{
*/
/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_CRS_ReadReg function
* @{
*/
#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
#define LL_CRS_ISR_ERRF CRS_ISR_ERRF
#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
/**
* @}
*/
/** @defgroup CRS_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions
* @{
*/
#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
#define LL_CRS_CR_ERRIE CRS_CR_ERRIE
#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
/**
* @}
*/
/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
* @{
*/
#define LL_CRS_SYNC_DIV_1 0x00000000U /*!< Synchro Signal not divided (default) */
#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
/**
* @}
*/
/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
* @{
*/
#define LL_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */
#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
#define LL_CRS_SYNC_SOURCE_OTG_FS CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source OTG_FS SOF (default) */
#define LL_CRS_SYNC_SOURCE_OTG_HS (CRS_CFGR_SYNCSRC_1 | CRS_CFGR_SYNCSRC_0) /*!< Synchro Signal source OTG_HS SOF */
/**
* @}
*/
/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
* @{
*/
#define LL_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */
#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
/**
* @}
*/
/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
* @{
*/
#define LL_CRS_FREQ_ERROR_DIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */
#define LL_CRS_FREQ_ERROR_DIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */
/**
* @}
*/
/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
* @{
*/
/**
* @brief Reset value of the RELOAD field
* @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
* and a synchronization signal frequency of 1 kHz (SOF signal from USB)
*/
#define LL_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU
/**
* @brief Reset value of Frequency error limit.
*/
#define LL_CRS_ERRORLIMIT_DEFAULT 0x00000022U
/**
* @brief Reset value of the HSI48 Calibration field
* @note The default value is 32, which corresponds to the middle of the trimming interval.
* The trimming step is specified in the product datasheet.
* A higher TRIM value corresponds to a higher output frequency.
*/
#define LL_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
* @{
*/
/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in CRS register
* @param __INSTANCE__ CRS Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in CRS register
* @param __INSTANCE__ CRS Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
* @{
*/
/**
* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
* @note The RELOAD value should be selected according to the ratio between
* the target frequency and the frequency of the synchronization source after
* prescaling. It is then decreased by one in order to reach the expected
* synchronization on the zero value. The formula is the following:
* RELOAD = (fTARGET / fSYNC) -1
* @param __FTARGET__ Target frequency (value in Hz)
* @param __FSYNC__ Synchronization signal frequency (value in Hz)
* @retval Reload value (in Hz)
*/
#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
* @{
*/
/** @defgroup CRS_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Enable Frequency error counter
* @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
* @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
{
SET_BIT(CRS->CR, CRS_CR_CEN);
}
/**
* @brief Disable Frequency error counter
* @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_CEN);
}
/**
* @brief Check if Frequency error counter is enabled or not
* @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL);
}
/**
* @brief Enable Automatic trimming counter
* @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
{
SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
}
/**
* @brief Disable Automatic trimming counter
* @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
}
/**
* @brief Check if Automatic trimming is enabled or not
* @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL : 0UL);
}
/**
* @brief Set HSI48 oscillator smooth trimming
* @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
* @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming
* @param Value a number between Min_Data = 0 and Max_Data = 63
* @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
{
MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);
}
/**
* @brief Get HSI48 oscillator smooth trimming
* @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming
* @retval a number between Min_Data = 0 and Max_Data = 63
*/
__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
{
return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
}
/**
* @brief Set counter reload value
* @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter
* @param Value a number between Min_Data = 0 and Max_Data = 65535 (0xFFFF)
* @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
* Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
}
/**
* @brief Get counter reload value
* @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter
* @retval a number between Min_Data = 0 and Max_Data = 65535 (0xFFFF)
*/
__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
}
/**
* @brief Set frequency error limit
* @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit
* @param Value a number between Min_Data = 0 and Max_Data = 255
* @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);
}
/**
* @brief Get frequency error limit
* @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit
* @retval A number between Min_Data = 0 and Max_Data = 255
*/
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);
}
/**
* @brief Set division factor for SYNC signal
* @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider
* @param Divider This parameter can be one of the following values:
* @arg @ref LL_CRS_SYNC_DIV_1
* @arg @ref LL_CRS_SYNC_DIV_2
* @arg @ref LL_CRS_SYNC_DIV_4
* @arg @ref LL_CRS_SYNC_DIV_8
* @arg @ref LL_CRS_SYNC_DIV_16
* @arg @ref LL_CRS_SYNC_DIV_32
* @arg @ref LL_CRS_SYNC_DIV_64
* @arg @ref LL_CRS_SYNC_DIV_128
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
}
/**
* @brief Get division factor for SYNC signal
* @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRS_SYNC_DIV_1
* @arg @ref LL_CRS_SYNC_DIV_2
* @arg @ref LL_CRS_SYNC_DIV_4
* @arg @ref LL_CRS_SYNC_DIV_8
* @arg @ref LL_CRS_SYNC_DIV_16
* @arg @ref LL_CRS_SYNC_DIV_32
* @arg @ref LL_CRS_SYNC_DIV_64
* @arg @ref LL_CRS_SYNC_DIV_128
*/
__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
}
/**
* @brief Set SYNC signal source
* @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO
* @arg @ref LL_CRS_SYNC_SOURCE_LSE
* @arg @ref LL_CRS_SYNC_SOURCE_OTG_FS
* @arg @ref LL_CRS_SYNC_SOURCE_OTG_HS
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
}
/**
* @brief Get SYNC signal source
* @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO
* @arg @ref LL_CRS_SYNC_SOURCE_LSE
* @arg @ref LL_CRS_SYNC_SOURCE_OTG_FS
* @arg @ref LL_CRS_SYNC_SOURCE_OTG_HS
*/
__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
}
/**
* @brief Set input polarity for the SYNC signal source
* @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_CRS_SYNC_POLARITY_RISING
* @arg @ref LL_CRS_SYNC_POLARITY_FALLING
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
}
/**
* @brief Get input polarity for the SYNC signal source
* @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRS_SYNC_POLARITY_RISING
* @arg @ref LL_CRS_SYNC_POLARITY_FALLING
*/
__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
}
/**
* @brief Configure CRS for the synchronization
* @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n
* CFGR RELOAD LL_CRS_ConfigSynchronization\n
* CFGR FELIM LL_CRS_ConfigSynchronization\n
* CFGR SYNCDIV LL_CRS_ConfigSynchronization\n
* CFGR SYNCSRC LL_CRS_ConfigSynchronization\n
* CFGR SYNCPOL LL_CRS_ConfigSynchronization
* @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
* @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 255
* @param ReloadValue a number between Min_Data = 0 and Max_Data = 65535 (0xFFFF)
* @param Settings This parameter can be a combination of the following values:
* @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4
* or @ref LL_CRS_SYNC_DIV_8 or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32
* or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE
* or @ref LL_CRS_SYNC_SOURCE_OTG_FS or @ref LL_CRS_SYNC_SOURCE_OTG_HS
* @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
* @retval None
*/
__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue,
uint32_t ReloadValue, uint32_t Settings)
{
MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue << CRS_CR_TRIM_Pos);
MODIFY_REG(CRS->CFGR,
CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
}
/**
* @}
*/
/** @defgroup CRS_LL_EF_CRS_Management CRS_Management
* @{
*/
/**
* @brief Generate software SYNC event
* @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
* @retval None
*/
__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
{
SET_BIT(CRS->CR, CRS_CR_SWSYNC);
}
/**
* @brief Get the frequency error direction latched in the time of the last
* SYNC event
* @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
* @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
*/
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
{
return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
}
/**
* @brief Get the frequency error counter value latched in the time of the last SYNC event
* @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture
* @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
*/
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
{
return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
}
/**
* @}
*/
/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Check if SYNC event OK signal occurred or not
* @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL : 0UL);
}
/**
* @brief Check if SYNC warning signal occurred or not
* @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL : 0UL);
}
/**
* @brief Check if Synchronization or trimming error signal occurred or not
* @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL);
}
/**
* @brief Check if Expected SYNC signal occurred or not
* @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL);
}
/**
* @brief Check if SYNC error signal occurred or not
* @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL : 0UL);
}
/**
* @brief Check if SYNC missed error signal occurred or not
* @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL : 0UL);
}
/**
* @brief Check if Trimming overflow or underflow occurred or not
* @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL : 0UL);
}
/**
* @brief Clear the SYNC event OK flag
* @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
* @retval None
*/
__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
{
WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
}
/**
* @brief Clear the SYNC warning flag
* @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
* @retval None
*/
__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
{
WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
}
/**
* @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
* the ERR flag
* @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR
* @retval None
*/
__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
{
WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
}
/**
* @brief Clear Expected SYNC flag
* @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC
* @retval None
*/
__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
{
WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
}
/**
* @}
*/
/** @defgroup CRS_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable SYNC event OK interrupt
* @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
{
SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
}
/**
* @brief Disable SYNC event OK interrupt
* @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
}
/**
* @brief Check if SYNC event OK interrupt is enabled or not
* @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL : 0UL);
}
/**
* @brief Enable SYNC warning interrupt
* @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
{
SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
}
/**
* @brief Disable SYNC warning interrupt
* @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
}
/**
* @brief Check if SYNC warning interrupt is enabled or not
* @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL : 0UL);
}
/**
* @brief Enable Synchronization or trimming error interrupt
* @rmtoll CR ERRIE LL_CRS_EnableIT_ERR
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
{
SET_BIT(CRS->CR, CRS_CR_ERRIE);
}
/**
* @brief Disable Synchronization or trimming error interrupt
* @rmtoll CR ERRIE LL_CRS_DisableIT_ERR
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
}
/**
* @brief Check if Synchronization or trimming error interrupt is enabled or not
* @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL);
}
/**
* @brief Enable Expected SYNC interrupt
* @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
{
SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
}
/**
* @brief Disable Expected SYNC interrupt
* @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
}
/**
* @brief Check if Expected SYNC interrupt is enabled or not
* @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_CRS_DeInit(void);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(CRS) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H7RSxx_LL_CRS_H */
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/**
******************************************************************************
* @file stm32h7rsxx_ll_gpio.h
* @author MCD Application Team
* @brief Header file of GPIO LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7RSxx_LL_GPIO_H
#define __STM32H7RSxx_LL_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx.h"
/** @addtogroup STM32H7RSxx_LL_Driver
* @{
*/
#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || \
defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || \
defined (GPIOM) || defined (GPION) || defined (GPIOO) || defined (GPIOP)
/** @defgroup GPIO_LL GPIO
* @{
*/
/** MISRA C:2012 deviation rule has been granted for following rules:
* Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..]
* which may be out of array bounds [..,UNKNOWN] in following APIs:
* LL_GPIO_GetAFPin_0_7
* LL_GPIO_SetAFPin_0_7
* LL_GPIO_SetAFPin_8_15
* LL_GPIO_GetAFPin_8_15
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
* @{
*/
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
* @{
*/
/**
* @brief LL GPIO Init Structure definition
*/
typedef struct
{
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_LL_EC_PIN */
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIO_LL_EC_MODE.
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
uint32_t Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIO_LL_EC_SPEED.
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
uint32_t OutputType; /*!< Specifies the operating output type for the selected pins.
This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
This parameter can be a value of @ref GPIO_LL_EC_PULL.
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins.
This parameter can be a value of @ref GPIO_LL_EC_AF.
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
} LL_GPIO_InitTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
* @{
*/
/** @defgroup GPIO_LL_EC_PIN PIN
* @{
*/
#define LL_GPIO_PIN_0 GPIO_BSRR_BS0 /*!< Select pin 0 */
#define LL_GPIO_PIN_1 GPIO_BSRR_BS1 /*!< Select pin 1 */
#define LL_GPIO_PIN_2 GPIO_BSRR_BS2 /*!< Select pin 2 */
#define LL_GPIO_PIN_3 GPIO_BSRR_BS3 /*!< Select pin 3 */
#define LL_GPIO_PIN_4 GPIO_BSRR_BS4 /*!< Select pin 4 */
#define LL_GPIO_PIN_5 GPIO_BSRR_BS5 /*!< Select pin 5 */
#define LL_GPIO_PIN_6 GPIO_BSRR_BS6 /*!< Select pin 6 */
#define LL_GPIO_PIN_7 GPIO_BSRR_BS7 /*!< Select pin 7 */
#define LL_GPIO_PIN_8 GPIO_BSRR_BS8 /*!< Select pin 8 */
#define LL_GPIO_PIN_9 GPIO_BSRR_BS9 /*!< Select pin 9 */
#define LL_GPIO_PIN_10 GPIO_BSRR_BS10 /*!< Select pin 10 */
#define LL_GPIO_PIN_11 GPIO_BSRR_BS11 /*!< Select pin 11 */
#define LL_GPIO_PIN_12 GPIO_BSRR_BS12 /*!< Select pin 12 */
#define LL_GPIO_PIN_13 GPIO_BSRR_BS13 /*!< Select pin 13 */
#define LL_GPIO_PIN_14 GPIO_BSRR_BS14 /*!< Select pin 14 */
#define LL_GPIO_PIN_15 GPIO_BSRR_BS15 /*!< Select pin 15 */
#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS0 | GPIO_BSRR_BS1 | GPIO_BSRR_BS2 | \
GPIO_BSRR_BS3 | GPIO_BSRR_BS4 | GPIO_BSRR_BS5 | \
GPIO_BSRR_BS6 | GPIO_BSRR_BS7 | GPIO_BSRR_BS8 | \
GPIO_BSRR_BS9 | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \
GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \
GPIO_BSRR_BS15) /*!< Select all pins */
/**
* @}
*/
/** @defgroup GPIO_LL_EC_MODE Mode
* @{
*/
#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */
#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0 /*!< Select output mode */
#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1 /*!< Select alternate function mode */
#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0 /*!< Select analog mode */
/**
* @}
*/
/** @defgroup GPIO_LL_EC_OUTPUT Output Type
* @{
*/
#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */
#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0 /*!< Select open-drain as output type */
/**
* @}
*/
/** @defgroup GPIO_LL_EC_SPEED Output Speed
* @{
*/
#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */
#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */
#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed */
#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0 /*!< Select I/O high output speed */
/**
* @}
*/
/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
* @{
*/
#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */
#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */
#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */
/**
* @}
*/
/** @defgroup GPIO_LL_EC_AF Alternate Function
* @{
*/
#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */
#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */
#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */
#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */
#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */
#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */
#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */
#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */
#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */
#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */
#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */
#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */
#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */
#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */
#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */
#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
* @{
*/
/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in GPIO register
* @param __INSTANCE__ GPIO Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in GPIO register
* @param __INSTANCE__ GPIO Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
* @{
*/
/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
* @{
*/
/**
* @brief Configure gpio mode for a dedicated pin on dedicated port.
* @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
* @note Warning: only one pin can be passed as parameter.
* @rmtoll MODER MODEy LL_GPIO_SetPinMode
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_GPIO_MODE_INPUT
* @arg @ref LL_GPIO_MODE_OUTPUT
* @arg @ref LL_GPIO_MODE_ALTERNATE
* @arg @ref LL_GPIO_MODE_ANALOG
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
{
MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos)),
(Mode << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos)));
}
/**
* @brief Return gpio mode for a dedicated pin on dedicated port.
* @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
* @note Warning: only one pin can be passed as parameter.
* @rmtoll MODER MODEy LL_GPIO_GetPinMode
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_GPIO_MODE_INPUT
* @arg @ref LL_GPIO_MODE_OUTPUT
* @arg @ref LL_GPIO_MODE_ALTERNATE
* @arg @ref LL_GPIO_MODE_ANALOG
*/
__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(const GPIO_TypeDef *GPIOx, uint32_t Pin)
{
return (uint32_t)(READ_BIT(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos)))
>> (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos));
}
/**
* @brief Configure gpio output type for several pins on dedicated port.
* @note Output type as to be set when gpio pin is in output or
* alternate modes. Possible type are Push-pull or Open-drain.
* @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @param OutputType This parameter can be one of the following values:
* @arg @ref LL_GPIO_OUTPUT_PUSHPULL
* @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
{
MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
}
/**
* @brief Return gpio output type for several pins on dedicated port.
* @note Output type as to be set when gpio pin is in output or
* alternate modes. Possible type are Push-pull or Open-drain.
* @note Warning: only one pin can be passed as parameter.
* @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval Returned value can be one of the following values:
* @arg @ref LL_GPIO_OUTPUT_PUSHPULL
* @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
*/
__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(const GPIO_TypeDef *GPIOx, uint32_t Pin)
{
return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin));
}
/**
* @brief Configure gpio speed for a dedicated pin on dedicated port.
* @note I/O speed can be Low, Medium, Fast or High speed.
* @note Warning: only one pin can be passed as parameter.
* @note Refer to datasheet for frequency specifications and the power
* supply and load conditions for each speed.
* @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @param Speed This parameter can be one of the following values:
* @arg @ref LL_GPIO_SPEED_FREQ_LOW
* @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
* @arg @ref LL_GPIO_SPEED_FREQ_HIGH
* @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
{
MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos)),
(Speed << (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos)));
}
/**
* @brief Return gpio speed for a dedicated pin on dedicated port.
* @note I/O speed can be Low, Medium, Fast or High speed.
* @note Warning: only one pin can be passed as parameter.
* @note Refer to datasheet for frequency specifications and the power
* supply and load conditions for each speed.
* @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_GPIO_SPEED_FREQ_LOW
* @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
* @arg @ref LL_GPIO_SPEED_FREQ_HIGH
* @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
*/
__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(const GPIO_TypeDef *GPIOx, uint32_t Pin)
{
return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos)))
>> (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos));
}
/**
* @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
* @note Warning: only one pin can be passed as parameter.
* @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @param Pull This parameter can be one of the following values:
* @arg @ref LL_GPIO_PULL_NO
* @arg @ref LL_GPIO_PULL_UP
* @arg @ref LL_GPIO_PULL_DOWN
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
{
MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos)),
(Pull << (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos)));
}
/**
* @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
* @note Warning: only one pin can be passed as parameter.
* @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_GPIO_PULL_NO
* @arg @ref LL_GPIO_PULL_UP
* @arg @ref LL_GPIO_PULL_DOWN
*/
__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(const GPIO_TypeDef *GPIOx, uint32_t Pin)
{
return (uint32_t)(READ_BIT(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos)))
>> (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos));
}
/**
* @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
* @note Possible values are from AF0 to AF15 depending on target.
* @note Warning: only one pin can be passed as parameter.
* @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @param Alternate This parameter can be one of the following values:
* @arg @ref LL_GPIO_AF_0
* @arg @ref LL_GPIO_AF_1
* @arg @ref LL_GPIO_AF_2
* @arg @ref LL_GPIO_AF_3
* @arg @ref LL_GPIO_AF_4
* @arg @ref LL_GPIO_AF_5
* @arg @ref LL_GPIO_AF_6
* @arg @ref LL_GPIO_AF_7
* @arg @ref LL_GPIO_AF_8
* @arg @ref LL_GPIO_AF_9
* @arg @ref LL_GPIO_AF_10
* @arg @ref LL_GPIO_AF_11
* @arg @ref LL_GPIO_AF_12
* @arg @ref LL_GPIO_AF_13
* @arg @ref LL_GPIO_AF_14
* @arg @ref LL_GPIO_AF_15
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
{
MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos)),
(Alternate << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos)));
}
/**
* @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
* @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @retval Returned value can be one of the following values:
* @arg @ref LL_GPIO_AF_0
* @arg @ref LL_GPIO_AF_1
* @arg @ref LL_GPIO_AF_2
* @arg @ref LL_GPIO_AF_3
* @arg @ref LL_GPIO_AF_4
* @arg @ref LL_GPIO_AF_5
* @arg @ref LL_GPIO_AF_6
* @arg @ref LL_GPIO_AF_7
* @arg @ref LL_GPIO_AF_8
* @arg @ref LL_GPIO_AF_9
* @arg @ref LL_GPIO_AF_10
* @arg @ref LL_GPIO_AF_11
* @arg @ref LL_GPIO_AF_12
* @arg @ref LL_GPIO_AF_13
* @arg @ref LL_GPIO_AF_14
* @arg @ref LL_GPIO_AF_15
*/
__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(const GPIO_TypeDef *GPIOx, uint32_t Pin)
{
return (uint32_t)(READ_BIT(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos)))
>> (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos));
}
/**
* @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
* @note Possible values are from AF0 to AF15 depending on target.
* @note Warning: only one pin can be passed as parameter.
* @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @param Alternate This parameter can be one of the following values:
* @arg @ref LL_GPIO_AF_0
* @arg @ref LL_GPIO_AF_1
* @arg @ref LL_GPIO_AF_2
* @arg @ref LL_GPIO_AF_3
* @arg @ref LL_GPIO_AF_4
* @arg @ref LL_GPIO_AF_5
* @arg @ref LL_GPIO_AF_6
* @arg @ref LL_GPIO_AF_7
* @arg @ref LL_GPIO_AF_8
* @arg @ref LL_GPIO_AF_9
* @arg @ref LL_GPIO_AF_10
* @arg @ref LL_GPIO_AF_11
* @arg @ref LL_GPIO_AF_12
* @arg @ref LL_GPIO_AF_13
* @arg @ref LL_GPIO_AF_14
* @arg @ref LL_GPIO_AF_15
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
{
MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos)),
(Alternate << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos)));
}
/**
* @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
* @note Possible values are from AF0 to AF15 depending on target.
* @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_GPIO_AF_0
* @arg @ref LL_GPIO_AF_1
* @arg @ref LL_GPIO_AF_2
* @arg @ref LL_GPIO_AF_3
* @arg @ref LL_GPIO_AF_4
* @arg @ref LL_GPIO_AF_5
* @arg @ref LL_GPIO_AF_6
* @arg @ref LL_GPIO_AF_7
* @arg @ref LL_GPIO_AF_8
* @arg @ref LL_GPIO_AF_9
* @arg @ref LL_GPIO_AF_10
* @arg @ref LL_GPIO_AF_11
* @arg @ref LL_GPIO_AF_12
* @arg @ref LL_GPIO_AF_13
* @arg @ref LL_GPIO_AF_14
* @arg @ref LL_GPIO_AF_15
*/
__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(const GPIO_TypeDef *GPIOx, uint32_t Pin)
{
return (uint32_t)(READ_BIT(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos)))
>> (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos));
}
/**
* @brief Lock configuration of several pins for a dedicated port.
* @note When the lock sequence has been applied on a port bit, the
* value of this port bit can no longer be modified until the
* next reset.
* @note Each lock bit freezes a specific configuration register
* (control and alternate function registers).
* @rmtoll LCKR LCKK LL_GPIO_LockPin
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval None
*/
__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
__IO uint32_t temp;
WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
WRITE_REG(GPIOx->LCKR, PinMask);
WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
/* Read LCKK register. This read is mandatory to complete key lock sequence */
temp = READ_REG(GPIOx->LCKR);
(void) temp;
}
/**
* @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
* @rmtoll LCKR LCKy LL_GPIO_IsPinLocked
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(const GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL);
}
/**
* @brief Return 1 if one of the pin of a dedicated port is locked. else return 0.
* @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked
* @param GPIOx GPIO Port
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(const GPIO_TypeDef *GPIOx)
{
return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup GPIO_LL_EF_Data_Access Data Access
* @{
*/
/**
* @brief Return full input data register value for a dedicated port.
* @rmtoll IDR IDy LL_GPIO_ReadInputPort
* @param GPIOx GPIO Port
* @retval Input data register value of port
*/
__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(const GPIO_TypeDef *GPIOx)
{
return (uint32_t)(READ_REG(GPIOx->IDR));
}
/**
* @brief Return if input data level for several pins of dedicated port is high or low.
* @rmtoll IDR IDy LL_GPIO_IsInputPinSet
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL);
}
/**
* @brief Write output data register for the port.
* @rmtoll ODR ODy LL_GPIO_WriteOutputPort
* @param GPIOx GPIO Port
* @param PortValue Level value for each pin of the port
* @retval None
*/
__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
{
WRITE_REG(GPIOx->ODR, PortValue);
}
/**
* @brief Return full output data register value for a dedicated port.
* @rmtoll ODR ODy LL_GPIO_ReadOutputPort
* @param GPIOx GPIO Port
* @retval Output data register value of port
*/
__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(const GPIO_TypeDef *GPIOx)
{
return (uint32_t)(READ_REG(GPIOx->ODR));
}
/**
* @brief Return if input data level for several pins of dedicated port is high or low.
* @rmtoll ODR ODy LL_GPIO_IsOutputPinSet
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL);
}
/**
* @brief Set several pins to high level on dedicated gpio port.
* @rmtoll BSRR BSy LL_GPIO_SetOutputPin
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
WRITE_REG(GPIOx->BSRR, PinMask);
}
/**
* @brief Set several pins to low level on dedicated gpio port.
* @rmtoll BRR BRy LL_GPIO_ResetOutputPin
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval None
*/
__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
WRITE_REG(GPIOx->BRR, PinMask);
}
/**
* @brief Toggle data value for several pin of dedicated port.
* @rmtoll ODR ODy LL_GPIO_TogglePin
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval None
*/
__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
uint32_t odr = READ_REG(GPIOx->ODR);
WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16U) | (~odr & PinMask));
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx);
ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, const LL_GPIO_InitTypeDef *GPIO_InitStruct);
void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || */
/* defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || */
/* defined (GPIOM) || defined (GPION) || defined (GPIOO) || defined (GPIOP) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H7RSxx_LL_GPIO_H */
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_i2c.h
+2372
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Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_icache.h
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/**
******************************************************************************
* @file stm32h7rsxx_ll_icache.h
* @author MCD Application Team
* @brief Header file of ICACHE LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion ------------------------------------*/
#ifndef STM32H7RSxx_LL_ICACHE_H
#define STM32H7RSxx_LL_ICACHE_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes -----------------------------------------------------------------*/
#include "stm32h7rsxx.h"
/** @addtogroup STM32H7RSxx_LL_Driver
* @{
*/
#if defined(ICACHE)
/** @defgroup ICACHE_LL ICACHE
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants -------------------------------------------------------*/
/** @defgroup ICACHE_LL_Exported_Constants ICACHE Exported Constants
* @{
*/
/** @defgroup ICACHE_LL_EC_WaysSelection Ways selection
* @{
*/
#define LL_ICACHE_1WAY 0U /*!< 1-way cache (direct mapped cache) */
#define LL_ICACHE_4WAYS ICACHE_CR_WAYSEL /*!< 4-ways set associative cache (default) */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_Monitor_Type Monitor type
* @{
*/
#define LL_ICACHE_MONITOR_HIT ICACHE_CR_HITMEN /*!< Hit monitor counter */
#define LL_ICACHE_MONITOR_MISS ICACHE_CR_MISSMEN /*!< Miss monitor counter */
#define LL_ICACHE_MONITOR_ALL (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< All monitors counters */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_ICACHE_ReadReg function
* @{
*/
#define LL_ICACHE_SR_BUSYF ICACHE_SR_BUSYF /*!< Busy flag */
#define LL_ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF /*!< Busy end flag */
#define LL_ICACHE_SR_ERRF ICACHE_SR_ERRF /*!< Cache error flag */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_CLEAR_FLAG Clear Flags Defines
* @brief Flags defines which can be used with LL_ICACHE_WriteReg function
* @{
*/
#define LL_ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF /*!< Busy end flag */
#define LL_ICACHE_FCR_CERRF ICACHE_FCR_CERRF /*!< Cache error flag */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_ICACHE_ReadReg and LL_ICACHE_WriteReg functions
* @{
*/
#define LL_ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE /*!< Busy end interrupt */
#define LL_ICACHE_IER_ERRIE ICACHE_IER_ERRIE /*!< Cache error interrupt */
/**
* @}
*/
/**
* @}
*/
/* Exported macros ----------------------------------------------------------*/
/** @defgroup ICACHE_LL_Exported_Macros ICACHE Exported Macros
* @{
*/
/** @defgroup ICACHE_LL_EM_WRITE_READ Common write and read registers Macros
* @{
*/
/**
* @brief Write a value in ICACHE register
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_ICACHE_WriteReg(__REG__, __VALUE__) WRITE_REG(ICACHE->__REG__, (__VALUE__))
/**
* @brief Read a value in ICACHE register
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_ICACHE_ReadReg(__REG__) READ_REG(ICACHE->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup ICACHE_LL_Exported_Functions ICACHE Exported Functions
* @{
*/
/** @defgroup ICACHE_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Enable the ICACHE.
* @rmtoll CR EN LL_ICACHE_Enable
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_Enable(void)
{
SET_BIT(ICACHE->CR, ICACHE_CR_EN);
}
/**
* @brief Disable the ICACHE.
* @rmtoll CR EN LL_ICACHE_Disable
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_Disable(void)
{
CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN);
}
/**
* @brief Return if ICACHE is enabled or not.
* @rmtoll CR EN LL_ICACHE_IsEnabled
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsEnabled(void)
{
return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) == (ICACHE_CR_EN)) ? 1UL : 0UL);
}
/**
* @brief Select the ICACHE operating mode.
* @rmtoll CR WAYSEL LL_ICACHE_SetMode
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_ICACHE_1WAY
* @arg @ref LL_ICACHE_4WAYS
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_SetMode(uint32_t Mode)
{
MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, Mode);
}
/**
* @brief Get the selected ICACHE operating mode.
* @rmtoll CR WAYSEL LL_ICACHE_GetMode
* @retval Returned value can be one of the following values:
* @arg @ref LL_ICACHE_1WAY
* @arg @ref LL_ICACHE_4WAYS
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetMode(void)
{
return (READ_BIT(ICACHE->CR, ICACHE_CR_WAYSEL));
}
/**
* @brief Invalidate the ICACHE.
* @note Until the BSYEND flag is set, the cache is bypassed.
* @rmtoll CR CACHEINV LL_ICACHE_Invalidate
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_Invalidate(void)
{
SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV);
}
/**
* @}
*/
/** @defgroup ICACHE_LL_EF_Monitors Monitors
* @{
*/
/**
* @brief Enable the hit/miss monitor(s).
* @rmtoll CR HITMEN LL_ICACHE_EnableMonitors
* @rmtoll CR MISSMEN LL_ICACHE_EnableMonitors
* @param Monitors This parameter can be one or a combination of the following values:
* @arg @ref LL_ICACHE_MONITOR_HIT
* @arg @ref LL_ICACHE_MONITOR_MISS
* @arg @ref LL_ICACHE_MONITOR_ALL
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_EnableMonitors(uint32_t Monitors)
{
SET_BIT(ICACHE->CR, Monitors);
}
/**
* @brief Disable the hit/miss monitor(s).
* @rmtoll CR HITMEN LL_ICACHE_DisableMonitors
* @rmtoll CR MISSMEN LL_ICACHE_DisableMonitors
* @param Monitors This parameter can be one or a combination of the following values:
* @arg @ref LL_ICACHE_MONITOR_HIT
* @arg @ref LL_ICACHE_MONITOR_MISS
* @arg @ref LL_ICACHE_MONITOR_ALL
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_DisableMonitors(uint32_t Monitors)
{
CLEAR_BIT(ICACHE->CR, Monitors);
}
/**
* @brief Check if the monitor(s) is(are) enabled or disabled.
* @rmtoll CR HITMEN LL_ICACHE_IsEnabledMonitors
* @rmtoll CR MISSMEN LL_ICACHE_IsEnabledMonitors
* @param Monitors This parameter can be one or a combination of the following values:
* @arg @ref LL_ICACHE_MONITOR_HIT
* @arg @ref LL_ICACHE_MONITOR_MISS
* @arg @ref LL_ICACHE_MONITOR_ALL
* @retval State of parameter value (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledMonitors(uint32_t Monitors)
{
return ((READ_BIT(ICACHE->CR, Monitors) == (Monitors)) ? 1UL : 0UL);
}
/**
* @brief Reset the hit/miss monitor(s).
* @rmtoll CR HITMRST LL_ICACHE_ResetMonitors
* @rmtoll CR MISSMRST LL_ICACHE_ResetMonitors
* @param Monitors This parameter can be one or a combination of the following values:
* @arg @ref LL_ICACHE_MONITOR_HIT
* @arg @ref LL_ICACHE_MONITOR_MISS
* @arg @ref LL_ICACHE_MONITOR_ALL
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_ResetMonitors(uint32_t Monitors)
{
/* Reset */
SET_BIT(ICACHE->CR, (Monitors << 2U));
/* Release reset */
CLEAR_BIT(ICACHE->CR, (Monitors << 2U));
}
/**
* @brief Get the Hit monitor.
* @note Upon reaching the 32-bit maximum value, hit monitor does not wrap.
* @rmtoll HMONR HITMON LL_ICACHE_GetHitMonitor
* @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetHitMonitor(void)
{
return (ICACHE->HMONR);
}
/**
* @brief Get the Miss monitor.
* @note Upon reaching the 16-bit maximum value, miss monitor does not wrap.
* @rmtoll MMONR MISSMON LL_ICACHE_GetMissMonitor
* @retval Value between Min_Data=0 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetMissMonitor(void)
{
return (ICACHE->MMONR);
}
/**
* @}
*/
/** @defgroup ICACHE_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable BSYEND interrupt.
* @rmtoll IER BSYENDIE LL_ICACHE_EnableIT_BSYEND
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_EnableIT_BSYEND(void)
{
SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
}
/**
* @brief Disable BSYEND interrupt.
* @rmtoll IER BSYENDIE LL_ICACHE_DisableIT_BSYEND
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_DisableIT_BSYEND(void)
{
CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
}
/**
* @brief Check if the BSYEND Interrupt is enabled or disabled.
* @rmtoll IER BSYENDIE LL_ICACHE_IsEnabledIT_BSYEND
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_BSYEND(void)
{
return ((READ_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE) == (ICACHE_IER_BSYENDIE)) ? 1UL : 0UL);
}
/**
* @brief Enable ERR interrupt.
* @rmtoll IER ERRIE LL_ICACHE_EnableIT_ERR
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_EnableIT_ERR(void)
{
SET_BIT(ICACHE->IER, ICACHE_IER_ERRIE);
}
/**
* @brief Disable ERR interrupt.
* @rmtoll IER ERRIE LL_ICACHE_DisableIT_ERR
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_DisableIT_ERR(void)
{
CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE);
}
/**
* @brief Check if the ERR Interrupt is enabled or disabled.
* @rmtoll IER ERRIE LL_ICACHE_IsEnabledIT_ERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_ERR(void)
{
return ((READ_BIT(ICACHE->IER, ICACHE_IER_ERRIE) == (ICACHE_IER_ERRIE)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup ICACHE_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Indicate the status of an ongoing operation flag.
* @rmtoll SR BUSYF LL_ICACHE_IsActiveFlag_BUSY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BUSY(void)
{
return ((READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == (ICACHE_SR_BUSYF)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of an operation end flag.
* @rmtoll SR BSYEND LL_ICACHE_IsActiveFlag_BSYEND
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BSYEND(void)
{
return ((READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == (ICACHE_SR_BSYENDF)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of an error flag.
* @rmtoll SR ERRF LL_ICACHE_IsActiveFlag_ERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_ERR(void)
{
return ((READ_BIT(ICACHE->SR, ICACHE_SR_ERRF) == (ICACHE_SR_ERRF)) ? 1UL : 0UL);
}
/**
* @brief Clear busy end of operation flag.
* @rmtoll FCR CBSYENDF LL_ICACHE_ClearFlag_BSYEND
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_ClearFlag_BSYEND(void)
{
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
}
/**
* @brief Clear error flag.
* @rmtoll FCR ERRF LL_ICACHE_ClearFlag_ERR
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_ClearFlag_ERR(void)
{
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* ICACHE */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H7RSxx_LL_ICACHE_H */
Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_pwr.h
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Drivers/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_utils.h
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/**
******************************************************************************
* @file stm32h7rsxx_ll_utils.h
* @author MCD Application Team
* @brief Header file of UTILS LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The LL UTILS driver contains a set of generic APIs that can be
used by user:
(+) Device electronic signature
(+) Timing functions
(+) PLL configuration functions
@endverbatim
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7RSxx_LL_UTILS_H
#define STM32H7RSxx_LL_UTILS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx.h"
#include "stm32h7rsxx_ll_system.h"
#include "stm32h7rsxx_ll_bus.h"
#include "stm32h7rsxx_ll_rcc.h"
/** @addtogroup STM32H7RSxx_LL_Driver
* @{
*/
/** @defgroup UTILS_LL UTILS
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
* @{
*/
/* Max delay can be used in LL_mDelay */
#define LL_MAX_DELAY 0xFFFFFFFFU
/**
* @brief Unique device ID register base address
*/
#define UID_BASE_ADDRESS UID_BASE
/**
* @brief Package data register base address
*/
#define PACKAGE_BASE_ADDRESS PACKAGE_BASE
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
* @{
*/
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
* @{
*/
/**
* @brief UTILS PLL structure definition
*/
typedef struct
{
uint32_t PLLM; /*!< Division factor for PLL VCO input clock.
This parameter must be a number between Min_Data = 0 and Max_Data = 63
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL1_SetM(). */
uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock.
This parameter must be a number between Min_Data = 4 and Max_Data = 512
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL1_SetN(). */
uint32_t PLLP; /*!< Division for the main system clock.
This parameter must be a number between Min_Data = 2 and Max_Data = 128
odd division factors are not allowed
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL1_SetP(). */
uint32_t FRACN; /*!< Fractional part of the multiplication factor for PLL VCO.
This parameter can be a value between 0 and 8191
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL1_SetFRACN(). */
uint32_t VCO_Input; /*!< PLL clock Input range.
This parameter can be a value of @ref RCC_LL_EC_PLLINPUTRANGE
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL1_SetVCOInputRange(). */
uint32_t VCO_Output; /*!< PLL clock Output range.
This parameter can be a value of @ref RCC_LL_EC_PLLVCORANGE
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL1_SetVCOOutputRange(). */
} LL_UTILS_PLLInitTypeDef;
/**
* @brief UTILS System, AHB and APB buses clock configuration structure definition
*/
typedef struct
{
uint32_t SYSCLKDivider; /*!< The System clock (SYSCLK) divider. This clock is derived from the PLL output.
This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetSysPrescaler(). */
uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
This parameter can be a value of @ref RCC_LL_EC_AHB_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAHBPrescaler(). */
uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAPB1Prescaler(). */
uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAPB2Prescaler(). */
uint32_t APB4CLKDivider; /*!< The APB4 clock (PCLK4) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_LL_EC_APB4_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAPB4Prescaler(). */
uint32_t APB5CLKDivider; /*!< The APB5 clock (PCLK5) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_LL_EC_APB5_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAPB5Prescaler(). */
} LL_UTILS_ClkInitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
* @{
*/
/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
* @{
*/
#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
/**
* @}
*/
/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
* @{
*/
#define LL_UTILS_PACKAGETYPE_VFQFPN68_GP 0U /*!< VFQFPN68 GP package type */
#define LL_UTILS_PACKAGETYPE_TFBGA100_SMPS_GP 1U /*!< TFBGA100 SMPS GP package type */
#define LL_UTILS_PACKAGETYPE_LQFP100_GP 2U /*!< LQFP100 GP package type */
#define LL_UTILS_PACKAGETYPE_LQFP144_GP 3U /*!< LQFP144 GP package type */
#define LL_UTILS_PACKAGETYPE_UFBGA144_SMPS_GP 4U /*!< UFBGA144 SMPS GP package type */
#define LL_UTILS_PACKAGETYPE_UFBGA144_SMPS_GFX 5U /*!< UFBGA144 SMPS GFX package type */
#define LL_UTILS_PACKAGETYPE_UFBGA169_SMPS_GFX 6U /*!< UFBGA169 SMPS GFX package type */
#define LL_UTILS_PACKAGETYPE_UFBGA169_SMPS_GP 7U /*!< UFBGA169 SMPS GP package type */
#define LL_UTILS_PACKAGETYPE_UFBGA176_25_SMPS_GP 8U /*!< UFBGA176+25 SMPS GP package type */
#define LL_UTILS_PACKAGETYPE_LQFP176_SMPS_GP 9U /*!< LQFP176 SMPS GP package type */
#define LL_UTILS_PACKAGETYPE_LQFP176_SMPS_GFX 10U /*!< LQFP176 SMPS GFX package type */
#define LL_UTILS_PACKAGETYPE_UFBGA176_25_SMPS_GFX 11U /*!< UFBGA176+25 SMPS GFX package type */
#define LL_UTILS_PACKAGETYPE_TFBGA225_OCTO 12U /*!< TFBGA225 OCTO package type */
#define LL_UTILS_PACKAGETYPE_TFBGA225_HEXA 13U /*!< TFBGA225 HEXA package type */
#define LL_UTILS_PACKAGETYPE_WLCSP_SMPS_GP 14U /*!< WLCSP SMPS GP package type */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
* @{
*/
/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
* @{
*/
/**
* @brief Get Word0 of the unique device identifier (UID based on 96 bits)
* @note The read address belongs to an area which may contain virgin data generating
* double ECC error (as never programmed). Thus, in case of cache activation
* the address range 0x08FFF000-0x08FFFFFF should be defined as non-cacheable
* through the MPU.
* @retval UID[31:0]
*/
__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
{
return (uint32_t)(READ_REG(*((__IO uint32_t *)UID_BASE_ADDRESS)));
}
/**
* @brief Get Word1 of the unique device identifier (UID based on 96 bits)
* @note The read address belongs to an area which may contain virgin data generating
* double ECC error (as never programmed). Thus, in case of cache activation
* the address range 0x08FFF000-0x08FFFFFF should be defined as non-cacheable
* through the MPU.
* @retval UID[63:32]
*/
__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
{
return (uint32_t)(READ_REG(*((__IO uint32_t *)(UID_BASE_ADDRESS + 4U))));
}
/**
* @brief Get Word2 of the unique device identifier (UID based on 96 bits)
* @note The read address belongs to an area which may contain virgin data generating
* double ECC error (as never programmed). Thus, in case of cache activation
* the address range 0x08FFF000-0x08FFFFFF should be defined as non-cacheable
* through the MPU.
* @retval UID[95:64]
*/
__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
{
return (uint32_t)(READ_REG(*((__IO uint32_t *)(UID_BASE_ADDRESS + 8U))));
}
/**
* @brief Get Package type
* @note The read address belongs to an area which may contain virgin data generating
* double ECC error (as never programmed). Thus, in case of cache activation
* the address range 0x08FFF000-0x08FFFFFF should be defined as non-cacheable
* through the MPU.
* @retval Returned value can be one of the following values:
* @arg @ref LL_UTILS_PACKAGETYPE_VFQFPN68_GP
* @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_SMPS_GP
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_GP
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_GP
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144_SMPS_GP
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144_SMPS_GFX
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_SMPS_GFX
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_SMPS_GP
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_25_SMPS_GP
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_SMPS_GP
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_SMPS_GFX
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_25_SMPS_GFX
* @arg @ref LL_UTILS_PACKAGETYPE_TFBGA225_OCTO
* @arg @ref LL_UTILS_PACKAGETYPE_TFBGA225_HEXA
* @arg @ref LL_UTILS_PACKAGETYPE_WLCSP_SMPS_GP
*/
__STATIC_INLINE uint32_t LL_GetPackageType(void)
{
return (uint32_t)((READ_REG(*((__IO uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x000F0000UL) >> 16UL);
}
/**
* @}
*/
/** @defgroup UTILS_LL_EF_DELAY DELAY
* @{
*/
/**
* @brief This function configures the Cortex-M SysTick source of the time base.
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
* configuration by calling this function, for a delay use rather osDelay RTOS service.
* @param Ticks Number of ticks
* @retval None
*/
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
{
if (Ticks > 0U)
{
/* Configure the SysTick to have interrupt in 1ms time base */
SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
}
}
void LL_Init1msTick(uint32_t CPU_Frequency);
void LL_mDelay(uint32_t Delay);
/**
* @}
*/
/** @defgroup UTILS_EF_SYSTEM SYSTEM
* @{
*/
void LL_SetSystemCoreClock(uint32_t CPU_Frequency);
ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency);
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
ErrorStatus LL_PLL_ConfigSystemClock_CSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency,
uint32_t HSEBypass,
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H7RSxx_LL_UTILS_H */
Drivers/STM32H7RSxx_HAL_Driver/LICENSE.md
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# Copyright (c) 2020 STMicroelectronics
This software component is licensed by STMicroelectronics under the **BSD-3-Clause** license. You may not use this software except in compliance with this license. You may obtain a copy of the license [here](https://opensource.org/licenses/BSD-3-Clause).
Drivers/STM32H7RSxx_HAL_Driver/LICENSE.txt
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This software component is provided to you as part of a software package and
applicable license terms are in the Package_license file. If you received this
software component outside of a package or without applicable license terms,
the terms of the BSD-3-Clause license shall apply.
You may obtain a copy of the BSD-3-Clause at:
https://opensource.org/licenses/BSD-3-Clause
Drivers/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal.c
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Drivers/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_cortex.c
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/**
******************************************************************************
* @file stm32h7rsxx_hal_cortex.c
* @author MCD Application Team
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:
* + Initialization and Configuration functions
* + Peripheral Control functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
*** How to configure Interrupts using CORTEX HAL driver ***
===========================================================
[..]
This section provides functions allowing to configure the NVIC interrupts (IRQ).
The Cortex-M7 exceptions are managed by CMSIS functions.
(#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
-@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
The pending IRQ priority will be managed only by the sub priority.
-@- IRQ priority order (sorted by highest to lowest priority):
(+@) Lowest pre-emption priority
(+@) Lowest sub priority
(+@) Lowest hardware priority (IRQ number)
[..]
*** How to configure SysTick using CORTEX HAL driver ***
========================================================
[..]
Setup SysTick Timer for time base.
(+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
is a CMSIS function that:
(++) Configures the SysTick Reload register with value passed as function parameter.
(++) Configures the SysTick IRQ priority to the lowest value (0x0F).
(++) Resets the SysTick Counter register.
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
(++) Enables the SysTick Interrupt.
(++) Starts the SysTick Counter.
(+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
__HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
inside the stm32h7rsxx_hal_cortex.h file.
(+) You can change the SysTick IRQ priority by calling the
HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
(+) To adjust the SysTick time base, use the following formula:
Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
(++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
(++) Reload Value should not exceed 0xFFFFFF
@endverbatim
******************************************************************************
The table below gives the allowed values of the pre-emption priority and subpriority according
to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
==========================================================================================================================
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
==========================================================================================================================
NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bit for pre-emption priority
| | | 4 bits for subpriority
--------------------------------------------------------------------------------------------------------------------------
NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority
| | | 3 bits for subpriority
--------------------------------------------------------------------------------------------------------------------------
NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
| | | 2 bits for subpriority
--------------------------------------------------------------------------------------------------------------------------
NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
| | | 1 bit for subpriority
--------------------------------------------------------------------------------------------------------------------------
NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
| | | 0 bit for subpriority
==========================================================================================================================
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @addtogroup CORTEX
* @brief CORTEX HAL module driver
* @{
*/
#ifdef HAL_CORTEX_MODULE_ENABLED
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CORTEX_Exported_Functions
* @{
*/
/** @addtogroup CORTEX_Exported_Functions_Group1
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and Configuration functions #####
==============================================================================
[..]
This section provides the CORTEX HAL driver functions allowing to configure Interrupts
SysTick functionalities
@endverbatim
* @{
*/
/**
* @brief Set the priority grouping field (pre-emption priority and subpriority)
* using the required unlock sequence.
* @param PriorityGroup The priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PRIORITYGROUP_0 0 bit for pre-emption priority,
* 4 bits for subpriority
* @arg NVIC_PRIORITYGROUP_1 1 bit for pre-emption priority,
* 3 bits for subpriority
* @arg NVIC_PRIORITYGROUP_2 2 bits for pre-emption priority,
* 2 bits for subpriority
* @arg NVIC_PRIORITYGROUP_3 3 bits for pre-emption priority,
* 1 bit for subpriority
* @arg NVIC_PRIORITYGROUP_4 4 bits for pre-emption priority,
* 0 bit for subpriority
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
}
/**
* @brief Set the priority of an interrupt.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer
* to the appropriate CMSIS device file (stm32h7rsxxxx.h))
* @param PreemptPriority The pre-emption priority for the IRQn channel.
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority
* @param SubPriority the subpriority level for the IRQ channel.
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t prioritygroup;
/* Check the parameters */
assert_param(IS_NVIC_PRIO_INTERRUPT(IRQn));
prioritygroup = NVIC_GetPriorityGrouping();
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority, prioritygroup));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority, prioritygroup));
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
}
/**
* @brief Enable a device specific interrupt in the NVIC interrupt controller.
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
* function should be called before.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer
* to the appropriate CMSIS device file (stm32h7rsxxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
}
/**
* @brief Disable a device specific interrupt in the NVIC interrupt controller.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer
* to the appropriate CMSIS device file (stm32h7rsxxxx.h))
* @retval None
*/
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Disable interrupt */
NVIC_DisableIRQ(IRQn);
}
/**
* @brief Initiate a system reset request to reset the MCU.
* @retval None
*/
void HAL_NVIC_SystemReset(void)
{
/* System Reset */
NVIC_SystemReset();
}
/**
* @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
* Counter is in free running mode to generate periodic interrupts.
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
return SysTick_Config(TicksNumb);
}
/**
* @}
*/
/** @addtogroup CORTEX_Exported_Functions_Group2
* @brief Cortex control functions
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to control the CORTEX
(NVIC, SYSTICK, MPU) functionalities.
@endverbatim
* @{
*/
/**
* @brief Get the priority grouping field from the NVIC Interrupt Controller.
* @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
*/
uint32_t HAL_NVIC_GetPriorityGrouping(void)
{
/* Get the PRIGROUP[10:8] field value */
return NVIC_GetPriorityGrouping();
}
/**
* @brief Get the priority of an interrupt.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer
* to the appropriate CMSIS device file (stm32h7rsxxxx.h))
* @param PriorityGroup the priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PRIORITYGROUP_0 0 bit for pre-emption priority,
* 4 bits for subpriority
* @arg NVIC_PRIORITYGROUP_1 1 bit for pre-emption priority,
* 3 bits for subpriority
* @arg NVIC_PRIORITYGROUP_2 2 bits for pre-emption priority,
* 2 bits for subpriority
* @arg NVIC_PRIORITYGROUP_3 3 bits for pre-emption priority,
* 1 bit for subpriority
* @arg NVIC_PRIORITYGROUP_4 4 bits for pre-emption priority,
* 0 bit for subpriority
* @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
* @param pSubPriority Pointer on the Subpriority value (starting from 0).
* @retval None
*/
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
{
/* Check the parameters */
assert_param(IS_NVIC_PRIO_INTERRUPT(IRQn));
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Get priority for Cortex-M system or device specific interrupts */
NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
}
/**
* @brief Set Pending bit of an external interrupt.
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer
* to the appropriate CMSIS device file (stm32h7rsxxxx.h))
* @retval None
*/
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Set interrupt pending */
NVIC_SetPendingIRQ(IRQn);
}
/**
* @brief Get Pending Interrupt (read the pending register in the NVIC
* and return the pending bit for the specified interrupt).
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer
* to the appropriate CMSIS device file (stm32h7rsxxxx.h))
* @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
*/
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Return 1 if pending else 0 */
return NVIC_GetPendingIRQ(IRQn);
}
/**
* @brief Clear the pending bit of an external interrupt.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer
* to the appropriate CMSIS device file (stm32h7rsxxxx.h))
* @retval None
*/
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Clear pending interrupt */
NVIC_ClearPendingIRQ(IRQn);
}
/**
* @brief Get active interrupt (read the active register in NVIC and return the active bit).
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer
* to the appropriate CMSIS device file (stm32h7rsxxxx.h))
* @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
*/
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
{
/* Return 1 if active else 0 */
return NVIC_GetActive(IRQn);
}
/**
* @brief Configure the SysTick clock source.
* @param CLKSource specifies the SysTick clock source.
* This parameter can be one of the following values:
* @arg SYSTICK_CLKSOURCE_HCLK AHB clock selected as SysTick clock source.
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8 AHB clock divided by 8 selected as SysTick clock source.
* @retval None
*/
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
{
/* Check the parameters */
assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
MODIFY_REG(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk, CLKSource);
}
/**
* @brief Handle SYSTICK interrupt request.
* @retval None
*/
void HAL_SYSTICK_IRQHandler(void)
{
HAL_SYSTICK_Callback();
}
/**
* @brief SYSTICK callback.
* @retval None
*/
__weak void HAL_SYSTICK_Callback(void)
{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SYSTICK_Callback could be implemented in the user file
*/
}
/**
* @brief Enable the MPU.
* @param MPU_Control Specifies the control mode of the MPU during hard fault,
* NMI, FAULTMASK and privileged access to the default memory
* This parameter can be one of the following values:
* @arg MPU_HFNMI_PRIVDEF_NONE
* @arg MPU_HARDFAULT_NMI
* @arg MPU_PRIVILEGED_DEFAULT
* @arg MPU_HFNMI_PRIVDEF
* @retval None
*/
void HAL_MPU_Enable(uint32_t MPU_Control)
{
/* Force any outstanding transfers to complete before enabling MPU */
__DMB();
/* Enable the MPU */
MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk);
/* Enable fault exceptions */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
/* Ensure MPU setting take effects */
__DSB();
__ISB();
}
/**
* @brief Disable the MPU.
* @retval None
*/
void HAL_MPU_Disable(void)
{
/* Force any outstanding transfers to complete before disabling MPU */
__DMB();
/* Disable fault exceptions */
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
/* Disable the MPU and clear the control register */
MPU->CTRL = 0U;
/* Ensure MPU setting take effects */
__DSB();
__ISB();
}
/**
* @brief Enable the MPU Region.
* @retval None
*/
void HAL_MPU_EnableRegion(uint32_t RegionNumber)
{
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
/* Set the Region number */
MPU->RNR = RegionNumber;
/* Enable the Region */
SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
}
/**
* @brief Disable the MPU Region.
* @retval None
*/
void HAL_MPU_DisableRegion(uint32_t RegionNumber)
{
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
/* Set the Region number */
MPU->RNR = RegionNumber;
/* Disable the Region */
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
}
/**
* @brief Initialize and configure the Region and the memory to be protected.
* @param pMPU_RegionInit Pointer to a MPU_Region_InitTypeDef structure that contains
* the initialization and configuration information.
* @note The region base address must be aligned to the size of the region.
* @retval None
*/
void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *pMPU_RegionInit)
{
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(pMPU_RegionInit->Number));
assert_param(IS_MPU_REGION_ENABLE(pMPU_RegionInit->Enable));
/* Set the Region number */
MPU->RNR = pMPU_RegionInit->Number;
/* Check the parameters */
assert_param(IS_MPU_INSTRUCTION_ACCESS(pMPU_RegionInit->DisableExec));
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(pMPU_RegionInit->AccessPermission));
assert_param(IS_MPU_TEX_LEVEL(pMPU_RegionInit->TypeExtField));
assert_param(IS_MPU_ACCESS_SHAREABLE(pMPU_RegionInit->IsShareable));
assert_param(IS_MPU_ACCESS_CACHEABLE(pMPU_RegionInit->IsCacheable));
assert_param(IS_MPU_ACCESS_BUFFERABLE(pMPU_RegionInit->IsBufferable));
assert_param(IS_MPU_SUB_REGION_DISABLE(pMPU_RegionInit->SubRegionDisable));
assert_param(IS_MPU_REGION_SIZE(pMPU_RegionInit->Size));
assert_param(IS_MPU_ADDRESS_MULTIPLE_SIZE(pMPU_RegionInit->BaseAddress, pMPU_RegionInit->Size));
/* Disable the Region */
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
/* Disable the Region */
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
MPU->RBAR = pMPU_RegionInit->BaseAddress;
MPU->RASR = ((uint32_t)pMPU_RegionInit->DisableExec << MPU_RASR_XN_Pos) |
((uint32_t)pMPU_RegionInit->AccessPermission << MPU_RASR_AP_Pos) |
((uint32_t)pMPU_RegionInit->TypeExtField << MPU_RASR_TEX_Pos) |
((uint32_t)pMPU_RegionInit->IsShareable << MPU_RASR_S_Pos) |
((uint32_t)pMPU_RegionInit->IsCacheable << MPU_RASR_C_Pos) |
((uint32_t)pMPU_RegionInit->IsBufferable << MPU_RASR_B_Pos) |
((uint32_t)pMPU_RegionInit->SubRegionDisable << MPU_RASR_SRD_Pos) |
((uint32_t)pMPU_RegionInit->Size << MPU_RASR_SIZE_Pos) |
((uint32_t)pMPU_RegionInit->Enable << MPU_RASR_ENABLE_Pos);
}
/**
* @brief Clear pending events.
* @retval None
*/
void HAL_CORTEX_ClearEvent(void)
{
__SEV();
__WFE();
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_CORTEX_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
Drivers/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_crc.c
+520
View File
@@ -0,0 +1,520 @@
/**
******************************************************************************
* @file stm32h7rsxx_hal_crc.c
* @author MCD Application Team
* @brief CRC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:
* + Initialization and de-initialization functions
* + Peripheral Control functions
* + Peripheral State functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
(+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
(+) Initialize CRC calculator
(++) specify generating polynomial (peripheral default or non-default one)
(++) specify initialization value (peripheral default or non-default one)
(++) specify input data format
(++) specify input or output data inversion mode if any
(+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
input data buffer starting with the previously computed CRC as
initialization value
(+) Use HAL_CRC_Calculate() function to compute the CRC value of the
input data buffer starting with the defined initialization value
(default or non-default) to initiate CRC calculation
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @defgroup CRC CRC
* @brief CRC HAL module driver.
* @{
*/
#ifdef HAL_CRC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup CRC_Private_Functions CRC Private Functions
* @{
*/
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRC_Exported_Functions CRC Exported Functions
* @{
*/
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions.
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize the CRC according to the specified parameters
in the CRC_InitTypeDef and create the associated handle
(+) DeInitialize the CRC peripheral
(+) Initialize the CRC MSP (MCU Specific Package)
(+) DeInitialize the CRC MSP
@endverbatim
* @{
*/
/**
* @brief Initialize the CRC according to the specified
* parameters in the CRC_InitTypeDef and create the associated handle.
* @param hcrc CRC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
{
/* Check the CRC handle allocation */
if (hcrc == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
if (hcrc->State == HAL_CRC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hcrc->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_CRC_MspInit(hcrc);
}
hcrc->State = HAL_CRC_STATE_BUSY;
/* check whether or not non-default generating polynomial has been
* picked up by user */
assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
{
/* initialize peripheral with default generating polynomial */
WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
}
else
{
/* initialize CRC peripheral with generating polynomial defined by user */
if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
{
return HAL_ERROR;
}
}
/* check whether or not non-default CRC initial value has been
* picked up by user */
assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
{
WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
}
else
{
WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
}
/* set input data inversion mode */
assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
/* set output data inversion mode */
assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
/* makes sure the input data format (bytes, halfwords or words stream)
* is properly specified by user */
assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief DeInitialize the CRC peripheral.
* @param hcrc CRC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
{
/* Check the CRC handle allocation */
if (hcrc == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
/* Check the CRC peripheral state */
if (hcrc->State == HAL_CRC_STATE_BUSY)
{
return HAL_BUSY;
}
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* Reset CRC calculation unit */
__HAL_CRC_DR_RESET(hcrc);
/* Reset IDR register content */
CLEAR_REG(hcrc->Instance->IDR);
/* DeInit the low level hardware */
HAL_CRC_MspDeInit(hcrc);
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_RESET;
/* Process unlocked */
__HAL_UNLOCK(hcrc);
/* Return function status */
return HAL_OK;
}
/**
* @brief Initializes the CRC MSP.
* @param hcrc CRC handle
* @retval None
*/
__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcrc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CRC_MspInit can be implemented in the user file
*/
}
/**
* @brief DeInitialize the CRC MSP.
* @param hcrc CRC handle
* @retval None
*/
__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcrc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CRC_MspDeInit can be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
* @brief management functions.
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
using combination of the previous CRC value and the new one.
[..] or
(+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
independently of the previous CRC value.
@endverbatim
* @{
*/
/**
* @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
* starting with the previously computed CRC as initialization value.
* @param hcrc CRC handle
* @param pBuffer pointer to the input data buffer, exact input data format is
* provided by hcrc->InputDataFormat.
* @param BufferLength input data buffer length (number of bytes if pBuffer
* type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
* number of words if pBuffer type is * uint32_t).
* @note By default, the API expects a uint32_t pointer as input buffer parameter.
* Input buffer pointers with other types simply need to be cast in uint32_t
* and the API will internally adjust its input data processing based on the
* handle field hcrc->InputDataFormat.
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
{
uint32_t index; /* CRC input data buffer index */
uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
switch (hcrc->InputDataFormat)
{
case CRC_INPUTDATA_FORMAT_WORDS:
/* Enter Data to the CRC calculator */
for (index = 0U; index < BufferLength; index++)
{
hcrc->Instance->DR = pBuffer[index];
}
temp = hcrc->Instance->DR;
break;
case CRC_INPUTDATA_FORMAT_BYTES:
temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
break;
case CRC_INPUTDATA_FORMAT_HALFWORDS:
temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */
break;
default:
break;
}
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Return the CRC computed value */
return temp;
}
/**
* @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
* starting with hcrc->Instance->INIT as initialization value.
* @param hcrc CRC handle
* @param pBuffer pointer to the input data buffer, exact input data format is
* provided by hcrc->InputDataFormat.
* @param BufferLength input data buffer length (number of bytes if pBuffer
* type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
* number of words if pBuffer type is * uint32_t).
* @note By default, the API expects a uint32_t pointer as input buffer parameter.
* Input buffer pointers with other types simply need to be cast in uint32_t
* and the API will internally adjust its input data processing based on the
* handle field hcrc->InputDataFormat.
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
{
uint32_t index; /* CRC input data buffer index */
uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* Reset CRC Calculation Unit (hcrc->Instance->INIT is
* written in hcrc->Instance->DR) */
__HAL_CRC_DR_RESET(hcrc);
switch (hcrc->InputDataFormat)
{
case CRC_INPUTDATA_FORMAT_WORDS:
/* Enter 32-bit input data to the CRC calculator */
for (index = 0U; index < BufferLength; index++)
{
hcrc->Instance->DR = pBuffer[index];
}
temp = hcrc->Instance->DR;
break;
case CRC_INPUTDATA_FORMAT_BYTES:
/* Specific 8-bit input data handling */
temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
break;
case CRC_INPUTDATA_FORMAT_HALFWORDS:
/* Specific 16-bit input data handling */
temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */
break;
default:
break;
}
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Return the CRC computed value */
return temp;
}
/**
* @}
*/
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
* @brief Peripheral State functions.
*
@verbatim
===============================================================================
##### Peripheral State functions #####
===============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral.
@endverbatim
* @{
*/
/**
* @brief Return the CRC handle state.
* @param hcrc CRC handle
* @retval HAL state
*/
HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc)
{
/* Return CRC handle state */
return hcrc->State;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup CRC_Private_Functions
* @{
*/
/**
* @brief Enter 8-bit input data to the CRC calculator.
* Specific data handling to optimize processing time.
* @param hcrc CRC handle
* @param pBuffer pointer to the input data buffer
* @param BufferLength input data buffer length
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
{
uint32_t i; /* input data buffer index */
uint16_t data;
__IO uint16_t *pReg;
/* Processing time optimization: 4 bytes are entered in a row with a single word write,
* last bytes must be carefully fed to the CRC calculator to ensure a correct type
* handling by the peripheral */
for (i = 0U; i < (BufferLength / 4U); i++)
{
hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \
((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \
(uint32_t)pBuffer[(4U * i) + 3U];
}
/* last bytes specific handling */
if ((BufferLength % 4U) != 0U)
{
if ((BufferLength % 4U) == 1U)
{
*(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */
}
else if ((BufferLength % 4U) == 2U)
{
data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
*pReg = data;
}
else if ((BufferLength % 4U) == 3U)
{
data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
*pReg = data;
*(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */
}
else
{
/* Nothing to do */
}
}
/* Return the CRC computed value */
return hcrc->Instance->DR;
}
/**
* @brief Enter 16-bit input data to the CRC calculator.
* Specific data handling to optimize processing time.
* @param hcrc CRC handle
* @param pBuffer pointer to the input data buffer
* @param BufferLength input data buffer length
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
{
uint32_t i; /* input data buffer index */
__IO uint16_t *pReg;
/* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
* in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
* a correct type handling by the peripheral */
for (i = 0U; i < (BufferLength / 2U); i++)
{
hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U];
}
if ((BufferLength % 2U) != 0U)
{
pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
*pReg = pBuffer[2U * i];
}
/* Return the CRC computed value */
return hcrc->Instance->DR;
}
/**
* @}
*/
#endif /* HAL_CRC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
Drivers/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_crc_ex.c
+230
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@@ -0,0 +1,230 @@
/**
******************************************************************************
* @file stm32h7rsxx_hal_crc_ex.c
* @author MCD Application Team
* @brief Extended CRC HAL module driver.
* This file provides firmware functions to manage the extended
* functionalities of the CRC peripheral.
*
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
================================================================================
##### How to use this driver #####
================================================================================
[..]
(+) Set user-defined generating polynomial through HAL_CRCEx_Polynomial_Set()
(+) Configure Input or Output data inversion
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @defgroup CRCEx CRCEx
* @brief CRC Extended HAL module driver
* @{
*/
#ifdef HAL_CRC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions
* @{
*/
/** @defgroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
* @brief Extended Initialization and Configuration functions.
*
@verbatim
===============================================================================
##### Extended configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure the generating polynomial
(+) Configure the input data inversion
(+) Configure the output data inversion
@endverbatim
* @{
*/
/**
* @brief Initialize the CRC polynomial if different from default one.
* @param hcrc CRC handle
* @param Pol CRC generating polynomial (7, 8, 16 or 32-bit long).
* This parameter is written in normal representation, e.g.
* @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
* @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
* @param PolyLength CRC polynomial length.
* This parameter can be one of the following values:
* @arg @ref CRC_POLYLENGTH_7B 7-bit long CRC (generating polynomial of degree 7)
* @arg @ref CRC_POLYLENGTH_8B 8-bit long CRC (generating polynomial of degree 8)
* @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
* @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
/* Check the parameters */
assert_param(IS_CRC_POL_LENGTH(PolyLength));
/* Ensure that the generating polynomial is odd */
if ((Pol & (uint32_t)(0x1U)) == 0U)
{
status = HAL_ERROR;
}
else
{
/* check polynomial definition vs polynomial size:
* polynomial length must be aligned with polynomial
* definition. HAL_ERROR is reported if Pol degree is
* larger than that indicated by PolyLength.
* Look for MSB position: msb will contain the degree of
* the second to the largest polynomial member. E.g., for
* X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
{
}
switch (PolyLength)
{
case CRC_POLYLENGTH_7B:
if (msb >= HAL_CRC_LENGTH_7B)
{
status = HAL_ERROR;
}
break;
case CRC_POLYLENGTH_8B:
if (msb >= HAL_CRC_LENGTH_8B)
{
status = HAL_ERROR;
}
break;
case CRC_POLYLENGTH_16B:
if (msb >= HAL_CRC_LENGTH_16B)
{
status = HAL_ERROR;
}
break;
case CRC_POLYLENGTH_32B:
/* no polynomial definition vs. polynomial length issue possible */
break;
default:
status = HAL_ERROR;
break;
}
}
if (status == HAL_OK)
{
/* set generating polynomial */
WRITE_REG(hcrc->Instance->POL, Pol);
/* set generating polynomial size */
MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
}
/* Return function status */
return status;
}
/**
* @brief Set the Reverse Input data mode.
* @param hcrc CRC handle
* @param InputReverseMode Input Data inversion mode.
* This parameter can be one of the following values:
* @arg @ref CRC_INPUTDATA_INVERSION_NONE no change in bit order (default value)
* @arg @ref CRC_INPUTDATA_INVERSION_BYTE Byte-wise bit reversal
* @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal
* @arg @ref CRC_INPUTDATA_INVERSION_WORD Word-wise bit reversal
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
{
/* Check the parameters */
assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* set input data inversion mode */
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Set the Reverse Output data mode.
* @param hcrc CRC handle
* @param OutputReverseMode Output Data inversion mode.
* This parameter can be one of the following values:
* @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value)
* @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
{
/* Check the parameters */
assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* set output data inversion mode */
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode);
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_CRC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
Drivers/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_dma.c
+1755
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Drivers/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_dma2d.c
+2186
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Drivers/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_dma_ex.c
+4680
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File diff suppressed because it is too large. Load diff
Drivers/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_exti.c
+639
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@@ -0,0 +1,639 @@
/**
******************************************************************************
* @file stm32h7rsxx_hal_exti.c
* @author MCD Application Team
* @brief EXTI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (EXTI) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### EXTI Peripheral features #####
==============================================================================
[..]
(+) Each Exti line can be configured within this driver.
(+) Exti line can be configured in 3 different modes
(++) Interrupt
(++) Event
(++) Both of them
(+) Configurable Exti lines can be configured with 3 different triggers
(++) Rising
(++) Falling
(++) Both of them
(+) When set in interrupt mode, configurable Exti lines have two different
interrupts pending registers which allow to distinguish which transition
occurs:
(++) Rising edge pending interrupt
(++) Falling
(+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
be selected through multiplexer.
##### How to use this driver #####
==============================================================================
[..]
(#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
(++) Choose the interrupt line number by setting "Line" member from
EXTI_ConfigTypeDef structure.
(++) Configure the interrupt and/or event mode using "Mode" member from
EXTI_ConfigTypeDef structure.
(++) For configurable lines, configure rising and/or falling trigger
"Trigger" member from EXTI_ConfigTypeDef structure.
(++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
member from GPIO_InitTypeDef structure.
(#) Get current Exti configuration of a dedicated line using
HAL_EXTI_GetConfigLine().
(++) Provide exiting handle as parameter.
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
(++) Provide exiting handle as parameter.
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
(++) Provide exiting handle as first parameter.
(++) Provide which callback will be registered using one value from
EXTI_CallbackIDTypeDef.
(++) Provide callback function pointer.
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
(#) Clear interrupt pending bit using HAL_EXTI_GetPending().
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @addtogroup EXTI
* @{
*/
#ifdef HAL_EXTI_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private defines ------------------------------------------------------------*/
/** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{
*/
#define EXTI_MODE_OFFSET 0x04u /* 0x10: Offset between MCU IMRx/EMRx registers */
#define EXTI_CONFIG_OFFSET 0x08u /* 0x20: Offset between MCU Rising/Falling configuration registers */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup EXTI_Exported_Functions
* @{
*/
/** @addtogroup EXTI_Exported_Functions_Group1
* @brief Configuration functions
*
@verbatim
===============================================================================
##### Configuration functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Set configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @param pExtiConfig Pointer on EXTI configuration to be set.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti,const EXTI_ConfigTypeDef *pExtiConfig)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check null pointer */
if ((hexti == NULL) || (pExtiConfig == NULL))
{
return HAL_ERROR;
}
/* Check parameters */
assert_param(IS_EXTI_LINE(pExtiConfig->Line));
assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
/* Assign line number to handle */
hexti->Line = pExtiConfig->Line;
/* Compute line register offset and line mask */
offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* Configure triggers for configurable lines */
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
{
assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
/* Configure rising trigger */
regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store rising trigger mode */
*regaddr = regval;
/* Configure falling trigger */
regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store falling trigger mode */
*regaddr = regval;
/* Configure gpio port selection in case of gpio exti line */
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SBS->EXTICR[linepos >> 2u];
regval &= ~(SBS_EXTICR1_PC_EXTI0 << (SBS_EXTICR1_PC_EXTI1_Pos * (linepos & 0x03u)));
regval |= (pExtiConfig->GPIOSel << (SBS_EXTICR1_PC_EXTI1_Pos * (linepos & 0x03u)));
SBS->EXTICR[linepos >> 2u] = regval;
}
}
/* Configure interrupt mode : read current mode */
regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store interrupt mode */
*regaddr = regval;
/* The event mode cannot be configured if the line does not support it */
assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_EVENT) != EXTI_MODE_EVENT));
/* Configure event mode : read current mode */
regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store event mode */
*regaddr = regval;
return HAL_OK;
}
/**
* @brief Get configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @param pExtiConfig Pointer on structure to store Exti configuration.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{
const __IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check null pointer */
if ((hexti == NULL) || (pExtiConfig == NULL))
{
return HAL_ERROR;
}
/* Check the parameter */
assert_param(IS_EXTI_LINE(hexti->Line));
/* Store handle line number to configuration structure */
pExtiConfig->Line = hexti->Line;
/* Compute line register offset and line mask */
offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* 1] Get core mode : interrupt */
regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Check if selected line is enable */
if ((regval & maskline) != 0x00u)
{
pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
}
else
{
pExtiConfig->Mode = EXTI_MODE_NONE;
}
/* Get event mode */
regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Check if selected line is enable */
if ((regval & maskline) != 0x00u)
{
pExtiConfig->Mode |= EXTI_MODE_EVENT;
}
/* 2] Get trigger for configurable lines : rising */
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
{
regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Check if configuration of selected line is enable */
if ((regval & maskline) != 0x00u)
{
pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
}
else
{
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
}
/* Get falling configuration */
regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Check if configuration of selected line is enable */
if ((regval & maskline) != 0x00u)
{
pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
}
/* Get Gpio port selection for gpio lines */
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SBS->EXTICR[linepos >> 2u];
pExtiConfig->GPIOSel = (regval >> (SBS_EXTICR1_PC_EXTI1_Pos * (linepos & 0x03u))) & SBS_EXTICR1_PC_EXTI0;
}
else
{
pExtiConfig->GPIOSel = 0x00u;
}
}
else
{
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
pExtiConfig->GPIOSel = 0x00u;
}
return HAL_OK;
}
/**
* @brief Clear whole configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check null pointer */
if (hexti == NULL)
{
return HAL_ERROR;
}
/* Check the parameter */
assert_param(IS_EXTI_LINE(hexti->Line));
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (hexti->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* 1] Clear interrupt mode */
regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
/* 2] Clear event mode */
regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
/* 3] Clear triggers in case of configurable lines */
if ((hexti->Line & EXTI_CONFIG) != 0x00u)
{
regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
/* Get Gpio port selection for gpio lines */
if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SBS->EXTICR[linepos >> 2u];
regval &= ~(SBS_EXTICR1_PC_EXTI0 << (SBS_EXTICR1_PC_EXTI1_Pos * (linepos & 0x03u)));
SBS->EXTICR[linepos >> 2u] = regval;
}
}
return HAL_OK;
}
/**
* @brief Register callback for a dedicated Exti line.
* @param hexti Exti handle.
* @param CallbackID User callback identifier.
* This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
* @param pPendingCbfn function pointer to be stored as callback.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
{
HAL_StatusTypeDef status = HAL_OK;
switch (CallbackID)
{
case HAL_EXTI_COMMON_CB_ID:
hexti->PendingCallback = pPendingCbfn;
break;
default:
status = HAL_ERROR;
break;
}
return status;
}
/**
* @brief Store line number as handle private field.
* @param hexti Exti handle.
* @param ExtiLine Exti line number.
* This parameter can be from 0 to @ref EXTI_LINE_NB.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE(ExtiLine));
/* Check null pointer */
if (hexti == NULL)
{
return HAL_ERROR;
}
else
{
/* Store line number as handle private field */
hexti->Line = ExtiLine;
return HAL_OK;
}
}
/**
* @}
*/
/** @addtogroup EXTI_Exported_Functions_Group2
* @brief EXTI IO functions.
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Handle EXTI interrupt request.
* @param hexti Exti handle.
* @retval none.
*/
void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t maskline;
uint32_t offset;
/* Compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
/* Get pending bit */
regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
regval = (*regaddr & maskline);
if (regval != 0x00u)
{
/* Clear pending bit */
*regaddr = maskline;
/* Call callback */
if (hexti->PendingCallback != NULL)
{
hexti->PendingCallback();
}
}
}
/**
* @brief Get interrupt pending bit of a dedicated line.
* @param hexti Exti handle.
* @param Edge Specify which pending edge as to be checked.
* This parameter can be one of the following values:
* @arg @ref EXTI_TRIGGER_RISING_FALLING
* This parameter is kept for compatibility with other series.
* @retval 1 if interrupt is pending else 0.
*/
uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
const __IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
/* Prevent unused argument(s) compilation warning */
UNUSED(Edge);
/* Compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (hexti->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* Get pending bit */
regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
/* return 1 if bit is set else 0 */
regval = ((*regaddr & maskline) >> linepos);
return regval;
}
/**
* @brief Clear interrupt pending bit of a dedicated line.
* @param hexti Exti handle.
* @param Edge Specify which pending edge as to be clear.
* This parameter can be one of the following values:
* @arg @ref EXTI_TRIGGER_RISING_FALLING
* This parameter is kept for compatibility with other series.
* @retval None.
*/
void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
__IO uint32_t *regaddr;
uint32_t maskline;
uint32_t offset;
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
/* Prevent unused argument(s) compilation warning */
UNUSED(Edge);
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
/* Get pending register address */
regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
/* Clear Pending bit */
*regaddr = maskline;
}
/**
* @brief Generate a software interrupt for a dedicated line.
* @param hexti Exti handle.
* @retval None.
*/
void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t maskline;
uint32_t offset;
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
regaddr = (__IO uint32_t *)(&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset));
*regaddr = maskline;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_EXTI_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
Drivers/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_flash.c
+962
View File
@@ -0,0 +1,962 @@
/**
******************************************************************************
* @file stm32h7rsxx_hal_flash.c
* @author MCD Application Team
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
* + Program operations functions
* + Memory Control functions
* + Peripheral Errors functions
*
@verbatim
==============================================================================
##### FLASH peripheral features #####
==============================================================================
[..] The Flash memory interface manages CPU AHB C-Bus accesses to the Flash memory.
It implements the erase and program Flash memory operations and the read
and write protection mechanisms.
[..] The FLASH main features are:
(+) Flash memory read operations
(+) Flash memory program/erase operations
(+) Read / write protections
(+) Option bytes programming
(+) Error code correction (ECC) : Data in flash are 137-bits word
(9 bits added per quad-word)
##### How to use this driver #####
==============================================================================
[..]
This driver provides functions and macros to configure and program the FLASH
memory of all STM32H7RSxx devices.
(#) Flash Memory IO Programming functions:
(++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
HAL_FLASH_Lock() functions
(++) Program functions: bytes, half-words, words, double-words and quad-words
(++) There are two modes of programming :
(+++) Polling mode using HAL_FLASH_Program() function
(+++) Interrupt mode using HAL_FLASH_Program_IT() function
(#) Interrupts and flags management functions :
(++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
(++) Callback functions are called when the flash operations are finished :
HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
HAL_FLASH_OperationErrorCallback()
(++) Get error flag status by calling HAL_GetError()
(#) Option bytes management functions :
(++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
HAL_FLASH_OB_Lock() functions
(++) Launch the reload of the option bytes using HAL_FLASH_Launch() function.
In this case, a reset is generated
[..]
In addition to these functions, this driver includes a set of macros allowing
to handle the following operations:
(+) Set the latency
(+) Enable/Disable the Flash interrupts
(+) Monitor the Flash flags status
@endverbatim
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @defgroup FLASH FLASH
* @brief FLASH HAL module driver
* @{
*/
#ifdef HAL_FLASH_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup FLASH_Private_Variables FLASH Private Variables
* @{
*/
/**
* @brief Variable used for Program/Erase sectors under interruption
*/
FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED, \
.ErrorCode = HAL_FLASH_ERROR_NONE, \
.ProcedureOnGoing = 0U, \
.Address = 0U, \
.Sector = 0U, \
.NbSectorsToErase = 0U
};
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup FLASH_Private_Functions FLASH Private Functions
* @{
*/
static void FLASH_Program_Byte(uint32_t Address, uint32_t DataAddress);
static void FLASH_Program_HalfWord(uint32_t Address, uint32_t DataAddress);
static void FLASH_Program_Word(uint32_t Address, uint32_t DataAddress);
static void FLASH_Program_DoubleWord(uint32_t Address, uint32_t DataAddress);
static void FLASH_Program_QuadWord(uint32_t Address, uint32_t DataAddress);
static void FLASH_Program_OTPHalfWord(uint32_t Address, uint32_t DataAddress);
static void FLASH_Program_OTPWord(uint32_t Address, uint32_t DataAddress);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
* @{
*/
/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
* @brief Programming operation functions
*
@verbatim
===============================================================================
##### Programming operation functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to manage the FLASH
program operations.
@endverbatim
* @{
*/
/**
* @brief Program a data at a specified address.
* @param TypeProgram Indicate the way to program at a specified address.
* This parameter can be a value of @ref FLASH_Type_Program
* @param Address specifies the address to be programmed.
* @param DataAddress specifies the address of data to be programmed.
*
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress)
{
HAL_StatusTypeDef status;
/* Check the parameters */
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
/* Process Locked */
__HAL_LOCK(&pFlash);
/* Reset error code */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
if (status == HAL_OK)
{
switch (TypeProgram)
{
case FLASH_TYPEPROGRAM_BYTE:
/* Program a byte (8-bit) at a specified address */
FLASH_Program_Byte(Address, DataAddress);
break;
case FLASH_TYPEPROGRAM_HALFWORD:
/* Program a half-word (16-bit) at a specified address */
FLASH_Program_HalfWord(Address, DataAddress);
break;
case FLASH_TYPEPROGRAM_WORD:
/* Program a word (32-bit) at a specified address */
FLASH_Program_Word(Address, DataAddress);
break;
case FLASH_TYPEPROGRAM_DOUBLEWORD:
/* Program a double-word (64-bit) at a specified address */
FLASH_Program_DoubleWord(Address, DataAddress);
break;
case FLASH_TYPEPROGRAM_QUADWORD:
/* Program a quad-word (128-bit) at a specified address */
FLASH_Program_QuadWord(Address, DataAddress);
break;
case FLASH_TYPEPROGRAM_OTP_HALFWORD:
/* Program a half-word (16-bit) at a OTP address */
FLASH_Program_OTPHalfWord(Address, DataAddress);
break;
case FLASH_TYPEPROGRAM_OTP_WORD:
/* Program a word (32-bit) at a OTP address */
FLASH_Program_OTPWord(Address, DataAddress);
break;
default:
status = HAL_ERROR;
break;
}
if (status != HAL_ERROR)
{
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
/* If the program operation is completed, disable the PG (and FW Bit in non quad-word mode) */
CLEAR_BIT(FLASH->CR, (TypeProgram & ~(FLASH_WORD_SIZE_MASK)));
}
}
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
/* return status */
return status;
}
/**
* @brief Program a data at a specified address with interrupt enabled.
* @param TypeProgram Indicate the way to program at a specified address.
* This parameter can be a value of @ref FLASH_Type_Program
* @param Address specifies the address to be programmed.
* @param DataAddress specifies the address of data to be programmed
*
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress)
{
HAL_StatusTypeDef status;
/* Check the parameters */
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
/* Process Locked */
__HAL_LOCK(&pFlash);
/* Reset error code */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
if (status != HAL_OK)
{
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
}
else
{
/* Set internal variables used by the IRQ handler */
pFlash.ProcedureOnGoing = TypeProgram;
pFlash.Address = Address;
/* Enable End of Operation and Error interrupts */
SET_BIT(FLASH->IER, (FLASH_IT_EOP | FLASH_IT_WRPERR | FLASH_IT_PGSERR | FLASH_IT_STRBERR | FLASH_IT_INCERR));
switch (TypeProgram)
{
case FLASH_TYPEPROGRAM_BYTE:
/* Program a byte (8-bit) at a specified address */
FLASH_Program_Byte(Address, DataAddress);
break;
case FLASH_TYPEPROGRAM_HALFWORD:
/* Program a half-word (16-bit) at a specified address */
FLASH_Program_HalfWord(Address, DataAddress);
break;
case FLASH_TYPEPROGRAM_WORD:
/* Program a word (32-bit) at a specified address */
FLASH_Program_Word(Address, DataAddress);
break;
case FLASH_TYPEPROGRAM_DOUBLEWORD:
/* Program a double-word (64-bit) at a specified address */
FLASH_Program_DoubleWord(Address, DataAddress);
break;
case FLASH_TYPEPROGRAM_QUADWORD:
/* Program a quad-word (128-bit) at a specified address */
FLASH_Program_QuadWord(Address, DataAddress);
break;
case FLASH_TYPEPROGRAM_OTP_HALFWORD:
/* Program a half-word (16-bit) at a OTP address */
FLASH_Program_OTPHalfWord(Address, DataAddress);
break;
case FLASH_TYPEPROGRAM_OTP_WORD:
/* Program a word (32-bit) at a OTP address */
FLASH_Program_OTPWord(Address, DataAddress);
break;
default:
status = HAL_ERROR;
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
break;
}
}
return status;
}
/**
* @brief Handle FLASH interrupt request.
* @retval None
*/
void HAL_FLASH_IRQHandler(void)
{
uint32_t param = 0U;
uint32_t error;
/* Save Flash errors */
error = FLASH->ISR & FLASH_FLAG_ISR_ERRORS;
error |= (FLASH->OPTISR & FLASH_FLAG_OPTISR_ERRORS);
/* Set parameter of the callback */
if (pFlash.ProcedureOnGoing == FLASH_TYPEERASE_SECTORS)
{
param = pFlash.Sector;
}
else if ((pFlash.ProcedureOnGoing & FLASH_CR_PG) != 0U)
{
param = pFlash.Address;
}
else
{
/* Empty statement (to be compliant MISRA 15.7) */
}
/* Clear operation bit on the on-going procedure */
CLEAR_BIT(FLASH->CR, (pFlash.ProcedureOnGoing & ~(FLASH_WORD_SIZE_MASK)));
/* Check FLASH operation error flags */
if (error != 0U)
{
/* Save the error code */
pFlash.ErrorCode |= error;
/* Clear error programming flags */
FLASH->ICR = (error & FLASH_FLAG_ISR_ERRORS);
FLASH->OPTICR = (error & FLASH_FLAG_OPTISR_ERRORS);
/* Stop the procedure ongoing */
pFlash.ProcedureOnGoing = 0U;
/* FLASH error interrupt user callback */
HAL_FLASH_OperationErrorCallback(param);
}
/* Check FLASH End of Operation flag */
if ((FLASH->ISR & FLASH_FLAG_EOP) != 0U)
{
/* Clear FLASH End of Operation pending bit */
FLASH->ICR = FLASH_FLAG_EOP;
if (pFlash.ProcedureOnGoing == FLASH_TYPEERASE_SECTORS)
{
/* Nb of sectors to erase can be decreased */
pFlash.NbSectorsToErase--;
/* Check if there are still sectors to erase */
if (pFlash.NbSectorsToErase != 0U)
{
/* Increment sector number */
pFlash.Sector++;
FLASH_SectorErase(pFlash.Sector);
}
else
{
/* No more sectors to Erase */
pFlash.ProcedureOnGoing = 0U;
param = 0xFFFFFFFFU;
}
}
else
{
/*Clear the procedure ongoing*/
pFlash.ProcedureOnGoing = 0U;
}
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(param);
}
if (pFlash.ProcedureOnGoing == 0U)
{
/* Disable End of Operation and Error interrupts */
CLEAR_BIT(FLASH->IER, (FLASH_IT_EOP | FLASH_IT_WRPERR | FLASH_IT_PGSERR | FLASH_IT_STRBERR | FLASH_IT_INCERR));
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
}
/* Check ECC Correction Error */
if ((FLASH->IER & FLASH_IT_SNECCERR) != 0U)
{
if ((FLASH->ISR & FLASH_FLAG_SNECCERR) != 0U)
{
/* Call User callback */
HAL_FLASHEx_EccCorrectionCallback();
/* Clear ECC correction flag in order to allow new ECC error record */
FLASH->ICR = FLASH_FLAG_SNECCERR;
}
}
/* Check ECC Detection Error */
if ((FLASH->IER & FLASH_IT_DBECCERR) != 0U)
{
if ((FLASH->ISR & FLASH_FLAG_DBECCERR) != 0U)
{
/* Call User callback */
HAL_FLASHEx_EccDetectionCallback();
/* Clear ECC detection flag in order to allow new ECC error record */
FLASH->ICR = FLASH_FLAG_DBECCERR;
}
}
}
/**
* @brief FLASH end of operation interrupt callback.
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure
* Mass Erase: Bank number which has been requested to erase
* Sector Erase: Sector which has been erased
* (if 0xFFFFFFFF, it means that all the selected sectors have been erased)
* Program: Address which was selected for data program
* @retval None
*/
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(ReturnValue);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
*/
}
/**
* @brief FLASH operation error interrupt callback.
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure
* Mass Erase: Bank number which has been requested to erase
* Sector Erase: Sector number which returned an error
* Program: Address which was selected for data program
* @retval None
*/
__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(ReturnValue);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_FLASH_OperationErrorCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
* @brief Management functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the FLASH
memory operations.
@endverbatim
* @{
*/
/**
* @brief Unlock the FLASH control register access.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
{
if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
{
/* Authorize the FLASH Registers access */
WRITE_REG(FLASH->KEYR, FLASH_KEY1);
WRITE_REG(FLASH->KEYR, FLASH_KEY2);
/* verify Flash is unlocked */
if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
{
return HAL_ERROR;
}
}
return HAL_OK;
}
/**
* @brief Lock the FLASH control register access.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Lock(void)
{
/* Set the LOCK Bit to lock the FLASH Registers access */
SET_BIT(FLASH->CR, FLASH_CR_LOCK);
/* verify Flash is locked */
if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
{
return HAL_OK;
}
return HAL_ERROR;
}
/**
* @brief Unlock the FLASH Option Bytes Registers access.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
{
if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != 0U)
{
/* Authorizes the Option Byte register programming */
WRITE_REG(FLASH->OPTKEYR, FLASH_OPT_KEY1);
WRITE_REG(FLASH->OPTKEYR, FLASH_OPT_KEY2);
/* Verify that the Option Bytes are unlocked */
if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != 0U)
{
return HAL_ERROR;
}
}
return HAL_OK;
}
/**
* @brief Lock the FLASH Option Bytes Registers access.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
{
/* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
SET_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK);
/* Verify that the Option Bytes are locked */
if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != 0U)
{
return HAL_OK;
}
return HAL_ERROR;
}
/**
* @}
*/
/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief Peripheral Errors functions
*
@verbatim
===============================================================================
##### Peripheral Errors functions #####
===============================================================================
[..]
This subsection permits to get in run-time Errors of the FLASH peripheral.
@endverbatim
* @{
*/
/**
* @brief Get the specific FLASH error flag.
* @retval FLASH_ErrorCode The returned value can be:
* @arg HAL_FLASH_ERROR_NONE: No error set
* @arg HAL_FLASH_ERROR_WRP: FLASH Write protection error
* @arg HAL_FLASH_ERROR_PGS: FLASH Programming sequence error
* @arg HAL_FLASH_ERROR_STRB: FLASH Strobe error
* @arg HAL_FLASH_ERROR_INC: FLASH Inconsistency error
* @arg HAL_FLASH_ERROR_RDS: FLASH Read security error
* @arg HAL_FLASH_ERROR_SNECC: FLASH ECC single error
* @arg HAL_FLASH_ERROR_DBECC: FLASH ECC double error
* @arg HAL_FLASH_ERROR_CRC: FLASH CRC error
* @arg HAL_FLASH_ERROR_KDR: FLASH Key data register error
* @arg HAL_FLASH_ERROR_OBC: FLASH Options byte change error
*/
uint32_t HAL_FLASH_GetError(void)
{
return pFlash.ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @addtogroup FLASH_Private_Functions
* @{
*/
/**
* @brief Wait for a FLASH operation to complete.
* @param Timeout maximum flash operation timeout
* @retval HAL Status
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
{
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
Even if the FLASH operation fails, the BUSY flag will be reset and an error
flag will be set */
uint32_t tickstart = HAL_GetTick();
uint32_t error;
while ((FLASH->SR & FLASH_SR_QW) != 0U)
{
if (Timeout != HAL_MAX_DELAY)
{
if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
return HAL_TIMEOUT;
}
}
}
/* Check FLASH operation error flags */
error = (FLASH->ISR & FLASH_FLAG_ISR_ERRORS);
error |= (FLASH->OPTISR & FLASH_FLAG_OPTISR_ERRORS);
if (error != 0U)
{
/*Save the error code*/
pFlash.ErrorCode |= error;
/* Clear error programming flags */
FLASH->ICR = (error & FLASH_FLAG_ISR_ERRORS);
FLASH->OPTICR = (error & FLASH_FLAG_OPTISR_ERRORS);
return HAL_ERROR;
}
/* Check FLASH End of Operation flag */
if ((FLASH->ISR & FLASH_FLAG_EOP) != 0U)
{
/* Clear FLASH End of Operation pending bit */
FLASH->ICR = FLASH_FLAG_EOP;
}
/* If there is no error flag set */
return HAL_OK;
}
/**
* @brief Program a byte (8-bit) at a specified address.
* @param Address specifies the address to be programmed.
* @param DataAddress specifies the address of data to be programmed.
* @retval None
*/
static void FLASH_Program_Byte(uint32_t Address, uint32_t DataAddress)
{
uint8_t *dest_addr = (uint8_t *)Address;
uint8_t *src_addr = (uint8_t *)DataAddress;
uint32_t primask_bit;
/* Check the parameters */
assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address));
/* Set PG bit */
SET_BIT(FLASH->CR, FLASH_CR_PG);
/* Enter critical section: Disable interrupts to avoid any interruption during the loop */
primask_bit = __get_PRIMASK();
__disable_irq();
/* Program the byte */
*dest_addr = *src_addr;
__ISB();
__DSB();
/* Set FW bit */
SET_BIT(FLASH->CR, FLASH_CR_FW);
/* Exit critical section: restore previous priority mask */
__set_PRIMASK(primask_bit);
}
/**
* @brief Program a half-word (16-bit) at a specified address.
* @param Address specifies the address to be programmed.
* @param DataAddress specifies the address of data to be programmed.
* @retval None
*/
static void FLASH_Program_HalfWord(uint32_t Address, uint32_t DataAddress)
{
uint16_t *dest_addr = (uint16_t *)Address;
uint16_t *src_addr = (uint16_t *)DataAddress;
uint32_t primask_bit;
/* Check the parameters */
assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address));
/* Set PG bit */
SET_BIT(FLASH->CR, FLASH_CR_PG);
/* Enter critical section: Disable interrupts to avoid any interruption during the loop */
primask_bit = __get_PRIMASK();
__disable_irq();
/* Program the half-word */
*dest_addr = *src_addr;
__ISB();
__DSB();
/* Set FW bit */
SET_BIT(FLASH->CR, FLASH_CR_FW);
/* Exit critical section: restore previous priority mask */
__set_PRIMASK(primask_bit);
}
/**
* @brief Program a word (32-bit) at a specified address.
* @param Address specifies the address to be programmed.
* @param DataAddress specifies the address of data to be programmed.
* @retval None
*/
static void FLASH_Program_Word(uint32_t Address, uint32_t DataAddress)
{
uint8_t index = 2;
uint16_t *dest_addr = (uint16_t *)Address;
uint16_t *src_addr = (uint16_t *)DataAddress;
uint32_t primask_bit;
/* Check the parameters */
assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address));
/* Set PG bit */
SET_BIT(FLASH->CR, FLASH_CR_PG);
/* Enter critical section: Disable interrupts to avoid any interruption during the loop */
primask_bit = __get_PRIMASK();
__disable_irq();
/* Program the word */
do
{
*dest_addr = *src_addr;
dest_addr++;
src_addr++;
index--;
} while (index != 0U);
__ISB();
__DSB();
/* Set FW bit */
SET_BIT(FLASH->CR, FLASH_CR_FW);
/* Exit critical section: restore previous priority mask */
__set_PRIMASK(primask_bit);
}
/**
* @brief Program a double-word (64-bit) at a specified address.
* @param Address specifies the address to be programmed.
* @param DataAddress specifies the address of data to be programmed.
* @retval None
*/
static void FLASH_Program_DoubleWord(uint32_t Address, uint32_t DataAddress)
{
uint8_t index = 4;
uint16_t *dest_addr = (uint16_t *)Address;
uint16_t *src_addr = (uint16_t *)DataAddress;
uint32_t primask_bit;
/* Check the parameters */
assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address));
/* Set PG bit */
SET_BIT(FLASH->CR, FLASH_CR_PG);
/* Enter critical section: Disable interrupts to avoid any interruption during the loop */
primask_bit = __get_PRIMASK();
__disable_irq();
/* Program the double-word */
do
{
*dest_addr = *src_addr;
dest_addr++;
src_addr++;
index--;
} while (index != 0U);
__ISB();
__DSB();
/* Set FW bit */
SET_BIT(FLASH->CR, FLASH_CR_FW);
/* Exit critical section: restore previous priority mask */
__set_PRIMASK(primask_bit);
}
/**
* @brief Program a quad-word (128-bit) at a specified address.
* @param Address specifies the address to be programmed.
* @param DataAddress specifies the address of data to be programmed.
* @retval None
*/
static void FLASH_Program_QuadWord(uint32_t Address, uint32_t DataAddress)
{
uint8_t index = 8;
uint16_t *dest_addr = (uint16_t *)Address;
uint16_t *src_addr = (uint16_t *)DataAddress;
uint32_t primask_bit;
/* Check the parameters */
assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address));
/* Set PG bit */
SET_BIT(FLASH->CR, FLASH_CR_PG);
/* Enter critical section: Disable interrupts to avoid any interruption during the loop */
primask_bit = __get_PRIMASK();
__disable_irq();
/* Program the quad-word */
do
{
*dest_addr = *src_addr;
dest_addr++;
src_addr++;
index--;
} while (index != 0U);
__ISB();
__DSB();
/* Exit critical section: restore previous priority mask */
__set_PRIMASK(primask_bit);
}
/**
* @brief Program a half-word (16-bit) at a OTP address.
* @param Address specifies the address to be programmed.
* @param DataAddress specifies the address of data to be programmed.
* @retval None
*/
static void FLASH_Program_OTPHalfWord(uint32_t Address, uint32_t DataAddress)
{
uint16_t *dest_addr = (uint16_t *)Address;
uint16_t *src_addr = (uint16_t *)DataAddress;
uint32_t primask_bit;
/* Check the parameters */
assert_param(IS_FLASH_OTP_ADDRESS(Address));
/* Set PG_OTP bit */
SET_BIT(FLASH->CR, FLASH_CR_PG_OTP);
/* Enter critical section: Disable interrupts to avoid any interruption during the loop */
primask_bit = __get_PRIMASK();
__disable_irq();
/* Program the half-word */
*dest_addr = *src_addr;
__ISB();
__DSB();
/* Set FW bit */
SET_BIT(FLASH->CR, FLASH_CR_FW);
/* Exit critical section: restore previous priority mask */
__set_PRIMASK(primask_bit);
}
/**
* @brief Program a word (32-bit) at a OTP address.
* @param Address specifies the address to be programmed.
* @param DataAddress specifies the address of data to be programmed.
* @retval None
*/
static void FLASH_Program_OTPWord(uint32_t Address, uint32_t DataAddress)
{
uint8_t index = 2;
uint16_t *dest_addr = (uint16_t *)Address;
uint16_t *src_addr = (uint16_t *)DataAddress;
uint32_t primask_bit;
/* Check the parameters */
assert_param(IS_FLASH_OTP_ADDRESS(Address));
/* Set PG_OTP bit */
SET_BIT(FLASH->CR, FLASH_CR_PG_OTP);
/* Enter critical section: Disable interrupts to avoid any interruption during the loop */
primask_bit = __get_PRIMASK();
__disable_irq();
/* Program the word */
do
{
*dest_addr = *src_addr;
dest_addr++;
src_addr++;
index--;
} while (index != 0U);
__ISB();
__DSB();
/* Set FW bit */
SET_BIT(FLASH->CR, FLASH_CR_FW);
/* Exit critical section: restore previous priority mask */
__set_PRIMASK(primask_bit);
}
/**
* @}
*/
#endif /* HAL_FLASH_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
Drivers/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_flash_ex.c
+1322
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Drivers/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_gpio.c
+556
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/**
******************************************************************************
* @file stm32h7rsxx_hal_gpio.c
* @author MCD Application Team
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### GPIO Peripheral features #####
==============================================================================
[..]
(+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
configured by software in several modes:
(++) Input mode
(++) Analog mode
(++) Output mode
(++) Alternate function mode
(++) External interrupt/event lines
(+) During and just after reset, the alternate functions and external interrupt
lines are not active and the I/O ports are configured in input floating mode.
(+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
activated or not.
(+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
type and the IO speed can be selected depending on the VDD value.
(+) The microcontroller IO pins are connected to onboard peripherals/modules through a
multiplexer that allows only one peripheral alternate function (AF) connected
to an IO pin at a time. In this way, there can be no conflict between peripherals
sharing the same IO pin.
(+) All ports have external interrupt/event capability. To use external interrupt
lines, the port must be configured in input mode. All available GPIO pins are
connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
(+) The external interrupt/event controller consists of up to 39 edge detectors
(16 lines are connected to GPIO) for generating event/interrupt requests (each
input line can be independently configured to select the type (interrupt or event)
and the corresponding trigger event (rising or falling or both). Each line can
also be masked independently.
##### How to use this driver #####
==============================================================================
[..]
(#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
(#) Configure the GPIO pin(s) using HAL_GPIO_Init().
(++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
(++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
structure.
(++) In case of Output or alternate function mode selection: the speed is
configured through "Speed" member from GPIO_InitTypeDef structure.
(++) In alternate mode is selection, the alternate function connected to the IO
is configured through "Alternate" member from GPIO_InitTypeDef structure.
(++) Analog mode is required when a pin is to be used as ADC channel
or DAC output.
(++) In case of external interrupt/event selection the "Mode" member from
GPIO_InitTypeDef structure select the type (interrupt or event) and
the corresponding trigger event (rising or falling or both).
(#) In case of external interrupt mode selection, configure NVIC IRQ priority
mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
HAL_NVIC_EnableIRQ().
(#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
(#) To set/reset the level of a pin configured in output mode use
HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
(#) To set the level of several pins and reset level of several other pins in
same cycle, use HAL_GPIO_WriteMultipleStatePin().
(#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
(#) During and just after reset, the alternate functions are not
active and the GPIO pins are configured in input floating mode (except JTAG
pins).
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
(PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
priority over the GPIO function.
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
The HSE has priority over the GPIO function.
@endverbatim
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @addtogroup GPIO
* @{
*/
/** MISRA C:2012 deviation rule has been granted for following rules:
* Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of
* range of the shift operator in following API :
* HAL_GPIO_Init
* HAL_GPIO_DeInit
*/
#ifdef HAL_GPIO_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private defines ------------------------------------------------------------*/
/** @addtogroup GPIO_Private_Constants
* @{
*/
#define GPIO_NUMBER (16U)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup GPIO_Exported_Functions
* @{
*/
/** @addtogroup GPIO_Exported_Functions_Group1
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
* @param GPIOx where x can be (A..H and M..P) to select the GPIO peripheral for STM32H7RSxx family
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init)
{
uint32_t position = 0x00U;
uint32_t iocurrent;
uint32_t temp;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00U)
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1UL << position);
if (iocurrent != 0x00U)
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos));
temp |= (GPIO_Init->Speed << (position * GPIO_OSPEEDR_OSPEED1_Pos));
GPIOx->OSPEEDR = temp;
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
temp &= ~(GPIO_OTYPER_OT0 << position) ;
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
GPIOx->OTYPER = temp;
}
if (((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) ||
(((GPIO_Init->Mode & GPIO_MODE) == MODE_ANALOG) && (GPIO_Init->Pull != GPIO_PULLUP)))
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
temp &= ~(GPIO_PUPDR_PUPD0 << (position * GPIO_PUPDR_PUPD1_Pos));
temp |= ((GPIO_Init->Pull) << (position * GPIO_PUPDR_PUPD1_Pos));
GPIOx->PUPDR = temp;
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
temp &= ~(0xFuL << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos));
temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos));
GPIOx->AFR[position >> 3U] = temp;
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
temp &= ~(GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos));
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * GPIO_MODER_MODE1_Pos));
GPIOx->MODER = temp;
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
{
temp = SBS->EXTICR[position >> 2U];
temp &= ~(0x0FuL << ((position & 0x03U) * SBS_EXTICR1_PC_EXTI1_Pos));
temp |= (GPIO_GET_INDEX(GPIOx) << ((position & 0x03U) * SBS_EXTICR1_PC_EXTI1_Pos));
SBS->EXTICR[position >> 2U] = temp;
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR1;
temp &= ~(iocurrent);
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
{
temp |= iocurrent;
}
EXTI->RTSR1 = temp;
temp = EXTI->FTSR1;
temp &= ~(iocurrent);
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
{
temp |= iocurrent;
}
EXTI->FTSR1 = temp;
/* Clear EXTI line configuration */
temp = EXTI->EMR1;
temp &= ~(iocurrent);
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
{
temp |= iocurrent;
}
EXTI->EMR1 = temp;
temp = EXTI->IMR1;
temp &= ~(iocurrent);
if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
{
temp |= iocurrent;
}
EXTI->IMR1 = temp;
}
}
position++;
}
}
/**
* @brief Reset the configuration of a pin or a set of pins for a GPIO port to the default one.
* @param GPIOx where x can be (A..H and M..P) to select the GPIO peripheral for STM32H7RSxx family
* @param GPIO_Pin specifies the port bit to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
*/
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
{
uint32_t position = 0x00U;
uint32_t iocurrent;
uint32_t tmp;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* Configure the port pins */
while ((GPIO_Pin >> position) != 0x00U)
{
/* Get current io position */
iocurrent = (GPIO_Pin) & (1UL << position);
if (iocurrent != 0x00U)
{
/*------------------------- EXTI Mode Configuration --------------------*/
/* Clear the External Interrupt or Event for the current IO */
tmp = SBS->EXTICR[position >> 2U];
tmp &= (0x0FuL << ((position & 0x03U) * SBS_EXTICR1_PC_EXTI1_Pos));
if (tmp == (GPIO_GET_INDEX(GPIOx) << ((position & 0x03U) * SBS_EXTICR1_PC_EXTI1_Pos)))
{
/* Clear EXTI line configuration */
EXTI->IMR1 &= ~(iocurrent);
EXTI->EMR1 &= ~(iocurrent);
/* Clear Rising Falling edge configuration */
EXTI->FTSR1 &= ~(iocurrent);
EXTI->RTSR1 &= ~(iocurrent);
/* Clear EXTICR configuration */
tmp = 0x0FuL << ((position & 0x03U) * SBS_EXTICR1_PC_EXTI1_Pos);
SBS->EXTICR[position >> 2U] &= ~tmp;
}
/*------------------------- GPIO Mode Configuration --------------------*/
/* Configure IO in Analog Mode */
GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos));
/* Configure the default Alternate Function in current IO */
GPIOx->AFR[position >> 3U] &= ~(0xFuL << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)) ;
/* Configure the default value for IO Speed */
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos));
/* Configure the default value IO Output Type */
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ;
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * GPIO_PUPDR_PUPD1_Pos));
}
position++;
}
}
/**
* @}
*/
/** @addtogroup GPIO_Exported_Functions_Group2
* @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Read the specified input port pin.
* @param GPIOx where x can be (A..H and M..P) to select the GPIO peripheral for STM32H7RSxx family
* @param GPIO_Pin specifies the port bit to read.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != 0x00U)
{
bitstatus = GPIO_PIN_SET;
}
else
{
bitstatus = GPIO_PIN_RESET;
}
return bitstatus;
}
/**
* @brief Set or clear the selected data port bit.
* @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
* accesses. In this way, there is no risk of an IRQ occurring between
* the read and the modify access.
* @param GPIOx where x can be (A..H and M..P) to select the GPIO peripheral for STM32H7RSxx family
* @param GPIO_Pin specifies the port bit to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @param PinState specifies the value to be written to the selected bit.
* This parameter can be one of the GPIO_PinState enum values:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
/**
* @brief Set and clear several pins of a dedicated port in same cycle.
* @param GPIOx where x can be (A..H and M..P) to select the GPIO peripheral for STM32H7RSxx family
* @param PinReset specifies the port bits to be reset
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero.
* @param PinSet specifies the port bits to be set
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero.
* @note Both PinReset and PinSet combinations shall not get any common bit, else
* assert would be triggered.
* @note At least one of the two parameters used to set or reset shall be different from zero.
* @retval None
*/
void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet)
{
uint32_t tmp;
/* Check the parameters */
/* Make sure at least one parameter is different from zero and that there is no common pin */
assert_param(IS_GPIO_PIN((uint32_t)PinReset | (uint32_t)PinSet));
assert_param(IS_GPIO_COMMON_PIN(PinReset, PinSet));
tmp = (((uint32_t)PinReset << 16) | PinSet);
GPIOx->BSRR = tmp;
}
/**
* @brief Toggle the specified GPIO pin.
* @param GPIOx where x can be (A..H and M..P) to select the GPIO peripheral for STM32H7RSxx family
* @param GPIO_Pin specifies the pin to be toggled.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
uint32_t odr;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* get current Output Data Register value */
odr = GPIOx->ODR;
/* Set selected pins that were at low level, and reset ones that were high */
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
}
/**
* @brief Lock GPIO Pins configuration registers.
* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
* @note The configuration of the locked GPIO pins can no longer be modified
* until the next reset.
* @param GPIOx where x can be (A..H and M..P) to select the GPIO peripheral for STM32H7RSxx family
* @param GPIO_Pin specifies the port bits to be locked.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
*/
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
__IO uint32_t tmp = GPIO_LCKR_LCKK;
/* Check the parameters */
assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* Apply lock key write sequence */
tmp |= GPIO_Pin;
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
GPIOx->LCKR = tmp;
/* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
GPIOx->LCKR = GPIO_Pin;
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
GPIOx->LCKR = tmp;
/* Read LCKK register. This read is mandatory to complete key lock sequence */
tmp = GPIOx->LCKR;
/* read again in order to confirm lock is active */
if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00U)
{
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @brief Handle EXTI interrupt request.
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
{
/* EXTI line interrupt detected */
if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0U)
{
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
HAL_GPIO_EXTI_Callback(GPIO_Pin);
}
}
/**
* @brief EXTI line detection callback.
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(GPIO_Pin);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_GPIO_EXTI_Callback could be implemented in the user file
*/
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_GPIO_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
Drivers/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_gpu2d.c
+750
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@@ -0,0 +1,750 @@
/**
******************************************************************************
* @file stm32h7rsxx_hal_gpu2d.c
* @author MCD Application Team
* @brief GPU2D HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the GPU2D peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral State and Errors functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
(#) Peripheral control is exclusively done by the accompanying middleware library.
*** Interrupt mode IO operation ***
===================================
[..]
(#) Configure the GPU2D hardware to perform graphics operation using the Third Party MW
Library APIs.
(#) Submit command List to the hardware.
(#) Wait indefinitely for the completion of submitted Command List by GPU2D hardware.
(#) Use HAL_GPU2D_IRQHandler() called under GPU2D_IRQHandler() interrupt subroutine.
(#) At the end of Command List execution HAL_GPU2D_IRQHandler() function is executed
and user can add his own function by customization of function pointer
(#) CommandListCpltCallback (member of GPU2D handle structure) to notify the upper level
about the completion of Command List execution.
(#) Callback HAL_GPU2D_CommandListCpltCallback is invoked when the GPU2D hardware executes
the programmed command list (Command List execution completion).
(++) This callback is called when the compilation defines USE_HAL_GPU2D_REGISTER_CALLBACKS
is set to 0 or not defined.
(++) This callback should be implemented in the application side. It should notify
the upper level that the programmed command list is completed.
(#) To control the GPU2D state, use the following function: HAL_GPU2D_GetState().
(#) To read the GPU2D error code, use the following function: HAL_GPU2D_GetError().
*** GPU2D HAL driver macros list ***
=============================================
[..]
Below the list of most used macros in GPU2D HAL driver :
(+) __HAL_GPU2D_RESET_HANDLE_STATE: Reset GPU2D handle state.
(+) __HAL_GPU2D_GET_FLAG: Get the GPU2D pending flags.
(+) __HAL_GPU2D_CLEAR_FLAG: Clear the GPU2D pending flags.
(+) __HAL_GPU2D_GET_IT_SOURCE: Check whether the specified GPU2D interrupt is enabled or not.
*** Callback registration ***
===================================
[..]
(#) The compilation define USE_HAL_GPU2D_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use function @ref HAL_GPU2D_RegisterCallback() to register a user callback.
(#) Function @ref HAL_GPU2D_RegisterCallback() allows to register following callbacks:
(+) CommandListCpltCallback : callback for Command List completion.
(+) MspInitCallback : GPU2D MspInit.
(+) MspDeInitCallback : GPU2D MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
(#) Use function @ref HAL_GPU2D_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
@ref HAL_GPU2D_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) CommandListCpltCallback : callback for Command List completion.
(+) MspInitCallback : GPU2D MspInit.
(+) MspDeInitCallback : GPU2D MspDeInit.
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_GPU2D_RegisterCallback before calling @ref HAL_GPU2D_DeInit
or @ref HAL_GPU2D_Init function.
When The compilation define USE_HAL_GPU2D_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
[..]
(@) You can refer to the GPU2D HAL driver header file for more useful macros
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal.h"
#ifdef HAL_GPU2D_MODULE_ENABLED
#if defined (GPU2D)
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @defgroup GPU2D GPU2D
* @brief GPU2D HAL module driver
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup GPU2D_Private_Macros GPU2D Private Macros
* @{
*/
/** @defgroup GPU2D_Write_Read Common write and read registers Macros
* @{
*/
/**
* @brief Write a value in GPU2D register
* @param __INSTANCE__ GPU2D Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define GPU2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(*(__IO uint32_t *)(__INSTANCE__\
+ __REG__), __VALUE__)
/**
* @brief Read a value in GPU2D register
* @param __INSTANCE__ GPU2D Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define GPU2D_ReadReg(__INSTANCE__, __REG__) READ_REG(*(__IO uint32_t *)(__INSTANCE__ + __REG__))
/**
* @}
*/
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup GPU2D_Exported_Functions GPU2D Exported Functions
* @{
*/
/** @defgroup GPU2D_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize and configure the GPU2D
(+) De-initialize the GPU2D
@endverbatim
* @{
*/
/**
* @brief Initialize the GPU2D according to the specified
* parameters in the GPU2D_InitTypeDef and create the associated handle.
* @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_GPU2D_Init(GPU2D_HandleTypeDef *hgpu2d)
{
/* Check the GPU2D handle validity */
if (hgpu2d == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_GPU2D_ALL_INSTANCE(hgpu2d->Instance));
if (hgpu2d->State == HAL_GPU2D_STATE_RESET)
{
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
/* Reset Callback pointers in HAL_GPU2D_STATE_RESET only */
hgpu2d->CommandListCpltCallback = HAL_GPU2D_CommandListCpltCallback;
if (hgpu2d->MspInitCallback == NULL)
{
hgpu2d->MspInitCallback = HAL_GPU2D_MspInit;
}
/* Init the low level hardware */
hgpu2d->MspInitCallback(hgpu2d);
#else /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 0 */
/* Init the low level hardware */
HAL_GPU2D_MspInit(hgpu2d);
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
/* Allocate lock resource and initialize it */
hgpu2d->Lock = HAL_UNLOCKED;
}
/* Process locked */
__HAL_LOCK(hgpu2d);
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
/* Reset the CommandListCpltCallback handler */
hgpu2d->CommandListCpltCallback = NULL;
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
/* Update error code */
hgpu2d->ErrorCode = HAL_GPU2D_ERROR_NONE;
/* Initialize the GPU2D state*/
hgpu2d->State = HAL_GPU2D_STATE_READY;
/* Release Lock */
__HAL_UNLOCK(hgpu2d);
return HAL_OK;
}
/**
* @brief Deinitializes the GPU2D peripheral registers to their default reset
* values.
* @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @retval None
*/
HAL_StatusTypeDef HAL_GPU2D_DeInit(GPU2D_HandleTypeDef *hgpu2d)
{
/* Check the GPU2D handle validity */
if (hgpu2d == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_GPU2D_ALL_INSTANCE(hgpu2d->Instance));
/* Process locked */
__HAL_LOCK(hgpu2d);
if (hgpu2d->State == HAL_GPU2D_STATE_READY)
{
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
if (hgpu2d->MspDeInitCallback == NULL)
{
hgpu2d->MspDeInitCallback = HAL_GPU2D_MspDeInit;
}
/* DeInit the low level hardware */
hgpu2d->MspDeInitCallback(hgpu2d);
#else /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 0 */
/* Carry on with de-initialization of low level hardware */
HAL_GPU2D_MspDeInit(hgpu2d);
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
}
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
/* Reset the CommandListCpltCallback handler */
hgpu2d->CommandListCpltCallback = NULL;
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
/* Update error code */
hgpu2d->ErrorCode = HAL_GPU2D_ERROR_NONE;
/* Reset the GPU2D state*/
hgpu2d->State = HAL_GPU2D_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hgpu2d);
return HAL_OK;
}
/**
* @brief Initializes the GPU2D MSP.
* @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @retval None
*/
__weak void HAL_GPU2D_MspInit(GPU2D_HandleTypeDef *hgpu2d)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hgpu2d);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_GPU2D_MspInit can be implemented in the user file.
*/
}
/**
* @brief DeInitializes the GPU2D MSP.
* @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @retval None
*/
__weak void HAL_GPU2D_MspDeInit(GPU2D_HandleTypeDef *hgpu2d)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hgpu2d);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_GPU2D_MspDeInit can be implemented in the user file.
*/
}
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User GPU2D callback
* To be used instead of the weak (surcharged) predefined callback
* @param hgpu2d GPU2D handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_GPU2D_MSPINIT_CB_ID GPU2D MspInit callback ID
* @arg @ref HAL_GPU2D_MSPDEINIT_CB_ID GPU2D MspDeInit callback ID
* @param pCallback pointer to the callback function
* @note Weak predefined callback is defined for HAL_GPU2D_MSPINIT_CB_ID and HAL_GPU2D_MSPDEINIT_CB_ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_GPU2D_RegisterCallback(GPU2D_HandleTypeDef *hgpu2d, HAL_GPU2D_CallbackIDTypeDef CallbackID,
pGPU2D_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the GPU2D handle validity */
if (hgpu2d == NULL)
{
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hgpu2d);
/* Check the pCallback parameter is valid or not */
if (pCallback == NULL)
{
/* Update the error code */
hgpu2d->ErrorCode |= HAL_GPU2D_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
}
else
{
if ((hgpu2d->State == HAL_GPU2D_STATE_READY)
|| (hgpu2d->State == HAL_GPU2D_STATE_RESET))
{
switch (CallbackID)
{
case HAL_GPU2D_MSPINIT_CB_ID:
hgpu2d->MspInitCallback = pCallback;
break;
case HAL_GPU2D_MSPDEINIT_CB_ID:
hgpu2d->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hgpu2d->ErrorCode |= HAL_GPU2D_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
break;
}
}
else
{
status = HAL_ERROR;
}
}
/* Release lock */
__HAL_UNLOCK(hgpu2d);
return status;
}
/**
* @brief Unregister a GPU2D callback
* GPU2D Callback is redirected to the weak (surcharged) predefined callback
* @param hgpu2d GPU2D handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_GPU2D_MSPINIT_CB_ID GPU2D MspInit callback ID
* @arg @ref HAL_GPU2D_MSPDEINIT_CB_ID GPU2D MspDeInit callback ID
* @note Callback pointers will be set to legacy weak predefined callbacks for HAL_GPU2D_MSPINIT_CB_ID and
* HAL_GPU2D_MSPDEINIT_CB_ID
* @retval status
*/
HAL_StatusTypeDef HAL_GPU2D_UnRegisterCallback(GPU2D_HandleTypeDef *hgpu2d, HAL_GPU2D_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the GPU2D handle validity */
if (hgpu2d == NULL)
{
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hgpu2d);
if ((HAL_GPU2D_STATE_READY == hgpu2d->State)
|| (HAL_GPU2D_STATE_RESET == hgpu2d->State))
{
switch (CallbackID)
{
case HAL_GPU2D_MSPINIT_CB_ID:
hgpu2d->MspInitCallback = HAL_GPU2D_MspInit; /* Legacy weak Msp Init */
break;
case HAL_GPU2D_MSPDEINIT_CB_ID:
hgpu2d->MspDeInitCallback = HAL_GPU2D_MspDeInit; /* Legacy weak Msp DeInit */
break;
default :
/* Update the error code */
hgpu2d->ErrorCode |= HAL_GPU2D_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
break;
}
}
else
{
status = HAL_ERROR;
}
/* Release lock */
__HAL_UNLOCK(hgpu2d);
return status;
}
/**
* @brief Register GPU2D Command List Complete Callback
* To be used instead of the weak (surcharged) predefined callback
* @param hgpu2d GPU2D handle
* @param pCallback pointer to the Command List Complete Callback function
* @note Weak predefined callback is defined for Command List Complete
* @retval status
*/
HAL_StatusTypeDef HAL_GPU2D_RegisterCommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d,
pGPU2D_CommandListCpltCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the GPU2D handle validity */
if (hgpu2d == NULL)
{
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hgpu2d);
/* Check the CallbackID is valid or not */
if (pCallback == NULL)
{
/* Update the error code */
hgpu2d->ErrorCode |= HAL_GPU2D_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
}
else
{
if ((HAL_GPU2D_STATE_READY == hgpu2d->State)
|| (HAL_GPU2D_STATE_RESET == hgpu2d->State))
{
hgpu2d->CommandListCpltCallback = pCallback;
}
else
{
status = HAL_ERROR;
}
}
/* Release lock */
__HAL_UNLOCK(hgpu2d);
return status;
}
/**
* @brief Unregister a GPU2D Command List Complete Callback
* GPU2D Command List Complete Callback is redirected to the weak (surcharged) predefined callback
* @param hgpu2d GPU2D handle
* @note Callback pointer will be invalidate (NULL value)
* @retval status
*/
HAL_StatusTypeDef HAL_GPU2D_UnRegisterCommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the GPU2D handle validity */
if (hgpu2d == NULL)
{
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hgpu2d);
if ((hgpu2d->State == HAL_GPU2D_STATE_READY)
|| (hgpu2d->State == HAL_GPU2D_STATE_RESET))
{
hgpu2d->CommandListCpltCallback = NULL; /* Invalidate the Callback pointer */
}
else
{
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hgpu2d);
return status;
}
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
/**
* @}
*/
/** @defgroup GPU2D_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Read GPU2D Register value.
(+) Write a value to GPU2D Register.
(+) handle GPU2D interrupt request.
(+) Command List Complete Transfer Complete callback.
@endverbatim
* @{
*/
/**
* @brief Read GPU2D Register. Helper function for the higher-level library.
* @param hgpu2d Pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @param offset The register offset from GPU2D base address to read.
* @retval Register value
*/
uint32_t HAL_GPU2D_ReadRegister(const GPU2D_HandleTypeDef *hgpu2d, uint32_t offset)
{
uint32_t value;
/* Check the GPU2D handle validity */
assert_param(hgpu2d != NULL);
/* Check the parameters */
assert_param(IS_GPU2D_ALL_INSTANCE(hgpu2d->Instance));
assert_param(IS_GPU2D_OFFSET(offset));
/* No locking is required since reading a register is an atomic operation
* and doesn't incur a state change in hal_gpu2d. */
value = GPU2D_ReadReg(hgpu2d->Instance, offset);
return value;
}
/**
* @brief Write a value to GPU2D Register. Helper function for the higher-level library.
* @param hgpu2d Pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @param offset The register offset from GPU2D base address to write.
* @param value The value to be written to provided register.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_GPU2D_WriteRegister(GPU2D_HandleTypeDef *hgpu2d, uint32_t offset, uint32_t value)
{
/* Check the GPU2D handle validity */
assert_param(hgpu2d != NULL);
/* Check the parameters */
assert_param(IS_GPU2D_ALL_INSTANCE(hgpu2d->Instance));
assert_param(IS_GPU2D_OFFSET(offset));
/* No locking is required since writing a register is an atomic operation
* and doesn't incur a state change in hal_gpu2d. */
GPU2D_WriteReg(hgpu2d->Instance, offset, value);
return HAL_OK;
}
/**
* @brief Handle GPU2D interrupt request.
* @param hgpu2d Pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @retval None
*/
void HAL_GPU2D_IRQHandler(GPU2D_HandleTypeDef *hgpu2d)
{
uint32_t isr_flags = GPU2D_ReadReg(hgpu2d->Instance, GPU2D_ITCTRL);
/* Command List Complete Interrupt management */
if ((isr_flags & GPU2D_FLAG_CLC) != 0U)
{
uint32_t last_cl_id;
/* Clear the completion flag */
__HAL_GPU2D_CLEAR_FLAG(hgpu2d, GPU2D_FLAG_CLC);
last_cl_id = GPU2D_ReadReg(hgpu2d->Instance, GPU2D_CLID);
/* Command List Complete Callback */
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
if (hgpu2d->CommandListCpltCallback != NULL)
{
hgpu2d->CommandListCpltCallback(hgpu2d, last_cl_id);
}
#else /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 0 */
HAL_GPU2D_CommandListCpltCallback(hgpu2d, last_cl_id);
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
}
}
/**
* @brief Handle GPU2D Error interrupt request.
* @param hgpu2d Pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @retval None
*/
void HAL_GPU2D_ER_IRQHandler(GPU2D_HandleTypeDef *hgpu2d)
{
HAL_GPU2D_ErrorCallback(hgpu2d);
}
/**
* @brief Command List Complete callback.
* @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @param CmdListID Command list ID that got completed.
* @retval None
*/
__weak void HAL_GPU2D_CommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d, uint32_t CmdListID)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hgpu2d);
UNUSED(CmdListID);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_GPU2D_CommandListCpltCallback can be implemented in the user file.
*/
}
/**
* @brief Error handler callback.
* @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @retval None
*/
__weak void HAL_GPU2D_ErrorCallback(GPU2D_HandleTypeDef *hgpu2d)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hgpu2d);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_GPU2D_ErrorCallback can be implemented in the user file.
The default implementation stops the execution as an error is considered
fatal and non recoverable.
*/
/* Infinite loop */
for (;;) {};
}
/**
* @}
*/
/** @defgroup GPU2D_Exported_Functions_Group3 Peripheral State and Error functions
* @brief Peripheral State functions
*
@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
===============================================================================
[..]
This subsection provides functions allowing to:
(+) Get the GPU2D state
(+) Get the GPU2D error code
@endverbatim
* @{
*/
/**
* @brief Return the GPU2D state
* @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @retval GPU2D state
*/
HAL_GPU2D_StateTypeDef HAL_GPU2D_GetState(GPU2D_HandleTypeDef const *const hgpu2d)
{
return hgpu2d->State;
}
/**
* @brief Return the GPU2D error code
* @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for GPU2D.
* @retval GPU2D Error Code
*/
uint32_t HAL_GPU2D_GetError(GPU2D_HandleTypeDef const *const hgpu2d)
{
return hgpu2d->ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* GPU2D */
#endif /* HAL_GPU2D_MODULE_ENABLED */
Drivers/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_i2c.c
+7824
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Drivers/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_i2c_ex.c
+359
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@@ -0,0 +1,359 @@
/**
******************************************************************************
* @file stm32h7rsxx_hal_i2c_ex.c
* @author MCD Application Team
* @brief I2C Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2C Extended peripheral:
* + Filter Mode Functions
* + WakeUp Mode Functions
* + FastModePlus Functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### I2C peripheral Extended features #####
==============================================================================
[..] Comparing to other previous devices, the I2C interface for STM32H7RSxx
devices contains the following additional features
(+) Possibility to disable or enable Analog Noise Filter
(+) Use of a configured Digital Noise Filter
(+) Disable or enable wakeup from Stop mode(s)
(+) Disable or enable Fast Mode Plus
##### How to use this driver #####
==============================================================================
[..] This driver provides functions to configure Noise Filter and Wake Up Feature
(#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
(#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
(#) Configure the enable or disable of I2C Wake Up Mode using the functions :
(++) HAL_I2CEx_EnableWakeUp()
(++) HAL_I2CEx_DisableWakeUp()
(#) Configure the enable or disable of fast mode plus driving capability using the functions :
(++) HAL_I2CEx_ConfigFastModePlus()
@endverbatim
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @defgroup I2CEx I2CEx
* @brief I2C Extended HAL module driver
* @{
*/
#ifdef HAL_I2C_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
* @{
*/
/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
* @brief Filter Mode Functions
*
@verbatim
===============================================================================
##### Filter Mode Functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Noise Filters
@endverbatim
* @{
*/
/**
* @brief Configure I2C Analog noise filter.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param AnalogFilter New state of the Analog filter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Reset I2Cx ANOFF bit */
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
/* Set analog filter bit*/
hi2c->Instance->CR1 |= AnalogFilter;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Configure I2C Digital noise filter.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
uint32_t tmpreg;
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Get the old register value */
tmpreg = hi2c->Instance->CR1;
/* Reset I2Cx DNF bits [11:8] */
tmpreg &= ~(I2C_CR1_DNF);
/* Set I2Cx DNF coefficient */
tmpreg |= DigitalFilter << 8U;
/* Store the new register value */
hi2c->Instance->CR1 = tmpreg;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @}
*/
/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
* @brief WakeUp Mode Functions
*
@verbatim
===============================================================================
##### WakeUp Mode Functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Wake Up Feature
@endverbatim
* @{
*/
/**
* @brief Enable I2C wakeup from Stop mode(s).
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
{
/* Check the parameters */
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Enable wakeup from stop mode */
hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Disable I2C wakeup from Stop mode(s).
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
{
/* Check the parameters */
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Enable wakeup from stop mode */
hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @}
*/
/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
* @brief Fast Mode Plus Functions
*
@verbatim
===============================================================================
##### Fast Mode Plus Functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Fast Mode Plus
@endverbatim
* @{
*/
/**
* @brief Configure I2C Fast Mode Plus.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param FastModePlus New state of the Fast Mode Plus.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigFastModePlus(I2C_HandleTypeDef *hi2c, uint32_t FastModePlus)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_FASTMODEPLUS(FastModePlus));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
if (FastModePlus == I2C_FASTMODEPLUS_ENABLE)
{
/* Set I2Cx FMP bit */
hi2c->Instance->CR1 |= (I2C_CR1_FMP);
}
else
{
/* Reset I2Cx FMP bit */
hi2c->Instance->CR1 &= ~(I2C_CR1_FMP);
}
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_I2C_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
Drivers/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_i2s.c
+2806
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Drivers/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_icache.c
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/**
******************************************************************************
* @file stm32h7rsxx_hal_icache.c
* @author MCD Application Team
* @brief ICACHE HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Instruction Cache (ICACHE).
* + Initialization and Configuration
* + Invalidate functions
* + Monitoring management
* + Memory address remap management
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### ICACHE main features #####
==============================================================================
[..]
The Texture Cache (ICACHE) is introduced on AXI read-only texture port of
the GPU2D to improve performance when reading texture data from internal and
external memories.
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
The ICACHE HAL driver can be used as follows:
(#) Optionally configure the Instruction Cache mode with
HAL_ICACHE_ConfigAssociativityMode() if the default configuration
does not suit the application requirements.
(#) Enable and disable the Instruction Cache with respectively
HAL_ICACHE_Enable() and HAL_ICACHE_Disable().
Use HAL_ICACHE_IsEnabled() to get the Instruction Cache status.
To ensure a deterministic cache behavior after power on, system reset or after
a call to @ref HAL_ICACHE_Disable(), the application must call
@ref HAL_ICACHE_WaitForInvalidateComplete(). Indeed on power on, system reset
or cache disable, an automatic cache invalidation procedure is launched and the
cache is bypassed until the operation completes.
(#) Initiate the cache maintenance invalidation procedure with either
HAL_ICACHE_Invalidate() (blocking mode) or HAL_ICACHE_Invalidate_IT()
(interrupt mode). When interrupt mode is used, the callback function
HAL_ICACHE_InvalidateCompleteCallback() is called when the invalidate
procedure is complete. The function HAL_ICACHE_WaitForInvalidateComplete()
may be called to wait for the end of the invalidate procedure automatically
initiated when disabling the Instruction Cache with HAL_ICACHE_Disable().
The cache operation is bypassed during the invalidation procedure.
(#) Use the performance monitoring counters for Hit and Miss with the following
functions: HAL_ICACHE_Monitor_Start(), HAL_ICACHE_Monitor_Stop(),
HAL_ICACHE_Monitor_Reset(), HAL_ICACHE_Monitor_GetHitValue() and
HAL_ICACHE_Monitor_GetMissValue()
@endverbatim
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @defgroup ICACHE ICACHE
* @brief HAL ICACHE module driver
* @{
*/
#if defined(ICACHE) && defined (HAL_ICACHE_MODULE_ENABLED)
/* Private typedef -----------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup ICACHE_Private_Constants ICACHE Private Constants
* @{
*/
#define ICACHE_INVALIDATE_TIMEOUT_VALUE 1U /* 1ms */
#define ICACHE_DISABLE_TIMEOUT_VALUE 1U /* 1ms */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup ICACHE_Private_Macros ICACHE Private Macros
* @{
*/
#define IS_ICACHE_ASSOCIATIVITY_MODE(__MODE__) (((__MODE__) == ICACHE_1WAY) || \
((__MODE__) == ICACHE_4WAYS))
#define IS_ICACHE_MONITOR_TYPE(__TYPE__) (((__TYPE__) == ICACHE_MONITOR_HIT_MISS) || \
((__TYPE__) == ICACHE_MONITOR_HIT) || \
((__TYPE__) == ICACHE_MONITOR_MISS))
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup ICACHE_Exported_Functions ICACHE Exported Functions
* @{
*/
/** @defgroup ICACHE_Exported_Functions_Group1 Initialization and control functions
* @brief Initialization and control functions
*
@verbatim
==============================================================================
##### Initialization and control functions #####
==============================================================================
[..]
This section provides functions allowing to initialize and control the
Instruction Cache (mode, invalidate procedure, performance counters).
@endverbatim
* @{
*/
/**
* @brief Configure the Instruction Cache cache associativity mode selection.
* @param AssociativityMode Associativity mode selection
* This parameter can be one of the following values:
* @arg ICACHE_1WAY 1-way cache (direct mapped cache)
* @arg ICACHE_4WAYS 4-ways set associative cache (default)
* @retval HAL status (HAL_OK/HAL_ERROR)
*/
HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_ICACHE_ASSOCIATIVITY_MODE(AssociativityMode));
/* Check cache is not enabled */
if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)
{
status = HAL_ERROR;
}
else
{
MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, AssociativityMode);
}
return status;
}
/**
* @brief DeInitialize the Instruction Cache.
* @retval HAL status (HAL_OK)
*/
HAL_StatusTypeDef HAL_ICACHE_DeInit(void)
{
/* Reset interrupt enable value */
WRITE_REG(ICACHE->IER, 0U);
/* Clear any pending flags */
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF);
/* Disable cache then set default associative mode value */
CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN);
WRITE_REG(ICACHE->CR, ICACHE_CR_WAYSEL);
/* Stop monitor and reset monitor values */
CLEAR_BIT(ICACHE->CR, ICACHE_MONITOR_HIT_MISS);
SET_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U));
CLEAR_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U));
return HAL_OK;
}
/**
* @brief Enable the Instruction Cache.
* @note This function always returns HAL_OK even if there is any ongoing
* cache operation. The Instruction Cache is bypassed until the
* cache operation completes.
* @retval HAL status (HAL_OK)
*/
HAL_StatusTypeDef HAL_ICACHE_Enable(void)
{
SET_BIT(ICACHE->CR, ICACHE_CR_EN);
return HAL_OK;
}
/**
* @brief Disable the Instruction Cache.
* @note This function waits for the cache being disabled but
* not for the end of the automatic cache invalidation procedure.
* @retval HAL status (HAL_OK/HAL_TIMEOUT)
*/
HAL_StatusTypeDef HAL_ICACHE_Disable(void)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tickstart;
/* Make sure BSYENDF is reset before to disable the instruction cache */
/* as it automatically starts a cache invalidation procedure */
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait for instruction cache being disabled */
while (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)
{
if ((HAL_GetTick() - tickstart) > ICACHE_DISABLE_TIMEOUT_VALUE)
{
/* New check to avoid false timeout detection in case of preemption */
if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)
{
status = HAL_TIMEOUT;
break;
}
}
}
return status;
}
/**
* @brief Check whether the Instruction Cache is enabled or not.
* @retval Status (0: disabled, 1: enabled)
*/
uint32_t HAL_ICACHE_IsEnabled(void)
{
return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) ? 1UL : 0UL);
}
/**
* @brief Invalidate the Instruction Cache.
* @note This function waits for the end of cache invalidation procedure
* and clears the associated BSYENDF flag.
* @retval HAL status (HAL_OK/HAL_ERROR/HAL_TIMEOUT)
*/
HAL_StatusTypeDef HAL_ICACHE_Invalidate(void)
{
HAL_StatusTypeDef status;
/* Check if no ongoing operation */
if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == 0U)
{
/* Launch cache invalidation */
SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV);
}
status = HAL_ICACHE_WaitForInvalidateComplete();
return status;
}
/**
* @brief Invalidate the Instruction Cache with interrupt.
* @note This function launches cache invalidation and returns.
* User application shall resort to interrupt generation to check
* the end of the cache invalidation with the BSYENDF flag and the
* HAL_ICACHE_InvalidateCompleteCallback() callback.
* @retval HAL status (HAL_OK/HAL_ERROR)
*/
HAL_StatusTypeDef HAL_ICACHE_Invalidate_IT(void)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check no ongoing operation */
if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U)
{
status = HAL_ERROR;
}
else
{
/* Make sure BSYENDF is reset before to start cache invalidation */
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
/* Enable end of cache invalidation interrupt */
SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
/* Launch cache invalidation */
SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV);
}
return status;
}
/**
* @brief Wait for the end of the Instruction Cache invalidate procedure.
* @note This function checks and clears the BSYENDF flag when set.
* @retval HAL status (HAL_OK/HAL_TIMEOUT)
*/
HAL_StatusTypeDef HAL_ICACHE_WaitForInvalidateComplete(void)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tickstart;
/* Check if ongoing invalidation operation */
if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U)
{
/* Get tick */
tickstart = HAL_GetTick();
/* Wait for end of cache invalidation */
while (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U)
{
if ((HAL_GetTick() - tickstart) > ICACHE_INVALIDATE_TIMEOUT_VALUE)
{
/* New check to avoid false timeout detection in case of preemption */
if (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U)
{
status = HAL_TIMEOUT;
break;
}
}
}
}
/* Clear BSYENDF */
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
return status;
}
/**
* @brief Start the Instruction Cache performance monitoring.
* @param MonitorType Monitoring type
* This parameter can be one of the following values:
* @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring
* @arg ICACHE_MONITOR_HIT Hit monitoring
* @arg ICACHE_MONITOR_MISS Miss monitoring
* @retval HAL status (HAL_OK)
*/
HAL_StatusTypeDef HAL_ICACHE_Monitor_Start(uint32_t MonitorType)
{
/* Check the parameters */
assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType));
SET_BIT(ICACHE->CR, MonitorType);
return HAL_OK;
}
/**
* @brief Stop the Instruction Cache performance monitoring.
* @note Stopping the monitoring does not reset the values.
* @param MonitorType Monitoring type
* This parameter can be one of the following values:
* @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring
* @arg ICACHE_MONITOR_HIT Hit monitoring
* @arg ICACHE_MONITOR_MISS Miss monitoring
* @retval HAL status (HAL_OK)
*/
HAL_StatusTypeDef HAL_ICACHE_Monitor_Stop(uint32_t MonitorType)
{
/* Check the parameters */
assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType));
CLEAR_BIT(ICACHE->CR, MonitorType);
return HAL_OK;
}
/**
* @brief Reset the Instruction Cache performance monitoring values.
* @param MonitorType Monitoring type
* This parameter can be one of the following values:
* @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring
* @arg ICACHE_MONITOR_HIT Hit monitoring
* @arg ICACHE_MONITOR_MISS Miss monitoring
* @retval HAL status (HAL_OK)
*/
HAL_StatusTypeDef HAL_ICACHE_Monitor_Reset(uint32_t MonitorType)
{
/* Check the parameters */
assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType));
/* Force/Release reset */
SET_BIT(ICACHE->CR, (MonitorType << 2U));
CLEAR_BIT(ICACHE->CR, (MonitorType << 2U));
return HAL_OK;
}
/**
* @brief Get the Instruction Cache performance Hit monitoring value.
* @note Upon reaching the 32-bit maximum value, monitor does not wrap.
* @retval Hit monitoring value
*/
uint32_t HAL_ICACHE_Monitor_GetHitValue(void)
{
return (ICACHE->HMONR);
}
/**
* @brief Get the Instruction Cache performance Miss monitoring value.
* @note Upon reaching the 32-bit maximum value, monitor does not wrap.
* @retval Miss monitoring value
*/
uint32_t HAL_ICACHE_Monitor_GetMissValue(void)
{
return (ICACHE->MMONR);
}
/**
* @}
*/
/** @defgroup ICACHE_Exported_Functions_Group2 IRQ and callback functions
* @brief IRQ and callback functions
*
@verbatim
==============================================================================
##### IRQ and callback functions #####
==============================================================================
[..]
This section provides functions allowing to handle ICACHE global interrupt
and the associated callback functions.
@endverbatim
* @{
*/
/**
* @brief Handle the Instruction Cache interrupt request.
* @note This function should be called under the ICACHE_IRQHandler().
* @note This function respectively disables the interrupt and clears the
* flag of any pending flag before calling the associated user callback.
* @retval None
*/
void HAL_ICACHE_IRQHandler(void)
{
/* Get current interrupt flags and interrupt sources value */
uint32_t itflags = READ_REG(ICACHE->SR);
uint32_t itsources = READ_REG(ICACHE->IER);
/* Check Instruction cache Error interrupt flag */
if (((itflags & itsources) & ICACHE_FLAG_ERROR) != 0U)
{
/* Disable error interrupt */
CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE);
/* Clear ERR pending flag */
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF);
/* Instruction cache error interrupt user callback */
HAL_ICACHE_ErrorCallback();
}
/* Check Instruction cache BusyEnd interrupt flag */
if (((itflags & itsources) & ICACHE_FLAG_BUSYEND) != 0U)
{
/* Disable end of cache invalidation interrupt */
CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
/* Clear BSYENDF pending flag */
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
/* Instruction cache busyend interrupt user callback */
HAL_ICACHE_InvalidateCompleteCallback();
}
}
/**
* @brief Cache invalidation complete callback.
*/
__weak void HAL_ICACHE_InvalidateCompleteCallback(void)
{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_ICACHE_InvalidateCompleteCallback() should be implemented in the user file
*/
}
/**
* @brief Error callback.
*/
__weak void HAL_ICACHE_ErrorCallback(void)
{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_ICACHE_ErrorCallback() should be implemented in the user file
*/
}
/**
* @}
*/
/**
* @}
*/
#endif /* ICACHE && HAL_ICACHE_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
Drivers/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_jpeg.c
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Drivers/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_ltdc.c
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Drivers/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_ltdc_ex.c
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/**
******************************************************************************
* @file stm32h7rsxx_hal_ltdc_ex.c
* @author MCD Application Team
* @brief LTDC Extension HAL module driver.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
#if defined(HAL_LTDC_MODULE_ENABLED) && defined(HAL_DSI_MODULE_ENABLED)
#if defined (LTDC) && defined (DSI)
/** @defgroup LTDCEx LTDCEx
* @brief LTDC HAL module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions
* @{
*/
/** @defgroup LTDCEx_Exported_Functions_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize and configure the LTDC
@endverbatim
* @{
*/
/**
* @brief Retrieve common parameters from DSI Video mode configuration structure
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains
* the DSI video mode configuration parameters
* @note The implementation of this function is taking into account the LTDC
* polarities inversion as described in the current LTDC specification
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg)
{
/* Retrieve signal polarities from DSI */
/* The following polarity is inverted:
LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH */
#if !defined(POLARITIES_INVERSION_UPDATED)
/* Note 1 : Code in line w/ Current LTDC specification */
hltdc->Init.DEPolarity = (VidCfg->DEPolarity == \
DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AH : LTDC_VSPOLARITY_AL;
hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AH : LTDC_HSPOLARITY_AL;
#else
/* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29;
hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29;
hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29;
#endif /* POLARITIES_INVERSION_UPDATED */
/* Retrieve vertical timing parameters from DSI */
hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1U;
hltdc->Init.AccumulatedVBP = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1U;
hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + \
VidCfg->VerticalActive - 1U;
hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + \
VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1U;
return HAL_OK;
}
/**
* @brief Retrieve common parameters from DSI Adapted command mode configuration structure
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains
* the DSI command mode configuration parameters
* @note The implementation of this function is taking into account the LTDC
* polarities inversion as described in the current LTDC specification
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg)
{
/* Retrieve signal polarities from DSI */
/* The following polarities are inverted:
LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH
LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH
LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/
#if !defined(POLARITIES_INVERSION_UPDATED)
/* Note 1 : Code in line w/ Current LTDC specification */
hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == \
DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH;
hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH;
#else
/* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29;
hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29;
hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29;
#endif /* POLARITIES_INVERSION_UPDATED */
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* LTDC && DSI */
#endif /* HAL_LTCD_MODULE_ENABLED && HAL_DSI_MODULE_ENABLED */
/**
* @}
*/
Drivers/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_mdf.c
+2236
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File diff suppressed because it is too large. Load diff
Drivers/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_pwr.c
+692
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@@ -0,0 +1,692 @@
/**
******************************************************************************
* @file stm32h7rsxx_hal_pwr.c
* @author MCD Application Team
* @brief PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
* + Initialization/De-Initialization Functions.
* + Peripheral Control Functions.
*
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### PWR peripheral overview #####
==============================================================================
[..]
(#) The Power control (PWR) provides an overview of the supply architecture
for the different power domains and of the supply configuration
controller.
(#) Several low-power modes are available to save power when the CPU does not need to
execute code :
(+) Sleep (CPU clock stopped and still in RUN mode)
(+) Stop (System clock stopped)
(+) Standby (System powered down)
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
(#) Call HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() functions
to enable/disable access to the backup domain (RCC Backup domain control
register RCC_BDCR, RTC registers, TAMP registers, backup registers and
backup SRAM).
(#) Call HAL_PWR_ConfigPVD() after setting parameters to be configured (event
mode and voltage threshold) in order to set up the Programmed Voltage
Detector, then use HAL_PWR_EnablePVD() and HAL_PWR_DisablePVD()
functions to start and stop the PVD detection.
(+) PVD level can be one of the following values :
(++) 2V0
(++) 2V2
(++) 2V4
(++) 2V5
(++) 2V6
(++) 2V8
(++) 2V9
(++) External input analog voltage PVD_IN (compared internally to
VREFINT)
(#) Call HAL_PWR_EnableWakeUpPin() and HAL_PWR_DisableWakeUpPin() functions
with the right parameter to configure the wake up pin polarity (Low or
High), the wake up pin selection and to enable and disable it.
(#) Call HAL_PWR_EnterSLEEPMode() function to enter the CPU in Sleep mode.
Wake-up from Sleep mode could be following to an event or an
interrupt according to low power mode intrinsic request called (__WFI()
or __WFE()).
(#) Call HAL_PWR_EnterSTOPMode() function to enter the whole system to Stop
mode. Wake-up from Stop mode could be following to an event or an
interrupt according to low power mode intrinsic request called (__WFI()
or __WFE()).
(#) Call HAL_PWR_EnterSTANDBYMode() function to enter the whole system in
Standby mode. Wake-up from Standby mode can be following only by an
interrupt.
(#) Call HAL_PWR_EnableSleepOnExit() and HAL_PWR_DisableSleepOnExit() APIs to
enable and disable the Cortex-M7 re-entry in Sleep mode after an
interruption handling is over.
(#) Call HAL_PWR_EnableSEVOnPend() and HAL_PWR_DisableSEVOnPend() functions
to configure the Cortex-M7 to wake-up after any pending event / interrupt
even if it's disabled or has insufficient priority to cause exception
entry.
*** PWR HAL driver macros list ***
=============================================
[..]
Below the list of most used macros in PWR HAL driver.
(+) __HAL_PWR_GET_FLAG() : Get the PWR pending flags.
(+) __HAL_PWR_CLEAR_FLAG() : Clear the PWR pending flags.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @defgroup PWR PWR
* @brief PWR HAL module driver
* @{
*/
#ifdef HAL_PWR_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup PWR_Private_Defines PWR Private Defines
* @{
*/
/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
* @{
*/
#define PVD_MODE_IT (0x00010000U)
#define PVD_MODE_EVT (0x00020000U)
#define PVD_RISING_EDGE (0x00000001U)
#define PVD_FALLING_EDGE (0x00000002U)
#define PVD_RISING_FALLING_EDGE (0x00000003U)
/**
* @}
*/
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PWR_Exported_Functions PWR Exported Functions
* @{
*/
/** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions
* @brief Initialization and de-Initialization functions
*
@verbatim
===============================================================================
##### Initialization and De-Initialization Functions #####
===============================================================================
[..]
This section provides functions allowing to deinitialize power peripheral.
[..]
After system reset, the backup domain (RCC Backup domain control register
RCC_BDCR, RTC registers, TAMP registers, backup registers and backup SRAM)
is protected against possible unwanted write accesses.
The HAL_PWR_EnableBkUpAccess() function enables the access to the backup
domain.
The HAL_PWR_DisableBkUpAccess() function disables the access to the backup
domain.
@endverbatim
* @{
*/
/**
* @brief Deinitialize the HAL PWR peripheral registers to their default reset
* values.
* @note This functionality is not available in this product.
* The prototype is kept just to maintain compatibility with other
* products.
* @retval None.
*/
void HAL_PWR_DeInit(void)
{
}
/**
* @brief Enable access to the backup domain (RCC Backup domain control
* register RCC_BDCR, RTC registers, TAMP registers, backup registers
* and backup SRAM).
* @note After a system reset, the backup domain is protected against
* possible unwanted write accesses.
* @retval None.
*/
void HAL_PWR_EnableBkUpAccess(void)
{
SET_BIT(PWR->CR1, PWR_CR1_DBP);
}
/**
* @brief Disable access to the backup domain (RCC Backup domain control
* register RCC_BDCR, RTC registers, TAMP registers, backup registers
* and backup SRAM).
* @retval None.
*/
void HAL_PWR_DisableBkUpAccess(void)
{
CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
}
/**
* @}
*/
/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control Functions
* @brief Power Control functions
*
@verbatim
===============================================================================
##### Peripheral Control Functions #####
===============================================================================
[..]
This section provides functions allowing to control power peripheral.
*** PVD configuration ***
=========================
[..]
(+) The PVD is used to monitor the VDD power supply by comparing it to a
threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR1
register).
(+) A PVDO flag is available to indicate if VDD is higher or lower
than the PVD threshold. This event is internally connected to the EXTI
line 16 to generate an interrupt if enabled.
It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
(+) The PVD is stopped in STANDBY mode.
*** Wake-up pin configuration ***
=================================
[..]
(+) Wake-up pin is used to wake up the system from STANDBY mode.
The pin pull is configurable through the WKUPEPR register to be in
No-pull, Pull-up and Pull-down.
The pin polarity is configurable through the WKUPEPR register to be
active on rising or falling edges.
(+) There are up to four Wake-up pin in the STM32H7RS devices family.
*** Low Power modes configuration ***
=====================================
[..]
The device present 3 principles low-power modes :
(+) SLEEP mode : Cortex-M7 is stopped and all PWR domains are remaining
active (Powered and Clocked).
(+) STOP mode : Cortex-M7 is stopped, clocks are stopped and the
regulator is running. The Main regulator or the LP
regulator could be selected.
(+) STANDBY mode : All PWR domains enter DSTANDBY mode and the VCORE
supply regulator is powered off.
*** SLEEP mode ***
==================
[..]
(+) Entry:
The SLEEP mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator,
SLEEPEntry) function.
(++) PWR_SLEEPENTRY_WFI : Enter SLEEP mode with WFI instruction.
(++) PWR_SLEEPENTRY_WFE : Enter SLEEP mode with WFE instruction and
clear of pending events before.
(++) PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR: Enter SLEEP mode with WFE instruction and
no clear of pending event before.
-@@- The Regulator parameter is not used for the STM32H7RS family
and is kept as parameter just to maintain compatibility with the
lower power families. (STM32L).
(+) Exit:
Any peripheral interrupt acknowledged by the nested vectored interrupt
controller (NVIC) can wake up the device from SLEEP mode.
*** STOP mode ***
=================
[..]
In system STOP mode, the CPU clock is stopped. All CPU subsystem peripheral
clocks are stopped too.
The voltage regulator can be configured either in normal or low-power mode.
To minimize the consumption in STOP mode, FLASH can be powered off before
entering the STOP mode using the HAL_PWREx_EnableFlashPowerDown() function.
It can be switched on again by software after exiting the STOP mode using
the HAL_PWREx_DisableFlashPowerDown() function.
(+) Entry:
The STOP mode is entered using the HAL_PWR_EnterSTOPMode(Regulator,
STOPEntry) function with:
(++) Regulator:
(+++) PWR_MAINREGULATOR_ON: Main regulator ON.
This parameter is not used for the STM32H7RS family and is kept as parameter
just to maintain compatibility with the lower power families.
(++) STOPEntry:
(+++) PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
(+++) PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction and
clear of pending events before.
(+++) PWR_STOPENTRY_WFE_NO_EVT_CLEAR: Enter STOP mode with WFE instruction and
no clear of pending event before.
(+) Exit:
Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
*** STANDBY mode ***
====================
[..]
(+)
The system STANDBY mode allows to achieve the lowest power consumption.
It is based on the Cortex-M7 deep SLEEP mode, with the voltage regulator
disabled. The system is consequently powered off. The PLL, the HSI
oscillator and the HSE oscillator are also switched off. SRAM and register
contents are lost except for the RTC registers, RTC backup registers,
backup SRAM and standby circuitry.
[..]
The voltage regulator is OFF.
(++) Entry:
(+++) The STANDBY mode is entered using the HAL_PWR_EnterSTANDBYMode()
function.
(++) Exit:
(+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B),
RTC wakeup, tamper event, time stamp event, external reset in NRST
pin, IWDG reset.
*** Auto-wakeup (AWU) from low-power mode ***
=============================================
[..]
(+) The MCU can be woken up from low-power mode by an RTC Alarm event, an
RTC Wakeup event, a tamper event or a time-stamp event, without
depending on an external interrupt (Auto-wakeup mode).
(+) RTC auto-wakeup (AWU) from the STOP and STANDBY modes
(++) To wake up from the STOP mode with an RTC alarm event, it is
necessary to configure the RTC to generate the RTC alarm using the
HAL_RTC_SetAlarm_IT() function.
(++) To wake up from the STOP mode with an RTC Tamper or time stamp event,
it is necessary to configure the RTC to detect the tamper or time
stamp event using the HAL_RTCEx_SetTimeStamp_IT() or
HAL_RTCEx_SetTamper_IT() functions.
(++) To wake up from the STOP mode with an RTC WakeUp event, it is
necessary to configure the RTC to generate the RTC WakeUp event
using the HAL_RTCEx_SetWakeUpTimer_IT() function.
@endverbatim
* @{
*/
/**
* @brief Configure the voltage threshold detected by the Programmed Voltage
* Detector (PVD).
* @param sConfigPVD : Pointer to a PWR_PVDTypeDef structure that contains the
* PVD configuration information (PVDLevel and EventMode).
* @note Refer to the electrical characteristics of your device datasheet for
* more details about the voltage threshold corresponding to each
* detection level.
* @note As PVD and AVD share the same EXTI line, the EXTI operating mode to
* configure will replace a possible previous configuration done through
* HAL_PWREx_ConfigAVD.
* @retval None.
*/
void HAL_PWR_ConfigPVD(const PWR_PVDTypeDef *sConfigPVD)
{
/* Check the PVD configuration parameter */
if (sConfigPVD == NULL)
{
return;
}
/* Check the parameters */
assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
/* Set PLS[7:5] bits according to PVDLevel value */
MODIFY_REG(PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);
/* Clear any previous config. Keep it clear if no event or IT mode is selected */
__HAL_PWR_PVD_EXTI_DISABLE_EVENT();
__HAL_PWR_PVD_EXTI_DISABLE_IT();
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
/* Configure the PVD in interrupt mode */
if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
{
__HAL_PWR_PVD_EXTI_ENABLE_IT();
}
/* Configure the PVD in event mode */
if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
{
__HAL_PWR_PVD_EXTI_ENABLE_EVENT();
}
/* Rising edge configuration */
if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
{
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
}
/* Falling edge configuration */
if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
{
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
}
}
/**
* @brief Enable the programmable voltage detector (PVD).
* @retval None.
*/
void HAL_PWR_EnablePVD(void)
{
SET_BIT(PWR->CR1, PWR_CR1_PVDE);
}
/**
* @brief Disable the programmable voltage detector (PVD).
* @retval None.
*/
void HAL_PWR_DisablePVD(void)
{
CLEAR_BIT(PWR->CR1, PWR_CR1_PVDE);
}
/**
* @brief Enable the WakeUp PINx functionality.
* @param WakeUpPinPolarity : Specifies which Wake-Up pin to enable.
* This parameter can be one of the following legacy values, which
* sets the default (rising edge):
* @arg PWR_WAKEUP_PIN1,
* PWR_WAKEUP_PIN2,
* PWR_WAKEUP_PIN3,
* PWR_WAKEUP_PIN4.
* or one of the following values where the user can explicitly states
* the enabled pin and the chosen polarity:
* @arg PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW,
* PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW,
* PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW,
* PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW.
* @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
* @retval None.
*/
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
{
/* Check the parameters */
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
/*
Enable and Specify the Wake-Up pin polarity and the pull configuration
for the event detection (rising or falling edge).
*/
MODIFY_REG(PWR->WKUPEPR, PWR_WKUPEPR_WKUPEN | PWR_WKUPEPR_WKUPP, WakeUpPinPolarity);
}
/**
* @brief Disable the WakeUp PINx functionality.
* @param WakeUpPinx : Specifies the Power Wake-Up pin to disable.
* This parameter can be one of the following values:
* @arg PWR_WAKEUP_PIN1,
* PWR_WAKEUP_PIN2,
* PWR_WAKEUP_PIN3,
* PWR_WAKEUP_PIN4,
* PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW,
* PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW,
* PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW,
* PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW.
* @retval None.
*/
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
{
/* Check the parameters */
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
/* Disable the wake up pin selected */
CLEAR_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPEN & WakeUpPinx));
}
/**
* @brief Enter the current core in SLEEP mode (CSLEEP).
* @param Regulator : NA in this family project
* Specifies the regulator state in SLEEP mode.
* @note This parameter is not used for the STM32H7RS family and is kept as
* parameter just to maintain compatibility with the lower power
* families.
* @param SLEEPEntry : Specifies if SLEEP mode is entered with WFI or WFE
* intrinsic instruction.
* This parameter can be one of the following values:
* @arg PWR_SLEEPENTRY_WFI : Enter SLEEP mode with WFI instruction.
* @arg PWR_SLEEPENTRY_WFE : Enter SLEEP mode with WFE instruction and
* clear of pending events before.
* @arg PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR : Enter SLEEP mode with WFE instruction and
* no clear of pending event before.
* @retval None.
*/
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(Regulator);
/* Check the parameters */
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
/* Clear SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
/* Select Sleep mode entry */
if (SLEEPEntry == PWR_SLEEPENTRY_WFI)
{
/* Request Wait For Interrupt */
__WFI();
}
else
{
if (SLEEPEntry != PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR)
{
/* Clear all pending event */
__SEV();
__WFE();
}
/* Request Wait For Event */
__WFE();
}
}
/**
* @brief Enter the whole system to Stop mode.
* @note This API will enter the system in STOP mode
* @param Regulator : This parameter is not used for this product family.
and is kept as parameter just to maintain compatibility with the
lower power families.
* @param STOPEntry : Specifies if STOP mode in entered with WFI or WFE
* intrinsic instruction.
* This parameter can be one of the following values:
* @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
* @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction and
* clear of pending events before.
* @arg PWR_STOPENTRY_WFE_NO_EVT_CLEAR : Enter STOP mode with WFE instruction and
* no clear of pending event before.
* @note In System STOP mode, all I/O pins keep the same state as in Run mode.
* @note When exiting System STOP mode by issuing an interrupt or a wakeup
* event, the HSI RC oscillator is selected as default system wakeup
* clock.
* @note In System STOP mode, when the voltage regulator operates in low
* power mode, an additional startup delay is incurred when the system
* is waking up. By keeping the internal regulator ON during STOP mode,
* the consumption is higher although the startup time is reduced.
* @retval None.
*/
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(Regulator);
/* Check the parameters */
assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
/* Select Stop mode when device enters Deepsleep */
CLEAR_BIT(PWR->CSR3, PWR_CSR3_PDDS);
/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
/* Ensure that all instructions are done before entering STOP mode */
__DSB();
__ISB();
/* Select Stop mode entry */
if (STOPEntry == PWR_STOPENTRY_WFI)
{
/* Request Wait For Interrupt */
__WFI();
}
else
{
if (STOPEntry != PWR_STOPENTRY_WFE_NO_EVT_CLEAR)
{
/* Clear all pending event */
__SEV();
__WFE();
}
/* Request Wait For Event */
__WFE();
}
/* Clear SLEEPDEEP bit of Cortex-M7 in the System Control Register */
CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
}
/**
* @brief Enter the whole system to Standby mode.
* @note The Standby mode allows achieving the lowest power consumption.
* @note When the system enters in Standby mode, the voltage regulator is disabled.
* The complete VCORE domain is consequently powered off.
* The PLLs, HSI oscillator, CSI oscillator, HSI48 and the HSE oscillator are
* also switched off.
* SRAM and register contents are lost except for backup domain registers
* (RTC registers, RTC backup register and backup RAM), and Standby circuitry.
* @note When the System exit STANDBY mode by issuing an interrupt or a
* wakeup event, the HSI RC oscillator is selected as system clock.
* @retval None.
*/
void HAL_PWR_EnterSTANDBYMode(void)
{
/* Select Standby when device enters Deepsleep */
SET_BIT(PWR->CSR3, PWR_CSR3_PDDS);
/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
/* Ensure that all instructions are done before entering STANDBY mode */
__DSB();
__ISB();
/* Request Wait For Interrupt */
__WFI();
}
/**
* @brief Indicate SLEEP-ON-EXIT feature when returning from handler mode to
* thread mode.
* @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the
* processor re-enters Sleep mode when an interruption handling is over.
* Setting this bit is useful when the processor is expected to run
* only on interruptions handling.
* @retval None.
*/
void HAL_PWR_EnableSleepOnExit(void)
{
/* Set SLEEPONEXIT bit of Cortex-M7 System Control Register */
SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
}
/**
* @brief Disable SLEEP-ON-EXIT feature when returning from handler mode to
* thread mode.
* @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the
* processor re-enters Sleep mode when an interruption handling is over.
* @retval None.
*/
void HAL_PWR_DisableSleepOnExit(void)
{
/* Clear SLEEPONEXIT bit of Cortex-M7 System Control Register */
CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
}
/**
* @brief Enable CORTEX SEV-ON-PEND feature.
* @note Sets SEVONPEND bit of SCR register. When this bit is set, any
* pending event / interrupt even if it's disabled or has insufficient
* priority to cause exception entry wakes up the Cortex-M7.
* @retval None.
*/
void HAL_PWR_EnableSEVOnPend(void)
{
/* Set SEVONPEND bit of Cortex-M7 System Control Register */
SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
}
/**
* @brief Disable CORTEX SEVONPEND feature.
* @note Resets SEVONPEND bit of SCR register. When this bit is reset, only
* enabled pending causes exception entry wakes up the Cortex-M7.
* @retval None.
*/
void HAL_PWR_DisableSEVOnPend(void)
{
/* Clear SEVONPEND bit of Cortex-M7 System Control Register */
CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_PWR_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
Drivers/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_pwr_ex.c
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Drivers/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_rcc.c
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Drivers/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_smbus.c
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/**
******************************************************************************
* @file stm32h7rsxx_hal_smbus_ex.c
* @author MCD Application Team
* @brief SMBUS Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of SMBUS Extended peripheral:
* + Extended features functions
* + WakeUp Mode Functions
* + FastModePlus Functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### SMBUS peripheral Extended features #####
==============================================================================
[..] Comparing to other previous devices, the SMBUS interface for STM32H7RSxx
devices contains the following additional features
(+) Disable or enable wakeup from Stop mode(s)
##### How to use this driver #####
==============================================================================
(#) Configure the enable or disable of SMBUS Wake Up Mode using the functions :
(++) HAL_SMBUSEx_EnableWakeUp()
(++) HAL_SMBUSEx_DisableWakeUp()
(#) Configure the enable or disable of fast mode plus driving capability using the functions :
(++) HAL_SMBUSEx_ConfigFastModePlus()
@endverbatim
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7rsxx_hal.h"
/** @addtogroup STM32H7RSxx_HAL_Driver
* @{
*/
/** @defgroup SMBUSEx SMBUSEx
* @brief SMBUS Extended HAL module driver
* @{
*/
#ifdef HAL_SMBUS_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions
* @{
*/
/** @defgroup SMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions
* @brief WakeUp Mode Functions
*
@verbatim
===============================================================================
##### WakeUp Mode Functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Wake Up Feature
@endverbatim
* @{
*/
/**
* @brief Enable SMBUS wakeup from Stop mode(s).
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUSx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp(SMBUS_HandleTypeDef *hsmbus)
{
/* Check the parameters */
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hsmbus->Instance));
if (hsmbus->State == HAL_SMBUS_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hsmbus);
hsmbus->State = HAL_SMBUS_STATE_BUSY;
/* Disable the selected SMBUS peripheral */
__HAL_SMBUS_DISABLE(hsmbus);
/* Enable wakeup from stop mode */
hsmbus->Instance->CR1 |= I2C_CR1_WUPEN;
__HAL_SMBUS_ENABLE(hsmbus);
hsmbus->State = HAL_SMBUS_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Disable SMBUS wakeup from Stop mode(s).
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUSx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus)
{
/* Check the parameters */
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hsmbus->Instance));
if (hsmbus->State == HAL_SMBUS_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hsmbus);
hsmbus->State = HAL_SMBUS_STATE_BUSY;
/* Disable the selected SMBUS peripheral */
__HAL_SMBUS_DISABLE(hsmbus);
/* Disable wakeup from stop mode */
hsmbus->Instance->CR1 &= ~(I2C_CR1_WUPEN);
__HAL_SMBUS_ENABLE(hsmbus);
hsmbus->State = HAL_SMBUS_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @}
*/
/** @defgroup SMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions
* @brief Fast Mode Plus Functions
*
@verbatim
===============================================================================
##### Fast Mode Plus Functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Fast Mode Plus
@endverbatim
* @{
*/
/**
* @brief Configure SMBUS Fast Mode Plus.
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUSx peripheral.
* @param FastModePlus New state of the Fast Mode Plus.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMBUSEx_ConfigFastModePlus(SMBUS_HandleTypeDef *hsmbus, uint32_t FastModePlus)
{
/* Check the parameters */
assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
assert_param(IS_SMBUS_FASTMODEPLUS(FastModePlus));
if (hsmbus->State == HAL_SMBUS_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hsmbus);
hsmbus->State = HAL_SMBUS_STATE_BUSY;
/* Disable the selected SMBUS peripheral */
__HAL_SMBUS_DISABLE(hsmbus);
if (FastModePlus == SMBUS_FASTMODEPLUS_ENABLE)
{
/* Set SMBUSx FMP bit */
hsmbus->Instance->CR1 |= (I2C_CR1_FMP);
}
else
{
/* Reset SMBUSx FMP bit */
hsmbus->Instance->CR1 &= ~(I2C_CR1_FMP);
}
__HAL_SMBUS_ENABLE(hsmbus);
hsmbus->State = HAL_SMBUS_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_SMBUS_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
Drivers/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_tim.c
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