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/**
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******************************************************************************
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* @file stm32h7rsxx_ll_icache.h
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* @author MCD Application Team
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* @brief Header file of ICACHE LL module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2022 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion ------------------------------------*/
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#ifndef STM32H7RSxx_LL_ICACHE_H
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#define STM32H7RSxx_LL_ICACHE_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes -----------------------------------------------------------------*/
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#include "stm32h7rsxx.h"
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/** @addtogroup STM32H7RSxx_LL_Driver
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* @{
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*/
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#if defined(ICACHE)
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/** @defgroup ICACHE_LL ICACHE
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/* Private macros ------------------------------------------------------------*/
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants -------------------------------------------------------*/
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/** @defgroup ICACHE_LL_Exported_Constants ICACHE Exported Constants
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* @{
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*/
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/** @defgroup ICACHE_LL_EC_WaysSelection Ways selection
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* @{
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*/
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#define LL_ICACHE_1WAY 0U /*!< 1-way cache (direct mapped cache) */
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#define LL_ICACHE_4WAYS ICACHE_CR_WAYSEL /*!< 4-ways set associative cache (default) */
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/**
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* @}
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*/
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/** @defgroup ICACHE_LL_EC_Monitor_Type Monitor type
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* @{
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*/
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#define LL_ICACHE_MONITOR_HIT ICACHE_CR_HITMEN /*!< Hit monitor counter */
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#define LL_ICACHE_MONITOR_MISS ICACHE_CR_MISSMEN /*!< Miss monitor counter */
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#define LL_ICACHE_MONITOR_ALL (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< All monitors counters */
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/**
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* @}
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*/
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/** @defgroup ICACHE_LL_EC_GET_FLAG Get Flags Defines
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* @brief Flags defines which can be used with LL_ICACHE_ReadReg function
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* @{
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*/
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#define LL_ICACHE_SR_BUSYF ICACHE_SR_BUSYF /*!< Busy flag */
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#define LL_ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF /*!< Busy end flag */
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#define LL_ICACHE_SR_ERRF ICACHE_SR_ERRF /*!< Cache error flag */
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/**
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* @}
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*/
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/** @defgroup ICACHE_LL_EC_CLEAR_FLAG Clear Flags Defines
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* @brief Flags defines which can be used with LL_ICACHE_WriteReg function
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* @{
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*/
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#define LL_ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF /*!< Busy end flag */
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#define LL_ICACHE_FCR_CERRF ICACHE_FCR_CERRF /*!< Cache error flag */
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/**
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* @}
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*/
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/** @defgroup ICACHE_LL_EC_IT IT Defines
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* @brief IT defines which can be used with LL_ICACHE_ReadReg and LL_ICACHE_WriteReg functions
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* @{
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*/
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#define LL_ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE /*!< Busy end interrupt */
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#define LL_ICACHE_IER_ERRIE ICACHE_IER_ERRIE /*!< Cache error interrupt */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macros ----------------------------------------------------------*/
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/** @defgroup ICACHE_LL_Exported_Macros ICACHE Exported Macros
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* @{
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*/
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/** @defgroup ICACHE_LL_EM_WRITE_READ Common write and read registers Macros
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* @{
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*/
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/**
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* @brief Write a value in ICACHE register
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* @param __REG__ Register to be written
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* @param __VALUE__ Value to be written in the register
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* @retval None
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*/
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#define LL_ICACHE_WriteReg(__REG__, __VALUE__) WRITE_REG(ICACHE->__REG__, (__VALUE__))
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/**
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* @brief Read a value in ICACHE register
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* @param __REG__ Register to be read
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* @retval Register value
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*/
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#define LL_ICACHE_ReadReg(__REG__) READ_REG(ICACHE->__REG__)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup ICACHE_LL_Exported_Functions ICACHE Exported Functions
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* @{
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*/
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/** @defgroup ICACHE_LL_EF_Configuration Configuration
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* @{
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*/
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/**
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* @brief Enable the ICACHE.
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* @rmtoll CR EN LL_ICACHE_Enable
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* @retval None
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*/
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__STATIC_INLINE void LL_ICACHE_Enable(void)
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{
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SET_BIT(ICACHE->CR, ICACHE_CR_EN);
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}
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/**
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* @brief Disable the ICACHE.
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* @rmtoll CR EN LL_ICACHE_Disable
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* @retval None
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*/
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__STATIC_INLINE void LL_ICACHE_Disable(void)
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{
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CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN);
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}
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/**
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* @brief Return if ICACHE is enabled or not.
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* @rmtoll CR EN LL_ICACHE_IsEnabled
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_ICACHE_IsEnabled(void)
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{
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return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) == (ICACHE_CR_EN)) ? 1UL : 0UL);
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}
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/**
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* @brief Select the ICACHE operating mode.
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* @rmtoll CR WAYSEL LL_ICACHE_SetMode
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* @param Mode This parameter can be one of the following values:
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* @arg @ref LL_ICACHE_1WAY
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* @arg @ref LL_ICACHE_4WAYS
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* @retval None
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*/
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__STATIC_INLINE void LL_ICACHE_SetMode(uint32_t Mode)
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{
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MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, Mode);
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}
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/**
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* @brief Get the selected ICACHE operating mode.
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* @rmtoll CR WAYSEL LL_ICACHE_GetMode
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* @retval Returned value can be one of the following values:
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* @arg @ref LL_ICACHE_1WAY
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* @arg @ref LL_ICACHE_4WAYS
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*/
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__STATIC_INLINE uint32_t LL_ICACHE_GetMode(void)
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{
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return (READ_BIT(ICACHE->CR, ICACHE_CR_WAYSEL));
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}
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/**
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* @brief Invalidate the ICACHE.
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* @note Until the BSYEND flag is set, the cache is bypassed.
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* @rmtoll CR CACHEINV LL_ICACHE_Invalidate
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* @retval None
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*/
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__STATIC_INLINE void LL_ICACHE_Invalidate(void)
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{
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SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV);
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}
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/**
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* @}
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*/
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/** @defgroup ICACHE_LL_EF_Monitors Monitors
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* @{
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*/
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/**
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* @brief Enable the hit/miss monitor(s).
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* @rmtoll CR HITMEN LL_ICACHE_EnableMonitors
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* @rmtoll CR MISSMEN LL_ICACHE_EnableMonitors
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* @param Monitors This parameter can be one or a combination of the following values:
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* @arg @ref LL_ICACHE_MONITOR_HIT
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* @arg @ref LL_ICACHE_MONITOR_MISS
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* @arg @ref LL_ICACHE_MONITOR_ALL
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* @retval None
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*/
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__STATIC_INLINE void LL_ICACHE_EnableMonitors(uint32_t Monitors)
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{
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SET_BIT(ICACHE->CR, Monitors);
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}
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/**
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* @brief Disable the hit/miss monitor(s).
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* @rmtoll CR HITMEN LL_ICACHE_DisableMonitors
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* @rmtoll CR MISSMEN LL_ICACHE_DisableMonitors
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* @param Monitors This parameter can be one or a combination of the following values:
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* @arg @ref LL_ICACHE_MONITOR_HIT
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* @arg @ref LL_ICACHE_MONITOR_MISS
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* @arg @ref LL_ICACHE_MONITOR_ALL
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* @retval None
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*/
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__STATIC_INLINE void LL_ICACHE_DisableMonitors(uint32_t Monitors)
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{
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CLEAR_BIT(ICACHE->CR, Monitors);
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}
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/**
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* @brief Check if the monitor(s) is(are) enabled or disabled.
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* @rmtoll CR HITMEN LL_ICACHE_IsEnabledMonitors
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* @rmtoll CR MISSMEN LL_ICACHE_IsEnabledMonitors
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* @param Monitors This parameter can be one or a combination of the following values:
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* @arg @ref LL_ICACHE_MONITOR_HIT
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* @arg @ref LL_ICACHE_MONITOR_MISS
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* @arg @ref LL_ICACHE_MONITOR_ALL
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* @retval State of parameter value (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledMonitors(uint32_t Monitors)
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{
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return ((READ_BIT(ICACHE->CR, Monitors) == (Monitors)) ? 1UL : 0UL);
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}
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/**
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* @brief Reset the hit/miss monitor(s).
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* @rmtoll CR HITMRST LL_ICACHE_ResetMonitors
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* @rmtoll CR MISSMRST LL_ICACHE_ResetMonitors
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* @param Monitors This parameter can be one or a combination of the following values:
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* @arg @ref LL_ICACHE_MONITOR_HIT
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* @arg @ref LL_ICACHE_MONITOR_MISS
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* @arg @ref LL_ICACHE_MONITOR_ALL
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* @retval None
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*/
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__STATIC_INLINE void LL_ICACHE_ResetMonitors(uint32_t Monitors)
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{
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/* Reset */
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SET_BIT(ICACHE->CR, (Monitors << 2U));
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/* Release reset */
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CLEAR_BIT(ICACHE->CR, (Monitors << 2U));
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}
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/**
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* @brief Get the Hit monitor.
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* @note Upon reaching the 32-bit maximum value, hit monitor does not wrap.
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* @rmtoll HMONR HITMON LL_ICACHE_GetHitMonitor
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* @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
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*/
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__STATIC_INLINE uint32_t LL_ICACHE_GetHitMonitor(void)
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{
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return (ICACHE->HMONR);
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}
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/**
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* @brief Get the Miss monitor.
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* @note Upon reaching the 16-bit maximum value, miss monitor does not wrap.
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* @rmtoll MMONR MISSMON LL_ICACHE_GetMissMonitor
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* @retval Value between Min_Data=0 and Max_Data=0xFFFF
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*/
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__STATIC_INLINE uint32_t LL_ICACHE_GetMissMonitor(void)
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{
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return (ICACHE->MMONR);
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}
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/**
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* @}
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*/
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/** @defgroup ICACHE_LL_EF_IT_Management IT_Management
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* @{
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*/
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/**
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* @brief Enable BSYEND interrupt.
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* @rmtoll IER BSYENDIE LL_ICACHE_EnableIT_BSYEND
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* @retval None
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*/
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__STATIC_INLINE void LL_ICACHE_EnableIT_BSYEND(void)
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{
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SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
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}
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/**
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* @brief Disable BSYEND interrupt.
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* @rmtoll IER BSYENDIE LL_ICACHE_DisableIT_BSYEND
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* @retval None
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*/
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__STATIC_INLINE void LL_ICACHE_DisableIT_BSYEND(void)
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{
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CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
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}
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/**
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* @brief Check if the BSYEND Interrupt is enabled or disabled.
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* @rmtoll IER BSYENDIE LL_ICACHE_IsEnabledIT_BSYEND
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_BSYEND(void)
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{
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return ((READ_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE) == (ICACHE_IER_BSYENDIE)) ? 1UL : 0UL);
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}
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/**
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* @brief Enable ERR interrupt.
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* @rmtoll IER ERRIE LL_ICACHE_EnableIT_ERR
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* @retval None
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*/
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__STATIC_INLINE void LL_ICACHE_EnableIT_ERR(void)
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{
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SET_BIT(ICACHE->IER, ICACHE_IER_ERRIE);
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}
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/**
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* @brief Disable ERR interrupt.
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* @rmtoll IER ERRIE LL_ICACHE_DisableIT_ERR
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* @retval None
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*/
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__STATIC_INLINE void LL_ICACHE_DisableIT_ERR(void)
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{
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CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE);
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}
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/**
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* @brief Check if the ERR Interrupt is enabled or disabled.
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* @rmtoll IER ERRIE LL_ICACHE_IsEnabledIT_ERR
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_ERR(void)
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{
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return ((READ_BIT(ICACHE->IER, ICACHE_IER_ERRIE) == (ICACHE_IER_ERRIE)) ? 1UL : 0UL);
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}
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/**
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* @}
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*/
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/** @defgroup ICACHE_LL_EF_FLAG_Management FLAG_Management
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* @{
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*/
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/**
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* @brief Indicate the status of an ongoing operation flag.
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* @rmtoll SR BUSYF LL_ICACHE_IsActiveFlag_BUSY
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BUSY(void)
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{
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return ((READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == (ICACHE_SR_BUSYF)) ? 1UL : 0UL);
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}
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/**
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* @brief Indicate the status of an operation end flag.
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* @rmtoll SR BSYEND LL_ICACHE_IsActiveFlag_BSYEND
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BSYEND(void)
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{
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return ((READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == (ICACHE_SR_BSYENDF)) ? 1UL : 0UL);
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}
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/**
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* @brief Indicate the status of an error flag.
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* @rmtoll SR ERRF LL_ICACHE_IsActiveFlag_ERR
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_ERR(void)
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{
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return ((READ_BIT(ICACHE->SR, ICACHE_SR_ERRF) == (ICACHE_SR_ERRF)) ? 1UL : 0UL);
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}
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/**
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* @brief Clear busy end of operation flag.
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* @rmtoll FCR CBSYENDF LL_ICACHE_ClearFlag_BSYEND
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* @retval None
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*/
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__STATIC_INLINE void LL_ICACHE_ClearFlag_BSYEND(void)
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{
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WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
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}
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/**
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* @brief Clear error flag.
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* @rmtoll FCR ERRF LL_ICACHE_ClearFlag_ERR
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* @retval None
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*/
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__STATIC_INLINE void LL_ICACHE_ClearFlag_ERR(void)
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{
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WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF);
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#endif /* ICACHE */
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* STM32H7RSxx_LL_ICACHE_H */
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