STM32H7S78-DK_Boot.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000002b0 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00009e70 080002b0 080002b0 000012b0 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 0000004c 0800a120 0800a120 0000b120 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 0800a16c 0800a16c 0000c00c 2**0 CONTENTS 4 .ARM 00000000 0800a16c 0800a16c 0000c00c 2**0 CONTENTS 5 .preinit_array 00000000 0800a16c 0800a16c 0000c00c 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 0800a16c 0800a16c 0000b16c 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 0800a170 0800a170 0000b170 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 0000000c 24000000 0800a174 0000c000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .tdata 00000000 2400000c 2400000c 0000c00c 2**2 CONTENTS, ALLOC, LOAD, DATA, THREAD_LOCAL 10 .tbss 00000000 2400000c 2400000c 00000000 2**2 ALLOC, THREAD_LOCAL 11 .bss 00000444 2400000c 0800a180 0000c00c 2**2 ALLOC 12 ._user_heap_stack 00002000 20000000 20000000 0000d000 2**0 ALLOC 13 .ARM.attributes 0000002e 00000000 00000000 0000c00c 2**0 CONTENTS, READONLY 14 .debug_info 0001adcf 00000000 00000000 0000c03a 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_abbrev 000036ac 00000000 00000000 00026e09 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_aranges 000011e8 00000000 00000000 0002a4b8 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_rnglists 00000d9f 00000000 00000000 0002b6a0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_macro 00032650 00000000 00000000 0002c43f 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .debug_line 0001916f 00000000 00000000 0005ea8f 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 20 .debug_str 00139df2 00000000 00000000 00077bfe 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .comment 00000043 00000000 00000000 001b19f0 2**0 CONTENTS, READONLY 22 .debug_frame 00004488 00000000 00000000 001b1a34 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 23 .debug_line_str 0000007e 00000000 00000000 001b5ebc 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080002b0 <__do_global_dtors_aux>: 80002b0: b510 push {r4, lr} 80002b2: 4c05 ldr r4, [pc, #20] @ (80002c8 <__do_global_dtors_aux+0x18>) 80002b4: 7823 ldrb r3, [r4, #0] 80002b6: b933 cbnz r3, 80002c6 <__do_global_dtors_aux+0x16> 80002b8: 4b04 ldr r3, [pc, #16] @ (80002cc <__do_global_dtors_aux+0x1c>) 80002ba: b113 cbz r3, 80002c2 <__do_global_dtors_aux+0x12> 80002bc: 4804 ldr r0, [pc, #16] @ (80002d0 <__do_global_dtors_aux+0x20>) 80002be: f3af 8000 nop.w 80002c2: 2301 movs r3, #1 80002c4: 7023 strb r3, [r4, #0] 80002c6: bd10 pop {r4, pc} 80002c8: 2400000c .word 0x2400000c 80002cc: 00000000 .word 0x00000000 80002d0: 0800a108 .word 0x0800a108 080002d4 : 80002d4: b508 push {r3, lr} 80002d6: 4b03 ldr r3, [pc, #12] @ (80002e4 ) 80002d8: b11b cbz r3, 80002e2 80002da: 4903 ldr r1, [pc, #12] @ (80002e8 ) 80002dc: 4803 ldr r0, [pc, #12] @ (80002ec ) 80002de: f3af 8000 nop.w 80002e2: bd08 pop {r3, pc} 80002e4: 00000000 .word 0x00000000 80002e8: 24000010 .word 0x24000010 80002ec: 0800a108 .word 0x0800a108 080002f0 : /** * Init External memory manager * @retval None */ void MX_EXTMEM_MANAGER_Init(void) { 80002f0: b580 push {r7, lr} 80002f2: af00 add r7, sp, #0 /* USER CODE BEGIN MX_EXTMEM_Init_PreTreatment */ /* USER CODE END MX_EXTMEM_Init_PreTreatment */ HAL_RCCEx_EnableClockProtection(RCC_CLOCKPROTECT_XSPI); 80002f4: 2001 movs r0, #1 80002f6: f005 fa35 bl 8005764 /* Initialization of the memory parameters */ memset(extmem_list_config, 0x0, sizeof(extmem_list_config)); 80002fa: f44f 72ac mov.w r2, #344 @ 0x158 80002fe: 2100 movs r1, #0 8000300: 4832 ldr r0, [pc, #200] @ (80003cc ) 8000302: f009 fec7 bl 800a094 /* EXTMEMORY_1 */ extmem_list_config[0].MemType = EXTMEM_NOR_SFDP; 8000306: 4b31 ldr r3, [pc, #196] @ (80003cc ) 8000308: 2200 movs r2, #0 800030a: 701a strb r2, [r3, #0] extmem_list_config[0].Handle = (void*)&hxspi2; 800030c: 4b2f ldr r3, [pc, #188] @ (80003cc ) 800030e: 4a30 ldr r2, [pc, #192] @ (80003d0 ) 8000310: 605a str r2, [r3, #4] extmem_list_config[0].ConfigType = EXTMEM_LINK_CONFIG_8LINES; 8000312: 4b2e ldr r3, [pc, #184] @ (80003cc ) 8000314: 2203 movs r2, #3 8000316: 721a strb r2, [r3, #8] /* EXTMEMORY_2 */ extmem_list_config[1].MemType = EXTMEM_PSRAM; 8000318: 4b2c ldr r3, [pc, #176] @ (80003cc ) 800031a: 2202 movs r2, #2 800031c: f883 20ac strb.w r2, [r3, #172] @ 0xac extmem_list_config[1].Handle = (void*)&hxspi1; 8000320: 4b2a ldr r3, [pc, #168] @ (80003cc ) 8000322: 4a2c ldr r2, [pc, #176] @ (80003d4 ) 8000324: f8c3 20b0 str.w r2, [r3, #176] @ 0xb0 extmem_list_config[1].ConfigType = EXTMEM_LINK_CONFIG_16LINES; 8000328: 4b28 ldr r3, [pc, #160] @ (80003cc ) 800032a: 2204 movs r2, #4 800032c: f883 20b4 strb.w r2, [r3, #180] @ 0xb4 extmem_list_config[1].PsramObject.psram_public.MemorySize = HAL_XSPI_SIZE_256MB; 8000330: 4b26 ldr r3, [pc, #152] @ (80003cc ) 8000332: 2218 movs r2, #24 8000334: f8c3 210c str.w r2, [r3, #268] @ 0x10c extmem_list_config[1].PsramObject.psram_public.FreqMax = 133 * 1000000u; 8000338: 4b24 ldr r3, [pc, #144] @ (80003cc ) 800033a: 4a27 ldr r2, [pc, #156] @ (80003d8 ) 800033c: f8c3 2110 str.w r2, [r3, #272] @ 0x110 extmem_list_config[1].PsramObject.psram_public.NumberOfConfig = 1u; 8000340: 4b22 ldr r3, [pc, #136] @ (80003cc ) 8000342: 2201 movs r2, #1 8000344: f883 2114 strb.w r2, [r3, #276] @ 0x114 /* Config */ extmem_list_config[1].PsramObject.psram_public.config[0].WriteMask = 0x40u; 8000348: 4b20 ldr r3, [pc, #128] @ (80003cc ) 800034a: 2240 movs r2, #64 @ 0x40 800034c: f883 2115 strb.w r2, [r3, #277] @ 0x115 extmem_list_config[1].PsramObject.psram_public.config[0].WriteValue = 0x40u; 8000350: 4b1e ldr r3, [pc, #120] @ (80003cc ) 8000352: 2240 movs r2, #64 @ 0x40 8000354: f883 2116 strb.w r2, [r3, #278] @ 0x116 extmem_list_config[1].PsramObject.psram_public.config[0].REGAddress = 0x08u; 8000358: 4b1c ldr r3, [pc, #112] @ (80003cc ) 800035a: 2208 movs r2, #8 800035c: f883 2117 strb.w r2, [r3, #279] @ 0x117 /* Memory command configuration */ extmem_list_config[1].PsramObject.psram_public.ReadREG = 0x40u; 8000360: 4b1a ldr r3, [pc, #104] @ (80003cc ) 8000362: 2240 movs r2, #64 @ 0x40 8000364: f883 211e strb.w r2, [r3, #286] @ 0x11e extmem_list_config[1].PsramObject.psram_public.WriteREG = 0xC0u; 8000368: 4b18 ldr r3, [pc, #96] @ (80003cc ) 800036a: 22c0 movs r2, #192 @ 0xc0 800036c: f883 211f strb.w r2, [r3, #287] @ 0x11f extmem_list_config[1].PsramObject.psram_public.ReadREGSize = 2u; 8000370: 4b16 ldr r3, [pc, #88] @ (80003cc ) 8000372: 2202 movs r2, #2 8000374: f883 2120 strb.w r2, [r3, #288] @ 0x120 extmem_list_config[1].PsramObject.psram_public.REG_DummyCycle = 4u; 8000378: 4b14 ldr r3, [pc, #80] @ (80003cc ) 800037a: 2204 movs r2, #4 800037c: f883 2121 strb.w r2, [r3, #289] @ 0x121 extmem_list_config[1].PsramObject.psram_public.Write_command = 0xA0u; 8000380: 4b12 ldr r3, [pc, #72] @ (80003cc ) 8000382: 22a0 movs r2, #160 @ 0xa0 8000384: f883 2122 strb.w r2, [r3, #290] @ 0x122 extmem_list_config[1].PsramObject.psram_public.Write_DummyCycle = 4u; 8000388: 4b10 ldr r3, [pc, #64] @ (80003cc ) 800038a: 2204 movs r2, #4 800038c: f883 2123 strb.w r2, [r3, #291] @ 0x123 extmem_list_config[1].PsramObject.psram_public.Read_command = 0x20u; 8000390: 4b0e ldr r3, [pc, #56] @ (80003cc ) 8000392: 2220 movs r2, #32 8000394: f883 2124 strb.w r2, [r3, #292] @ 0x124 extmem_list_config[1].PsramObject.psram_public.WrapRead_command = 0x00u; 8000398: 4b0c ldr r3, [pc, #48] @ (80003cc ) 800039a: 2200 movs r2, #0 800039c: f883 2125 strb.w r2, [r3, #293] @ 0x125 extmem_list_config[1].PsramObject.psram_public.Read_DummyCycle = 4u; 80003a0: 4b0a ldr r3, [pc, #40] @ (80003cc ) 80003a2: 2204 movs r2, #4 80003a4: f883 2126 strb.w r2, [r3, #294] @ 0x126 EXTMEM_Init(EXTMEMORY_1, HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_XSPI2)); 80003a8: 2004 movs r0, #4 80003aa: f003 fe9b bl 80040e4 80003ae: 4603 mov r3, r0 80003b0: 4619 mov r1, r3 80003b2: 2000 movs r0, #0 80003b4: f006 ff36 bl 8007224 EXTMEM_Init(EXTMEMORY_2, HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_XSPI1)); 80003b8: 2002 movs r0, #2 80003ba: f003 fe93 bl 80040e4 80003be: 4603 mov r3, r0 80003c0: 4619 mov r1, r3 80003c2: 2001 movs r0, #1 80003c4: f006 ff2e bl 8007224 /* USER CODE BEGIN MX_EXTMEM_Init_PostTreatment */ /* USER CODE END MX_EXTMEM_Init_PostTreatment */ } 80003c8: bf00 nop 80003ca: bd80 pop {r7, pc} 80003cc: 2400016c .word 0x2400016c 80003d0: 240000b8 .word 0x240000b8 80003d4: 24000028 .word 0x24000028 80003d8: 07ed6b40 .word 0x07ed6b40 080003dc
: /** * @brief The application entry point. * @retval int */ int main(void) { 80003dc: b580 push {r7, lr} 80003de: b084 sub sp, #16 80003e0: af00 add r7, sp, #0 \details Turns on I-Cache */ __STATIC_FORCEINLINE void SCB_EnableICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ 80003e2: 4b40 ldr r3, [pc, #256] @ (80004e4 ) 80003e4: 695b ldr r3, [r3, #20] 80003e6: f403 3300 and.w r3, r3, #131072 @ 0x20000 80003ea: 2b00 cmp r3, #0 80003ec: d11b bne.n 8000426 \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 80003ee: f3bf 8f4f dsb sy } 80003f2: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 80003f4: f3bf 8f6f isb sy } 80003f8: bf00 nop __DSB(); __ISB(); SCB->ICIALLU = 0UL; /* invalidate I-Cache */ 80003fa: 4b3a ldr r3, [pc, #232] @ (80004e4 ) 80003fc: 2200 movs r2, #0 80003fe: f8c3 2250 str.w r2, [r3, #592] @ 0x250 __ASM volatile ("dsb 0xF":::"memory"); 8000402: f3bf 8f4f dsb sy } 8000406: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8000408: f3bf 8f6f isb sy } 800040c: bf00 nop __DSB(); __ISB(); SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ 800040e: 4b35 ldr r3, [pc, #212] @ (80004e4 ) 8000410: 695b ldr r3, [r3, #20] 8000412: 4a34 ldr r2, [pc, #208] @ (80004e4 ) 8000414: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8000418: 6153 str r3, [r2, #20] __ASM volatile ("dsb 0xF":::"memory"); 800041a: f3bf 8f4f dsb sy } 800041e: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8000420: f3bf 8f6f isb sy } 8000424: e000 b.n 8000428 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ 8000426: bf00 nop #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ 8000428: 4b2e ldr r3, [pc, #184] @ (80004e4 ) 800042a: 695b ldr r3, [r3, #20] 800042c: f403 3380 and.w r3, r3, #65536 @ 0x10000 8000430: 2b00 cmp r3, #0 8000432: d138 bne.n 80004a6 SCB->CSSELR = 0U; /* select Level 1 data cache */ 8000434: 4b2b ldr r3, [pc, #172] @ (80004e4 ) 8000436: 2200 movs r2, #0 8000438: f8c3 2084 str.w r2, [r3, #132] @ 0x84 __ASM volatile ("dsb 0xF":::"memory"); 800043c: f3bf 8f4f dsb sy } 8000440: bf00 nop __DSB(); ccsidr = SCB->CCSIDR; 8000442: 4b28 ldr r3, [pc, #160] @ (80004e4 ) 8000444: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8000448: 60fb str r3, [r7, #12] /* invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 800044a: 68fb ldr r3, [r7, #12] 800044c: 0b5b lsrs r3, r3, #13 800044e: f3c3 030e ubfx r3, r3, #0, #15 8000452: 60bb str r3, [r7, #8] do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 8000454: 68fb ldr r3, [r7, #12] 8000456: 08db lsrs r3, r3, #3 8000458: f3c3 0309 ubfx r3, r3, #0, #10 800045c: 607b str r3, [r7, #4] do { SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 800045e: 68bb ldr r3, [r7, #8] 8000460: 015a lsls r2, r3, #5 8000462: f643 73e0 movw r3, #16352 @ 0x3fe0 8000466: 4013 ands r3, r2 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); 8000468: 687a ldr r2, [r7, #4] 800046a: 0792 lsls r2, r2, #30 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 800046c: 491d ldr r1, [pc, #116] @ (80004e4 ) 800046e: 4313 orrs r3, r2 8000470: f8c1 3260 str.w r3, [r1, #608] @ 0x260 #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); 8000474: 687b ldr r3, [r7, #4] 8000476: 1e5a subs r2, r3, #1 8000478: 607a str r2, [r7, #4] 800047a: 2b00 cmp r3, #0 800047c: d1ef bne.n 800045e } while(sets-- != 0U); 800047e: 68bb ldr r3, [r7, #8] 8000480: 1e5a subs r2, r3, #1 8000482: 60ba str r2, [r7, #8] 8000484: 2b00 cmp r3, #0 8000486: d1e5 bne.n 8000454 __ASM volatile ("dsb 0xF":::"memory"); 8000488: f3bf 8f4f dsb sy } 800048c: bf00 nop __DSB(); SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ 800048e: 4b15 ldr r3, [pc, #84] @ (80004e4 ) 8000490: 695b ldr r3, [r3, #20] 8000492: 4a14 ldr r2, [pc, #80] @ (80004e4 ) 8000494: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8000498: 6153 str r3, [r2, #20] __ASM volatile ("dsb 0xF":::"memory"); 800049a: f3bf 8f4f dsb sy } 800049e: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 80004a0: f3bf 8f6f isb sy } 80004a4: e000 b.n 80004a8 if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ 80004a6: bf00 nop SCB_EnableDCache(); /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 80004a8: f000 fbba bl 8000c20 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 80004ac: f000 f81c bl 80004e8 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 80004b0: f000 f9ee bl 8000890 MX_HPDMA1_Init(); 80004b4: f000 f91a bl 80006ec MX_GPDMA1_Init(); 80004b8: f000 f900 bl 80006bc MX_XSPI1_Init(); 80004bc: f000 f936 bl 800072c MX_XSPI2_Init(); 80004c0: f000 f98e bl 80007e0 MX_FLASH_Init(); 80004c4: f000 f8a5 bl 8000612 MX_SBS_Init(); 80004c8: f000 f928 bl 800071c MX_EXTMEM_MANAGER_Init(); 80004cc: f7ff ff10 bl 80002f0 /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ /* Launch the application */ if (BOOT_OK != BOOT_Application()) 80004d0: f006 fdbe bl 8007050 80004d4: 4603 mov r3, r0 80004d6: 2b00 cmp r3, #0 80004d8: d002 beq.n 80004e0 { Error_Handler(); 80004da: f000 fa0b bl 80008f4 } /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 80004de: bf00 nop 80004e0: bf00 nop 80004e2: e7fd b.n 80004e0 80004e4: e000ed00 .word 0xe000ed00 080004e8 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 80004e8: b580 push {r7, lr} 80004ea: b0b0 sub sp, #192 @ 0xc0 80004ec: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 80004ee: f107 0324 add.w r3, r7, #36 @ 0x24 80004f2: 229c movs r2, #156 @ 0x9c 80004f4: 2100 movs r1, #0 80004f6: 4618 mov r0, r3 80004f8: f009 fdcc bl 800a094 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 80004fc: 1d3b adds r3, r7, #4 80004fe: 2220 movs r2, #32 8000500: 2100 movs r1, #0 8000502: 4618 mov r0, r3 8000504: f009 fdc6 bl 800a094 /** Configure the main internal regulator output voltage */ if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE0) != HAL_OK) 8000508: 2001 movs r0, #1 800050a: f001 fc25 bl 8001d58 800050e: 4603 mov r3, r0 8000510: 2b00 cmp r3, #0 8000512: d001 beq.n 8000518 { Error_Handler(); 8000514: f000 f9ee bl 80008f4 } /** Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); 8000518: f001 fbbc bl 8001c94 /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 800051c: 2301 movs r3, #1 800051e: 627b str r3, [r7, #36] @ 0x24 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; 8000520: f44f 23a0 mov.w r3, #327680 @ 0x50000 8000524: 62bb str r3, [r7, #40] @ 0x28 RCC_OscInitStruct.PLL1.PLLState = RCC_PLL_ON; 8000526: 2302 movs r3, #2 8000528: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.PLL1.PLLSource = RCC_PLLSOURCE_HSE; 800052a: 2302 movs r3, #2 800052c: 64fb str r3, [r7, #76] @ 0x4c RCC_OscInitStruct.PLL1.PLLM = 4; 800052e: 2304 movs r3, #4 8000530: 653b str r3, [r7, #80] @ 0x50 RCC_OscInitStruct.PLL1.PLLN = 200; 8000532: 23c8 movs r3, #200 @ 0xc8 8000534: 657b str r3, [r7, #84] @ 0x54 RCC_OscInitStruct.PLL1.PLLP = 2; 8000536: 2302 movs r3, #2 8000538: 65bb str r3, [r7, #88] @ 0x58 RCC_OscInitStruct.PLL1.PLLQ = 2; 800053a: 2302 movs r3, #2 800053c: 65fb str r3, [r7, #92] @ 0x5c RCC_OscInitStruct.PLL1.PLLR = 2; 800053e: 2302 movs r3, #2 8000540: 663b str r3, [r7, #96] @ 0x60 RCC_OscInitStruct.PLL1.PLLS = 2; 8000542: 2302 movs r3, #2 8000544: 667b str r3, [r7, #100] @ 0x64 RCC_OscInitStruct.PLL1.PLLT = 2; 8000546: 2302 movs r3, #2 8000548: 66bb str r3, [r7, #104] @ 0x68 RCC_OscInitStruct.PLL1.PLLFractional = 0; 800054a: 2300 movs r3, #0 800054c: 66fb str r3, [r7, #108] @ 0x6c RCC_OscInitStruct.PLL2.PLLState = RCC_PLL_ON; 800054e: 2302 movs r3, #2 8000550: 673b str r3, [r7, #112] @ 0x70 RCC_OscInitStruct.PLL2.PLLSource = RCC_PLLSOURCE_HSE; 8000552: 2302 movs r3, #2 8000554: 677b str r3, [r7, #116] @ 0x74 RCC_OscInitStruct.PLL2.PLLM = 5; 8000556: 2305 movs r3, #5 8000558: 67bb str r3, [r7, #120] @ 0x78 RCC_OscInitStruct.PLL2.PLLN = 128; 800055a: 2380 movs r3, #128 @ 0x80 800055c: 67fb str r3, [r7, #124] @ 0x7c RCC_OscInitStruct.PLL2.PLLP = 25; 800055e: 2319 movs r3, #25 8000560: f8c7 3080 str.w r3, [r7, #128] @ 0x80 RCC_OscInitStruct.PLL2.PLLQ = 10; 8000564: 230a movs r3, #10 8000566: f8c7 3084 str.w r3, [r7, #132] @ 0x84 RCC_OscInitStruct.PLL2.PLLR = 2; 800056a: 2302 movs r3, #2 800056c: f8c7 3088 str.w r3, [r7, #136] @ 0x88 RCC_OscInitStruct.PLL2.PLLS = 2; 8000570: 2302 movs r3, #2 8000572: f8c7 308c str.w r3, [r7, #140] @ 0x8c RCC_OscInitStruct.PLL2.PLLT = 2; 8000576: 2302 movs r3, #2 8000578: f8c7 3090 str.w r3, [r7, #144] @ 0x90 RCC_OscInitStruct.PLL2.PLLFractional = 0; 800057c: 2300 movs r3, #0 800057e: f8c7 3094 str.w r3, [r7, #148] @ 0x94 RCC_OscInitStruct.PLL3.PLLState = RCC_PLL_ON; 8000582: 2302 movs r3, #2 8000584: f8c7 3098 str.w r3, [r7, #152] @ 0x98 RCC_OscInitStruct.PLL3.PLLSource = RCC_PLLSOURCE_HSE; 8000588: 2302 movs r3, #2 800058a: f8c7 309c str.w r3, [r7, #156] @ 0x9c RCC_OscInitStruct.PLL3.PLLM = 2; 800058e: 2302 movs r3, #2 8000590: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 RCC_OscInitStruct.PLL3.PLLN = 50; 8000594: 2332 movs r3, #50 @ 0x32 8000596: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 RCC_OscInitStruct.PLL3.PLLP = 2; 800059a: 2302 movs r3, #2 800059c: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 RCC_OscInitStruct.PLL3.PLLQ = 2; 80005a0: 2302 movs r3, #2 80005a2: f8c7 30ac str.w r3, [r7, #172] @ 0xac RCC_OscInitStruct.PLL3.PLLR = 24; 80005a6: 2318 movs r3, #24 80005a8: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 RCC_OscInitStruct.PLL3.PLLS = 2; 80005ac: 2302 movs r3, #2 80005ae: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 RCC_OscInitStruct.PLL3.PLLT = 2; 80005b2: 2302 movs r3, #2 80005b4: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 RCC_OscInitStruct.PLL3.PLLFractional = 0; 80005b8: 2300 movs r3, #0 80005ba: f8c7 30bc str.w r3, [r7, #188] @ 0xbc if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 80005be: f107 0324 add.w r3, r7, #36 @ 0x24 80005c2: 4618 mov r0, r3 80005c4: f001 fc10 bl 8001de8 80005c8: 4603 mov r3, r0 80005ca: 2b00 cmp r3, #0 80005cc: d001 beq.n 80005d2 { Error_Handler(); 80005ce: f000 f991 bl 80008f4 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 80005d2: 233f movs r3, #63 @ 0x3f 80005d4: 607b str r3, [r7, #4] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 |RCC_CLOCKTYPE_PCLK4|RCC_CLOCKTYPE_PCLK5; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 80005d6: 2303 movs r3, #3 80005d8: 60bb str r3, [r7, #8] RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; 80005da: 2300 movs r3, #0 80005dc: 60fb str r3, [r7, #12] RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; 80005de: 2308 movs r3, #8 80005e0: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; 80005e2: 2304 movs r3, #4 80005e4: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; 80005e6: 2340 movs r3, #64 @ 0x40 80005e8: 61bb str r3, [r7, #24] RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; 80005ea: f44f 6380 mov.w r3, #1024 @ 0x400 80005ee: 61fb str r3, [r7, #28] RCC_ClkInitStruct.APB5CLKDivider = RCC_APB5_DIV2; 80005f0: f44f 4380 mov.w r3, #16384 @ 0x4000 80005f4: 623b str r3, [r7, #32] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) 80005f6: 1d3b adds r3, r7, #4 80005f8: 2137 movs r1, #55 @ 0x37 80005fa: 4618 mov r0, r3 80005fc: f001 ff2e bl 800245c 8000600: 4603 mov r3, r0 8000602: 2b00 cmp r3, #0 8000604: d001 beq.n 800060a { Error_Handler(); 8000606: f000 f975 bl 80008f4 } } 800060a: bf00 nop 800060c: 37c0 adds r7, #192 @ 0xc0 800060e: 46bd mov sp, r7 8000610: bd80 pop {r7, pc} 08000612 : * @brief FLASH Initialization Function * @param None * @retval None */ static void MX_FLASH_Init(void) { 8000612: b580 push {r7, lr} 8000614: b08c sub sp, #48 @ 0x30 8000616: af00 add r7, sp, #0 /* USER CODE BEGIN FLASH_Init 0 */ /* USER CODE END FLASH_Init 0 */ FLASH_OBProgramInitTypeDef pOBInit = {0}; 8000618: 1d3b adds r3, r7, #4 800061a: 222c movs r2, #44 @ 0x2c 800061c: 2100 movs r1, #0 800061e: 4618 mov r0, r3 8000620: f009 fd38 bl 800a094 /* USER CODE BEGIN FLASH_Init 1 */ /* USER CODE END FLASH_Init 1 */ HAL_FLASHEx_OBGetConfig(&pOBInit); 8000624: 1d3b adds r3, r7, #4 8000626: 4618 mov r0, r3 8000628: f000 ffd6 bl 80015d8 if ((pOBInit.USERConfig1 & OB_IWDG_SW) != OB_IWDG_SW|| 800062c: 697b ldr r3, [r7, #20] 800062e: f003 0310 and.w r3, r3, #16 8000632: 2b00 cmp r3, #0 8000634: d00e beq.n 8000654 (pOBInit.USERConfig1 & OB_XSPI1_HSLV_ENABLE) != OB_XSPI1_HSLV_ENABLE|| 8000636: 697b ldr r3, [r7, #20] 8000638: f403 7380 and.w r3, r3, #256 @ 0x100 if ((pOBInit.USERConfig1 & OB_IWDG_SW) != OB_IWDG_SW|| 800063c: 2b00 cmp r3, #0 800063e: d009 beq.n 8000654 (pOBInit.USERConfig1 & OB_XSPI2_HSLV_ENABLE) != OB_XSPI2_HSLV_ENABLE|| 8000640: 697b ldr r3, [r7, #20] 8000642: f403 7300 and.w r3, r3, #512 @ 0x200 (pOBInit.USERConfig1 & OB_XSPI1_HSLV_ENABLE) != OB_XSPI1_HSLV_ENABLE|| 8000646: 2b00 cmp r3, #0 8000648: d004 beq.n 8000654 (pOBInit.USERConfig2 & OB_I2C_NI3C_I2C) != OB_I2C_NI3C_I2C) 800064a: 69bb ldr r3, [r7, #24] 800064c: f403 7300 and.w r3, r3, #512 @ 0x200 (pOBInit.USERConfig1 & OB_XSPI2_HSLV_ENABLE) != OB_XSPI2_HSLV_ENABLE|| 8000650: 2b00 cmp r3, #0 8000652: d12f bne.n 80006b4 { if (HAL_FLASH_Unlock() != HAL_OK) 8000654: f000 fe76 bl 8001344 8000658: 4603 mov r3, r0 800065a: 2b00 cmp r3, #0 800065c: d001 beq.n 8000662 { Error_Handler(); 800065e: f000 f949 bl 80008f4 } if (HAL_FLASH_OB_Unlock() != HAL_OK) 8000662: f000 fea9 bl 80013b8 8000666: 4603 mov r3, r0 8000668: 2b00 cmp r3, #0 800066a: d001 beq.n 8000670 { Error_Handler(); 800066c: f000 f942 bl 80008f4 } pOBInit.OptionType = OPTIONBYTE_USER; 8000670: 2302 movs r3, #2 8000672: 607b str r3, [r7, #4] pOBInit.USERType = OB_USER_IWDG_SW|OB_USER_XSPI1_HSLV 8000674: f241 0332 movw r3, #4146 @ 0x1032 8000678: 613b str r3, [r7, #16] |OB_USER_XSPI2_HSLV|OB_USER_I2C_NI3C; pOBInit.USERConfig1 = OB_IWDG_SW|OB_XSPI1_HSLV_ENABLE 800067a: f44f 7344 mov.w r3, #784 @ 0x310 800067e: 617b str r3, [r7, #20] |OB_XSPI2_HSLV_ENABLE; pOBInit.USERConfig2 = OB_I2C_NI3C_I2C; 8000680: f44f 7300 mov.w r3, #512 @ 0x200 8000684: 61bb str r3, [r7, #24] if (HAL_FLASHEx_OBProgram(&pOBInit) != HAL_OK) 8000686: 1d3b adds r3, r7, #4 8000688: 4618 mov r0, r3 800068a: f000 ff2f bl 80014ec 800068e: 4603 mov r3, r0 8000690: 2b00 cmp r3, #0 8000692: d001 beq.n 8000698 { Error_Handler(); 8000694: f000 f92e bl 80008f4 } if (HAL_FLASH_OB_Lock() != HAL_OK) 8000698: f000 feb4 bl 8001404 800069c: 4603 mov r3, r0 800069e: 2b00 cmp r3, #0 80006a0: d001 beq.n 80006a6 { Error_Handler(); 80006a2: f000 f927 bl 80008f4 } if (HAL_FLASH_Lock() != HAL_OK) 80006a6: f000 fe6f bl 8001388 80006aa: 4603 mov r3, r0 80006ac: 2b00 cmp r3, #0 80006ae: d001 beq.n 80006b4 { Error_Handler(); 80006b0: f000 f920 bl 80008f4 } /* USER CODE BEGIN FLASH_Init 2 */ /* USER CODE END FLASH_Init 2 */ } 80006b4: bf00 nop 80006b6: 3730 adds r7, #48 @ 0x30 80006b8: 46bd mov sp, r7 80006ba: bd80 pop {r7, pc} 080006bc : * @brief GPDMA1 Initialization Function * @param None * @retval None */ static void MX_GPDMA1_Init(void) { 80006bc: b480 push {r7} 80006be: b083 sub sp, #12 80006c0: af00 add r7, sp, #0 /* USER CODE BEGIN GPDMA1_Init 0 */ /* USER CODE END GPDMA1_Init 0 */ /* Peripheral clock enable */ __HAL_RCC_GPDMA1_CLK_ENABLE(); 80006c2: 4b09 ldr r3, [pc, #36] @ (80006e8 ) 80006c4: f8d3 3138 ldr.w r3, [r3, #312] @ 0x138 80006c8: 4a07 ldr r2, [pc, #28] @ (80006e8 ) 80006ca: f043 0310 orr.w r3, r3, #16 80006ce: f8c2 3138 str.w r3, [r2, #312] @ 0x138 80006d2: 4b05 ldr r3, [pc, #20] @ (80006e8 ) 80006d4: f8d3 3138 ldr.w r3, [r3, #312] @ 0x138 80006d8: 607b str r3, [r7, #4] 80006da: 687b ldr r3, [r7, #4] /* USER CODE END GPDMA1_Init 1 */ /* USER CODE BEGIN GPDMA1_Init 2 */ /* USER CODE END GPDMA1_Init 2 */ } 80006dc: bf00 nop 80006de: 370c adds r7, #12 80006e0: 46bd mov sp, r7 80006e2: f85d 7b04 ldr.w r7, [sp], #4 80006e6: 4770 bx lr 80006e8: 58024400 .word 0x58024400 080006ec : * @brief HPDMA1 Initialization Function * @param None * @retval None */ static void MX_HPDMA1_Init(void) { 80006ec: b480 push {r7} 80006ee: b083 sub sp, #12 80006f0: af00 add r7, sp, #0 /* USER CODE BEGIN HPDMA1_Init 0 */ /* USER CODE END HPDMA1_Init 0 */ /* Peripheral clock enable */ __HAL_RCC_HPDMA1_CLK_ENABLE(); 80006f2: 4b09 ldr r3, [pc, #36] @ (8000718 ) 80006f4: f8d3 3134 ldr.w r3, [r3, #308] @ 0x134 80006f8: 4a07 ldr r2, [pc, #28] @ (8000718 ) 80006fa: f043 0301 orr.w r3, r3, #1 80006fe: f8c2 3134 str.w r3, [r2, #308] @ 0x134 8000702: 4b05 ldr r3, [pc, #20] @ (8000718 ) 8000704: f8d3 3134 ldr.w r3, [r3, #308] @ 0x134 8000708: 607b str r3, [r7, #4] 800070a: 687b ldr r3, [r7, #4] /* USER CODE END HPDMA1_Init 1 */ /* USER CODE BEGIN HPDMA1_Init 2 */ /* USER CODE END HPDMA1_Init 2 */ } 800070c: bf00 nop 800070e: 370c adds r7, #12 8000710: 46bd mov sp, r7 8000712: f85d 7b04 ldr.w r7, [sp], #4 8000716: 4770 bx lr 8000718: 58024400 .word 0x58024400 0800071c : * @brief SBS Initialization Function * @param None * @retval None */ static void MX_SBS_Init(void) { 800071c: b480 push {r7} 800071e: af00 add r7, sp, #0 /* USER CODE END SBS_Init 1 */ /* USER CODE BEGIN SBS_Init 2 */ /* USER CODE END SBS_Init 2 */ } 8000720: bf00 nop 8000722: 46bd mov sp, r7 8000724: f85d 7b04 ldr.w r7, [sp], #4 8000728: 4770 bx lr ... 0800072c : * @brief XSPI1 Initialization Function * @param None * @retval None */ static void MX_XSPI1_Init(void) { 800072c: b580 push {r7, lr} 800072e: b084 sub sp, #16 8000730: af00 add r7, sp, #0 /* USER CODE BEGIN XSPI1_Init 0 */ /* USER CODE END XSPI1_Init 0 */ XSPIM_CfgTypeDef sXspiManagerCfg = {0}; 8000732: 1d3b adds r3, r7, #4 8000734: 2200 movs r2, #0 8000736: 601a str r2, [r3, #0] 8000738: 605a str r2, [r3, #4] 800073a: 609a str r2, [r3, #8] /* USER CODE BEGIN XSPI1_Init 1 */ /* USER CODE END XSPI1_Init 1 */ /* XSPI1 parameter configuration*/ hxspi1.Instance = XSPI1; 800073c: 4b26 ldr r3, [pc, #152] @ (80007d8 ) 800073e: 4a27 ldr r2, [pc, #156] @ (80007dc ) 8000740: 601a str r2, [r3, #0] hxspi1.Init.FifoThresholdByte = 2; 8000742: 4b25 ldr r3, [pc, #148] @ (80007d8 ) 8000744: 2202 movs r2, #2 8000746: 605a str r2, [r3, #4] hxspi1.Init.MemoryMode = HAL_XSPI_SINGLE_MEM; 8000748: 4b23 ldr r3, [pc, #140] @ (80007d8 ) 800074a: 2200 movs r2, #0 800074c: 609a str r2, [r3, #8] hxspi1.Init.MemoryType = HAL_XSPI_MEMTYPE_APMEM_16BITS; 800074e: 4b22 ldr r3, [pc, #136] @ (80007d8 ) 8000750: f04f 62c0 mov.w r2, #100663296 @ 0x6000000 8000754: 60da str r2, [r3, #12] hxspi1.Init.MemorySize = HAL_XSPI_SIZE_256MB; 8000756: 4b20 ldr r3, [pc, #128] @ (80007d8 ) 8000758: 2218 movs r2, #24 800075a: 611a str r2, [r3, #16] hxspi1.Init.ChipSelectHighTimeCycle = 5; 800075c: 4b1e ldr r3, [pc, #120] @ (80007d8 ) 800075e: 2205 movs r2, #5 8000760: 615a str r2, [r3, #20] hxspi1.Init.FreeRunningClock = HAL_XSPI_FREERUNCLK_DISABLE; 8000762: 4b1d ldr r3, [pc, #116] @ (80007d8 ) 8000764: 2200 movs r2, #0 8000766: 619a str r2, [r3, #24] hxspi1.Init.ClockMode = HAL_XSPI_CLOCK_MODE_0; 8000768: 4b1b ldr r3, [pc, #108] @ (80007d8 ) 800076a: 2200 movs r2, #0 800076c: 61da str r2, [r3, #28] hxspi1.Init.WrapSize = HAL_XSPI_WRAP_32_BYTES; 800076e: 4b1a ldr r3, [pc, #104] @ (80007d8 ) 8000770: f44f 3240 mov.w r2, #196608 @ 0x30000 8000774: 621a str r2, [r3, #32] hxspi1.Init.ClockPrescaler = 0; 8000776: 4b18 ldr r3, [pc, #96] @ (80007d8 ) 8000778: 2200 movs r2, #0 800077a: 625a str r2, [r3, #36] @ 0x24 hxspi1.Init.SampleShifting = HAL_XSPI_SAMPLE_SHIFT_NONE; 800077c: 4b16 ldr r3, [pc, #88] @ (80007d8 ) 800077e: 2200 movs r2, #0 8000780: 629a str r2, [r3, #40] @ 0x28 hxspi1.Init.ChipSelectBoundary = HAL_XSPI_BONDARYOF_16KB; 8000782: 4b15 ldr r3, [pc, #84] @ (80007d8 ) 8000784: 220b movs r2, #11 8000786: 631a str r2, [r3, #48] @ 0x30 hxspi1.Init.MaxTran = 0; 8000788: 4b13 ldr r3, [pc, #76] @ (80007d8 ) 800078a: 2200 movs r2, #0 800078c: 635a str r2, [r3, #52] @ 0x34 hxspi1.Init.Refresh = 400; 800078e: 4b12 ldr r3, [pc, #72] @ (80007d8 ) 8000790: f44f 72c8 mov.w r2, #400 @ 0x190 8000794: 639a str r2, [r3, #56] @ 0x38 hxspi1.Init.MemorySelect = HAL_XSPI_CSSEL_NCS1; 8000796: 4b10 ldr r3, [pc, #64] @ (80007d8 ) 8000798: 2200 movs r2, #0 800079a: 63da str r2, [r3, #60] @ 0x3c if (HAL_XSPI_Init(&hxspi1) != HAL_OK) 800079c: 480e ldr r0, [pc, #56] @ (80007d8 ) 800079e: f005 f841 bl 8005824 80007a2: 4603 mov r3, r0 80007a4: 2b00 cmp r3, #0 80007a6: d001 beq.n 80007ac { Error_Handler(); 80007a8: f000 f8a4 bl 80008f4 } sXspiManagerCfg.nCSOverride = HAL_XSPI_CSSEL_OVR_NCS1; 80007ac: 2310 movs r3, #16 80007ae: 607b str r3, [r7, #4] sXspiManagerCfg.IOPort = HAL_XSPIM_IOPORT_1; 80007b0: 2300 movs r3, #0 80007b2: 60bb str r3, [r7, #8] sXspiManagerCfg.Req2AckTime = 1; 80007b4: 2301 movs r3, #1 80007b6: 60fb str r3, [r7, #12] if (HAL_XSPIM_Config(&hxspi1, &sXspiManagerCfg, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) 80007b8: 1d3b adds r3, r7, #4 80007ba: f241 3288 movw r2, #5000 @ 0x1388 80007be: 4619 mov r1, r3 80007c0: 4805 ldr r0, [pc, #20] @ (80007d8 ) 80007c2: f006 f887 bl 80068d4 80007c6: 4603 mov r3, r0 80007c8: 2b00 cmp r3, #0 80007ca: d001 beq.n 80007d0 { Error_Handler(); 80007cc: f000 f892 bl 80008f4 } /* USER CODE BEGIN XSPI1_Init 2 */ /* USER CODE END XSPI1_Init 2 */ } 80007d0: bf00 nop 80007d2: 3710 adds r7, #16 80007d4: 46bd mov sp, r7 80007d6: bd80 pop {r7, pc} 80007d8: 24000028 .word 0x24000028 80007dc: 52005000 .word 0x52005000 080007e0 : * @brief XSPI2 Initialization Function * @param None * @retval None */ static void MX_XSPI2_Init(void) { 80007e0: b580 push {r7, lr} 80007e2: b084 sub sp, #16 80007e4: af00 add r7, sp, #0 /* USER CODE BEGIN XSPI2_Init 0 */ /* USER CODE END XSPI2_Init 0 */ XSPIM_CfgTypeDef sXspiManagerCfg = {0}; 80007e6: 1d3b adds r3, r7, #4 80007e8: 2200 movs r2, #0 80007ea: 601a str r2, [r3, #0] 80007ec: 605a str r2, [r3, #4] 80007ee: 609a str r2, [r3, #8] /* USER CODE BEGIN XSPI2_Init 1 */ /* USER CODE END XSPI2_Init 1 */ /* XSPI2 parameter configuration*/ hxspi2.Instance = XSPI2; 80007f0: 4b25 ldr r3, [pc, #148] @ (8000888 ) 80007f2: 4a26 ldr r2, [pc, #152] @ (800088c ) 80007f4: 601a str r2, [r3, #0] hxspi2.Init.FifoThresholdByte = 4; 80007f6: 4b24 ldr r3, [pc, #144] @ (8000888 ) 80007f8: 2204 movs r2, #4 80007fa: 605a str r2, [r3, #4] hxspi2.Init.MemoryMode = HAL_XSPI_SINGLE_MEM; 80007fc: 4b22 ldr r3, [pc, #136] @ (8000888 ) 80007fe: 2200 movs r2, #0 8000800: 609a str r2, [r3, #8] hxspi2.Init.MemoryType = HAL_XSPI_MEMTYPE_MACRONIX; 8000802: 4b21 ldr r3, [pc, #132] @ (8000888 ) 8000804: f04f 7280 mov.w r2, #16777216 @ 0x1000000 8000808: 60da str r2, [r3, #12] hxspi2.Init.MemorySize = HAL_XSPI_SIZE_1GB; 800080a: 4b1f ldr r3, [pc, #124] @ (8000888 ) 800080c: 221a movs r2, #26 800080e: 611a str r2, [r3, #16] hxspi2.Init.ChipSelectHighTimeCycle = 2; 8000810: 4b1d ldr r3, [pc, #116] @ (8000888 ) 8000812: 2202 movs r2, #2 8000814: 615a str r2, [r3, #20] hxspi2.Init.FreeRunningClock = HAL_XSPI_FREERUNCLK_DISABLE; 8000816: 4b1c ldr r3, [pc, #112] @ (8000888 ) 8000818: 2200 movs r2, #0 800081a: 619a str r2, [r3, #24] hxspi2.Init.ClockMode = HAL_XSPI_CLOCK_MODE_0; 800081c: 4b1a ldr r3, [pc, #104] @ (8000888 ) 800081e: 2200 movs r2, #0 8000820: 61da str r2, [r3, #28] hxspi2.Init.WrapSize = HAL_XSPI_WRAP_NOT_SUPPORTED; 8000822: 4b19 ldr r3, [pc, #100] @ (8000888 ) 8000824: 2200 movs r2, #0 8000826: 621a str r2, [r3, #32] hxspi2.Init.ClockPrescaler = 0; 8000828: 4b17 ldr r3, [pc, #92] @ (8000888 ) 800082a: 2200 movs r2, #0 800082c: 625a str r2, [r3, #36] @ 0x24 hxspi2.Init.SampleShifting = HAL_XSPI_SAMPLE_SHIFT_NONE; 800082e: 4b16 ldr r3, [pc, #88] @ (8000888 ) 8000830: 2200 movs r2, #0 8000832: 629a str r2, [r3, #40] @ 0x28 hxspi2.Init.ChipSelectBoundary = HAL_XSPI_BONDARYOF_NONE; 8000834: 4b14 ldr r3, [pc, #80] @ (8000888 ) 8000836: 2200 movs r2, #0 8000838: 631a str r2, [r3, #48] @ 0x30 hxspi2.Init.MaxTran = 0; 800083a: 4b13 ldr r3, [pc, #76] @ (8000888 ) 800083c: 2200 movs r2, #0 800083e: 635a str r2, [r3, #52] @ 0x34 hxspi2.Init.Refresh = 0; 8000840: 4b11 ldr r3, [pc, #68] @ (8000888 ) 8000842: 2200 movs r2, #0 8000844: 639a str r2, [r3, #56] @ 0x38 hxspi2.Init.MemorySelect = HAL_XSPI_CSSEL_NCS1; 8000846: 4b10 ldr r3, [pc, #64] @ (8000888 ) 8000848: 2200 movs r2, #0 800084a: 63da str r2, [r3, #60] @ 0x3c if (HAL_XSPI_Init(&hxspi2) != HAL_OK) 800084c: 480e ldr r0, [pc, #56] @ (8000888 ) 800084e: f004 ffe9 bl 8005824 8000852: 4603 mov r3, r0 8000854: 2b00 cmp r3, #0 8000856: d001 beq.n 800085c { Error_Handler(); 8000858: f000 f84c bl 80008f4 } sXspiManagerCfg.nCSOverride = HAL_XSPI_CSSEL_OVR_NCS1; 800085c: 2310 movs r3, #16 800085e: 607b str r3, [r7, #4] sXspiManagerCfg.IOPort = HAL_XSPIM_IOPORT_2; 8000860: 2301 movs r3, #1 8000862: 60bb str r3, [r7, #8] sXspiManagerCfg.Req2AckTime = 1; 8000864: 2301 movs r3, #1 8000866: 60fb str r3, [r7, #12] if (HAL_XSPIM_Config(&hxspi2, &sXspiManagerCfg, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) 8000868: 1d3b adds r3, r7, #4 800086a: f241 3288 movw r2, #5000 @ 0x1388 800086e: 4619 mov r1, r3 8000870: 4805 ldr r0, [pc, #20] @ (8000888 ) 8000872: f006 f82f bl 80068d4 8000876: 4603 mov r3, r0 8000878: 2b00 cmp r3, #0 800087a: d001 beq.n 8000880 { Error_Handler(); 800087c: f000 f83a bl 80008f4 } /* USER CODE BEGIN XSPI2_Init 2 */ /* USER CODE END XSPI2_Init 2 */ } 8000880: bf00 nop 8000882: 3710 adds r7, #16 8000884: 46bd mov sp, r7 8000886: bd80 pop {r7, pc} 8000888: 240000b8 .word 0x240000b8 800088c: 5200a000 .word 0x5200a000 08000890 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8000890: b480 push {r7} 8000892: b085 sub sp, #20 8000894: af00 add r7, sp, #0 /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPION_CLK_ENABLE(); 8000896: 4b16 ldr r3, [pc, #88] @ (80008f0 ) 8000898: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140 800089c: 4a14 ldr r2, [pc, #80] @ (80008f0 ) 800089e: f443 5300 orr.w r3, r3, #8192 @ 0x2000 80008a2: f8c2 3140 str.w r3, [r2, #320] @ 0x140 80008a6: 4b12 ldr r3, [pc, #72] @ (80008f0 ) 80008a8: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140 80008ac: 60fb str r3, [r7, #12] 80008ae: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOO_CLK_ENABLE(); 80008b0: 4b0f ldr r3, [pc, #60] @ (80008f0 ) 80008b2: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140 80008b6: 4a0e ldr r2, [pc, #56] @ (80008f0 ) 80008b8: f443 4380 orr.w r3, r3, #16384 @ 0x4000 80008bc: f8c2 3140 str.w r3, [r2, #320] @ 0x140 80008c0: 4b0b ldr r3, [pc, #44] @ (80008f0 ) 80008c2: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140 80008c6: 60bb str r3, [r7, #8] 80008c8: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOP_CLK_ENABLE(); 80008ca: 4b09 ldr r3, [pc, #36] @ (80008f0 ) 80008cc: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140 80008d0: 4a07 ldr r2, [pc, #28] @ (80008f0 ) 80008d2: f443 4300 orr.w r3, r3, #32768 @ 0x8000 80008d6: f8c2 3140 str.w r3, [r2, #320] @ 0x140 80008da: 4b05 ldr r3, [pc, #20] @ (80008f0 ) 80008dc: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140 80008e0: 607b str r3, [r7, #4] 80008e2: 687b ldr r3, [r7, #4] /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 80008e4: bf00 nop 80008e6: 3714 adds r7, #20 80008e8: 46bd mov sp, r7 80008ea: f85d 7b04 ldr.w r7, [sp], #4 80008ee: 4770 bx lr 80008f0: 58024400 .word 0x58024400 080008f4 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 80008f4: b480 push {r7} 80008f6: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting special-purpose register PRIMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 80008f8: b672 cpsid i } 80008fa: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 80008fc: bf00 nop 80008fe: e7fd b.n 80008fc 08000900 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8000900: b580 push {r7, lr} 8000902: b082 sub sp, #8 8000904: af00 add r7, sp, #0 /* Configure the system Power Supply */ if (HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY) != HAL_OK) 8000906: 2004 movs r0, #4 8000908: f001 f9d4 bl 8001cb4 800090c: 4603 mov r3, r0 800090e: 2b00 cmp r3, #0 8000910: d001 beq.n 8000916 { /* Initialization error */ Error_Handler(); 8000912: f7ff ffef bl 80008f4 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SBS_CLK_ENABLE(); 8000916: 4b0e ldr r3, [pc, #56] @ (8000950 ) 8000918: f8d3 3154 ldr.w r3, [r3, #340] @ 0x154 800091c: 4a0c ldr r2, [pc, #48] @ (8000950 ) 800091e: f043 0302 orr.w r3, r3, #2 8000922: f8c2 3154 str.w r3, [r2, #340] @ 0x154 8000926: 4b0a ldr r3, [pc, #40] @ (8000950 ) 8000928: f8d3 3154 ldr.w r3, [r3, #340] @ 0x154 800092c: 607b str r3, [r7, #4] 800092e: 687b ldr r3, [r7, #4] /* System interrupt init*/ /* Enable the XSPIM_P1 interface */ HAL_PWREx_EnableXSPIM1(); 8000930: f001 fa3a bl 8001da8 /* Enable the XSPIM_P2 interface */ HAL_PWREx_EnableXSPIM2(); 8000934: f001 fa48 bl 8001dc8 /* USER CODE BEGIN MspInit 1 */ /* high speed low voltage config */ HAL_SBS_EnableIOSpeedOptimize(SBS_IO_XSPI1_HSLV); 8000938: f44f 3000 mov.w r0, #131072 @ 0x20000 800093c: f000 fa18 bl 8000d70 HAL_SBS_EnableIOSpeedOptimize(SBS_IO_XSPI2_HSLV); 8000940: f44f 2080 mov.w r0, #262144 @ 0x40000 8000944: f000 fa14 bl 8000d70 /* USER CODE END MspInit 1 */ } 8000948: bf00 nop 800094a: 3708 adds r7, #8 800094c: 46bd mov sp, r7 800094e: bd80 pop {r7, pc} 8000950: 58024400 .word 0x58024400 08000954 : * This function configures the hardware resources used in this example * @param hxspi: XSPI handle pointer * @retval None */ void HAL_XSPI_MspInit(XSPI_HandleTypeDef* hxspi) { 8000954: b580 push {r7, lr} 8000956: b0b0 sub sp, #192 @ 0xc0 8000958: af00 add r7, sp, #0 800095a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800095c: f107 03ac add.w r3, r7, #172 @ 0xac 8000960: 2200 movs r2, #0 8000962: 601a str r2, [r3, #0] 8000964: 605a str r2, [r3, #4] 8000966: 609a str r2, [r3, #8] 8000968: 60da str r2, [r3, #12] 800096a: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 800096c: f107 0328 add.w r3, r7, #40 @ 0x28 8000970: 2284 movs r2, #132 @ 0x84 8000972: 2100 movs r1, #0 8000974: 4618 mov r0, r3 8000976: f009 fb8d bl 800a094 if(hxspi->Instance==XSPI1) 800097a: 687b ldr r3, [r7, #4] 800097c: 681b ldr r3, [r3, #0] 800097e: 4a6b ldr r2, [pc, #428] @ (8000b2c ) 8000980: 4293 cmp r3, r2 8000982: d176 bne.n 8000a72 /* USER CODE END XSPI1_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_XSPI1; 8000984: 2302 movs r3, #2 8000986: 62bb str r3, [r7, #40] @ 0x28 PeriphClkInit.Xspi1ClockSelection = RCC_XSPI1CLKSOURCE_PLL2S; 8000988: 2310 movs r3, #16 800098a: 633b str r3, [r7, #48] @ 0x30 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 800098c: f107 0328 add.w r3, r7, #40 @ 0x28 8000990: 4618 mov r0, r3 8000992: f002 fca3 bl 80032dc 8000996: 4603 mov r3, r0 8000998: 2b00 cmp r3, #0 800099a: d001 beq.n 80009a0 { Error_Handler(); 800099c: f7ff ffaa bl 80008f4 } /* Peripheral clock enable */ HAL_RCC_XSPIM_CLK_ENABLED++; 80009a0: 4b63 ldr r3, [pc, #396] @ (8000b30 ) 80009a2: 681b ldr r3, [r3, #0] 80009a4: 3301 adds r3, #1 80009a6: 4a62 ldr r2, [pc, #392] @ (8000b30 ) 80009a8: 6013 str r3, [r2, #0] if(HAL_RCC_XSPIM_CLK_ENABLED==1){ 80009aa: 4b61 ldr r3, [pc, #388] @ (8000b30 ) 80009ac: 681b ldr r3, [r3, #0] 80009ae: 2b01 cmp r3, #1 80009b0: d10c bne.n 80009cc __HAL_RCC_XSPIM_CLK_ENABLE(); 80009b2: 4b60 ldr r3, [pc, #384] @ (8000b34 ) 80009b4: f8d3 3134 ldr.w r3, [r3, #308] @ 0x134 80009b8: 4a5e ldr r2, [pc, #376] @ (8000b34 ) 80009ba: f443 4380 orr.w r3, r3, #16384 @ 0x4000 80009be: f8c2 3134 str.w r3, [r2, #308] @ 0x134 80009c2: 4b5c ldr r3, [pc, #368] @ (8000b34 ) 80009c4: f8d3 3134 ldr.w r3, [r3, #308] @ 0x134 80009c8: 627b str r3, [r7, #36] @ 0x24 80009ca: 6a7b ldr r3, [r7, #36] @ 0x24 } __HAL_RCC_XSPI1_CLK_ENABLE(); 80009cc: 4b59 ldr r3, [pc, #356] @ (8000b34 ) 80009ce: f8d3 3134 ldr.w r3, [r3, #308] @ 0x134 80009d2: 4a58 ldr r2, [pc, #352] @ (8000b34 ) 80009d4: f043 0320 orr.w r3, r3, #32 80009d8: f8c2 3134 str.w r3, [r2, #308] @ 0x134 80009dc: 4b55 ldr r3, [pc, #340] @ (8000b34 ) 80009de: f8d3 3134 ldr.w r3, [r3, #308] @ 0x134 80009e2: 623b str r3, [r7, #32] 80009e4: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOO_CLK_ENABLE(); 80009e6: 4b53 ldr r3, [pc, #332] @ (8000b34 ) 80009e8: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140 80009ec: 4a51 ldr r2, [pc, #324] @ (8000b34 ) 80009ee: f443 4380 orr.w r3, r3, #16384 @ 0x4000 80009f2: f8c2 3140 str.w r3, [r2, #320] @ 0x140 80009f6: 4b4f ldr r3, [pc, #316] @ (8000b34 ) 80009f8: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140 80009fc: 61fb str r3, [r7, #28] 80009fe: 69fb ldr r3, [r7, #28] __HAL_RCC_GPIOP_CLK_ENABLE(); 8000a00: 4b4c ldr r3, [pc, #304] @ (8000b34 ) 8000a02: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140 8000a06: 4a4b ldr r2, [pc, #300] @ (8000b34 ) 8000a08: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8000a0c: f8c2 3140 str.w r3, [r2, #320] @ 0x140 8000a10: 4b48 ldr r3, [pc, #288] @ (8000b34 ) 8000a12: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140 8000a16: 61bb str r3, [r7, #24] 8000a18: 69bb ldr r3, [r7, #24] PO4 ------> XSPIM_P1_CLK PP6 ------> XSPIM_P1_IO6 PO0 ------> XSPIM_P1_NCS1 PP9 ------> XSPIM_P1_IO9 */ GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_0; 8000a1a: 231d movs r3, #29 8000a1c: f8c7 30ac str.w r3, [r7, #172] @ 0xac GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000a20: 2302 movs r3, #2 8000a22: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000a26: 2300 movs r3, #0 8000a28: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8000a2c: 2303 movs r3, #3 8000a2e: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 GPIO_InitStruct.Alternate = GPIO_AF9_XSPIM_P1; 8000a32: 2309 movs r3, #9 8000a34: f8c7 30bc str.w r3, [r7, #188] @ 0xbc HAL_GPIO_Init(GPIOO, &GPIO_InitStruct); 8000a38: f107 03ac add.w r3, r7, #172 @ 0xac 8000a3c: 4619 mov r1, r3 8000a3e: 483e ldr r0, [pc, #248] @ (8000b38 ) 8000a40: f000 ffc8 bl 80019d4 GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_12|GPIO_PIN_14|GPIO_PIN_2 8000a44: f64f 73ff movw r3, #65535 @ 0xffff 8000a48: f8c7 30ac str.w r3, [r7, #172] @ 0xac |GPIO_PIN_5|GPIO_PIN_1|GPIO_PIN_11|GPIO_PIN_15 |GPIO_PIN_3|GPIO_PIN_0|GPIO_PIN_7|GPIO_PIN_8 |GPIO_PIN_13|GPIO_PIN_4|GPIO_PIN_6|GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000a4c: 2302 movs r3, #2 8000a4e: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000a52: 2300 movs r3, #0 8000a54: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8000a58: 2303 movs r3, #3 8000a5a: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 GPIO_InitStruct.Alternate = GPIO_AF9_XSPIM_P1; 8000a5e: 2309 movs r3, #9 8000a60: f8c7 30bc str.w r3, [r7, #188] @ 0xbc HAL_GPIO_Init(GPIOP, &GPIO_InitStruct); 8000a64: f107 03ac add.w r3, r7, #172 @ 0xac 8000a68: 4619 mov r1, r3 8000a6a: 4834 ldr r0, [pc, #208] @ (8000b3c ) 8000a6c: f000 ffb2 bl 80019d4 /* USER CODE BEGIN XSPI2_MspInit 1 */ /* USER CODE END XSPI2_MspInit 1 */ } } 8000a70: e058 b.n 8000b24 else if(hxspi->Instance==XSPI2) 8000a72: 687b ldr r3, [r7, #4] 8000a74: 681b ldr r3, [r3, #0] 8000a76: 4a32 ldr r2, [pc, #200] @ (8000b40 ) 8000a78: 4293 cmp r3, r2 8000a7a: d153 bne.n 8000b24 PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_XSPI2; 8000a7c: 2304 movs r3, #4 8000a7e: 62bb str r3, [r7, #40] @ 0x28 PeriphClkInit.Xspi2ClockSelection = RCC_XSPI2CLKSOURCE_PLL2S; 8000a80: 2340 movs r3, #64 @ 0x40 8000a82: 637b str r3, [r7, #52] @ 0x34 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8000a84: f107 0328 add.w r3, r7, #40 @ 0x28 8000a88: 4618 mov r0, r3 8000a8a: f002 fc27 bl 80032dc 8000a8e: 4603 mov r3, r0 8000a90: 2b00 cmp r3, #0 8000a92: d001 beq.n 8000a98 Error_Handler(); 8000a94: f7ff ff2e bl 80008f4 HAL_RCC_XSPIM_CLK_ENABLED++; 8000a98: 4b25 ldr r3, [pc, #148] @ (8000b30 ) 8000a9a: 681b ldr r3, [r3, #0] 8000a9c: 3301 adds r3, #1 8000a9e: 4a24 ldr r2, [pc, #144] @ (8000b30 ) 8000aa0: 6013 str r3, [r2, #0] if(HAL_RCC_XSPIM_CLK_ENABLED==1){ 8000aa2: 4b23 ldr r3, [pc, #140] @ (8000b30 ) 8000aa4: 681b ldr r3, [r3, #0] 8000aa6: 2b01 cmp r3, #1 8000aa8: d10c bne.n 8000ac4 __HAL_RCC_XSPIM_CLK_ENABLE(); 8000aaa: 4b22 ldr r3, [pc, #136] @ (8000b34 ) 8000aac: f8d3 3134 ldr.w r3, [r3, #308] @ 0x134 8000ab0: 4a20 ldr r2, [pc, #128] @ (8000b34 ) 8000ab2: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8000ab6: f8c2 3134 str.w r3, [r2, #308] @ 0x134 8000aba: 4b1e ldr r3, [pc, #120] @ (8000b34 ) 8000abc: f8d3 3134 ldr.w r3, [r3, #308] @ 0x134 8000ac0: 617b str r3, [r7, #20] 8000ac2: 697b ldr r3, [r7, #20] __HAL_RCC_XSPI2_CLK_ENABLE(); 8000ac4: 4b1b ldr r3, [pc, #108] @ (8000b34 ) 8000ac6: f8d3 3134 ldr.w r3, [r3, #308] @ 0x134 8000aca: 4a1a ldr r2, [pc, #104] @ (8000b34 ) 8000acc: f443 5380 orr.w r3, r3, #4096 @ 0x1000 8000ad0: f8c2 3134 str.w r3, [r2, #308] @ 0x134 8000ad4: 4b17 ldr r3, [pc, #92] @ (8000b34 ) 8000ad6: f8d3 3134 ldr.w r3, [r3, #308] @ 0x134 8000ada: 613b str r3, [r7, #16] 8000adc: 693b ldr r3, [r7, #16] __HAL_RCC_GPION_CLK_ENABLE(); 8000ade: 4b15 ldr r3, [pc, #84] @ (8000b34 ) 8000ae0: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140 8000ae4: 4a13 ldr r2, [pc, #76] @ (8000b34 ) 8000ae6: f443 5300 orr.w r3, r3, #8192 @ 0x2000 8000aea: f8c2 3140 str.w r3, [r2, #320] @ 0x140 8000aee: 4b11 ldr r3, [pc, #68] @ (8000b34 ) 8000af0: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140 8000af4: 60fb str r3, [r7, #12] 8000af6: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_3|GPIO_PIN_0|GPIO_PIN_11 8000af8: f640 737f movw r3, #3967 @ 0xf7f 8000afc: f8c7 30ac str.w r3, [r7, #172] @ 0xac GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000b00: 2302 movs r3, #2 8000b02: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000b06: 2300 movs r3, #0 8000b08: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8000b0c: 2303 movs r3, #3 8000b0e: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 GPIO_InitStruct.Alternate = GPIO_AF9_XSPIM_P2; 8000b12: 2309 movs r3, #9 8000b14: f8c7 30bc str.w r3, [r7, #188] @ 0xbc HAL_GPIO_Init(GPION, &GPIO_InitStruct); 8000b18: f107 03ac add.w r3, r7, #172 @ 0xac 8000b1c: 4619 mov r1, r3 8000b1e: 4809 ldr r0, [pc, #36] @ (8000b44 ) 8000b20: f000 ff58 bl 80019d4 } 8000b24: bf00 nop 8000b26: 37c0 adds r7, #192 @ 0xc0 8000b28: 46bd mov sp, r7 8000b2a: bd80 pop {r7, pc} 8000b2c: 52005000 .word 0x52005000 8000b30: 24000148 .word 0x24000148 8000b34: 58024400 .word 0x58024400 8000b38: 58023800 .word 0x58023800 8000b3c: 58023c00 .word 0x58023c00 8000b40: 5200a000 .word 0x5200a000 8000b44: 58023400 .word 0x58023400 08000b48 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8000b48: b480 push {r7} 8000b4a: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8000b4c: bf00 nop 8000b4e: e7fd b.n 8000b4c 08000b50 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8000b50: b480 push {r7} 8000b52: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8000b54: bf00 nop 8000b56: e7fd b.n 8000b54 08000b58 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8000b58: b480 push {r7} 8000b5a: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8000b5c: bf00 nop 8000b5e: e7fd b.n 8000b5c 08000b60 : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 8000b60: b480 push {r7} 8000b62: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8000b64: bf00 nop 8000b66: e7fd b.n 8000b64 08000b68 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8000b68: b480 push {r7} 8000b6a: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8000b6c: bf00 nop 8000b6e: e7fd b.n 8000b6c 08000b70 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8000b70: b480 push {r7} 8000b72: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8000b74: bf00 nop 8000b76: 46bd mov sp, r7 8000b78: f85d 7b04 ldr.w r7, [sp], #4 8000b7c: 4770 bx lr 08000b7e : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8000b7e: b480 push {r7} 8000b80: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8000b82: bf00 nop 8000b84: 46bd mov sp, r7 8000b86: f85d 7b04 ldr.w r7, [sp], #4 8000b8a: 4770 bx lr 08000b8c : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8000b8c: b480 push {r7} 8000b8e: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8000b90: bf00 nop 8000b92: 46bd mov sp, r7 8000b94: f85d 7b04 ldr.w r7, [sp], #4 8000b98: 4770 bx lr 08000b9a : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8000b9a: b580 push {r7, lr} 8000b9c: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8000b9e: f000 f893 bl 8000cc8 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8000ba2: bf00 nop 8000ba4: bd80 pop {r7, pc} ... 08000ba8 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr r0, =_estack 8000ba8: 480d ldr r0, [pc, #52] @ (8000be0 ) mov sp, r0 /* set stack pointer */ 8000baa: 4685 mov sp, r0 /* Call the clock system initialization function.*/ bl SystemInit 8000bac: f000 f826 bl 8000bfc /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8000bb0: 480c ldr r0, [pc, #48] @ (8000be4 ) ldr r1, =_edata 8000bb2: 490d ldr r1, [pc, #52] @ (8000be8 ) ldr r2, =_sidata 8000bb4: 4a0d ldr r2, [pc, #52] @ (8000bec ) movs r3, #0 8000bb6: 2300 movs r3, #0 b LoopCopyDataInit 8000bb8: e002 b.n 8000bc0 08000bba : CopyDataInit: ldr r4, [r2, r3] 8000bba: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8000bbc: 50c4 str r4, [r0, r3] adds r3, r3, #4 8000bbe: 3304 adds r3, #4 08000bc0 : LoopCopyDataInit: adds r4, r0, r3 8000bc0: 18c4 adds r4, r0, r3 cmp r4, r1 8000bc2: 428c cmp r4, r1 bcc CopyDataInit 8000bc4: d3f9 bcc.n 8000bba /* Zero fill the bss segment. */ ldr r2, =_sbss 8000bc6: 4a0a ldr r2, [pc, #40] @ (8000bf0 ) ldr r4, =_ebss 8000bc8: 4c0a ldr r4, [pc, #40] @ (8000bf4 ) movs r3, #0 8000bca: 2300 movs r3, #0 b LoopFillZerobss 8000bcc: e001 b.n 8000bd2 08000bce : FillZerobss: str r3, [r2] 8000bce: 6013 str r3, [r2, #0] adds r2, r2, #4 8000bd0: 3204 adds r2, #4 08000bd2 : LoopFillZerobss: cmp r2, r4 8000bd2: 42a2 cmp r2, r4 bcc FillZerobss 8000bd4: d3fb bcc.n 8000bce /* Call static constructors */ bl __libc_init_array 8000bd6: f009 fa65 bl 800a0a4 <__libc_init_array> /* Call the application's entry point.*/ bl main 8000bda: f7ff fbff bl 80003dc
08000bde : LoopForever: b LoopForever 8000bde: e7fe b.n 8000bde ldr r0, =_estack 8000be0: 20010000 .word 0x20010000 ldr r0, =_sdata 8000be4: 24000000 .word 0x24000000 ldr r1, =_edata 8000be8: 2400000c .word 0x2400000c ldr r2, =_sidata 8000bec: 0800a174 .word 0x0800a174 ldr r2, =_sbss 8000bf0: 2400000c .word 0x2400000c ldr r4, =_ebss 8000bf4: 24000450 .word 0x24000450 08000bf8 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8000bf8: e7fe b.n 8000bf8 ... 08000bfc : * @brief Setup the microcontroller system. * @retval None */ void SystemInit(void) { 8000bfc: b480 push {r7} 8000bfe: af00 add r7, sp, #0 SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; #endif /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ 8000c00: 4b06 ldr r3, [pc, #24] @ (8000c1c ) 8000c02: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8000c06: 4a05 ldr r2, [pc, #20] @ (8000c1c ) 8000c08: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 8000c0c: f8c2 3088 str.w r3, [r2, #136] @ 0x88 #endif } 8000c10: bf00 nop 8000c12: 46bd mov sp, r7 8000c14: f85d 7b04 ldr.w r7, [sp], #4 8000c18: 4770 bx lr 8000c1a: bf00 nop 8000c1c: e000ed00 .word 0xe000ed00 08000c20 : * each 1ms in the SysTick_Handler() interrupt handler. * * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8000c20: b580 push {r7, lr} 8000c22: b082 sub sp, #8 8000c24: af00 add r7, sp, #0 HAL_StatusTypeDef status = HAL_OK; 8000c26: 2300 movs r3, #0 8000c28: 71fb strb r3, [r7, #7] /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8000c2a: 2003 movs r0, #3 8000c2c: f000 f966 bl 8000efc /* Use SysTick as time base source and configure 1ms tick */ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 8000c30: 200f movs r0, #15 8000c32: f000 f80d bl 8000c50 8000c36: 4603 mov r3, r0 8000c38: 2b00 cmp r3, #0 8000c3a: d002 beq.n 8000c42 { status = HAL_ERROR; 8000c3c: 2301 movs r3, #1 8000c3e: 71fb strb r3, [r7, #7] 8000c40: e001 b.n 8000c46 } else { /* Init the low level hardware */ HAL_MspInit(); 8000c42: f7ff fe5d bl 8000900 } /* Return function status */ return status; 8000c46: 79fb ldrb r3, [r7, #7] } 8000c48: 4618 mov r0, r3 8000c4a: 3708 adds r7, #8 8000c4c: 46bd mov sp, r7 8000c4e: bd80 pop {r7, pc} 08000c50 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8000c50: b580 push {r7, lr} 8000c52: b084 sub sp, #16 8000c54: af00 add r7, sp, #0 8000c56: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8000c58: 2300 movs r3, #0 8000c5a: 73fb strb r3, [r7, #15] /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/ if ((uint32_t)uwTickFreq != 0U) 8000c5c: 4b17 ldr r3, [pc, #92] @ (8000cbc ) 8000c5e: 781b ldrb r3, [r3, #0] 8000c60: 2b00 cmp r3, #0 8000c62: d023 beq.n 8000cac { /*Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / (uint32_t)uwTickFreq)) == 0U) 8000c64: 4b16 ldr r3, [pc, #88] @ (8000cc0 ) 8000c66: 681a ldr r2, [r3, #0] 8000c68: 4b14 ldr r3, [pc, #80] @ (8000cbc ) 8000c6a: 781b ldrb r3, [r3, #0] 8000c6c: 4619 mov r1, r3 8000c6e: f44f 737a mov.w r3, #1000 @ 0x3e8 8000c72: fbb3 f3f1 udiv r3, r3, r1 8000c76: fbb2 f3f3 udiv r3, r2, r3 8000c7a: 4618 mov r0, r3 8000c7c: f000 f963 bl 8000f46 8000c80: 4603 mov r3, r0 8000c82: 2b00 cmp r3, #0 8000c84: d10f bne.n 8000ca6 { /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8000c86: 687b ldr r3, [r7, #4] 8000c88: 2b0f cmp r3, #15 8000c8a: d809 bhi.n 8000ca0 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8000c8c: 2200 movs r2, #0 8000c8e: 6879 ldr r1, [r7, #4] 8000c90: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8000c94: f000 f93d bl 8000f12 uwTickPrio = TickPriority; 8000c98: 4a0a ldr r2, [pc, #40] @ (8000cc4 ) 8000c9a: 687b ldr r3, [r7, #4] 8000c9c: 6013 str r3, [r2, #0] 8000c9e: e007 b.n 8000cb0 } else { status = HAL_ERROR; 8000ca0: 2301 movs r3, #1 8000ca2: 73fb strb r3, [r7, #15] 8000ca4: e004 b.n 8000cb0 } } else { status = HAL_ERROR; 8000ca6: 2301 movs r3, #1 8000ca8: 73fb strb r3, [r7, #15] 8000caa: e001 b.n 8000cb0 } } else { status = HAL_ERROR; 8000cac: 2301 movs r3, #1 8000cae: 73fb strb r3, [r7, #15] } /* Return function status */ return status; 8000cb0: 7bfb ldrb r3, [r7, #15] } 8000cb2: 4618 mov r0, r3 8000cb4: 3710 adds r7, #16 8000cb6: 46bd mov sp, r7 8000cb8: bd80 pop {r7, pc} 8000cba: bf00 nop 8000cbc: 24000008 .word 0x24000008 8000cc0: 24000000 .word 0x24000000 8000cc4: 24000004 .word 0x24000004 08000cc8 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8000cc8: b480 push {r7} 8000cca: af00 add r7, sp, #0 uwTick += (uint32_t)uwTickFreq; 8000ccc: 4b06 ldr r3, [pc, #24] @ (8000ce8 ) 8000cce: 781b ldrb r3, [r3, #0] 8000cd0: 461a mov r2, r3 8000cd2: 4b06 ldr r3, [pc, #24] @ (8000cec ) 8000cd4: 681b ldr r3, [r3, #0] 8000cd6: 4413 add r3, r2 8000cd8: 4a04 ldr r2, [pc, #16] @ (8000cec ) 8000cda: 6013 str r3, [r2, #0] } 8000cdc: bf00 nop 8000cde: 46bd mov sp, r7 8000ce0: f85d 7b04 ldr.w r7, [sp], #4 8000ce4: 4770 bx lr 8000ce6: bf00 nop 8000ce8: 24000008 .word 0x24000008 8000cec: 2400014c .word 0x2400014c 08000cf0 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8000cf0: b480 push {r7} 8000cf2: af00 add r7, sp, #0 return uwTick; 8000cf4: 4b03 ldr r3, [pc, #12] @ (8000d04 ) 8000cf6: 681b ldr r3, [r3, #0] } 8000cf8: 4618 mov r0, r3 8000cfa: 46bd mov sp, r7 8000cfc: f85d 7b04 ldr.w r7, [sp], #4 8000d00: 4770 bx lr 8000d02: bf00 nop 8000d04: 2400014c .word 0x2400014c 08000d08 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8000d08: b580 push {r7, lr} 8000d0a: b084 sub sp, #16 8000d0c: af00 add r7, sp, #0 8000d0e: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8000d10: f7ff ffee bl 8000cf0 8000d14: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 8000d16: 687b ldr r3, [r7, #4] 8000d18: 60fb str r3, [r7, #12] /* Add a period to ensure minimum wait */ if (wait < HAL_MAX_DELAY) 8000d1a: 68fb ldr r3, [r7, #12] 8000d1c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8000d20: d005 beq.n 8000d2e { wait += (uint32_t)uwTickFreq; 8000d22: 4b0a ldr r3, [pc, #40] @ (8000d4c ) 8000d24: 781b ldrb r3, [r3, #0] 8000d26: 461a mov r2, r3 8000d28: 68fb ldr r3, [r7, #12] 8000d2a: 4413 add r3, r2 8000d2c: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 8000d2e: bf00 nop 8000d30: f7ff ffde bl 8000cf0 8000d34: 4602 mov r2, r0 8000d36: 68bb ldr r3, [r7, #8] 8000d38: 1ad3 subs r3, r2, r3 8000d3a: 68fa ldr r2, [r7, #12] 8000d3c: 429a cmp r2, r3 8000d3e: d8f7 bhi.n 8000d30 { } } 8000d40: bf00 nop 8000d42: bf00 nop 8000d44: 3710 adds r7, #16 8000d46: 46bd mov sp, r7 8000d48: bd80 pop {r7, pc} 8000d4a: bf00 nop 8000d4c: 24000008 .word 0x24000008 08000d50 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_SuspendTick(void) { 8000d50: b480 push {r7} 8000d52: af00 add r7, sp, #0 /* Disable SysTick Interrupt */ SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; 8000d54: 4b05 ldr r3, [pc, #20] @ (8000d6c ) 8000d56: 681b ldr r3, [r3, #0] 8000d58: 4a04 ldr r2, [pc, #16] @ (8000d6c ) 8000d5a: f023 0302 bic.w r3, r3, #2 8000d5e: 6013 str r3, [r2, #0] } 8000d60: bf00 nop 8000d62: 46bd mov sp, r7 8000d64: f85d 7b04 ldr.w r7, [sp], #4 8000d68: 4770 bx lr 8000d6a: bf00 nop 8000d6c: e000e010 .word 0xe000e010 08000d70 : * @arg SBS_IO_XSPI1_HSLV High speed at low voltage for the I/O of the XSPI1 * @arg SBS_IO_XSPI2_HSLV High speed at low voltage for the I/O of the XSPI2 * @retval None */ void HAL_SBS_EnableIOSpeedOptimize(uint32_t Selection) { 8000d70: b480 push {r7} 8000d72: b083 sub sp, #12 8000d74: af00 add r7, sp, #0 8000d76: 6078 str r0, [r7, #4] /* Check the parameter */ assert_param(IS_SBS_IOHSLV(Selection)); SET_BIT(SBS->CCCSR, Selection); 8000d78: 4b06 ldr r3, [pc, #24] @ (8000d94 ) 8000d7a: f8d3 2110 ldr.w r2, [r3, #272] @ 0x110 8000d7e: 4905 ldr r1, [pc, #20] @ (8000d94 ) 8000d80: 687b ldr r3, [r7, #4] 8000d82: 4313 orrs r3, r2 8000d84: f8c1 3110 str.w r3, [r1, #272] @ 0x110 } 8000d88: bf00 nop 8000d8a: 370c adds r7, #12 8000d8c: 46bd mov sp, r7 8000d8e: f85d 7b04 ldr.w r7, [sp], #4 8000d92: 4770 bx lr 8000d94: 58000400 .word 0x58000400 08000d98 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8000d98: b480 push {r7} 8000d9a: b085 sub sp, #20 8000d9c: af00 add r7, sp, #0 8000d9e: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8000da0: 687b ldr r3, [r7, #4] 8000da2: f003 0307 and.w r3, r3, #7 8000da6: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8000da8: 4b0b ldr r3, [pc, #44] @ (8000dd8 <__NVIC_SetPriorityGrouping+0x40>) 8000daa: 68db ldr r3, [r3, #12] 8000dac: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8000dae: 68ba ldr r2, [r7, #8] 8000db0: f64f 03ff movw r3, #63743 @ 0xf8ff 8000db4: 4013 ands r3, r2 8000db6: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8000db8: 68fb ldr r3, [r7, #12] 8000dba: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8000dbc: 68bb ldr r3, [r7, #8] 8000dbe: 431a orrs r2, r3 reg_value = (reg_value | 8000dc0: 4b06 ldr r3, [pc, #24] @ (8000ddc <__NVIC_SetPriorityGrouping+0x44>) 8000dc2: 4313 orrs r3, r2 8000dc4: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8000dc6: 4a04 ldr r2, [pc, #16] @ (8000dd8 <__NVIC_SetPriorityGrouping+0x40>) 8000dc8: 68bb ldr r3, [r7, #8] 8000dca: 60d3 str r3, [r2, #12] } 8000dcc: bf00 nop 8000dce: 3714 adds r7, #20 8000dd0: 46bd mov sp, r7 8000dd2: f85d 7b04 ldr.w r7, [sp], #4 8000dd6: 4770 bx lr 8000dd8: e000ed00 .word 0xe000ed00 8000ddc: 05fa0000 .word 0x05fa0000 08000de0 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8000de0: b480 push {r7} 8000de2: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8000de4: 4b04 ldr r3, [pc, #16] @ (8000df8 <__NVIC_GetPriorityGrouping+0x18>) 8000de6: 68db ldr r3, [r3, #12] 8000de8: 0a1b lsrs r3, r3, #8 8000dea: f003 0307 and.w r3, r3, #7 } 8000dee: 4618 mov r0, r3 8000df0: 46bd mov sp, r7 8000df2: f85d 7b04 ldr.w r7, [sp], #4 8000df6: 4770 bx lr 8000df8: e000ed00 .word 0xe000ed00 08000dfc <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8000dfc: b480 push {r7} 8000dfe: b083 sub sp, #12 8000e00: af00 add r7, sp, #0 8000e02: 4603 mov r3, r0 8000e04: 6039 str r1, [r7, #0] 8000e06: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 8000e08: f9b7 3006 ldrsh.w r3, [r7, #6] 8000e0c: 2b00 cmp r3, #0 8000e0e: db0a blt.n 8000e26 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8000e10: 683b ldr r3, [r7, #0] 8000e12: b2da uxtb r2, r3 8000e14: 490c ldr r1, [pc, #48] @ (8000e48 <__NVIC_SetPriority+0x4c>) 8000e16: f9b7 3006 ldrsh.w r3, [r7, #6] 8000e1a: 0112 lsls r2, r2, #4 8000e1c: b2d2 uxtb r2, r2 8000e1e: 440b add r3, r1 8000e20: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8000e24: e00a b.n 8000e3c <__NVIC_SetPriority+0x40> SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8000e26: 683b ldr r3, [r7, #0] 8000e28: b2da uxtb r2, r3 8000e2a: 4908 ldr r1, [pc, #32] @ (8000e4c <__NVIC_SetPriority+0x50>) 8000e2c: 88fb ldrh r3, [r7, #6] 8000e2e: f003 030f and.w r3, r3, #15 8000e32: 3b04 subs r3, #4 8000e34: 0112 lsls r2, r2, #4 8000e36: b2d2 uxtb r2, r2 8000e38: 440b add r3, r1 8000e3a: 761a strb r2, [r3, #24] } 8000e3c: bf00 nop 8000e3e: 370c adds r7, #12 8000e40: 46bd mov sp, r7 8000e42: f85d 7b04 ldr.w r7, [sp], #4 8000e46: 4770 bx lr 8000e48: e000e100 .word 0xe000e100 8000e4c: e000ed00 .word 0xe000ed00 08000e50 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8000e50: b480 push {r7} 8000e52: b089 sub sp, #36 @ 0x24 8000e54: af00 add r7, sp, #0 8000e56: 60f8 str r0, [r7, #12] 8000e58: 60b9 str r1, [r7, #8] 8000e5a: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8000e5c: 68fb ldr r3, [r7, #12] 8000e5e: f003 0307 and.w r3, r3, #7 8000e62: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8000e64: 69fb ldr r3, [r7, #28] 8000e66: f1c3 0307 rsb r3, r3, #7 8000e6a: 2b04 cmp r3, #4 8000e6c: bf28 it cs 8000e6e: 2304 movcs r3, #4 8000e70: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8000e72: 69fb ldr r3, [r7, #28] 8000e74: 3304 adds r3, #4 8000e76: 2b06 cmp r3, #6 8000e78: d902 bls.n 8000e80 8000e7a: 69fb ldr r3, [r7, #28] 8000e7c: 3b03 subs r3, #3 8000e7e: e000 b.n 8000e82 8000e80: 2300 movs r3, #0 8000e82: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8000e84: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8000e88: 69bb ldr r3, [r7, #24] 8000e8a: fa02 f303 lsl.w r3, r2, r3 8000e8e: 43da mvns r2, r3 8000e90: 68bb ldr r3, [r7, #8] 8000e92: 401a ands r2, r3 8000e94: 697b ldr r3, [r7, #20] 8000e96: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8000e98: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8000e9c: 697b ldr r3, [r7, #20] 8000e9e: fa01 f303 lsl.w r3, r1, r3 8000ea2: 43d9 mvns r1, r3 8000ea4: 687b ldr r3, [r7, #4] 8000ea6: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8000ea8: 4313 orrs r3, r2 ); } 8000eaa: 4618 mov r0, r3 8000eac: 3724 adds r7, #36 @ 0x24 8000eae: 46bd mov sp, r7 8000eb0: f85d 7b04 ldr.w r7, [sp], #4 8000eb4: 4770 bx lr ... 08000eb8 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8000eb8: b580 push {r7, lr} 8000eba: b082 sub sp, #8 8000ebc: af00 add r7, sp, #0 8000ebe: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8000ec0: 687b ldr r3, [r7, #4] 8000ec2: 3b01 subs r3, #1 8000ec4: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8000ec8: d301 bcc.n 8000ece { return (1UL); /* Reload value impossible */ 8000eca: 2301 movs r3, #1 8000ecc: e00f b.n 8000eee } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8000ece: 4a0a ldr r2, [pc, #40] @ (8000ef8 ) 8000ed0: 687b ldr r3, [r7, #4] 8000ed2: 3b01 subs r3, #1 8000ed4: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8000ed6: 210f movs r1, #15 8000ed8: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8000edc: f7ff ff8e bl 8000dfc <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8000ee0: 4b05 ldr r3, [pc, #20] @ (8000ef8 ) 8000ee2: 2200 movs r2, #0 8000ee4: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8000ee6: 4b04 ldr r3, [pc, #16] @ (8000ef8 ) 8000ee8: 2207 movs r2, #7 8000eea: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8000eec: 2300 movs r3, #0 } 8000eee: 4618 mov r0, r3 8000ef0: 3708 adds r7, #8 8000ef2: 46bd mov sp, r7 8000ef4: bd80 pop {r7, pc} 8000ef6: bf00 nop 8000ef8: e000e010 .word 0xe000e010 08000efc : * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8000efc: b580 push {r7, lr} 8000efe: b082 sub sp, #8 8000f00: af00 add r7, sp, #0 8000f02: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8000f04: 6878 ldr r0, [r7, #4] 8000f06: f7ff ff47 bl 8000d98 <__NVIC_SetPriorityGrouping> } 8000f0a: bf00 nop 8000f0c: 3708 adds r7, #8 8000f0e: 46bd mov sp, r7 8000f10: bd80 pop {r7, pc} 08000f12 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8000f12: b580 push {r7, lr} 8000f14: b086 sub sp, #24 8000f16: af00 add r7, sp, #0 8000f18: 4603 mov r3, r0 8000f1a: 60b9 str r1, [r7, #8] 8000f1c: 607a str r2, [r7, #4] 8000f1e: 81fb strh r3, [r7, #14] uint32_t prioritygroup; /* Check the parameters */ assert_param(IS_NVIC_PRIO_INTERRUPT(IRQn)); prioritygroup = NVIC_GetPriorityGrouping(); 8000f20: f7ff ff5e bl 8000de0 <__NVIC_GetPriorityGrouping> 8000f24: 6178 str r0, [r7, #20] assert_param(IS_NVIC_SUB_PRIORITY(SubPriority, prioritygroup)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority, prioritygroup)); NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8000f26: 687a ldr r2, [r7, #4] 8000f28: 68b9 ldr r1, [r7, #8] 8000f2a: 6978 ldr r0, [r7, #20] 8000f2c: f7ff ff90 bl 8000e50 8000f30: 4602 mov r2, r0 8000f32: f9b7 300e ldrsh.w r3, [r7, #14] 8000f36: 4611 mov r1, r2 8000f38: 4618 mov r0, r3 8000f3a: f7ff ff5f bl 8000dfc <__NVIC_SetPriority> } 8000f3e: bf00 nop 8000f40: 3718 adds r7, #24 8000f42: 46bd mov sp, r7 8000f44: bd80 pop {r7, pc} 08000f46 : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8000f46: b580 push {r7, lr} 8000f48: b082 sub sp, #8 8000f4a: af00 add r7, sp, #0 8000f4c: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8000f4e: 6878 ldr r0, [r7, #4] 8000f50: f7ff ffb2 bl 8000eb8 8000f54: 4603 mov r3, r0 } 8000f56: 4618 mov r0, r3 8000f58: 3708 adds r7, #8 8000f5a: 46bd mov sp, r7 8000f5c: bd80 pop {r7, pc} 08000f5e : */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *const hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SrcDataSize) { 8000f5e: b580 push {r7, lr} 8000f60: b084 sub sp, #16 8000f62: af00 add r7, sp, #0 8000f64: 60f8 str r0, [r7, #12] 8000f66: 60b9 str r1, [r7, #8] 8000f68: 607a str r2, [r7, #4] 8000f6a: 603b str r3, [r7, #0] /* Check the DMA peripheral handle parameter */ if (hdma == NULL) 8000f6c: 68fb ldr r3, [r7, #12] 8000f6e: 2b00 cmp r3, #0 8000f70: d101 bne.n 8000f76 { return HAL_ERROR; 8000f72: 2301 movs r3, #1 8000f74: e04f b.n 8001016 /* Check the parameters */ assert_param(IS_DMA_BLOCK_SIZE(SrcDataSize)); /* Process locked */ __HAL_LOCK(hdma); 8000f76: 68fb ldr r3, [r7, #12] 8000f78: f893 304c ldrb.w r3, [r3, #76] @ 0x4c 8000f7c: 2b01 cmp r3, #1 8000f7e: d101 bne.n 8000f84 8000f80: 2302 movs r3, #2 8000f82: e048 b.n 8001016 8000f84: 68fb ldr r3, [r7, #12] 8000f86: 2201 movs r2, #1 8000f88: f883 204c strb.w r2, [r3, #76] @ 0x4c /* Check DMA channel state */ if (hdma->State == HAL_DMA_STATE_READY) 8000f8c: 68fb ldr r3, [r7, #12] 8000f8e: f893 3054 ldrb.w r3, [r3, #84] @ 0x54 8000f92: b2db uxtb r3, r3 8000f94: 2b01 cmp r3, #1 8000f96: d136 bne.n 8001006 { /* Update the DMA channel state */ hdma->State = HAL_DMA_STATE_BUSY; 8000f98: 68fb ldr r3, [r7, #12] 8000f9a: 2202 movs r2, #2 8000f9c: f883 2054 strb.w r2, [r3, #84] @ 0x54 /* Update the DMA channel error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8000fa0: 68fb ldr r3, [r7, #12] 8000fa2: 2200 movs r2, #0 8000fa4: 659a str r2, [r3, #88] @ 0x58 /* Configure the source address, destination address, the data size and clear flags */ DMA_SetConfig(hdma, SrcAddress, DstAddress, SrcDataSize); 8000fa6: 683b ldr r3, [r7, #0] 8000fa8: 687a ldr r2, [r7, #4] 8000faa: 68b9 ldr r1, [r7, #8] 8000fac: 68f8 ldr r0, [r7, #12] 8000fae: f000 f8db bl 8001168 /* Enable common interrupts: Transfer Complete and Transfer Errors ITs */ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_DTE | DMA_IT_ULE | DMA_IT_USE | DMA_IT_TO)); 8000fb2: 68fb ldr r3, [r7, #12] 8000fb4: 681b ldr r3, [r3, #0] 8000fb6: 695a ldr r2, [r3, #20] 8000fb8: 68fb ldr r3, [r7, #12] 8000fba: 681b ldr r3, [r3, #0] 8000fbc: f442 42ba orr.w r2, r2, #23808 @ 0x5d00 8000fc0: 615a str r2, [r3, #20] /* Check half transfer complete callback */ if (hdma->XferHalfCpltCallback != NULL) 8000fc2: 68fb ldr r3, [r7, #12] 8000fc4: 6e5b ldr r3, [r3, #100] @ 0x64 8000fc6: 2b00 cmp r3, #0 8000fc8: d007 beq.n 8000fda { /* If Half Transfer complete callback is set, enable the corresponding IT */ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT); 8000fca: 68fb ldr r3, [r7, #12] 8000fcc: 681b ldr r3, [r3, #0] 8000fce: 695a ldr r2, [r3, #20] 8000fd0: 68fb ldr r3, [r7, #12] 8000fd2: 681b ldr r3, [r3, #0] 8000fd4: f442 7200 orr.w r2, r2, #512 @ 0x200 8000fd8: 615a str r2, [r3, #20] } /* Check Half suspend callback */ if (hdma->XferSuspendCallback != NULL) 8000fda: 68fb ldr r3, [r7, #12] 8000fdc: 6f1b ldr r3, [r3, #112] @ 0x70 8000fde: 2b00 cmp r3, #0 8000fe0: d007 beq.n 8000ff2 { /* If Transfer suspend callback is set, enable the corresponding IT */ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_SUSP); 8000fe2: 68fb ldr r3, [r7, #12] 8000fe4: 681b ldr r3, [r3, #0] 8000fe6: 695a ldr r2, [r3, #20] 8000fe8: 68fb ldr r3, [r7, #12] 8000fea: 681b ldr r3, [r3, #0] 8000fec: f442 5200 orr.w r2, r2, #8192 @ 0x2000 8000ff0: 615a str r2, [r3, #20] } /* Enable DMA channel */ __HAL_DMA_ENABLE(hdma); 8000ff2: 68fb ldr r3, [r7, #12] 8000ff4: 681b ldr r3, [r3, #0] 8000ff6: 695a ldr r2, [r3, #20] 8000ff8: 68fb ldr r3, [r7, #12] 8000ffa: 681b ldr r3, [r3, #0] 8000ffc: f042 0201 orr.w r2, r2, #1 8001000: 615a str r2, [r3, #20] __HAL_UNLOCK(hdma); return HAL_ERROR; } return HAL_OK; 8001002: 2300 movs r3, #0 8001004: e007 b.n 8001016 hdma->ErrorCode = HAL_DMA_ERROR_BUSY; 8001006: 68fb ldr r3, [r7, #12] 8001008: 2240 movs r2, #64 @ 0x40 800100a: 659a str r2, [r3, #88] @ 0x58 __HAL_UNLOCK(hdma); 800100c: 68fb ldr r3, [r7, #12] 800100e: 2200 movs r2, #0 8001010: f883 204c strb.w r2, [r3, #76] @ 0x4c return HAL_ERROR; 8001014: 2301 movs r3, #1 } 8001016: 4618 mov r0, r3 8001018: 3710 adds r7, #16 800101a: 46bd mov sp, r7 800101c: bd80 pop {r7, pc} 0800101e : * is suspended while a data transfer is on-going, the current data will be transferred and the channel will be * effectively suspended only after the transfer of any on-going data is finished. * @retval HAL status. */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *const hdma) { 800101e: b580 push {r7, lr} 8001020: b084 sub sp, #16 8001022: af00 add r7, sp, #0 8001024: 6078 str r0, [r7, #4] /* Get tick number */ uint32_t tickstart = HAL_GetTick(); 8001026: f7ff fe63 bl 8000cf0 800102a: 60f8 str r0, [r7, #12] /* Check the DMA peripheral handle parameter */ if (hdma == NULL) 800102c: 687b ldr r3, [r7, #4] 800102e: 2b00 cmp r3, #0 8001030: d101 bne.n 8001036 { return HAL_ERROR; 8001032: 2301 movs r3, #1 8001034: e06b b.n 800110e } /* Check DMA channel state */ if (hdma->State != HAL_DMA_STATE_BUSY) 8001036: 687b ldr r3, [r7, #4] 8001038: f893 3054 ldrb.w r3, [r3, #84] @ 0x54 800103c: b2db uxtb r3, r3 800103e: 2b02 cmp r3, #2 8001040: d008 beq.n 8001054 { /* Update the DMA channel error code */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8001042: 687b ldr r3, [r7, #4] 8001044: 2220 movs r2, #32 8001046: 659a str r2, [r3, #88] @ 0x58 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8001048: 687b ldr r3, [r7, #4] 800104a: 2200 movs r2, #0 800104c: f883 204c strb.w r2, [r3, #76] @ 0x4c return HAL_ERROR; 8001050: 2301 movs r3, #1 8001052: e05c b.n 800110e } else { /* Suspend the channel */ hdma->Instance->CCR |= DMA_CCR_SUSP; 8001054: 687b ldr r3, [r7, #4] 8001056: 681b ldr r3, [r3, #0] 8001058: 695a ldr r2, [r3, #20] 800105a: 687b ldr r3, [r7, #4] 800105c: 681b ldr r3, [r3, #0] 800105e: f042 0204 orr.w r2, r2, #4 8001062: 615a str r2, [r3, #20] /* Update the DMA channel state */ hdma->State = HAL_DMA_STATE_SUSPEND; 8001064: 687b ldr r3, [r7, #4] 8001066: 2205 movs r2, #5 8001068: f883 2054 strb.w r2, [r3, #84] @ 0x54 /* Check if the DMA Channel is suspended */ while ((hdma->Instance->CSR & DMA_CSR_SUSPF) == 0U) 800106c: e020 b.n 80010b0 { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) 800106e: f7ff fe3f bl 8000cf0 8001072: 4602 mov r2, r0 8001074: 68fb ldr r3, [r7, #12] 8001076: 1ad3 subs r3, r2, r3 8001078: 2b05 cmp r3, #5 800107a: d919 bls.n 80010b0 { /* Update the DMA channel error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; 800107c: 687b ldr r3, [r7, #4] 800107e: 6d9b ldr r3, [r3, #88] @ 0x58 8001080: f043 0210 orr.w r2, r3, #16 8001084: 687b ldr r3, [r7, #4] 8001086: 659a str r2, [r3, #88] @ 0x58 /* Update the DMA channel state */ hdma->State = HAL_DMA_STATE_ERROR; 8001088: 687b ldr r3, [r7, #4] 800108a: 2203 movs r2, #3 800108c: f883 2054 strb.w r2, [r3, #84] @ 0x54 /* Check DMA channel transfer mode */ if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) 8001090: 687b ldr r3, [r7, #4] 8001092: 6d1b ldr r3, [r3, #80] @ 0x50 8001094: f003 0380 and.w r3, r3, #128 @ 0x80 8001098: 2b00 cmp r3, #0 800109a: d003 beq.n 80010a4 { /* Update the linked-list queue state */ hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; 800109c: 687b ldr r3, [r7, #4] 800109e: 6f5b ldr r3, [r3, #116] @ 0x74 80010a0: 2201 movs r2, #1 80010a2: 731a strb r2, [r3, #12] } /* Process Unlocked */ __HAL_UNLOCK(hdma); 80010a4: 687b ldr r3, [r7, #4] 80010a6: 2200 movs r2, #0 80010a8: f883 204c strb.w r2, [r3, #76] @ 0x4c return HAL_ERROR; 80010ac: 2301 movs r3, #1 80010ae: e02e b.n 800110e while ((hdma->Instance->CSR & DMA_CSR_SUSPF) == 0U) 80010b0: 687b ldr r3, [r7, #4] 80010b2: 681b ldr r3, [r3, #0] 80010b4: 691b ldr r3, [r3, #16] 80010b6: f403 5300 and.w r3, r3, #8192 @ 0x2000 80010ba: 2b00 cmp r3, #0 80010bc: d0d7 beq.n 800106e } } /* Reset the channel */ hdma->Instance->CCR |= DMA_CCR_RESET; 80010be: 687b ldr r3, [r7, #4] 80010c0: 681b ldr r3, [r3, #0] 80010c2: 695a ldr r2, [r3, #20] 80010c4: 687b ldr r3, [r7, #4] 80010c6: 681b ldr r3, [r3, #0] 80010c8: f042 0202 orr.w r2, r2, #2 80010cc: 615a str r2, [r3, #20] /* Update the DMA channel state */ hdma->State = HAL_DMA_STATE_ABORT; 80010ce: 687b ldr r3, [r7, #4] 80010d0: 2204 movs r2, #4 80010d2: f883 2054 strb.w r2, [r3, #84] @ 0x54 /* Clear all status flags */ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | 80010d6: 687b ldr r3, [r7, #4] 80010d8: 681b ldr r3, [r3, #0] 80010da: f44f 42fe mov.w r2, #32512 @ 0x7f00 80010de: 60da str r2, [r3, #12] DMA_FLAG_TO)); /* Update the DMA channel state */ hdma->State = HAL_DMA_STATE_READY; 80010e0: 687b ldr r3, [r7, #4] 80010e2: 2201 movs r2, #1 80010e4: f883 2054 strb.w r2, [r3, #84] @ 0x54 /* Check DMA channel transfer mode */ if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) 80010e8: 687b ldr r3, [r7, #4] 80010ea: 6d1b ldr r3, [r3, #80] @ 0x50 80010ec: f003 0380 and.w r3, r3, #128 @ 0x80 80010f0: 2b00 cmp r3, #0 80010f2: d007 beq.n 8001104 { /* Update the linked-list queue state */ hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; 80010f4: 687b ldr r3, [r7, #4] 80010f6: 6f5b ldr r3, [r3, #116] @ 0x74 80010f8: 2201 movs r2, #1 80010fa: 731a strb r2, [r3, #12] /* Clear remaining data size to ensure loading linked-list from memory next start */ hdma->Instance->CBR1 = 0U; 80010fc: 687b ldr r3, [r7, #4] 80010fe: 681b ldr r3, [r3, #0] 8001100: 2200 movs r2, #0 8001102: 649a str r2, [r3, #72] @ 0x48 } /* Process Unlocked */ __HAL_UNLOCK(hdma); 8001104: 687b ldr r3, [r7, #4] 8001106: 2200 movs r2, #0 8001108: f883 204c strb.w r2, [r3, #76] @ 0x4c } return HAL_OK; 800110c: 2300 movs r3, #0 } 800110e: 4618 mov r0, r3 8001110: 3710 adds r7, #16 8001112: 46bd mov sp, r7 8001114: bd80 pop {r7, pc} 08001116 : * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the * specified DMA Channel. * @retval HAL status. */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *const hdma) { 8001116: b480 push {r7} 8001118: b083 sub sp, #12 800111a: af00 add r7, sp, #0 800111c: 6078 str r0, [r7, #4] /* Check the DMA peripheral handle parameter */ if (hdma == NULL) 800111e: 687b ldr r3, [r7, #4] 8001120: 2b00 cmp r3, #0 8001122: d101 bne.n 8001128 { return HAL_ERROR; 8001124: 2301 movs r3, #1 8001126: e018 b.n 800115a } /* Check DMA channel state */ if (hdma->State != HAL_DMA_STATE_BUSY) 8001128: 687b ldr r3, [r7, #4] 800112a: f893 3054 ldrb.w r3, [r3, #84] @ 0x54 800112e: b2db uxtb r3, r3 8001130: 2b02 cmp r3, #2 8001132: d004 beq.n 800113e { /* Update the DMA channel error code */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8001134: 687b ldr r3, [r7, #4] 8001136: 2220 movs r2, #32 8001138: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 800113a: 2301 movs r3, #1 800113c: e00d b.n 800115a } else { /* Update the DMA channel state */ hdma->State = HAL_DMA_STATE_ABORT; 800113e: 687b ldr r3, [r7, #4] 8001140: 2204 movs r2, #4 8001142: f883 2054 strb.w r2, [r3, #84] @ 0x54 /* Suspend the channel and activate suspend interrupt */ hdma->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_SUSPIE); 8001146: 687b ldr r3, [r7, #4] 8001148: 681b ldr r3, [r3, #0] 800114a: 6959 ldr r1, [r3, #20] 800114c: 687b ldr r3, [r7, #4] 800114e: 681a ldr r2, [r3, #0] 8001150: f242 0304 movw r3, #8196 @ 0x2004 8001154: 430b orrs r3, r1 8001156: 6153 str r3, [r2, #20] } return HAL_OK; 8001158: 2300 movs r3, #0 } 800115a: 4618 mov r0, r3 800115c: 370c adds r7, #12 800115e: 46bd mov sp, r7 8001160: f85d 7b04 ldr.w r7, [sp], #4 8001164: 4770 bx lr ... 08001168 : */ static void DMA_SetConfig(DMA_HandleTypeDef const *const hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SrcDataSize) { 8001168: b480 push {r7} 800116a: b085 sub sp, #20 800116c: af00 add r7, sp, #0 800116e: 60f8 str r0, [r7, #12] 8001170: 60b9 str r1, [r7, #8] 8001172: 607a str r2, [r7, #4] 8001174: 603b str r3, [r7, #0] /* Configure the DMA channel data size */ MODIFY_REG(hdma->Instance->CBR1, DMA_CBR1_BNDT, (SrcDataSize & DMA_CBR1_BNDT)); 8001176: 68fb ldr r3, [r7, #12] 8001178: 681b ldr r3, [r3, #0] 800117a: 6c9a ldr r2, [r3, #72] @ 0x48 800117c: 4b0d ldr r3, [pc, #52] @ (80011b4 ) 800117e: 4013 ands r3, r2 8001180: 683a ldr r2, [r7, #0] 8001182: b291 uxth r1, r2 8001184: 68fa ldr r2, [r7, #12] 8001186: 6812 ldr r2, [r2, #0] 8001188: 430b orrs r3, r1 800118a: 6493 str r3, [r2, #72] @ 0x48 /* Clear all interrupt flags */ __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | 800118c: 68fb ldr r3, [r7, #12] 800118e: 681b ldr r3, [r3, #0] 8001190: f44f 42fe mov.w r2, #32512 @ 0x7f00 8001194: 60da str r2, [r3, #12] DMA_FLAG_TO); /* Configure DMA channel source address */ hdma->Instance->CSAR = SrcAddress; 8001196: 68fb ldr r3, [r7, #12] 8001198: 681b ldr r3, [r3, #0] 800119a: 68ba ldr r2, [r7, #8] 800119c: 64da str r2, [r3, #76] @ 0x4c /* Configure DMA channel destination address */ hdma->Instance->CDAR = DstAddress; 800119e: 68fb ldr r3, [r7, #12] 80011a0: 681b ldr r3, [r3, #0] 80011a2: 687a ldr r2, [r7, #4] 80011a4: 651a str r2, [r3, #80] @ 0x50 } 80011a6: bf00 nop 80011a8: 3714 adds r7, #20 80011aa: 46bd mov sp, r7 80011ac: f85d 7b04 ldr.w r7, [sp], #4 80011b0: 4770 bx lr 80011b2: bf00 nop 80011b4: ffff0000 .word 0xffff0000 080011b8 : * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the * specified DMA Channel. * @retval HAL status. */ HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma) { 80011b8: b580 push {r7, lr} 80011ba: b086 sub sp, #24 80011bc: af00 add r7, sp, #0 80011be: 6078 str r0, [r7, #4] HAL_DMA_StateTypeDef dma_state; uint32_t ccr_value; uint32_t cllr_mask; /* Check the DMA peripheral handle and the linked-list queue parameters */ if ((hdma == NULL) || (hdma->LinkedListQueue == NULL)) 80011c0: 687b ldr r3, [r7, #4] 80011c2: 2b00 cmp r3, #0 80011c4: d003 beq.n 80011ce 80011c6: 687b ldr r3, [r7, #4] 80011c8: 6f5b ldr r3, [r3, #116] @ 0x74 80011ca: 2b00 cmp r3, #0 80011cc: d101 bne.n 80011d2 { return HAL_ERROR; 80011ce: 2301 movs r3, #1 80011d0: e082 b.n 80012d8 } /* Check DMA channel state */ dma_state = hdma->State; 80011d2: 687b ldr r3, [r7, #4] 80011d4: f893 3054 ldrb.w r3, [r3, #84] @ 0x54 80011d8: 75fb strb r3, [r7, #23] ccr_value = hdma->Instance->CCR & DMA_CCR_LSM; 80011da: 687b ldr r3, [r7, #4] 80011dc: 681b ldr r3, [r3, #0] 80011de: 695b ldr r3, [r3, #20] 80011e0: f403 3380 and.w r3, r3, #65536 @ 0x10000 80011e4: 613b str r3, [r7, #16] if ((dma_state == HAL_DMA_STATE_READY) || ((dma_state == HAL_DMA_STATE_BUSY) && (ccr_value != 0U))) 80011e6: 7dfb ldrb r3, [r7, #23] 80011e8: 2b01 cmp r3, #1 80011ea: d005 beq.n 80011f8 80011ec: 7dfb ldrb r3, [r7, #23] 80011ee: 2b02 cmp r3, #2 80011f0: d16a bne.n 80012c8 80011f2: 693b ldr r3, [r7, #16] 80011f4: 2b00 cmp r3, #0 80011f6: d067 beq.n 80012c8 { /* Check DMA channel state is ready */ if (hdma->State == HAL_DMA_STATE_READY) 80011f8: 687b ldr r3, [r7, #4] 80011fa: f893 3054 ldrb.w r3, [r3, #84] @ 0x54 80011fe: b2db uxtb r3, r3 8001200: 2b01 cmp r3, #1 8001202: d157 bne.n 80012b4 { /* Process locked */ __HAL_LOCK(hdma); 8001204: 687b ldr r3, [r7, #4] 8001206: f893 304c ldrb.w r3, [r3, #76] @ 0x4c 800120a: 2b01 cmp r3, #1 800120c: d101 bne.n 8001212 800120e: 2302 movs r3, #2 8001210: e062 b.n 80012d8 8001212: 687b ldr r3, [r7, #4] 8001214: 2201 movs r2, #1 8001216: f883 204c strb.w r2, [r3, #76] @ 0x4c /* Update the DMA channel and the queue states */ hdma->State = HAL_DMA_STATE_BUSY; 800121a: 687b ldr r3, [r7, #4] 800121c: 2202 movs r2, #2 800121e: f883 2054 strb.w r2, [r3, #84] @ 0x54 hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_BUSY; 8001222: 687b ldr r3, [r7, #4] 8001224: 6f5b ldr r3, [r3, #116] @ 0x74 8001226: 2202 movs r2, #2 8001228: 731a strb r2, [r3, #12] /* Update the DMA channel and the queue error codes */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 800122a: 687b ldr r3, [r7, #4] 800122c: 2200 movs r2, #0 800122e: 659a str r2, [r3, #88] @ 0x58 hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; 8001230: 687b ldr r3, [r7, #4] 8001232: 6f5b ldr r3, [r3, #116] @ 0x74 8001234: 2200 movs r2, #0 8001236: 611a str r2, [r3, #16] /* Enable common interrupts: Transfer Complete and Transfer Errors ITs */ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_DTE | DMA_IT_ULE | DMA_IT_USE | DMA_IT_TO)); 8001238: 687b ldr r3, [r7, #4] 800123a: 681b ldr r3, [r3, #0] 800123c: 695a ldr r2, [r3, #20] 800123e: 687b ldr r3, [r7, #4] 8001240: 681b ldr r3, [r3, #0] 8001242: f442 42ba orr.w r2, r2, #23808 @ 0x5d00 8001246: 615a str r2, [r3, #20] /* Check half transfer complete callback */ if (hdma->XferHalfCpltCallback != NULL) 8001248: 687b ldr r3, [r7, #4] 800124a: 6e5b ldr r3, [r3, #100] @ 0x64 800124c: 2b00 cmp r3, #0 800124e: d007 beq.n 8001260 { /* If half transfer complete callback is set, enable the corresponding IT */ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT); 8001250: 687b ldr r3, [r7, #4] 8001252: 681b ldr r3, [r3, #0] 8001254: 695a ldr r2, [r3, #20] 8001256: 687b ldr r3, [r7, #4] 8001258: 681b ldr r3, [r3, #0] 800125a: f442 7200 orr.w r2, r2, #512 @ 0x200 800125e: 615a str r2, [r3, #20] } /* Check suspend callback */ if (hdma->XferSuspendCallback != NULL) 8001260: 687b ldr r3, [r7, #4] 8001262: 6f1b ldr r3, [r3, #112] @ 0x70 8001264: 2b00 cmp r3, #0 8001266: d007 beq.n 8001278 { /* If transfer suspend callback is set, enable the corresponding IT */ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_SUSP); 8001268: 687b ldr r3, [r7, #4] 800126a: 681b ldr r3, [r3, #0] 800126c: 695a ldr r2, [r3, #20] 800126e: 687b ldr r3, [r7, #4] 8001270: 681b ldr r3, [r3, #0] 8001272: f442 5200 orr.w r2, r2, #8192 @ 0x2000 8001276: 615a str r2, [r3, #20] } /* Get CLLR register mask and offset */ DMA_List_GetCLLRNodeInfo(hdma->LinkedListQueue->Head, &cllr_mask, NULL); 8001278: 687b ldr r3, [r7, #4] 800127a: 6f5b ldr r3, [r3, #116] @ 0x74 800127c: 681b ldr r3, [r3, #0] 800127e: f107 010c add.w r1, r7, #12 8001282: 2200 movs r2, #0 8001284: 4618 mov r0, r3 8001286: f000 f82d bl 80012e4 /* Update DMA registers for linked-list transfer */ hdma->Instance->CLBAR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLBAR_LBA); 800128a: 687b ldr r3, [r7, #4] 800128c: 6f5b ldr r3, [r3, #116] @ 0x74 800128e: 681b ldr r3, [r3, #0] 8001290: 4619 mov r1, r3 8001292: 687b ldr r3, [r7, #4] 8001294: 681a ldr r2, [r3, #0] 8001296: 4b12 ldr r3, [pc, #72] @ (80012e0 ) 8001298: 400b ands r3, r1 800129a: 6013 str r3, [r2, #0] hdma->Instance->CLLR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLLR_LA) | cllr_mask; 800129c: 687b ldr r3, [r7, #4] 800129e: 6f5b ldr r3, [r3, #116] @ 0x74 80012a0: 681b ldr r3, [r3, #0] 80012a2: 461a mov r2, r3 80012a4: f64f 73fc movw r3, #65532 @ 0xfffc 80012a8: 4013 ands r3, r2 80012aa: 68f9 ldr r1, [r7, #12] 80012ac: 687a ldr r2, [r7, #4] 80012ae: 6812 ldr r2, [r2, #0] 80012b0: 430b orrs r3, r1 80012b2: 67d3 str r3, [r2, #124] @ 0x7c } /* Enable DMA channel */ __HAL_DMA_ENABLE(hdma); 80012b4: 687b ldr r3, [r7, #4] 80012b6: 681b ldr r3, [r3, #0] 80012b8: 695a ldr r2, [r3, #20] 80012ba: 687b ldr r3, [r7, #4] 80012bc: 681b ldr r3, [r3, #0] 80012be: f042 0201 orr.w r2, r2, #1 80012c2: 615a str r2, [r3, #20] __HAL_UNLOCK(hdma); return HAL_ERROR; } return HAL_OK; 80012c4: 2300 movs r3, #0 80012c6: e007 b.n 80012d8 hdma->ErrorCode = HAL_DMA_ERROR_BUSY; 80012c8: 687b ldr r3, [r7, #4] 80012ca: 2240 movs r2, #64 @ 0x40 80012cc: 659a str r2, [r3, #88] @ 0x58 __HAL_UNLOCK(hdma); 80012ce: 687b ldr r3, [r7, #4] 80012d0: 2200 movs r2, #0 80012d2: f883 204c strb.w r2, [r3, #76] @ 0x4c return HAL_ERROR; 80012d6: 2301 movs r3, #1 } 80012d8: 4618 mov r0, r3 80012da: 3718 adds r7, #24 80012dc: 46bd mov sp, r7 80012de: bd80 pop {r7, pc} 80012e0: ffff0000 .word 0xffff0000 080012e4 : * @retval None. */ static void DMA_List_GetCLLRNodeInfo(DMA_NodeTypeDef const *const pNode, uint32_t *const cllr_mask, uint32_t *const cllr_offset) { 80012e4: b480 push {r7} 80012e6: b085 sub sp, #20 80012e8: af00 add r7, sp, #0 80012ea: 60f8 str r0, [r7, #12] 80012ec: 60b9 str r1, [r7, #8] 80012ee: 607a str r2, [r7, #4] /* Check node type */ if ((pNode->NodeInfo & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) 80012f0: 68fb ldr r3, [r7, #12] 80012f2: 6a1b ldr r3, [r3, #32] 80012f4: f003 0302 and.w r3, r3, #2 80012f8: 2b00 cmp r3, #0 80012fa: d00c beq.n 8001316 { /* Update CLLR register mask value */ if (cllr_mask != NULL) 80012fc: 68bb ldr r3, [r7, #8] 80012fe: 2b00 cmp r3, #0 8001300: d002 beq.n 8001308 { *cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | 8001302: 68bb ldr r3, [r7, #8] 8001304: 4a0d ldr r2, [pc, #52] @ (800133c ) 8001306: 601a str r2, [r3, #0] DMA_CLLR_UB2 | DMA_CLLR_ULL; } /* Update CLLR register offset */ if (cllr_offset != NULL) 8001308: 687b ldr r3, [r7, #4] 800130a: 2b00 cmp r3, #0 800130c: d00f beq.n 800132e { *cllr_offset = NODE_CLLR_2D_DEFAULT_OFFSET; 800130e: 687b ldr r3, [r7, #4] 8001310: 2207 movs r2, #7 8001312: 601a str r2, [r3, #0] if (cllr_offset != NULL) { *cllr_offset = NODE_CLLR_LINEAR_DEFAULT_OFFSET; } } } 8001314: e00b b.n 800132e if (cllr_mask != NULL) 8001316: 68bb ldr r3, [r7, #8] 8001318: 2b00 cmp r3, #0 800131a: d002 beq.n 8001322 *cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_ULL; 800131c: 68bb ldr r3, [r7, #8] 800131e: 4a08 ldr r2, [pc, #32] @ (8001340 ) 8001320: 601a str r2, [r3, #0] if (cllr_offset != NULL) 8001322: 687b ldr r3, [r7, #4] 8001324: 2b00 cmp r3, #0 8001326: d002 beq.n 800132e *cllr_offset = NODE_CLLR_LINEAR_DEFAULT_OFFSET; 8001328: 687b ldr r3, [r7, #4] 800132a: 2205 movs r2, #5 800132c: 601a str r2, [r3, #0] } 800132e: bf00 nop 8001330: 3714 adds r7, #20 8001332: 46bd mov sp, r7 8001334: f85d 7b04 ldr.w r7, [sp], #4 8001338: 4770 bx lr 800133a: bf00 nop 800133c: fe010000 .word 0xfe010000 8001340: f8010000 .word 0xf8010000 08001344 : /** * @brief Unlock the FLASH control register access. * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_Unlock(void) { 8001344: b480 push {r7} 8001346: af00 add r7, sp, #0 if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U) 8001348: 4b0c ldr r3, [pc, #48] @ (800137c ) 800134a: 691b ldr r3, [r3, #16] 800134c: f003 0301 and.w r3, r3, #1 8001350: 2b00 cmp r3, #0 8001352: d00d beq.n 8001370 { /* Authorize the FLASH Registers access */ WRITE_REG(FLASH->KEYR, FLASH_KEY1); 8001354: 4b09 ldr r3, [pc, #36] @ (800137c ) 8001356: 4a0a ldr r2, [pc, #40] @ (8001380 ) 8001358: 605a str r2, [r3, #4] WRITE_REG(FLASH->KEYR, FLASH_KEY2); 800135a: 4b08 ldr r3, [pc, #32] @ (800137c ) 800135c: 4a09 ldr r2, [pc, #36] @ (8001384 ) 800135e: 605a str r2, [r3, #4] /* verify Flash is unlocked */ if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U) 8001360: 4b06 ldr r3, [pc, #24] @ (800137c ) 8001362: 691b ldr r3, [r3, #16] 8001364: f003 0301 and.w r3, r3, #1 8001368: 2b00 cmp r3, #0 800136a: d001 beq.n 8001370 { return HAL_ERROR; 800136c: 2301 movs r3, #1 800136e: e000 b.n 8001372 } } return HAL_OK; 8001370: 2300 movs r3, #0 } 8001372: 4618 mov r0, r3 8001374: 46bd mov sp, r7 8001376: f85d 7b04 ldr.w r7, [sp], #4 800137a: 4770 bx lr 800137c: 52002000 .word 0x52002000 8001380: 45670123 .word 0x45670123 8001384: cdef89ab .word 0xcdef89ab 08001388 : /** * @brief Lock the FLASH control register access. * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_Lock(void) { 8001388: b480 push {r7} 800138a: af00 add r7, sp, #0 /* Set the LOCK Bit to lock the FLASH Registers access */ SET_BIT(FLASH->CR, FLASH_CR_LOCK); 800138c: 4b09 ldr r3, [pc, #36] @ (80013b4 ) 800138e: 691b ldr r3, [r3, #16] 8001390: 4a08 ldr r2, [pc, #32] @ (80013b4 ) 8001392: f043 0301 orr.w r3, r3, #1 8001396: 6113 str r3, [r2, #16] /* verify Flash is locked */ if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U) 8001398: 4b06 ldr r3, [pc, #24] @ (80013b4 ) 800139a: 691b ldr r3, [r3, #16] 800139c: f003 0301 and.w r3, r3, #1 80013a0: 2b00 cmp r3, #0 80013a2: d001 beq.n 80013a8 { return HAL_OK; 80013a4: 2300 movs r3, #0 80013a6: e000 b.n 80013aa } return HAL_ERROR; 80013a8: 2301 movs r3, #1 } 80013aa: 4618 mov r0, r3 80013ac: 46bd mov sp, r7 80013ae: f85d 7b04 ldr.w r7, [sp], #4 80013b2: 4770 bx lr 80013b4: 52002000 .word 0x52002000 080013b8 : /** * @brief Unlock the FLASH Option Bytes Registers access. * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) { 80013b8: b480 push {r7} 80013ba: af00 add r7, sp, #0 if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != 0U) 80013bc: 4b0e ldr r3, [pc, #56] @ (80013f8 ) 80013be: f8d3 3104 ldr.w r3, [r3, #260] @ 0x104 80013c2: f003 0301 and.w r3, r3, #1 80013c6: 2b00 cmp r3, #0 80013c8: d010 beq.n 80013ec { /* Authorizes the Option Byte register programming */ WRITE_REG(FLASH->OPTKEYR, FLASH_OPT_KEY1); 80013ca: 4b0b ldr r3, [pc, #44] @ (80013f8 ) 80013cc: 4a0b ldr r2, [pc, #44] @ (80013fc ) 80013ce: f8c3 2100 str.w r2, [r3, #256] @ 0x100 WRITE_REG(FLASH->OPTKEYR, FLASH_OPT_KEY2); 80013d2: 4b09 ldr r3, [pc, #36] @ (80013f8 ) 80013d4: 4a0a ldr r2, [pc, #40] @ (8001400 ) 80013d6: f8c3 2100 str.w r2, [r3, #256] @ 0x100 /* Verify that the Option Bytes are unlocked */ if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != 0U) 80013da: 4b07 ldr r3, [pc, #28] @ (80013f8 ) 80013dc: f8d3 3104 ldr.w r3, [r3, #260] @ 0x104 80013e0: f003 0301 and.w r3, r3, #1 80013e4: 2b00 cmp r3, #0 80013e6: d001 beq.n 80013ec { return HAL_ERROR; 80013e8: 2301 movs r3, #1 80013ea: e000 b.n 80013ee } } return HAL_OK; 80013ec: 2300 movs r3, #0 } 80013ee: 4618 mov r0, r3 80013f0: 46bd mov sp, r7 80013f2: f85d 7b04 ldr.w r7, [sp], #4 80013f6: 4770 bx lr 80013f8: 52002000 .word 0x52002000 80013fc: 08192a3b .word 0x08192a3b 8001400: 4c5d6e7f .word 0x4c5d6e7f 08001404 : /** * @brief Lock the FLASH Option Bytes Registers access. * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) { 8001404: b480 push {r7} 8001406: af00 add r7, sp, #0 /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ SET_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK); 8001408: 4b0b ldr r3, [pc, #44] @ (8001438 ) 800140a: f8d3 3104 ldr.w r3, [r3, #260] @ 0x104 800140e: 4a0a ldr r2, [pc, #40] @ (8001438 ) 8001410: f043 0301 orr.w r3, r3, #1 8001414: f8c2 3104 str.w r3, [r2, #260] @ 0x104 /* Verify that the Option Bytes are locked */ if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != 0U) 8001418: 4b07 ldr r3, [pc, #28] @ (8001438 ) 800141a: f8d3 3104 ldr.w r3, [r3, #260] @ 0x104 800141e: f003 0301 and.w r3, r3, #1 8001422: 2b00 cmp r3, #0 8001424: d001 beq.n 800142a { return HAL_OK; 8001426: 2300 movs r3, #0 8001428: e000 b.n 800142c } return HAL_ERROR; 800142a: 2301 movs r3, #1 } 800142c: 4618 mov r0, r3 800142e: 46bd mov sp, r7 8001430: f85d 7b04 ldr.w r7, [sp], #4 8001434: 4770 bx lr 8001436: bf00 nop 8001438: 52002000 .word 0x52002000 0800143c : * @brief Wait for a FLASH operation to complete. * @param Timeout maximum flash operation timeout * @retval HAL Status */ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) { 800143c: b580 push {r7, lr} 800143e: b084 sub sp, #16 8001440: af00 add r7, sp, #0 8001442: 6078 str r0, [r7, #4] /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. Even if the FLASH operation fails, the BUSY flag will be reset and an error flag will be set */ uint32_t tickstart = HAL_GetTick(); 8001444: f7ff fc54 bl 8000cf0 8001448: 60f8 str r0, [r7, #12] uint32_t error; while ((FLASH->SR & FLASH_SR_QW) != 0U) 800144a: e010 b.n 800146e { if (Timeout != HAL_MAX_DELAY) 800144c: 687b ldr r3, [r7, #4] 800144e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8001452: d00c beq.n 800146e { if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) 8001454: f7ff fc4c bl 8000cf0 8001458: 4602 mov r2, r0 800145a: 68fb ldr r3, [r7, #12] 800145c: 1ad3 subs r3, r2, r3 800145e: 687a ldr r2, [r7, #4] 8001460: 429a cmp r2, r3 8001462: d302 bcc.n 800146a 8001464: 687b ldr r3, [r7, #4] 8001466: 2b00 cmp r3, #0 8001468: d101 bne.n 800146e { return HAL_TIMEOUT; 800146a: 2303 movs r3, #3 800146c: e033 b.n 80014d6 while ((FLASH->SR & FLASH_SR_QW) != 0U) 800146e: 4b1c ldr r3, [pc, #112] @ (80014e0 ) 8001470: 695b ldr r3, [r3, #20] 8001472: f003 0304 and.w r3, r3, #4 8001476: 2b00 cmp r3, #0 8001478: d1e8 bne.n 800144c } } } /* Check FLASH operation error flags */ error = (FLASH->ISR & FLASH_FLAG_ISR_ERRORS); 800147a: 4b19 ldr r3, [pc, #100] @ (80014e0 ) 800147c: 6a5a ldr r2, [r3, #36] @ 0x24 800147e: 4b19 ldr r3, [pc, #100] @ (80014e4 ) 8001480: 4013 ands r3, r2 8001482: 60bb str r3, [r7, #8] error |= (FLASH->OPTISR & FLASH_FLAG_OPTISR_ERRORS); 8001484: 4b16 ldr r3, [pc, #88] @ (80014e0 ) 8001486: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 800148a: f003 43b0 and.w r3, r3, #1476395008 @ 0x58000000 800148e: 68ba ldr r2, [r7, #8] 8001490: 4313 orrs r3, r2 8001492: 60bb str r3, [r7, #8] if (error != 0U) 8001494: 68bb ldr r3, [r7, #8] 8001496: 2b00 cmp r3, #0 8001498: d012 beq.n 80014c0 { /*Save the error code*/ pFlash.ErrorCode |= error; 800149a: 4b13 ldr r3, [pc, #76] @ (80014e8 ) 800149c: 685a ldr r2, [r3, #4] 800149e: 68bb ldr r3, [r7, #8] 80014a0: 4313 orrs r3, r2 80014a2: 4a11 ldr r2, [pc, #68] @ (80014e8 ) 80014a4: 6053 str r3, [r2, #4] /* Clear error programming flags */ FLASH->ICR = (error & FLASH_FLAG_ISR_ERRORS); 80014a6: 490e ldr r1, [pc, #56] @ (80014e0 ) 80014a8: 68ba ldr r2, [r7, #8] 80014aa: 4b0e ldr r3, [pc, #56] @ (80014e4 ) 80014ac: 4013 ands r3, r2 80014ae: 628b str r3, [r1, #40] @ 0x28 FLASH->OPTICR = (error & FLASH_FLAG_OPTISR_ERRORS); 80014b0: 4a0b ldr r2, [pc, #44] @ (80014e0 ) 80014b2: 68bb ldr r3, [r7, #8] 80014b4: f003 43b0 and.w r3, r3, #1476395008 @ 0x58000000 80014b8: f8c2 310c str.w r3, [r2, #268] @ 0x10c return HAL_ERROR; 80014bc: 2301 movs r3, #1 80014be: e00a b.n 80014d6 } /* Check FLASH End of Operation flag */ if ((FLASH->ISR & FLASH_FLAG_EOP) != 0U) 80014c0: 4b07 ldr r3, [pc, #28] @ (80014e0 ) 80014c2: 6a5b ldr r3, [r3, #36] @ 0x24 80014c4: f403 3380 and.w r3, r3, #65536 @ 0x10000 80014c8: 2b00 cmp r3, #0 80014ca: d003 beq.n 80014d4 { /* Clear FLASH End of Operation pending bit */ FLASH->ICR = FLASH_FLAG_EOP; 80014cc: 4b04 ldr r3, [pc, #16] @ (80014e0 ) 80014ce: f44f 3280 mov.w r2, #65536 @ 0x10000 80014d2: 629a str r2, [r3, #40] @ 0x28 } /* If there is no error flag set */ return HAL_OK; 80014d4: 2300 movs r3, #0 } 80014d6: 4618 mov r0, r3 80014d8: 3710 adds r7, #16 80014da: 46bd mov sp, r7 80014dc: bd80 pop {r7, pc} 80014de: bf00 nop 80014e0: 52002000 .word 0x52002000 80014e4: 113e0000 .word 0x113e0000 80014e8: 24000150 .word 0x24000150 080014ec : * - after a power reset (BOR reset or exit from Standby/Shutdown modes) * * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(const FLASH_OBProgramInitTypeDef *pOBInit) { 80014ec: b580 push {r7, lr} 80014ee: b084 sub sp, #16 80014f0: af00 add r7, sp, #0 80014f2: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); /* Process Locked */ __HAL_LOCK(&pFlash); 80014f4: 4b36 ldr r3, [pc, #216] @ (80015d0 ) 80014f6: 781b ldrb r3, [r3, #0] 80014f8: 2b01 cmp r3, #1 80014fa: d101 bne.n 8001500 80014fc: 2302 movs r3, #2 80014fe: e062 b.n 80015c6 8001500: 4b33 ldr r3, [pc, #204] @ (80015d0 ) 8001502: 2201 movs r2, #1 8001504: 701a strb r2, [r3, #0] /* Reset error code */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; 8001506: 4b32 ldr r3, [pc, #200] @ (80015d0 ) 8001508: 2200 movs r2, #0 800150a: 605a str r2, [r3, #4] /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); 800150c: f44f 707a mov.w r0, #1000 @ 0x3e8 8001510: f7ff ff94 bl 800143c 8001514: 4603 mov r3, r0 8001516: 73fb strb r3, [r7, #15] if ((status == HAL_OK) && (pOBInit->OptionType != 0U)) 8001518: 7bfb ldrb r3, [r7, #15] 800151a: 2b00 cmp r3, #0 800151c: d14f bne.n 80015be 800151e: 687b ldr r3, [r7, #4] 8001520: 681b ldr r3, [r3, #0] 8001522: 2b00 cmp r3, #0 8001524: d04b beq.n 80015be { /* Set PG_OPT Bit */ SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OPT); 8001526: 4b2b ldr r3, [pc, #172] @ (80015d4 ) 8001528: f8d3 3104 ldr.w r3, [r3, #260] @ 0x104 800152c: 4a29 ldr r2, [pc, #164] @ (80015d4 ) 800152e: f043 0302 orr.w r3, r3, #2 8001532: f8c2 3104 str.w r3, [r2, #260] @ 0x104 /* Write protection configuration */ if ((pOBInit->OptionType & OPTIONBYTE_WRP) != 0U) 8001536: 687b ldr r3, [r7, #4] 8001538: 681b ldr r3, [r3, #0] 800153a: f003 0301 and.w r3, r3, #1 800153e: 2b00 cmp r3, #0 8001540: d007 beq.n 8001552 { /* Configure of Write protection on the selected area */ FLASH_OB_WRPConfig(pOBInit->WRPState, pOBInit->WRPSector); 8001542: 687b ldr r3, [r7, #4] 8001544: 685a ldr r2, [r3, #4] 8001546: 687b ldr r3, [r7, #4] 8001548: 689b ldr r3, [r3, #8] 800154a: 4619 mov r1, r3 800154c: 4610 mov r0, r2 800154e: f000 f875 bl 800163c } /* User Configuration */ if ((pOBInit->OptionType & OPTIONBYTE_USER) != 0U) 8001552: 687b ldr r3, [r7, #4] 8001554: 681b ldr r3, [r3, #0] 8001556: f003 0302 and.w r3, r3, #2 800155a: 2b00 cmp r3, #0 800155c: d008 beq.n 8001570 { /* Configure the user option bytes */ FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig1, pOBInit->USERConfig2); 800155e: 687b ldr r3, [r7, #4] 8001560: 68d8 ldr r0, [r3, #12] 8001562: 687b ldr r3, [r7, #4] 8001564: 6919 ldr r1, [r3, #16] 8001566: 687b ldr r3, [r7, #4] 8001568: 695b ldr r3, [r3, #20] 800156a: 461a mov r2, r3 800156c: f000 f88e bl 800168c } /* HDP configuration */ if ((pOBInit->OptionType & OPTIONBYTE_HDP) != 0U) 8001570: 687b ldr r3, [r7, #4] 8001572: 681b ldr r3, [r3, #0] 8001574: f003 0304 and.w r3, r3, #4 8001578: 2b00 cmp r3, #0 800157a: d007 beq.n 800158c { /* Configure the HDP Protection */ FLASH_OB_HDPConfig(pOBInit->HDPStartPage, pOBInit->HDPEndPage); 800157c: 687b ldr r3, [r7, #4] 800157e: 699a ldr r2, [r3, #24] 8001580: 687b ldr r3, [r7, #4] 8001582: 69db ldr r3, [r3, #28] 8001584: 4619 mov r1, r3 8001586: 4610 mov r0, r2 8001588: f000 f976 bl 8001878 } /* Non-volatile state configuration */ if ((pOBInit->OptionType & OPTIONBYTE_NV) != 0U) 800158c: 687b ldr r3, [r7, #4] 800158e: 681b ldr r3, [r3, #0] 8001590: f003 0308 and.w r3, r3, #8 8001594: 2b00 cmp r3, #0 8001596: d004 beq.n 80015a2 { /* Configure the non-volatile state */ FLASH_OB_NVConfig(pOBInit->NVState); 8001598: 687b ldr r3, [r7, #4] 800159a: 6a1b ldr r3, [r3, #32] 800159c: 4618 mov r0, r3 800159e: f000 f985 bl 80018ac } /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); 80015a2: f44f 707a mov.w r0, #1000 @ 0x3e8 80015a6: f7ff ff49 bl 800143c 80015aa: 4603 mov r3, r0 80015ac: 73fb strb r3, [r7, #15] /* Clear PG_OPT Bit */ CLEAR_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OPT); 80015ae: 4b09 ldr r3, [pc, #36] @ (80015d4 ) 80015b0: f8d3 3104 ldr.w r3, [r3, #260] @ 0x104 80015b4: 4a07 ldr r2, [pc, #28] @ (80015d4 ) 80015b6: f023 0302 bic.w r3, r3, #2 80015ba: f8c2 3104 str.w r3, [r2, #260] @ 0x104 } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); 80015be: 4b04 ldr r3, [pc, #16] @ (80015d0 ) 80015c0: 2200 movs r2, #0 80015c2: 701a strb r2, [r3, #0] return status; 80015c4: 7bfb ldrb r3, [r7, #15] } 80015c6: 4618 mov r0, r3 80015c8: 3710 adds r7, #16 80015ca: 46bd mov sp, r7 80015cc: bd80 pop {r7, pc} 80015ce: bf00 nop 80015d0: 24000150 .word 0x24000150 80015d4: 52002000 .word 0x52002000 080015d8 : * Boot Address, else no information will be returned * * @retval None */ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) { 80015d8: b580 push {r7, lr} 80015da: b082 sub sp, #8 80015dc: af00 add r7, sp, #0 80015de: 6078 str r0, [r7, #4] /* Get write protection on the selected area */ FLASH_OB_GetWRP(&(pOBInit->WRPState), &(pOBInit->WRPSector)); 80015e0: 687b ldr r3, [r7, #4] 80015e2: 1d1a adds r2, r3, #4 80015e4: 687b ldr r3, [r7, #4] 80015e6: 3308 adds r3, #8 80015e8: 4619 mov r1, r3 80015ea: 4610 mov r0, r2 80015ec: f000 f974 bl 80018d8 /* Get the user option bytes */ FLASH_OB_GetUser(&(pOBInit->USERConfig1), &(pOBInit->USERConfig2)); 80015f0: 687b ldr r3, [r7, #4] 80015f2: f103 0210 add.w r2, r3, #16 80015f6: 687b ldr r3, [r7, #4] 80015f8: 3314 adds r3, #20 80015fa: 4619 mov r1, r3 80015fc: 4610 mov r0, r2 80015fe: f000 f98d bl 800191c /* Get the HDP Protection */ FLASH_OB_GetHDP(&(pOBInit->HDPStartPage), &(pOBInit->HDPEndPage)); 8001602: 687b ldr r3, [r7, #4] 8001604: f103 0218 add.w r2, r3, #24 8001608: 687b ldr r3, [r7, #4] 800160a: 331c adds r3, #28 800160c: 4619 mov r1, r3 800160e: 4610 mov r0, r2 8001610: f000 f99c bl 800194c /* Get the non-volatile state */ pOBInit->NVState = FLASH_OB_GetNV(); 8001614: f000 f9b4 bl 8001980 8001618: 4602 mov r2, r0 800161a: 687b ldr r3, [r7, #4] 800161c: 621a str r2, [r3, #32] /* Get the Root-Of-Trust configuration */ pOBInit->ROTConfig = FLASH_OB_GetRoT(); 800161e: f000 f9bd bl 800199c 8001622: 4602 mov r2, r0 8001624: 687b ldr r3, [r7, #4] 8001626: 625a str r2, [r3, #36] @ 0x24 /* Get the epoch */ pOBInit->EPOCH = FLASH_OB_GetEpoch(); 8001628: f000 f9c6 bl 80019b8 800162c: 4602 mov r2, r0 800162e: 687b ldr r3, [r7, #4] 8001630: 629a str r2, [r3, #40] @ 0x28 } 8001632: bf00 nop 8001634: 3708 adds r7, #8 8001636: 46bd mov sp, r7 8001638: bd80 pop {r7, pc} ... 0800163c : * @param WRPSector * * @retval None */ static void FLASH_OB_WRPConfig(uint32_t WRPState, uint32_t WRPSector) { 800163c: b480 push {r7} 800163e: b083 sub sp, #12 8001640: af00 add r7, sp, #0 8001642: 6078 str r0, [r7, #4] 8001644: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_OB_WRPSTATE(WRPState)); /* Configure the write protected area */ if (WRPState == OB_WRPSTATE_DISABLE) 8001646: 687b ldr r3, [r7, #4] 8001648: 2b00 cmp r3, #0 800164a: d109 bne.n 8001660 { FLASH->WRPSRP |= (WRPSector & FLASH_WRPSRP_WRPS); 800164c: 4b0e ldr r3, [pc, #56] @ (8001688 ) 800164e: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c 8001652: 683b ldr r3, [r7, #0] 8001654: b2db uxtb r3, r3 8001656: 490c ldr r1, [pc, #48] @ (8001688 ) 8001658: 4313 orrs r3, r2 800165a: f8c1 321c str.w r3, [r1, #540] @ 0x21c } else { /* Empty statement (to be compliant MISRA 15.7) */ } } 800165e: e00c b.n 800167a else if (WRPState == OB_WRPSTATE_ENABLE) 8001660: 687b ldr r3, [r7, #4] 8001662: 2b01 cmp r3, #1 8001664: d109 bne.n 800167a FLASH->WRPSRP &= (~(WRPSector & FLASH_WRPSRP_WRPS)); 8001666: 4b08 ldr r3, [pc, #32] @ (8001688 ) 8001668: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c 800166c: 683b ldr r3, [r7, #0] 800166e: b2db uxtb r3, r3 8001670: 43db mvns r3, r3 8001672: 4905 ldr r1, [pc, #20] @ (8001688 ) 8001674: 4013 ands r3, r2 8001676: f8c1 321c str.w r3, [r1, #540] @ 0x21c } 800167a: bf00 nop 800167c: 370c adds r7, #12 800167e: 46bd mov sp, r7 8001680: f85d 7b04 ldr.w r7, [sp], #4 8001684: 4770 bx lr 8001686: bf00 nop 8001688: 52002000 .word 0x52002000 0800168c : * @param UserConfig1 The selected User Option Bytes values * @param UserConfig2 The selected User Option Bytes values * @retval None */ static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig1, uint32_t UserConfig2) { 800168c: b480 push {r7} 800168e: b087 sub sp, #28 8001690: af00 add r7, sp, #0 8001692: 60f8 str r0, [r7, #12] 8001694: 60b9 str r1, [r7, #8] 8001696: 607a str r2, [r7, #4] uint32_t optr_reg_val = 0; 8001698: 2300 movs r3, #0 800169a: 617b str r3, [r7, #20] uint32_t optr_reg_mask = 0; 800169c: 2300 movs r3, #0 800169e: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_OB_USER_TYPE(UserType)); if ((UserType & OB_USER_BOR_LEV) != 0U) 80016a0: 68fb ldr r3, [r7, #12] 80016a2: f003 0301 and.w r3, r3, #1 80016a6: 2b00 cmp r3, #0 80016a8: d009 beq.n 80016be { /* BOR level option byte should be modified */ assert_param(IS_OB_USER_BOR_LEVEL(UserConfig1 & FLASH_OBW1SR_BOR_LEVEL)); /* Set value and mask for BOR level option byte */ optr_reg_val |= (UserConfig1 & FLASH_OBW1SR_BOR_LEVEL); 80016aa: 68bb ldr r3, [r7, #8] 80016ac: f003 030c and.w r3, r3, #12 80016b0: 697a ldr r2, [r7, #20] 80016b2: 4313 orrs r3, r2 80016b4: 617b str r3, [r7, #20] optr_reg_mask |= FLASH_OBW1SR_BOR_LEVEL; 80016b6: 693b ldr r3, [r7, #16] 80016b8: f043 030c orr.w r3, r3, #12 80016bc: 613b str r3, [r7, #16] } if ((UserType & OB_USER_IWDG_SW) != 0U) 80016be: 68fb ldr r3, [r7, #12] 80016c0: f003 0302 and.w r3, r3, #2 80016c4: 2b00 cmp r3, #0 80016c6: d009 beq.n 80016dc { /* IWDG1_HW option byte should be modified */ assert_param(IS_OB_USER_IWDG(UserConfig1 & FLASH_OBW1SR_IWDG_HW)); /* Set value and mask for IWDG1_HW option byte */ optr_reg_val |= (UserConfig1 & FLASH_OBW1SR_IWDG_HW); 80016c8: 68bb ldr r3, [r7, #8] 80016ca: f003 0310 and.w r3, r3, #16 80016ce: 697a ldr r2, [r7, #20] 80016d0: 4313 orrs r3, r2 80016d2: 617b str r3, [r7, #20] optr_reg_mask |= FLASH_OBW1SR_IWDG_HW; 80016d4: 693b ldr r3, [r7, #16] 80016d6: f043 0310 orr.w r3, r3, #16 80016da: 613b str r3, [r7, #16] } if ((UserType & OB_USER_NRST_STOP) != 0U) 80016dc: 68fb ldr r3, [r7, #12] 80016de: f003 0304 and.w r3, r3, #4 80016e2: 2b00 cmp r3, #0 80016e4: d009 beq.n 80016fa { /* NRST_STOP_D1 option byte should be modified */ assert_param(IS_OB_USER_STOP(UserConfig1 & FLASH_OBW1SR_NRST_STOP)); /* Set value and mask for NRST_STOP_D1 option byte */ optr_reg_val |= (UserConfig1 & FLASH_OBW1SR_NRST_STOP); 80016e6: 68bb ldr r3, [r7, #8] 80016e8: f003 0340 and.w r3, r3, #64 @ 0x40 80016ec: 697a ldr r2, [r7, #20] 80016ee: 4313 orrs r3, r2 80016f0: 617b str r3, [r7, #20] optr_reg_mask |= FLASH_OBW1SR_NRST_STOP; 80016f2: 693b ldr r3, [r7, #16] 80016f4: f043 0340 orr.w r3, r3, #64 @ 0x40 80016f8: 613b str r3, [r7, #16] } if ((UserType & OB_USER_NRST_STDBY) != 0U) 80016fa: 68fb ldr r3, [r7, #12] 80016fc: f003 0308 and.w r3, r3, #8 8001700: 2b00 cmp r3, #0 8001702: d009 beq.n 8001718 { /* NRST_STBY_D1 option byte should be modified */ assert_param(IS_OB_USER_STANDBY(UserConfig1 & FLASH_OBW1SR_NRST_STBY)); /* Set value and mask for NRST_STBY_D1 option byte */ optr_reg_val |= (UserConfig1 & FLASH_OBW1SR_NRST_STBY); 8001704: 68bb ldr r3, [r7, #8] 8001706: f003 0380 and.w r3, r3, #128 @ 0x80 800170a: 697a ldr r2, [r7, #20] 800170c: 4313 orrs r3, r2 800170e: 617b str r3, [r7, #20] optr_reg_mask |= FLASH_OBW1SR_NRST_STBY; 8001710: 693b ldr r3, [r7, #16] 8001712: f043 0380 orr.w r3, r3, #128 @ 0x80 8001716: 613b str r3, [r7, #16] } if ((UserType & OB_USER_XSPI1_HSLV) != 0U) 8001718: 68fb ldr r3, [r7, #12] 800171a: f003 0310 and.w r3, r3, #16 800171e: 2b00 cmp r3, #0 8001720: d009 beq.n 8001736 { /* XSPI1_HSLV option byte should be modified */ assert_param(IS_OB_USER_XSPI1_HSLV(UserConfig1 & FLASH_OBW1SR_XSPI1_HSLV)); /* Set value and mask for XSPI1_HSLV option byte */ optr_reg_val |= (UserConfig1 & FLASH_OBW1SR_XSPI1_HSLV); 8001722: 68bb ldr r3, [r7, #8] 8001724: f403 7380 and.w r3, r3, #256 @ 0x100 8001728: 697a ldr r2, [r7, #20] 800172a: 4313 orrs r3, r2 800172c: 617b str r3, [r7, #20] optr_reg_mask |= FLASH_OBW1SR_XSPI1_HSLV; 800172e: 693b ldr r3, [r7, #16] 8001730: f443 7380 orr.w r3, r3, #256 @ 0x100 8001734: 613b str r3, [r7, #16] } if ((UserType & OB_USER_XSPI2_HSLV) != 0U) 8001736: 68fb ldr r3, [r7, #12] 8001738: f003 0320 and.w r3, r3, #32 800173c: 2b00 cmp r3, #0 800173e: d009 beq.n 8001754 { /* XSPI2_HSLV option byte should be modified */ assert_param(IS_OB_USER_XSPI2_HSLV(UserConfig1 & FLASH_OBW1SR_XSPI2_HSLV)); /* Set value and mask for XSPI2_HSLV option byte */ optr_reg_val |= (UserConfig1 & FLASH_OBW1SR_XSPI2_HSLV); 8001740: 68bb ldr r3, [r7, #8] 8001742: f403 7300 and.w r3, r3, #512 @ 0x200 8001746: 697a ldr r2, [r7, #20] 8001748: 4313 orrs r3, r2 800174a: 617b str r3, [r7, #20] optr_reg_mask |= FLASH_OBW1SR_XSPI2_HSLV; 800174c: 693b ldr r3, [r7, #16] 800174e: f443 7300 orr.w r3, r3, #512 @ 0x200 8001752: 613b str r3, [r7, #16] } if ((UserType & OB_USER_IWDG_STOP) != 0U) 8001754: 68fb ldr r3, [r7, #12] 8001756: f003 0340 and.w r3, r3, #64 @ 0x40 800175a: 2b00 cmp r3, #0 800175c: d009 beq.n 8001772 { /* IWDG_FZ_STOP option byte should be modified */ assert_param(IS_OB_USER_IWDG_STOP(UserConfig1 & FLASH_OBW1SR_IWDG_FZ_STOP)); /* Set value and mask for IWDG_FZ_STOP option byte */ optr_reg_val |= (UserConfig1 & FLASH_OBW1SR_IWDG_FZ_STOP); 800175e: 68bb ldr r3, [r7, #8] 8001760: f403 3300 and.w r3, r3, #131072 @ 0x20000 8001764: 697a ldr r2, [r7, #20] 8001766: 4313 orrs r3, r2 8001768: 617b str r3, [r7, #20] optr_reg_mask |= FLASH_OBW1SR_IWDG_FZ_STOP; 800176a: 693b ldr r3, [r7, #16] 800176c: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8001770: 613b str r3, [r7, #16] } if ((UserType & OB_USER_IWDG_STDBY) != 0U) 8001772: 68fb ldr r3, [r7, #12] 8001774: f003 0380 and.w r3, r3, #128 @ 0x80 8001778: 2b00 cmp r3, #0 800177a: d009 beq.n 8001790 { /* IWDG_FZ_SDBY option byte should be modified */ assert_param(IS_OB_USER_IWDG_STDBY(UserConfig1 & FLASH_OBW1SR_IWDG_FZ_STBY)); /* Set value and mask for IWDG_FZ_SDBY option byte */ optr_reg_val |= (UserConfig1 & FLASH_OBW1SR_IWDG_FZ_STBY); 800177c: 68bb ldr r3, [r7, #8] 800177e: f403 2380 and.w r3, r3, #262144 @ 0x40000 8001782: 697a ldr r2, [r7, #20] 8001784: 4313 orrs r3, r2 8001786: 617b str r3, [r7, #20] optr_reg_mask |= FLASH_OBW1SR_IWDG_FZ_STBY; 8001788: 693b ldr r3, [r7, #16] 800178a: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800178e: 613b str r3, [r7, #16] } if ((UserType & OB_USER_VDDIO_HSLV) != 0U) 8001790: 68fb ldr r3, [r7, #12] 8001792: f403 7380 and.w r3, r3, #256 @ 0x100 8001796: 2b00 cmp r3, #0 8001798: d009 beq.n 80017ae { /* VDDIO_HSLV option byte should be modified */ assert_param(IS_OB_USER_VDDIO_HSLV(UserConfig1 & FLASH_OBW1SR_VDDIO_HSLV)); /* Set value and mask for VDDIO_HSLV option byte */ optr_reg_val |= (UserConfig1 & FLASH_OBW1SR_VDDIO_HSLV); 800179a: 68bb ldr r3, [r7, #8] 800179c: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 80017a0: 697a ldr r2, [r7, #20] 80017a2: 4313 orrs r3, r2 80017a4: 617b str r3, [r7, #20] optr_reg_mask |= FLASH_OBW1SR_VDDIO_HSLV; 80017a6: 693b ldr r3, [r7, #16] 80017a8: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 80017ac: 613b str r3, [r7, #16] } /* Configure the option bytes register 1 if necessary */ if (optr_reg_mask != 0U) 80017ae: 693b ldr r3, [r7, #16] 80017b0: 2b00 cmp r3, #0 80017b2: d00a beq.n 80017ca { MODIFY_REG(FLASH->OBW1SRP, optr_reg_mask, optr_reg_val); 80017b4: 4b2f ldr r3, [pc, #188] @ (8001874 ) 80017b6: f8d3 2264 ldr.w r2, [r3, #612] @ 0x264 80017ba: 693b ldr r3, [r7, #16] 80017bc: 43db mvns r3, r3 80017be: 401a ands r2, r3 80017c0: 492c ldr r1, [pc, #176] @ (8001874 ) 80017c2: 697b ldr r3, [r7, #20] 80017c4: 4313 orrs r3, r2 80017c6: f8c1 3264 str.w r3, [r1, #612] @ 0x264 } optr_reg_val = 0; 80017ca: 2300 movs r3, #0 80017cc: 617b str r3, [r7, #20] optr_reg_mask = 0; 80017ce: 2300 movs r3, #0 80017d0: 613b str r3, [r7, #16] if ((UserType & OB_USER_ITCM_AXI_SHARE) != 0U) 80017d2: 68fb ldr r3, [r7, #12] 80017d4: f403 7300 and.w r3, r3, #512 @ 0x200 80017d8: 2b00 cmp r3, #0 80017da: d009 beq.n 80017f0 { /* ITCM_AXI_SHARE option byte should be modified */ assert_param(IS_OB_USER_ITCM_AXI_SHARE(UserConfig2 & FLASH_OBW2SR_ITCM_AXI_SHARE)); /* Set value and mask for ITCM_AXI_SHARE option byte */ optr_reg_val |= (UserConfig2 & FLASH_OBW2SR_ITCM_AXI_SHARE); 80017dc: 687b ldr r3, [r7, #4] 80017de: f003 0307 and.w r3, r3, #7 80017e2: 697a ldr r2, [r7, #20] 80017e4: 4313 orrs r3, r2 80017e6: 617b str r3, [r7, #20] optr_reg_mask |= FLASH_OBW2SR_ITCM_AXI_SHARE; 80017e8: 693b ldr r3, [r7, #16] 80017ea: f043 0307 orr.w r3, r3, #7 80017ee: 613b str r3, [r7, #16] } if ((UserType & OB_USER_DTCM_AXI_SHARE) != 0U) 80017f0: 68fb ldr r3, [r7, #12] 80017f2: f403 6380 and.w r3, r3, #1024 @ 0x400 80017f6: 2b00 cmp r3, #0 80017f8: d009 beq.n 800180e { /* DTCM_AXI_SHARE option byte should be modified */ assert_param(IS_OB_USER_DTCM_AXI_SHARE(UserConfig2 & FLASH_OBW2SR_DTCM_AXI_SHARE)); /* Set value and mask for DTCM_AXI_SHARE option byte */ optr_reg_val |= (UserConfig2 & FLASH_OBW2SR_DTCM_AXI_SHARE); 80017fa: 687b ldr r3, [r7, #4] 80017fc: f003 0370 and.w r3, r3, #112 @ 0x70 8001800: 697a ldr r2, [r7, #20] 8001802: 4313 orrs r3, r2 8001804: 617b str r3, [r7, #20] optr_reg_mask |= FLASH_OBW2SR_DTCM_AXI_SHARE; 8001806: 693b ldr r3, [r7, #16] 8001808: f043 0370 orr.w r3, r3, #112 @ 0x70 800180c: 613b str r3, [r7, #16] } if ((UserType & OB_USER_SRAM_ECC) != 0U) 800180e: 68fb ldr r3, [r7, #12] 8001810: f403 6300 and.w r3, r3, #2048 @ 0x800 8001814: 2b00 cmp r3, #0 8001816: d009 beq.n 800182c { /* SRAM_ECC option byte should be modified */ assert_param(IS_OB_USER_AXISRAM_ECC(UserConfig2 & FLASH_OBW2SR_ECC_ON_SRAM)); /* Set value and mask for SRAM_ECC option byte */ optr_reg_val |= (UserConfig2 & FLASH_OBW2SR_ECC_ON_SRAM); 8001818: 687b ldr r3, [r7, #4] 800181a: f403 7380 and.w r3, r3, #256 @ 0x100 800181e: 697a ldr r2, [r7, #20] 8001820: 4313 orrs r3, r2 8001822: 617b str r3, [r7, #20] optr_reg_mask |= FLASH_OBW2SR_ECC_ON_SRAM; 8001824: 693b ldr r3, [r7, #16] 8001826: f443 7380 orr.w r3, r3, #256 @ 0x100 800182a: 613b str r3, [r7, #16] } if ((UserType & OB_USER_I2C_NI3C) != 0U) 800182c: 68fb ldr r3, [r7, #12] 800182e: f403 5380 and.w r3, r3, #4096 @ 0x1000 8001832: 2b00 cmp r3, #0 8001834: d009 beq.n 800184a { /* I2C_NI3C option byte should be modified */ assert_param(IS_OB_USER_I2C_NI3C(UserConfig2 & FLASH_OBW2SR_I2C_NI3C)); /* Set value and mask for I2C_NI3C option byte */ optr_reg_val |= (UserConfig2 & FLASH_OBW2SR_I2C_NI3C); 8001836: 687b ldr r3, [r7, #4] 8001838: f403 7300 and.w r3, r3, #512 @ 0x200 800183c: 697a ldr r2, [r7, #20] 800183e: 4313 orrs r3, r2 8001840: 617b str r3, [r7, #20] optr_reg_mask |= FLASH_OBW2SR_I2C_NI3C; 8001842: 693b ldr r3, [r7, #16] 8001844: f443 7300 orr.w r3, r3, #512 @ 0x200 8001848: 613b str r3, [r7, #16] } /* Configure the option bytes register 2 if necessary */ if (optr_reg_mask != 0U) 800184a: 693b ldr r3, [r7, #16] 800184c: 2b00 cmp r3, #0 800184e: d00a beq.n 8001866 { MODIFY_REG(FLASH->OBW2SRP, optr_reg_mask, optr_reg_val); 8001850: 4b08 ldr r3, [pc, #32] @ (8001874 ) 8001852: f8d3 226c ldr.w r2, [r3, #620] @ 0x26c 8001856: 693b ldr r3, [r7, #16] 8001858: 43db mvns r3, r3 800185a: 401a ands r2, r3 800185c: 4905 ldr r1, [pc, #20] @ (8001874 ) 800185e: 697b ldr r3, [r7, #20] 8001860: 4313 orrs r3, r2 8001862: f8c1 326c str.w r3, [r1, #620] @ 0x26c } } 8001866: bf00 nop 8001868: 371c adds r7, #28 800186a: 46bd mov sp, r7 800186c: f85d 7b04 ldr.w r7, [sp], #4 8001870: 4770 bx lr 8001872: bf00 nop 8001874: 52002000 .word 0x52002000 08001878 : * @param HDPEndPage * * @retval None */ static void FLASH_OB_HDPConfig(uint32_t HDPStartPage, uint32_t HDPEndPage) { 8001878: b480 push {r7} 800187a: b083 sub sp, #12 800187c: af00 add r7, sp, #0 800187e: 6078 str r0, [r7, #4] 8001880: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_OB_HDP_PAGE(HDPStartPage)); assert_param(IS_OB_HDP_PAGE(HDPEndPage)); MODIFY_REG(FLASH->HDPSRP, (FLASH_HDPSRP_HDP_AREA_START | FLASH_HDPSRP_HDP_AREA_END), \ 8001882: 4b09 ldr r3, [pc, #36] @ (80018a8 ) 8001884: f8d3 3234 ldr.w r3, [r3, #564] @ 0x234 8001888: f003 22ff and.w r2, r3, #4278255360 @ 0xff00ff00 800188c: 683b ldr r3, [r7, #0] 800188e: 0419 lsls r1, r3, #16 8001890: 687b ldr r3, [r7, #4] 8001892: 430b orrs r3, r1 8001894: 4904 ldr r1, [pc, #16] @ (80018a8 ) 8001896: 4313 orrs r3, r2 8001898: f8c1 3234 str.w r3, [r1, #564] @ 0x234 (HDPStartPage | (HDPEndPage << FLASH_HDPSRP_HDP_AREA_END_Pos))); } 800189c: bf00 nop 800189e: 370c adds r7, #12 80018a0: 46bd mov sp, r7 80018a2: f85d 7b04 ldr.w r7, [sp], #4 80018a6: 4770 bx lr 80018a8: 52002000 .word 0x52002000 080018ac : * @param NVState * * @retval None */ static void FLASH_OB_NVConfig(uint32_t NVState) { 80018ac: b480 push {r7} 80018ae: b083 sub sp, #12 80018b0: af00 add r7, sp, #0 80018b2: 6078 str r0, [r7, #4] /* Check the parameter */ assert_param(IS_OB_NVSTATE(NVState)); MODIFY_REG(FLASH->NVSRP, FLASH_NVSRP_NVSTATE, NVState); 80018b4: 4b07 ldr r3, [pc, #28] @ (80018d4 ) 80018b6: f8d3 3204 ldr.w r3, [r3, #516] @ 0x204 80018ba: f023 02ff bic.w r2, r3, #255 @ 0xff 80018be: 4905 ldr r1, [pc, #20] @ (80018d4 ) 80018c0: 687b ldr r3, [r7, #4] 80018c2: 4313 orrs r3, r2 80018c4: f8c1 3204 str.w r3, [r1, #516] @ 0x204 } 80018c8: bf00 nop 80018ca: 370c adds r7, #12 80018cc: 46bd mov sp, r7 80018ce: f85d 7b04 ldr.w r7, [sp], #4 80018d2: 4770 bx lr 80018d4: 52002000 .word 0x52002000 080018d8 : * @param WRPSector * * @retval None */ static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector) { 80018d8: b480 push {r7} 80018da: b083 sub sp, #12 80018dc: af00 add r7, sp, #0 80018de: 6078 str r0, [r7, #4] 80018e0: 6039 str r1, [r7, #0] if ((FLASH->WRPSR & FLASH_WRPSR_WRPS) == FLASH_WRPSR_WRPS) 80018e2: 4b0d ldr r3, [pc, #52] @ (8001918 ) 80018e4: f8d3 3218 ldr.w r3, [r3, #536] @ 0x218 80018e8: b2db uxtb r3, r3 80018ea: 2bff cmp r3, #255 @ 0xff 80018ec: d103 bne.n 80018f6 { /* All sectors aren't write protected */ *WRPState = OB_WRPSTATE_DISABLE; 80018ee: 687b ldr r3, [r7, #4] 80018f0: 2200 movs r2, #0 80018f2: 601a str r2, [r3, #0] { /* Some sectors are write protected */ *WRPState = OB_WRPSTATE_ENABLE; *WRPSector = ((~(FLASH->WRPSR)) & FLASH_WRPSR_WRPS); } } 80018f4: e009 b.n 800190a *WRPState = OB_WRPSTATE_ENABLE; 80018f6: 687b ldr r3, [r7, #4] 80018f8: 2201 movs r2, #1 80018fa: 601a str r2, [r3, #0] *WRPSector = ((~(FLASH->WRPSR)) & FLASH_WRPSR_WRPS); 80018fc: 4b06 ldr r3, [pc, #24] @ (8001918 ) 80018fe: f8d3 3218 ldr.w r3, [r3, #536] @ 0x218 8001902: 43db mvns r3, r3 8001904: b2da uxtb r2, r3 8001906: 683b ldr r3, [r7, #0] 8001908: 601a str r2, [r3, #0] } 800190a: bf00 nop 800190c: 370c adds r7, #12 800190e: 46bd mov sp, r7 8001910: f85d 7b04 ldr.w r7, [sp], #4 8001914: 4770 bx lr 8001916: bf00 nop 8001918: 52002000 .word 0x52002000 0800191c : * The return value can be a combination of * * @retval None */ static void FLASH_OB_GetUser(uint32_t *UserConfig1, uint32_t *UserConfig2) { 800191c: b480 push {r7} 800191e: b083 sub sp, #12 8001920: af00 add r7, sp, #0 8001922: 6078 str r0, [r7, #4] 8001924: 6039 str r1, [r7, #0] *UserConfig1 = FLASH->OBW1SR; 8001926: 4b08 ldr r3, [pc, #32] @ (8001948 ) 8001928: f8d3 2260 ldr.w r2, [r3, #608] @ 0x260 800192c: 687b ldr r3, [r7, #4] 800192e: 601a str r2, [r3, #0] *UserConfig2 = FLASH->OBW2SR; 8001930: 4b05 ldr r3, [pc, #20] @ (8001948 ) 8001932: f8d3 2268 ldr.w r2, [r3, #616] @ 0x268 8001936: 683b ldr r3, [r7, #0] 8001938: 601a str r2, [r3, #0] } 800193a: bf00 nop 800193c: 370c adds r7, #12 800193e: 46bd mov sp, r7 8001940: f85d 7b04 ldr.w r7, [sp], #4 8001944: 4770 bx lr 8001946: bf00 nop 8001948: 52002000 .word 0x52002000 0800194c : * The return value can be a combination of * * @retval None */ static void FLASH_OB_GetHDP(uint32_t *HDPStartPage, uint32_t *HDPEndPage) { 800194c: b480 push {r7} 800194e: b083 sub sp, #12 8001950: af00 add r7, sp, #0 8001952: 6078 str r0, [r7, #4] 8001954: 6039 str r1, [r7, #0] *HDPStartPage = (FLASH->HDPSR & FLASH_HDPSR_HDP_AREA_START); 8001956: 4b09 ldr r3, [pc, #36] @ (800197c ) 8001958: f8d3 3230 ldr.w r3, [r3, #560] @ 0x230 800195c: b2da uxtb r2, r3 800195e: 687b ldr r3, [r7, #4] 8001960: 601a str r2, [r3, #0] *HDPEndPage = ((FLASH->HDPSR & FLASH_HDPSR_HDP_AREA_END) >> FLASH_HDPSR_HDP_AREA_END_Pos); 8001962: 4b06 ldr r3, [pc, #24] @ (800197c ) 8001964: f8d3 3230 ldr.w r3, [r3, #560] @ 0x230 8001968: 0c1b lsrs r3, r3, #16 800196a: b2da uxtb r2, r3 800196c: 683b ldr r3, [r7, #0] 800196e: 601a str r2, [r3, #0] } 8001970: bf00 nop 8001972: 370c adds r7, #12 8001974: 46bd mov sp, r7 8001976: f85d 7b04 ldr.w r7, [sp], #4 800197a: 4770 bx lr 800197c: 52002000 .word 0x52002000 08001980 : * @brief Return the FLASH Non-volatile state Option Bytes value. * * @retval Value of Non-volatile state */ static uint32_t FLASH_OB_GetNV(void) { 8001980: b480 push {r7} 8001982: af00 add r7, sp, #0 return (FLASH->NVSR & FLASH_NVSR_NVSTATE); 8001984: 4b04 ldr r3, [pc, #16] @ (8001998 ) 8001986: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800198a: b2db uxtb r3, r3 } 800198c: 4618 mov r0, r3 800198e: 46bd mov sp, r7 8001990: f85d 7b04 ldr.w r7, [sp], #4 8001994: 4770 bx lr 8001996: bf00 nop 8001998: 52002000 .word 0x52002000 0800199c : * @brief Return the FLASH RoT Option Bytes value. * * @retval Value of the RoT */ static uint32_t FLASH_OB_GetRoT(void) { 800199c: b480 push {r7} 800199e: af00 add r7, sp, #0 return (FLASH->ROTSR & (FLASH_ROTSR_OEM_PROVD | FLASH_ROTSR_DBG_AUTH | FLASH_ROTSR_IROT_SELECT)); 80019a0: 4b04 ldr r3, [pc, #16] @ (80019b4 ) 80019a2: f8d3 3208 ldr.w r3, [r3, #520] @ 0x208 80019a6: f423 037f bic.w r3, r3, #16711680 @ 0xff0000 } 80019aa: 4618 mov r0, r3 80019ac: 46bd mov sp, r7 80019ae: f85d 7b04 ldr.w r7, [sp], #4 80019b2: 4770 bx lr 80019b4: 52002000 .word 0x52002000 080019b8 : * @brief Return the FLASH Epoch Option Bytes value. * * @retval Value of the Epoch */ static uint32_t FLASH_OB_GetEpoch(void) { 80019b8: b480 push {r7} 80019ba: af00 add r7, sp, #0 return (FLASH->EPOCHSR & FLASH_EPOCHSR_EPOCH); 80019bc: 4b04 ldr r3, [pc, #16] @ (80019d0 ) 80019be: f8d3 3250 ldr.w r3, [r3, #592] @ 0x250 80019c2: f023 437f bic.w r3, r3, #4278190080 @ 0xff000000 } 80019c6: 4618 mov r0, r3 80019c8: 46bd mov sp, r7 80019ca: f85d 7b04 ldr.w r7, [sp], #4 80019ce: 4770 bx lr 80019d0: 52002000 .word 0x52002000 080019d4 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init) { 80019d4: b480 push {r7} 80019d6: b087 sub sp, #28 80019d8: af00 add r7, sp, #0 80019da: 6078 str r0, [r7, #4] 80019dc: 6039 str r1, [r7, #0] uint32_t position = 0x00U; 80019de: 2300 movs r3, #0 80019e0: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00U) 80019e2: e143 b.n 8001c6c { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1UL << position); 80019e4: 683b ldr r3, [r7, #0] 80019e6: 681a ldr r2, [r3, #0] 80019e8: 2101 movs r1, #1 80019ea: 697b ldr r3, [r7, #20] 80019ec: fa01 f303 lsl.w r3, r1, r3 80019f0: 4013 ands r3, r2 80019f2: 60fb str r3, [r7, #12] if (iocurrent != 0x00U) 80019f4: 68fb ldr r3, [r7, #12] 80019f6: 2b00 cmp r3, #0 80019f8: f000 8135 beq.w 8001c66 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 80019fc: 683b ldr r3, [r7, #0] 80019fe: 685b ldr r3, [r3, #4] 8001a00: f003 0303 and.w r3, r3, #3 8001a04: 2b01 cmp r3, #1 8001a06: d005 beq.n 8001a14 8001a08: 683b ldr r3, [r7, #0] 8001a0a: 685b ldr r3, [r3, #4] 8001a0c: f003 0303 and.w r3, r3, #3 8001a10: 2b02 cmp r3, #2 8001a12: d130 bne.n 8001a76 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8001a14: 687b ldr r3, [r7, #4] 8001a16: 689b ldr r3, [r3, #8] 8001a18: 613b str r3, [r7, #16] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos)); 8001a1a: 697b ldr r3, [r7, #20] 8001a1c: 005b lsls r3, r3, #1 8001a1e: 2203 movs r2, #3 8001a20: fa02 f303 lsl.w r3, r2, r3 8001a24: 43db mvns r3, r3 8001a26: 693a ldr r2, [r7, #16] 8001a28: 4013 ands r3, r2 8001a2a: 613b str r3, [r7, #16] temp |= (GPIO_Init->Speed << (position * GPIO_OSPEEDR_OSPEED1_Pos)); 8001a2c: 683b ldr r3, [r7, #0] 8001a2e: 68da ldr r2, [r3, #12] 8001a30: 697b ldr r3, [r7, #20] 8001a32: 005b lsls r3, r3, #1 8001a34: fa02 f303 lsl.w r3, r2, r3 8001a38: 693a ldr r2, [r7, #16] 8001a3a: 4313 orrs r3, r2 8001a3c: 613b str r3, [r7, #16] GPIOx->OSPEEDR = temp; 8001a3e: 687b ldr r3, [r7, #4] 8001a40: 693a ldr r2, [r7, #16] 8001a42: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8001a44: 687b ldr r3, [r7, #4] 8001a46: 685b ldr r3, [r3, #4] 8001a48: 613b str r3, [r7, #16] temp &= ~(GPIO_OTYPER_OT0 << position) ; 8001a4a: 2201 movs r2, #1 8001a4c: 697b ldr r3, [r7, #20] 8001a4e: fa02 f303 lsl.w r3, r2, r3 8001a52: 43db mvns r3, r3 8001a54: 693a ldr r2, [r7, #16] 8001a56: 4013 ands r3, r2 8001a58: 613b str r3, [r7, #16] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8001a5a: 683b ldr r3, [r7, #0] 8001a5c: 685b ldr r3, [r3, #4] 8001a5e: 091b lsrs r3, r3, #4 8001a60: f003 0201 and.w r2, r3, #1 8001a64: 697b ldr r3, [r7, #20] 8001a66: fa02 f303 lsl.w r3, r2, r3 8001a6a: 693a ldr r2, [r7, #16] 8001a6c: 4313 orrs r3, r2 8001a6e: 613b str r3, [r7, #16] GPIOx->OTYPER = temp; 8001a70: 687b ldr r3, [r7, #4] 8001a72: 693a ldr r2, [r7, #16] 8001a74: 605a str r2, [r3, #4] } if (((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) || 8001a76: 683b ldr r3, [r7, #0] 8001a78: 685b ldr r3, [r3, #4] 8001a7a: f003 0303 and.w r3, r3, #3 8001a7e: 2b03 cmp r3, #3 8001a80: d109 bne.n 8001a96 (((GPIO_Init->Mode & GPIO_MODE) == MODE_ANALOG) && (GPIO_Init->Pull != GPIO_PULLUP))) 8001a82: 683b ldr r3, [r7, #0] 8001a84: 685b ldr r3, [r3, #4] 8001a86: f003 0303 and.w r3, r3, #3 if (((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) || 8001a8a: 2b03 cmp r3, #3 8001a8c: d11b bne.n 8001ac6 (((GPIO_Init->Mode & GPIO_MODE) == MODE_ANALOG) && (GPIO_Init->Pull != GPIO_PULLUP))) 8001a8e: 683b ldr r3, [r7, #0] 8001a90: 689b ldr r3, [r3, #8] 8001a92: 2b01 cmp r3, #1 8001a94: d017 beq.n 8001ac6 { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8001a96: 687b ldr r3, [r7, #4] 8001a98: 68db ldr r3, [r3, #12] 8001a9a: 613b str r3, [r7, #16] temp &= ~(GPIO_PUPDR_PUPD0 << (position * GPIO_PUPDR_PUPD1_Pos)); 8001a9c: 697b ldr r3, [r7, #20] 8001a9e: 005b lsls r3, r3, #1 8001aa0: 2203 movs r2, #3 8001aa2: fa02 f303 lsl.w r3, r2, r3 8001aa6: 43db mvns r3, r3 8001aa8: 693a ldr r2, [r7, #16] 8001aaa: 4013 ands r3, r2 8001aac: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Pull) << (position * GPIO_PUPDR_PUPD1_Pos)); 8001aae: 683b ldr r3, [r7, #0] 8001ab0: 689a ldr r2, [r3, #8] 8001ab2: 697b ldr r3, [r7, #20] 8001ab4: 005b lsls r3, r3, #1 8001ab6: fa02 f303 lsl.w r3, r2, r3 8001aba: 693a ldr r2, [r7, #16] 8001abc: 4313 orrs r3, r2 8001abe: 613b str r3, [r7, #16] GPIOx->PUPDR = temp; 8001ac0: 687b ldr r3, [r7, #4] 8001ac2: 693a ldr r2, [r7, #16] 8001ac4: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8001ac6: 683b ldr r3, [r7, #0] 8001ac8: 685b ldr r3, [r3, #4] 8001aca: f003 0303 and.w r3, r3, #3 8001ace: 2b02 cmp r3, #2 8001ad0: d123 bne.n 8001b1a /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 8001ad2: 697b ldr r3, [r7, #20] 8001ad4: 08da lsrs r2, r3, #3 8001ad6: 687b ldr r3, [r7, #4] 8001ad8: 3208 adds r2, #8 8001ada: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8001ade: 613b str r3, [r7, #16] temp &= ~(0xFuL << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)); 8001ae0: 697b ldr r3, [r7, #20] 8001ae2: f003 0307 and.w r3, r3, #7 8001ae6: 009b lsls r3, r3, #2 8001ae8: 220f movs r2, #15 8001aea: fa02 f303 lsl.w r3, r2, r3 8001aee: 43db mvns r3, r3 8001af0: 693a ldr r2, [r7, #16] 8001af2: 4013 ands r3, r2 8001af4: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)); 8001af6: 683b ldr r3, [r7, #0] 8001af8: 691a ldr r2, [r3, #16] 8001afa: 697b ldr r3, [r7, #20] 8001afc: f003 0307 and.w r3, r3, #7 8001b00: 009b lsls r3, r3, #2 8001b02: fa02 f303 lsl.w r3, r2, r3 8001b06: 693a ldr r2, [r7, #16] 8001b08: 4313 orrs r3, r2 8001b0a: 613b str r3, [r7, #16] GPIOx->AFR[position >> 3U] = temp; 8001b0c: 697b ldr r3, [r7, #20] 8001b0e: 08da lsrs r2, r3, #3 8001b10: 687b ldr r3, [r7, #4] 8001b12: 3208 adds r2, #8 8001b14: 6939 ldr r1, [r7, #16] 8001b16: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8001b1a: 687b ldr r3, [r7, #4] 8001b1c: 681b ldr r3, [r3, #0] 8001b1e: 613b str r3, [r7, #16] temp &= ~(GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos)); 8001b20: 697b ldr r3, [r7, #20] 8001b22: 005b lsls r3, r3, #1 8001b24: 2203 movs r2, #3 8001b26: fa02 f303 lsl.w r3, r2, r3 8001b2a: 43db mvns r3, r3 8001b2c: 693a ldr r2, [r7, #16] 8001b2e: 4013 ands r3, r2 8001b30: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * GPIO_MODER_MODE1_Pos)); 8001b32: 683b ldr r3, [r7, #0] 8001b34: 685b ldr r3, [r3, #4] 8001b36: f003 0203 and.w r2, r3, #3 8001b3a: 697b ldr r3, [r7, #20] 8001b3c: 005b lsls r3, r3, #1 8001b3e: fa02 f303 lsl.w r3, r2, r3 8001b42: 693a ldr r2, [r7, #16] 8001b44: 4313 orrs r3, r2 8001b46: 613b str r3, [r7, #16] GPIOx->MODER = temp; 8001b48: 687b ldr r3, [r7, #4] 8001b4a: 693a ldr r2, [r7, #16] 8001b4c: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 8001b4e: 683b ldr r3, [r7, #0] 8001b50: 685b ldr r3, [r3, #4] 8001b52: f403 3340 and.w r3, r3, #196608 @ 0x30000 8001b56: 2b00 cmp r3, #0 8001b58: f000 8085 beq.w 8001c66 { temp = SBS->EXTICR[position >> 2U]; 8001b5c: 4a4b ldr r2, [pc, #300] @ (8001c8c ) 8001b5e: 697b ldr r3, [r7, #20] 8001b60: 089b lsrs r3, r3, #2 8001b62: 334c adds r3, #76 @ 0x4c 8001b64: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8001b68: 613b str r3, [r7, #16] temp &= ~(0x0FuL << ((position & 0x03U) * SBS_EXTICR1_PC_EXTI1_Pos)); 8001b6a: 697b ldr r3, [r7, #20] 8001b6c: f003 0303 and.w r3, r3, #3 8001b70: 009b lsls r3, r3, #2 8001b72: 220f movs r2, #15 8001b74: fa02 f303 lsl.w r3, r2, r3 8001b78: 43db mvns r3, r3 8001b7a: 693a ldr r2, [r7, #16] 8001b7c: 4013 ands r3, r2 8001b7e: 613b str r3, [r7, #16] temp |= (GPIO_GET_INDEX(GPIOx) << ((position & 0x03U) * SBS_EXTICR1_PC_EXTI1_Pos)); 8001b80: 687b ldr r3, [r7, #4] 8001b82: 0a9a lsrs r2, r3, #10 8001b84: 4b42 ldr r3, [pc, #264] @ (8001c90 ) 8001b86: 4013 ands r3, r2 8001b88: 697a ldr r2, [r7, #20] 8001b8a: f002 0203 and.w r2, r2, #3 8001b8e: 0092 lsls r2, r2, #2 8001b90: 4093 lsls r3, r2 8001b92: 693a ldr r2, [r7, #16] 8001b94: 4313 orrs r3, r2 8001b96: 613b str r3, [r7, #16] SBS->EXTICR[position >> 2U] = temp; 8001b98: 493c ldr r1, [pc, #240] @ (8001c8c ) 8001b9a: 697b ldr r3, [r7, #20] 8001b9c: 089b lsrs r3, r3, #2 8001b9e: 334c adds r3, #76 @ 0x4c 8001ba0: 693a ldr r2, [r7, #16] 8001ba2: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 8001ba6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8001baa: 681b ldr r3, [r3, #0] 8001bac: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8001bae: 68fb ldr r3, [r7, #12] 8001bb0: 43db mvns r3, r3 8001bb2: 693a ldr r2, [r7, #16] 8001bb4: 4013 ands r3, r2 8001bb6: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 8001bb8: 683b ldr r3, [r7, #0] 8001bba: 685b ldr r3, [r3, #4] 8001bbc: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8001bc0: 2b00 cmp r3, #0 8001bc2: d003 beq.n 8001bcc { temp |= iocurrent; 8001bc4: 693a ldr r2, [r7, #16] 8001bc6: 68fb ldr r3, [r7, #12] 8001bc8: 4313 orrs r3, r2 8001bca: 613b str r3, [r7, #16] } EXTI->RTSR1 = temp; 8001bcc: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8001bd0: 693b ldr r3, [r7, #16] 8001bd2: 6013 str r3, [r2, #0] temp = EXTI->FTSR1; 8001bd4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8001bd8: 685b ldr r3, [r3, #4] 8001bda: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8001bdc: 68fb ldr r3, [r7, #12] 8001bde: 43db mvns r3, r3 8001be0: 693a ldr r2, [r7, #16] 8001be2: 4013 ands r3, r2 8001be4: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 8001be6: 683b ldr r3, [r7, #0] 8001be8: 685b ldr r3, [r3, #4] 8001bea: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8001bee: 2b00 cmp r3, #0 8001bf0: d003 beq.n 8001bfa { temp |= iocurrent; 8001bf2: 693a ldr r2, [r7, #16] 8001bf4: 68fb ldr r3, [r7, #12] 8001bf6: 4313 orrs r3, r2 8001bf8: 613b str r3, [r7, #16] } EXTI->FTSR1 = temp; 8001bfa: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8001bfe: 693b ldr r3, [r7, #16] 8001c00: 6053 str r3, [r2, #4] /* Clear EXTI line configuration */ temp = EXTI->EMR1; 8001c02: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8001c06: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8001c0a: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8001c0c: 68fb ldr r3, [r7, #12] 8001c0e: 43db mvns r3, r3 8001c10: 693a ldr r2, [r7, #16] 8001c12: 4013 ands r3, r2 8001c14: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 8001c16: 683b ldr r3, [r7, #0] 8001c18: 685b ldr r3, [r3, #4] 8001c1a: f403 3300 and.w r3, r3, #131072 @ 0x20000 8001c1e: 2b00 cmp r3, #0 8001c20: d003 beq.n 8001c2a { temp |= iocurrent; 8001c22: 693a ldr r2, [r7, #16] 8001c24: 68fb ldr r3, [r7, #12] 8001c26: 4313 orrs r3, r2 8001c28: 613b str r3, [r7, #16] } EXTI->EMR1 = temp; 8001c2a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8001c2e: 693b ldr r3, [r7, #16] 8001c30: f8c2 3084 str.w r3, [r2, #132] @ 0x84 temp = EXTI->IMR1; 8001c34: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8001c38: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8001c3c: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8001c3e: 68fb ldr r3, [r7, #12] 8001c40: 43db mvns r3, r3 8001c42: 693a ldr r2, [r7, #16] 8001c44: 4013 ands r3, r2 8001c46: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) 8001c48: 683b ldr r3, [r7, #0] 8001c4a: 685b ldr r3, [r3, #4] 8001c4c: f403 3380 and.w r3, r3, #65536 @ 0x10000 8001c50: 2b00 cmp r3, #0 8001c52: d003 beq.n 8001c5c { temp |= iocurrent; 8001c54: 693a ldr r2, [r7, #16] 8001c56: 68fb ldr r3, [r7, #12] 8001c58: 4313 orrs r3, r2 8001c5a: 613b str r3, [r7, #16] } EXTI->IMR1 = temp; 8001c5c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8001c60: 693b ldr r3, [r7, #16] 8001c62: f8c2 3080 str.w r3, [r2, #128] @ 0x80 } } position++; 8001c66: 697b ldr r3, [r7, #20] 8001c68: 3301 adds r3, #1 8001c6a: 617b str r3, [r7, #20] while (((GPIO_Init->Pin) >> position) != 0x00U) 8001c6c: 683b ldr r3, [r7, #0] 8001c6e: 681a ldr r2, [r3, #0] 8001c70: 697b ldr r3, [r7, #20] 8001c72: fa22 f303 lsr.w r3, r2, r3 8001c76: 2b00 cmp r3, #0 8001c78: f47f aeb4 bne.w 80019e4 } } 8001c7c: bf00 nop 8001c7e: bf00 nop 8001c80: 371c adds r7, #28 8001c82: 46bd mov sp, r7 8001c84: f85d 7b04 ldr.w r7, [sp], #4 8001c88: 4770 bx lr 8001c8a: bf00 nop 8001c8c: 58000400 .word 0x58000400 8001c90: 0029ff7f .word 0x0029ff7f 08001c94 : * @note After a system reset, the backup domain is protected against * possible unwanted write accesses. * @retval None. */ void HAL_PWR_EnableBkUpAccess(void) { 8001c94: b480 push {r7} 8001c96: af00 add r7, sp, #0 SET_BIT(PWR->CR1, PWR_CR1_DBP); 8001c98: 4b05 ldr r3, [pc, #20] @ (8001cb0 ) 8001c9a: 681b ldr r3, [r3, #0] 8001c9c: 4a04 ldr r2, [pc, #16] @ (8001cb0 ) 8001c9e: f443 7380 orr.w r3, r3, #256 @ 0x100 8001ca2: 6013 str r3, [r2, #0] } 8001ca4: bf00 nop 8001ca6: 46bd mov sp, r7 8001ca8: f85d 7b04 ldr.w r7, [sp], #4 8001cac: 4770 bx lr 8001cae: bf00 nop 8001cb0: 58024800 .word 0x58024800 08001cb4 : * PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO and PWR_SMPS_1V8_SUPPLIES_EXT are used * only for lines that supports SMPS regulator. * @retval HAL status. */ HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource) { 8001cb4: b580 push {r7, lr} 8001cb6: b084 sub sp, #16 8001cb8: af00 add r7, sp, #0 8001cba: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_PWR_SUPPLY(SupplySource)); /* Check if supply source was configured */ if ((PWR->CSR2 & (PWR_CSR2_SDEN | PWR_CSR2_LDOEN | PWR_CSR2_BYPASS)) != (PWR_CSR2_SDEN | PWR_CSR2_LDOEN)) 8001cbc: 4b25 ldr r3, [pc, #148] @ (8001d54 ) 8001cbe: 68db ldr r3, [r3, #12] 8001cc0: f003 0307 and.w r3, r3, #7 8001cc4: 2b06 cmp r3, #6 8001cc6: d00a beq.n 8001cde { /* Check supply configuration */ if ((PWR->CSR2 & PWR_SUPPLY_CONFIG_MASK) != SupplySource) 8001cc8: 4b22 ldr r3, [pc, #136] @ (8001d54 ) 8001cca: 68db ldr r3, [r3, #12] 8001ccc: f003 031f and.w r3, r3, #31 8001cd0: 687a ldr r2, [r7, #4] 8001cd2: 429a cmp r2, r3 8001cd4: d001 beq.n 8001cda { /* Supply configuration update locked, can't apply a new supply config */ return HAL_ERROR; 8001cd6: 2301 movs r3, #1 8001cd8: e038 b.n 8001d4c else { /* Supply configuration update locked, but new supply configuration matches with old supply configuration : nothing to do */ return HAL_OK; 8001cda: 2300 movs r3, #0 8001cdc: e036 b.n 8001d4c } } /* Set the power supply configuration */ MODIFY_REG(PWR->CSR2, PWR_SUPPLY_CONFIG_MASK, SupplySource); 8001cde: 4b1d ldr r3, [pc, #116] @ (8001d54 ) 8001ce0: 68db ldr r3, [r3, #12] 8001ce2: f023 021f bic.w r2, r3, #31 8001ce6: 491b ldr r1, [pc, #108] @ (8001d54 ) 8001ce8: 687b ldr r3, [r7, #4] 8001cea: 4313 orrs r3, r2 8001cec: 60cb str r3, [r1, #12] /* Get tick */ tickstart = HAL_GetTick(); 8001cee: f7fe ffff bl 8000cf0 8001cf2: 60f8 str r0, [r7, #12] /* Wait till voltage level flag is set */ while ((PWR->SR1 & PWR_SR1_ACTVOSRDY) == 0U) 8001cf4: e009 b.n 8001d0a { if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY) 8001cf6: f7fe fffb bl 8000cf0 8001cfa: 4602 mov r2, r0 8001cfc: 68fb ldr r3, [r7, #12] 8001cfe: 1ad3 subs r3, r2, r3 8001d00: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8001d04: d901 bls.n 8001d0a { return HAL_ERROR; 8001d06: 2301 movs r3, #1 8001d08: e020 b.n 8001d4c while ((PWR->SR1 & PWR_SR1_ACTVOSRDY) == 0U) 8001d0a: 4b12 ldr r3, [pc, #72] @ (8001d54 ) 8001d0c: 685b ldr r3, [r3, #4] 8001d0e: f003 0302 and.w r3, r3, #2 8001d12: 2b00 cmp r3, #0 8001d14: d0ef beq.n 8001cf6 } } /* When the SMPS supplies external circuits verify that SDEXTRDY flag is set */ if ((SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) || 8001d16: 687b ldr r3, [r7, #4] 8001d18: 2b1e cmp r3, #30 8001d1a: d002 beq.n 8001d22 8001d1c: 687b ldr r3, [r7, #4] 8001d1e: 2b1d cmp r3, #29 8001d20: d113 bne.n 8001d4a (SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT)) { /* Get the current tick number */ tickstart = HAL_GetTick(); 8001d22: f7fe ffe5 bl 8000cf0 8001d26: 60f8 str r0, [r7, #12] /* Wait till SMPS external supply ready flag is set */ while ((PWR->CSR2 & PWR_CSR2_SDEXTRDY) == 0U) 8001d28: e009 b.n 8001d3e { if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY) 8001d2a: f7fe ffe1 bl 8000cf0 8001d2e: 4602 mov r2, r0 8001d30: 68fb ldr r3, [r7, #12] 8001d32: 1ad3 subs r3, r2, r3 8001d34: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8001d38: d901 bls.n 8001d3e { return HAL_ERROR; 8001d3a: 2301 movs r3, #1 8001d3c: e006 b.n 8001d4c while ((PWR->CSR2 & PWR_CSR2_SDEXTRDY) == 0U) 8001d3e: 4b05 ldr r3, [pc, #20] @ (8001d54 ) 8001d40: 68db ldr r3, [r3, #12] 8001d42: f403 3380 and.w r3, r3, #65536 @ 0x10000 8001d46: 2b00 cmp r3, #0 8001d48: d0ef beq.n 8001d2a } } } return HAL_OK; 8001d4a: 2300 movs r3, #0 } 8001d4c: 4618 mov r0, r3 8001d4e: 3710 adds r7, #16 8001d50: 46bd mov sp, r7 8001d52: bd80 pop {r7, pc} 8001d54: 58024800 .word 0x58024800 08001d58 : * @note When exiting from Stop mode or Standby mode, the Run mode voltage * scaling is reset to the default VOS low value. * @retval HAL Status */ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) { 8001d58: b580 push {r7, lr} 8001d5a: b084 sub sp, #16 8001d5c: af00 add r7, sp, #0 8001d5e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_PWR_REGULATOR_VOLTAGE(VoltageScaling)); /* Set the voltage range */ MODIFY_REG(PWR->CSR4, PWR_CSR4_VOS, VoltageScaling); 8001d60: 4b10 ldr r3, [pc, #64] @ (8001da4 ) 8001d62: 695b ldr r3, [r3, #20] 8001d64: f023 0201 bic.w r2, r3, #1 8001d68: 490e ldr r1, [pc, #56] @ (8001da4 ) 8001d6a: 687b ldr r3, [r7, #4] 8001d6c: 4313 orrs r3, r2 8001d6e: 614b str r3, [r1, #20] /* Get tick */ tickstart = HAL_GetTick(); 8001d70: f7fe ffbe bl 8000cf0 8001d74: 60f8 str r0, [r7, #12] /* Wait till voltage level flag is set */ while ((PWR->CSR4 & PWR_CSR4_VOSRDY) == 0U) 8001d76: e009 b.n 8001d8c { if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY) 8001d78: f7fe ffba bl 8000cf0 8001d7c: 4602 mov r2, r0 8001d7e: 68fb ldr r3, [r7, #12] 8001d80: 1ad3 subs r3, r2, r3 8001d82: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8001d86: d901 bls.n 8001d8c { return HAL_ERROR; 8001d88: 2301 movs r3, #1 8001d8a: e006 b.n 8001d9a while ((PWR->CSR4 & PWR_CSR4_VOSRDY) == 0U) 8001d8c: 4b05 ldr r3, [pc, #20] @ (8001da4 ) 8001d8e: 695b ldr r3, [r3, #20] 8001d90: f003 0302 and.w r3, r3, #2 8001d94: 2b00 cmp r3, #0 8001d96: d0ef beq.n 8001d78 } } return HAL_OK; 8001d98: 2300 movs r3, #0 } 8001d9a: 4618 mov r0, r3 8001d9c: 3710 adds r7, #16 8001d9e: 46bd mov sp, r7 8001da0: bd80 pop {r7, pc} 8001da2: bf00 nop 8001da4: 58024800 .word 0x58024800 08001da8 : * @note The XSPIM_P1 supply must be stable prior to setting this bit. * @retval None. */ void HAL_PWREx_EnableXSPIM1(void) { 8001da8: b480 push {r7} 8001daa: af00 add r7, sp, #0 SET_BIT(PWR->CSR2, PWR_CSR2_EN_XSPIM1); 8001dac: 4b05 ldr r3, [pc, #20] @ (8001dc4 ) 8001dae: 68db ldr r3, [r3, #12] 8001db0: 4a04 ldr r2, [pc, #16] @ (8001dc4 ) 8001db2: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8001db6: 60d3 str r3, [r2, #12] } 8001db8: bf00 nop 8001dba: 46bd mov sp, r7 8001dbc: f85d 7b04 ldr.w r7, [sp], #4 8001dc0: 4770 bx lr 8001dc2: bf00 nop 8001dc4: 58024800 .word 0x58024800 08001dc8 : * @note The XSPIM_P2 supply must be stable prior to setting this bit. * @retval None. */ void HAL_PWREx_EnableXSPIM2(void) { 8001dc8: b480 push {r7} 8001dca: af00 add r7, sp, #0 SET_BIT(PWR->CSR2, PWR_CSR2_EN_XSPIM2); 8001dcc: 4b05 ldr r3, [pc, #20] @ (8001de4 ) 8001dce: 68db ldr r3, [r3, #12] 8001dd0: 4a04 ldr r2, [pc, #16] @ (8001de4 ) 8001dd2: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8001dd6: 60d3 str r3, [r2, #12] } 8001dd8: bf00 nop 8001dda: 46bd mov sp, r7 8001ddc: f85d 7b04 ldr.w r7, [sp], #4 8001de0: 4770 bx lr 8001de2: bf00 nop 8001de4: 58024800 .word 0x58024800 08001de8 : * supported by this function. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8001de8: b580 push {r7, lr} 8001dea: b088 sub sp, #32 8001dec: af00 add r7, sp, #0 8001dee: 6078 str r0, [r7, #4] uint32_t pllsrc; uint32_t pllrdy; uint32_t tmpreg1; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8001df0: 687b ldr r3, [r7, #4] 8001df2: 2b00 cmp r3, #0 8001df4: d101 bne.n 8001dfa { return HAL_ERROR; 8001df6: 2301 movs r3, #1 8001df8: e328 b.n 800244c } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8001dfa: 4b97 ldr r3, [pc, #604] @ (8002058 ) 8001dfc: 691b ldr r3, [r3, #16] 8001dfe: f003 0338 and.w r3, r3, #56 @ 0x38 8001e02: 61fb str r3, [r7, #28] pllsrc = __HAL_RCC_GET_PLL_OSCSOURCE(); 8001e04: 4b94 ldr r3, [pc, #592] @ (8002058 ) 8001e06: 6a9b ldr r3, [r3, #40] @ 0x28 8001e08: f003 0303 and.w r3, r3, #3 8001e0c: 61bb str r3, [r7, #24] pllrdy = RCC->CR & (RCC_CR_PLL1RDY | RCC_CR_PLL2RDY | RCC_CR_PLL3RDY); 8001e0e: 4b92 ldr r3, [pc, #584] @ (8002058 ) 8001e10: 681b ldr r3, [r3, #0] 8001e12: f003 5328 and.w r3, r3, #704643072 @ 0x2a000000 8001e16: 617b str r3, [r7, #20] /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8001e18: 687b ldr r3, [r7, #4] 8001e1a: 681b ldr r3, [r3, #0] 8001e1c: f003 0301 and.w r3, r3, #1 8001e20: 2b00 cmp r3, #0 8001e22: f000 809c beq.w 8001f5e { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ if ((sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE) || 8001e26: 69fb ldr r3, [r7, #28] 8001e28: 2b10 cmp r3, #16 8001e2a: d005 beq.n 8001e38 8001e2c: 697b ldr r3, [r7, #20] 8001e2e: 2b00 cmp r3, #0 8001e30: d009 beq.n 8001e46 ((pllrdy != 0U) && (pllsrc == RCC_PLLSOURCE_HSE))) 8001e32: 69bb ldr r3, [r7, #24] 8001e34: 2b02 cmp r3, #2 8001e36: d106 bne.n 8001e46 { if (RCC_OscInitStruct->HSEState == RCC_HSE_OFF) 8001e38: 687b ldr r3, [r7, #4] 8001e3a: 685b ldr r3, [r3, #4] 8001e3c: 2b00 cmp r3, #0 8001e3e: f040 808e bne.w 8001f5e { return HAL_ERROR; 8001e42: 2301 movs r3, #1 8001e44: e302 b.n 800244c } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8001e46: 687b ldr r3, [r7, #4] 8001e48: 685b ldr r3, [r3, #4] 8001e4a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8001e4e: d106 bne.n 8001e5e 8001e50: 4b81 ldr r3, [pc, #516] @ (8002058 ) 8001e52: 681b ldr r3, [r3, #0] 8001e54: 4a80 ldr r2, [pc, #512] @ (8002058 ) 8001e56: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8001e5a: 6013 str r3, [r2, #0] 8001e5c: e058 b.n 8001f10 8001e5e: 687b ldr r3, [r7, #4] 8001e60: 685b ldr r3, [r3, #4] 8001e62: 2b00 cmp r3, #0 8001e64: d112 bne.n 8001e8c 8001e66: 4b7c ldr r3, [pc, #496] @ (8002058 ) 8001e68: 681b ldr r3, [r3, #0] 8001e6a: 4a7b ldr r2, [pc, #492] @ (8002058 ) 8001e6c: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8001e70: 6013 str r3, [r2, #0] 8001e72: 4b79 ldr r3, [pc, #484] @ (8002058 ) 8001e74: 681b ldr r3, [r3, #0] 8001e76: 4a78 ldr r2, [pc, #480] @ (8002058 ) 8001e78: f423 2300 bic.w r3, r3, #524288 @ 0x80000 8001e7c: 6013 str r3, [r2, #0] 8001e7e: 4b76 ldr r3, [pc, #472] @ (8002058 ) 8001e80: 681b ldr r3, [r3, #0] 8001e82: 4a75 ldr r2, [pc, #468] @ (8002058 ) 8001e84: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8001e88: 6013 str r3, [r2, #0] 8001e8a: e041 b.n 8001f10 8001e8c: 687b ldr r3, [r7, #4] 8001e8e: 685b ldr r3, [r3, #4] 8001e90: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8001e94: d112 bne.n 8001ebc 8001e96: 4b70 ldr r3, [pc, #448] @ (8002058 ) 8001e98: 681b ldr r3, [r3, #0] 8001e9a: 4a6f ldr r2, [pc, #444] @ (8002058 ) 8001e9c: f443 2380 orr.w r3, r3, #262144 @ 0x40000 8001ea0: 6013 str r3, [r2, #0] 8001ea2: 4b6d ldr r3, [pc, #436] @ (8002058 ) 8001ea4: 681b ldr r3, [r3, #0] 8001ea6: 4a6c ldr r2, [pc, #432] @ (8002058 ) 8001ea8: f423 2300 bic.w r3, r3, #524288 @ 0x80000 8001eac: 6013 str r3, [r2, #0] 8001eae: 4b6a ldr r3, [pc, #424] @ (8002058 ) 8001eb0: 681b ldr r3, [r3, #0] 8001eb2: 4a69 ldr r2, [pc, #420] @ (8002058 ) 8001eb4: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8001eb8: 6013 str r3, [r2, #0] 8001eba: e029 b.n 8001f10 8001ebc: 687b ldr r3, [r7, #4] 8001ebe: 685b ldr r3, [r3, #4] 8001ec0: f5b3 2f50 cmp.w r3, #851968 @ 0xd0000 8001ec4: d112 bne.n 8001eec 8001ec6: 4b64 ldr r3, [pc, #400] @ (8002058 ) 8001ec8: 681b ldr r3, [r3, #0] 8001eca: 4a63 ldr r2, [pc, #396] @ (8002058 ) 8001ecc: f443 2380 orr.w r3, r3, #262144 @ 0x40000 8001ed0: 6013 str r3, [r2, #0] 8001ed2: 4b61 ldr r3, [pc, #388] @ (8002058 ) 8001ed4: 681b ldr r3, [r3, #0] 8001ed6: 4a60 ldr r2, [pc, #384] @ (8002058 ) 8001ed8: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8001edc: 6013 str r3, [r2, #0] 8001ede: 4b5e ldr r3, [pc, #376] @ (8002058 ) 8001ee0: 681b ldr r3, [r3, #0] 8001ee2: 4a5d ldr r2, [pc, #372] @ (8002058 ) 8001ee4: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8001ee8: 6013 str r3, [r2, #0] 8001eea: e011 b.n 8001f10 8001eec: 4b5a ldr r3, [pc, #360] @ (8002058 ) 8001eee: 681b ldr r3, [r3, #0] 8001ef0: 4a59 ldr r2, [pc, #356] @ (8002058 ) 8001ef2: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8001ef6: 6013 str r3, [r2, #0] 8001ef8: 4b57 ldr r3, [pc, #348] @ (8002058 ) 8001efa: 681b ldr r3, [r3, #0] 8001efc: 4a56 ldr r2, [pc, #344] @ (8002058 ) 8001efe: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8001f02: 6013 str r3, [r2, #0] 8001f04: 4b54 ldr r3, [pc, #336] @ (8002058 ) 8001f06: 681b ldr r3, [r3, #0] 8001f08: 4a53 ldr r2, [pc, #332] @ (8002058 ) 8001f0a: f423 2300 bic.w r3, r3, #524288 @ 0x80000 8001f0e: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8001f10: f7fe feee bl 8000cf0 8001f14: 6138 str r0, [r7, #16] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8001f16: 687b ldr r3, [r7, #4] 8001f18: 685b ldr r3, [r3, #4] 8001f1a: 2b00 cmp r3, #0 8001f1c: d019 beq.n 8001f52 { /* Wait till HSE is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 8001f1e: e008 b.n 8001f32 { if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE) 8001f20: f7fe fee6 bl 8000cf0 8001f24: 4602 mov r2, r0 8001f26: 693b ldr r3, [r7, #16] 8001f28: 1ad3 subs r3, r2, r3 8001f2a: 2b64 cmp r3, #100 @ 0x64 8001f2c: d901 bls.n 8001f32 { return HAL_TIMEOUT; 8001f2e: 2303 movs r3, #3 8001f30: e28c b.n 800244c while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 8001f32: 4b49 ldr r3, [pc, #292] @ (8002058 ) 8001f34: 681b ldr r3, [r3, #0] 8001f36: f403 3300 and.w r3, r3, #131072 @ 0x20000 8001f3a: 2b00 cmp r3, #0 8001f3c: d0f0 beq.n 8001f20 8001f3e: e00e b.n 8001f5e else { /* Wait till HSE is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) { if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE) 8001f40: f7fe fed6 bl 8000cf0 8001f44: 4602 mov r2, r0 8001f46: 693b ldr r3, [r7, #16] 8001f48: 1ad3 subs r3, r2, r3 8001f4a: 2b64 cmp r3, #100 @ 0x64 8001f4c: d901 bls.n 8001f52 { return HAL_TIMEOUT; 8001f4e: 2303 movs r3, #3 8001f50: e27c b.n 800244c while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 8001f52: 4b41 ldr r3, [pc, #260] @ (8002058 ) 8001f54: 681b ldr r3, [r3, #0] 8001f56: f403 3300 and.w r3, r3, #131072 @ 0x20000 8001f5a: 2b00 cmp r3, #0 8001f5c: d1f0 bne.n 8001f40 } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8001f5e: 687b ldr r3, [r7, #4] 8001f60: 681b ldr r3, [r3, #0] 8001f62: f003 0302 and.w r3, r3, #2 8001f66: 2b00 cmp r3, #0 8001f68: f000 809e beq.w 80020a8 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL1 source when PLL1 is selected as system clock */ if ((sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI) || 8001f6c: 69fb ldr r3, [r7, #28] 8001f6e: 2b00 cmp r3, #0 8001f70: d005 beq.n 8001f7e 8001f72: 697b ldr r3, [r7, #20] 8001f74: 2b00 cmp r3, #0 8001f76: d047 beq.n 8002008 ((pllrdy != 0U) && (pllsrc == RCC_PLLSOURCE_HSI))) 8001f78: 69bb ldr r3, [r7, #24] 8001f7a: 2b00 cmp r3, #0 8001f7c: d144 bne.n 8002008 { /* When HSI is used as system clock it will not be disabled */ if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF) 8001f7e: 687b ldr r3, [r7, #4] 8001f80: 68db ldr r3, [r3, #12] 8001f82: 2b00 cmp r3, #0 8001f84: d101 bne.n 8001f8a { return HAL_ERROR; 8001f86: 2301 movs r3, #1 8001f88: e260 b.n 800244c } /* Otherwise, calibration is allowed, divider update also unless used for any enabled PLL */ else { /* HSI must not be used as reference clock for any enabled PLL clock source */ tmpreg1 = (RCC->CR & RCC_CR_HSIDIV); 8001f8a: 4b33 ldr r3, [pc, #204] @ (8002058 ) 8001f8c: 681b ldr r3, [r3, #0] 8001f8e: f003 0318 and.w r3, r3, #24 8001f92: 60fb str r3, [r7, #12] if ((pllsrc == RCC_PLLSOURCE_HSI) && (pllrdy != 0U) && \ 8001f94: 69bb ldr r3, [r7, #24] 8001f96: 2b00 cmp r3, #0 8001f98: d109 bne.n 8001fae 8001f9a: 697b ldr r3, [r7, #20] 8001f9c: 2b00 cmp r3, #0 8001f9e: d006 beq.n 8001fae (tmpreg1 != RCC_OscInitStruct->HSIDiv)) 8001fa0: 687b ldr r3, [r7, #4] 8001fa2: 691b ldr r3, [r3, #16] if ((pllsrc == RCC_PLLSOURCE_HSI) && (pllrdy != 0U) && \ 8001fa4: 68fa ldr r2, [r7, #12] 8001fa6: 429a cmp r2, r3 8001fa8: d001 beq.n 8001fae { return HAL_ERROR; 8001faa: 2301 movs r3, #1 8001fac: e24e b.n 800244c } assert_param(IS_RCC_HSIDIV(RCC_OscInitStruct->HSIDiv)); /* Set the Internal High Speed oscillator new divider */ __HAL_RCC_HSI_CONFIG(RCC_HSI_ON | RCC_OscInitStruct->HSIDiv); 8001fae: 4b2a ldr r3, [pc, #168] @ (8002058 ) 8001fb0: 681b ldr r3, [r3, #0] 8001fb2: f023 0219 bic.w r2, r3, #25 8001fb6: 687b ldr r3, [r7, #4] 8001fb8: 691b ldr r3, [r3, #16] 8001fba: 4313 orrs r3, r2 8001fbc: 4a26 ldr r2, [pc, #152] @ (8002058 ) 8001fbe: f043 0301 orr.w r3, r3, #1 8001fc2: 6013 str r3, [r2, #0] if (sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI) 8001fc4: 69fb ldr r3, [r7, #28] 8001fc6: 2b00 cmp r3, #0 8001fc8: d109 bne.n 8001fde { SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos))); 8001fca: 4b23 ldr r3, [pc, #140] @ (8002058 ) 8001fcc: 681b ldr r3, [r3, #0] 8001fce: 08db lsrs r3, r3, #3 8001fd0: f003 0303 and.w r3, r3, #3 8001fd4: 4a21 ldr r2, [pc, #132] @ (800205c ) 8001fd6: fa22 f303 lsr.w r3, r2, r3 8001fda: 4a21 ldr r2, [pc, #132] @ (8002060 ) 8001fdc: 6013 str r3, [r2, #0] } /* Adapt Systick interrupt period */ if (HAL_InitTick(uwTickPrio) != HAL_OK) 8001fde: 4b21 ldr r3, [pc, #132] @ (8002064 ) 8001fe0: 681b ldr r3, [r3, #0] 8001fe2: 4618 mov r0, r3 8001fe4: f7fe fe34 bl 8000c50 8001fe8: 4603 mov r3, r0 8001fea: 2b00 cmp r3, #0 8001fec: d001 beq.n 8001ff2 { return HAL_ERROR; 8001fee: 2301 movs r3, #1 8001ff0: e22c b.n 800244c } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8001ff2: 4b19 ldr r3, [pc, #100] @ (8002058 ) 8001ff4: 685b ldr r3, [r3, #4] 8001ff6: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 8001ffa: 687b ldr r3, [r7, #4] 8001ffc: 695b ldr r3, [r3, #20] 8001ffe: 061b lsls r3, r3, #24 8002000: 4915 ldr r1, [pc, #84] @ (8002058 ) 8002002: 4313 orrs r3, r2 8002004: 604b str r3, [r1, #4] 8002006: e04f b.n 80020a8 } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8002008: 687b ldr r3, [r7, #4] 800200a: 68db ldr r3, [r3, #12] 800200c: 2b00 cmp r3, #0 800200e: d032 beq.n 8002076 { /* Enable the Internal High Speed oscillator */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState | RCC_OscInitStruct->HSIDiv); 8002010: 4b11 ldr r3, [pc, #68] @ (8002058 ) 8002012: 681b ldr r3, [r3, #0] 8002014: f023 0219 bic.w r2, r3, #25 8002018: 687b ldr r3, [r7, #4] 800201a: 68d9 ldr r1, [r3, #12] 800201c: 687b ldr r3, [r7, #4] 800201e: 691b ldr r3, [r3, #16] 8002020: 430b orrs r3, r1 8002022: 490d ldr r1, [pc, #52] @ (8002058 ) 8002024: 4313 orrs r3, r2 8002026: 600b str r3, [r1, #0] /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8002028: 4b0b ldr r3, [pc, #44] @ (8002058 ) 800202a: 685b ldr r3, [r3, #4] 800202c: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 8002030: 687b ldr r3, [r7, #4] 8002032: 695b ldr r3, [r3, #20] 8002034: 061b lsls r3, r3, #24 8002036: 4908 ldr r1, [pc, #32] @ (8002058 ) 8002038: 4313 orrs r3, r2 800203a: 604b str r3, [r1, #4] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800203c: f7fe fe58 bl 8000cf0 8002040: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8002042: e011 b.n 8002068 { if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE) 8002044: f7fe fe54 bl 8000cf0 8002048: 4602 mov r2, r0 800204a: 693b ldr r3, [r7, #16] 800204c: 1ad3 subs r3, r2, r3 800204e: 2b01 cmp r3, #1 8002050: d90a bls.n 8002068 { return HAL_TIMEOUT; 8002052: 2303 movs r3, #3 8002054: e1fa b.n 800244c 8002056: bf00 nop 8002058: 58024400 .word 0x58024400 800205c: 03d09000 .word 0x03d09000 8002060: 24000000 .word 0x24000000 8002064: 24000004 .word 0x24000004 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8002068: 4b95 ldr r3, [pc, #596] @ (80022c0 ) 800206a: 681b ldr r3, [r3, #0] 800206c: f003 0304 and.w r3, r3, #4 8002070: 2b00 cmp r3, #0 8002072: d0e7 beq.n 8002044 8002074: e018 b.n 80020a8 } } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8002076: 4b92 ldr r3, [pc, #584] @ (80022c0 ) 8002078: 681b ldr r3, [r3, #0] 800207a: 4a91 ldr r2, [pc, #580] @ (80022c0 ) 800207c: f023 0301 bic.w r3, r3, #1 8002080: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002082: f7fe fe35 bl 8000cf0 8002086: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 8002088: e008 b.n 800209c { if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE) 800208a: f7fe fe31 bl 8000cf0 800208e: 4602 mov r2, r0 8002090: 693b ldr r3, [r7, #16] 8002092: 1ad3 subs r3, r2, r3 8002094: 2b01 cmp r3, #1 8002096: d901 bls.n 800209c { return HAL_TIMEOUT; 8002098: 2303 movs r3, #3 800209a: e1d7 b.n 800244c while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 800209c: 4b88 ldr r3, [pc, #544] @ (80022c0 ) 800209e: 681b ldr r3, [r3, #0] 80020a0: f003 0304 and.w r3, r3, #4 80020a4: 2b00 cmp r3, #0 80020a6: d1f0 bne.n 800208a } } } } /*----------------------------- CSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) 80020a8: 687b ldr r3, [r7, #4] 80020aa: 681b ldr r3, [r3, #0] 80020ac: f003 0310 and.w r3, r3, #16 80020b0: 2b00 cmp r3, #0 80020b2: d045 beq.n 8002140 { /* Check the parameters */ assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState)); /* When the CSI is used as system clock it will not disabled */ if ((sysclksrc == RCC_SYSCLKSOURCE_STATUS_CSI) || 80020b4: 69fb ldr r3, [r7, #28] 80020b6: 2b08 cmp r3, #8 80020b8: d005 beq.n 80020c6 80020ba: 697b ldr r3, [r7, #20] 80020bc: 2b00 cmp r3, #0 80020be: d008 beq.n 80020d2 ((pllrdy != 0U) && (pllsrc == RCC_PLLSOURCE_CSI))) 80020c0: 69bb ldr r3, [r7, #24] 80020c2: 2b01 cmp r3, #1 80020c4: d105 bne.n 80020d2 { /* When CSI is used as system clock it will not disabled */ if (RCC_OscInitStruct->CSIState == RCC_CSI_OFF) 80020c6: 687b ldr r3, [r7, #4] 80020c8: 6a1b ldr r3, [r3, #32] 80020ca: 2b00 cmp r3, #0 80020cc: d138 bne.n 8002140 { return HAL_ERROR; 80020ce: 2301 movs r3, #1 80020d0: e1bc b.n 800244c } } else { /* Check the CSI State */ if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF) 80020d2: 687b ldr r3, [r7, #4] 80020d4: 6a1b ldr r3, [r3, #32] 80020d6: 2b00 cmp r3, #0 80020d8: d019 beq.n 800210e { /* Enable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_ENABLE(); 80020da: 4b79 ldr r3, [pc, #484] @ (80022c0 ) 80020dc: 681b ldr r3, [r3, #0] 80020de: 4a78 ldr r2, [pc, #480] @ (80022c0 ) 80020e0: f043 0380 orr.w r3, r3, #128 @ 0x80 80020e4: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80020e6: f7fe fe03 bl 8000cf0 80020ea: 6138 str r0, [r7, #16] /* Wait till CSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_CSIRDY) == 0U) 80020ec: e008 b.n 8002100 { if ((HAL_GetTick() - tickstart) > RCC_CSI_TIMEOUT_VALUE) 80020ee: f7fe fdff bl 8000cf0 80020f2: 4602 mov r2, r0 80020f4: 693b ldr r3, [r7, #16] 80020f6: 1ad3 subs r3, r2, r3 80020f8: 2b01 cmp r3, #1 80020fa: d901 bls.n 8002100 { return HAL_TIMEOUT; 80020fc: 2303 movs r3, #3 80020fe: e1a5 b.n 800244c while (READ_BIT(RCC->CR, RCC_CR_CSIRDY) == 0U) 8002100: 4b6f ldr r3, [pc, #444] @ (80022c0 ) 8002102: 681b ldr r3, [r3, #0] 8002104: f403 7380 and.w r3, r3, #256 @ 0x100 8002108: 2b00 cmp r3, #0 800210a: d0f0 beq.n 80020ee 800210c: e018 b.n 8002140 } } else { /* Disable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_DISABLE(); 800210e: 4b6c ldr r3, [pc, #432] @ (80022c0 ) 8002110: 681b ldr r3, [r3, #0] 8002112: 4a6b ldr r2, [pc, #428] @ (80022c0 ) 8002114: f023 0380 bic.w r3, r3, #128 @ 0x80 8002118: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800211a: f7fe fde9 bl 8000cf0 800211e: 6138 str r0, [r7, #16] /* Wait till CSI is disabled */ while (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U) 8002120: e008 b.n 8002134 { if ((HAL_GetTick() - tickstart) > RCC_CSI_TIMEOUT_VALUE) 8002122: f7fe fde5 bl 8000cf0 8002126: 4602 mov r2, r0 8002128: 693b ldr r3, [r7, #16] 800212a: 1ad3 subs r3, r2, r3 800212c: 2b01 cmp r3, #1 800212e: d901 bls.n 8002134 { return HAL_TIMEOUT; 8002130: 2303 movs r3, #3 8002132: e18b b.n 800244c while (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U) 8002134: 4b62 ldr r3, [pc, #392] @ (80022c0 ) 8002136: 681b ldr r3, [r3, #0] 8002138: f403 7380 and.w r3, r3, #256 @ 0x100 800213c: 2b00 cmp r3, #0 800213e: d1f0 bne.n 8002122 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8002140: 687b ldr r3, [r7, #4] 8002142: 681b ldr r3, [r3, #0] 8002144: f003 0308 and.w r3, r3, #8 8002148: 2b00 cmp r3, #0 800214a: d036 beq.n 80021ba { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) 800214c: 687b ldr r3, [r7, #4] 800214e: 699b ldr r3, [r3, #24] 8002150: 2b00 cmp r3, #0 8002152: d019 beq.n 8002188 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8002154: 4b5a ldr r3, [pc, #360] @ (80022c0 ) 8002156: 6f5b ldr r3, [r3, #116] @ 0x74 8002158: 4a59 ldr r2, [pc, #356] @ (80022c0 ) 800215a: f043 0301 orr.w r3, r3, #1 800215e: 6753 str r3, [r2, #116] @ 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002160: f7fe fdc6 bl 8000cf0 8002164: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) 8002166: e008 b.n 800217a { if ((HAL_GetTick() - tickstart) > RCC_LSI_TIMEOUT_VALUE) 8002168: f7fe fdc2 bl 8000cf0 800216c: 4602 mov r2, r0 800216e: 693b ldr r3, [r7, #16] 8002170: 1ad3 subs r3, r2, r3 8002172: 2b01 cmp r3, #1 8002174: d901 bls.n 800217a { return HAL_TIMEOUT; 8002176: 2303 movs r3, #3 8002178: e168 b.n 800244c while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) 800217a: 4b51 ldr r3, [pc, #324] @ (80022c0 ) 800217c: 6f5b ldr r3, [r3, #116] @ 0x74 800217e: f003 0302 and.w r3, r3, #2 8002182: 2b00 cmp r3, #0 8002184: d0f0 beq.n 8002168 8002186: e018 b.n 80021ba } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8002188: 4b4d ldr r3, [pc, #308] @ (80022c0 ) 800218a: 6f5b ldr r3, [r3, #116] @ 0x74 800218c: 4a4c ldr r2, [pc, #304] @ (80022c0 ) 800218e: f023 0301 bic.w r3, r3, #1 8002192: 6753 str r3, [r2, #116] @ 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002194: f7fe fdac bl 8000cf0 8002198: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) 800219a: e008 b.n 80021ae { if ((HAL_GetTick() - tickstart) > RCC_LSI_TIMEOUT_VALUE) 800219c: f7fe fda8 bl 8000cf0 80021a0: 4602 mov r2, r0 80021a2: 693b ldr r3, [r7, #16] 80021a4: 1ad3 subs r3, r2, r3 80021a6: 2b01 cmp r3, #1 80021a8: d901 bls.n 80021ae { return HAL_TIMEOUT; 80021aa: 2303 movs r3, #3 80021ac: e14e b.n 800244c while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) 80021ae: 4b44 ldr r3, [pc, #272] @ (80022c0 ) 80021b0: 6f5b ldr r3, [r3, #116] @ 0x74 80021b2: f003 0302 and.w r3, r3, #2 80021b6: 2b00 cmp r3, #0 80021b8: d1f0 bne.n 800219c } } } /*------------------------------ HSI48 Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) 80021ba: 687b ldr r3, [r7, #4] 80021bc: 681b ldr r3, [r3, #0] 80021be: f003 0320 and.w r3, r3, #32 80021c2: 2b00 cmp r3, #0 80021c4: d036 beq.n 8002234 { /* Check the parameters */ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); /* Check the HSI48 State */ if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF) 80021c6: 687b ldr r3, [r7, #4] 80021c8: 69db ldr r3, [r3, #28] 80021ca: 2b00 cmp r3, #0 80021cc: d019 beq.n 8002202 { /* Enable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_ENABLE(); 80021ce: 4b3c ldr r3, [pc, #240] @ (80022c0 ) 80021d0: 681b ldr r3, [r3, #0] 80021d2: 4a3b ldr r2, [pc, #236] @ (80022c0 ) 80021d4: f443 5380 orr.w r3, r3, #4096 @ 0x1000 80021d8: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 80021da: f7fe fd89 bl 8000cf0 80021de: 6138 str r0, [r7, #16] /* Wait till HSI48 is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == 0U) 80021e0: e008 b.n 80021f4 { if ((HAL_GetTick() - tickstart) > RCC_HSI48_TIMEOUT_VALUE) 80021e2: f7fe fd85 bl 8000cf0 80021e6: 4602 mov r2, r0 80021e8: 693b ldr r3, [r7, #16] 80021ea: 1ad3 subs r3, r2, r3 80021ec: 2b01 cmp r3, #1 80021ee: d901 bls.n 80021f4 { return HAL_TIMEOUT; 80021f0: 2303 movs r3, #3 80021f2: e12b b.n 800244c while (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == 0U) 80021f4: 4b32 ldr r3, [pc, #200] @ (80022c0 ) 80021f6: 681b ldr r3, [r3, #0] 80021f8: f403 5300 and.w r3, r3, #8192 @ 0x2000 80021fc: 2b00 cmp r3, #0 80021fe: d0f0 beq.n 80021e2 8002200: e018 b.n 8002234 } } else { /* Disable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_DISABLE(); 8002202: 4b2f ldr r3, [pc, #188] @ (80022c0 ) 8002204: 681b ldr r3, [r3, #0] 8002206: 4a2e ldr r2, [pc, #184] @ (80022c0 ) 8002208: f423 5380 bic.w r3, r3, #4096 @ 0x1000 800220c: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 800220e: f7fe fd6f bl 8000cf0 8002212: 6138 str r0, [r7, #16] /* Wait till HSI48 is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) != 0U) 8002214: e008 b.n 8002228 { if ((HAL_GetTick() - tickstart) > RCC_HSI48_TIMEOUT_VALUE) 8002216: f7fe fd6b bl 8000cf0 800221a: 4602 mov r2, r0 800221c: 693b ldr r3, [r7, #16] 800221e: 1ad3 subs r3, r2, r3 8002220: 2b01 cmp r3, #1 8002222: d901 bls.n 8002228 { return HAL_TIMEOUT; 8002224: 2303 movs r3, #3 8002226: e111 b.n 800244c while (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) != 0U) 8002228: 4b25 ldr r3, [pc, #148] @ (80022c0 ) 800222a: 681b ldr r3, [r3, #0] 800222c: f403 5300 and.w r3, r3, #8192 @ 0x2000 8002230: 2b00 cmp r3, #0 8002232: d1f0 bne.n 8002216 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8002234: 687b ldr r3, [r7, #4] 8002236: 681b ldr r3, [r3, #0] 8002238: f003 0304 and.w r3, r3, #4 800223c: 2b00 cmp r3, #0 800223e: f000 809b beq.w 8002378 { /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Enable write access to Backup domain */ PWR->CR1 |= PWR_CR1_DBP; 8002242: 4b20 ldr r3, [pc, #128] @ (80022c4 ) 8002244: 681b ldr r3, [r3, #0] 8002246: 4a1f ldr r2, [pc, #124] @ (80022c4 ) 8002248: f443 7380 orr.w r3, r3, #256 @ 0x100 800224c: 6013 str r3, [r2, #0] /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 800224e: 687b ldr r3, [r7, #4] 8002250: 689b ldr r3, [r3, #8] 8002252: 2b01 cmp r3, #1 8002254: d106 bne.n 8002264 8002256: 4b1a ldr r3, [pc, #104] @ (80022c0 ) 8002258: 6f1b ldr r3, [r3, #112] @ 0x70 800225a: 4a19 ldr r2, [pc, #100] @ (80022c0 ) 800225c: f043 0301 orr.w r3, r3, #1 8002260: 6713 str r3, [r2, #112] @ 0x70 8002262: e05a b.n 800231a 8002264: 687b ldr r3, [r7, #4] 8002266: 689b ldr r3, [r3, #8] 8002268: 2b00 cmp r3, #0 800226a: d112 bne.n 8002292 800226c: 4b14 ldr r3, [pc, #80] @ (80022c0 ) 800226e: 6f1b ldr r3, [r3, #112] @ 0x70 8002270: 4a13 ldr r2, [pc, #76] @ (80022c0 ) 8002272: f023 0301 bic.w r3, r3, #1 8002276: 6713 str r3, [r2, #112] @ 0x70 8002278: 4b11 ldr r3, [pc, #68] @ (80022c0 ) 800227a: 6f1b ldr r3, [r3, #112] @ 0x70 800227c: 4a10 ldr r2, [pc, #64] @ (80022c0 ) 800227e: f023 0380 bic.w r3, r3, #128 @ 0x80 8002282: 6713 str r3, [r2, #112] @ 0x70 8002284: 4b0e ldr r3, [pc, #56] @ (80022c0 ) 8002286: 6f1b ldr r3, [r3, #112] @ 0x70 8002288: 4a0d ldr r2, [pc, #52] @ (80022c0 ) 800228a: f023 0304 bic.w r3, r3, #4 800228e: 6713 str r3, [r2, #112] @ 0x70 8002290: e043 b.n 800231a 8002292: 687b ldr r3, [r7, #4] 8002294: 689b ldr r3, [r3, #8] 8002296: 2b05 cmp r3, #5 8002298: d116 bne.n 80022c8 800229a: 4b09 ldr r3, [pc, #36] @ (80022c0 ) 800229c: 6f1b ldr r3, [r3, #112] @ 0x70 800229e: 4a08 ldr r2, [pc, #32] @ (80022c0 ) 80022a0: f043 0304 orr.w r3, r3, #4 80022a4: 6713 str r3, [r2, #112] @ 0x70 80022a6: 4b06 ldr r3, [pc, #24] @ (80022c0 ) 80022a8: 6f1b ldr r3, [r3, #112] @ 0x70 80022aa: 4a05 ldr r2, [pc, #20] @ (80022c0 ) 80022ac: f023 0380 bic.w r3, r3, #128 @ 0x80 80022b0: 6713 str r3, [r2, #112] @ 0x70 80022b2: 4b03 ldr r3, [pc, #12] @ (80022c0 ) 80022b4: 6f1b ldr r3, [r3, #112] @ 0x70 80022b6: 4a02 ldr r2, [pc, #8] @ (80022c0 ) 80022b8: f043 0301 orr.w r3, r3, #1 80022bc: 6713 str r3, [r2, #112] @ 0x70 80022be: e02c b.n 800231a 80022c0: 58024400 .word 0x58024400 80022c4: 58024800 .word 0x58024800 80022c8: 687b ldr r3, [r7, #4] 80022ca: 689b ldr r3, [r3, #8] 80022cc: 2b85 cmp r3, #133 @ 0x85 80022ce: d112 bne.n 80022f6 80022d0: 4b60 ldr r3, [pc, #384] @ (8002454 ) 80022d2: 6f1b ldr r3, [r3, #112] @ 0x70 80022d4: 4a5f ldr r2, [pc, #380] @ (8002454 ) 80022d6: f043 0304 orr.w r3, r3, #4 80022da: 6713 str r3, [r2, #112] @ 0x70 80022dc: 4b5d ldr r3, [pc, #372] @ (8002454 ) 80022de: 6f1b ldr r3, [r3, #112] @ 0x70 80022e0: 4a5c ldr r2, [pc, #368] @ (8002454 ) 80022e2: f043 0380 orr.w r3, r3, #128 @ 0x80 80022e6: 6713 str r3, [r2, #112] @ 0x70 80022e8: 4b5a ldr r3, [pc, #360] @ (8002454 ) 80022ea: 6f1b ldr r3, [r3, #112] @ 0x70 80022ec: 4a59 ldr r2, [pc, #356] @ (8002454 ) 80022ee: f043 0301 orr.w r3, r3, #1 80022f2: 6713 str r3, [r2, #112] @ 0x70 80022f4: e011 b.n 800231a 80022f6: 4b57 ldr r3, [pc, #348] @ (8002454 ) 80022f8: 6f1b ldr r3, [r3, #112] @ 0x70 80022fa: 4a56 ldr r2, [pc, #344] @ (8002454 ) 80022fc: f023 0301 bic.w r3, r3, #1 8002300: 6713 str r3, [r2, #112] @ 0x70 8002302: 4b54 ldr r3, [pc, #336] @ (8002454 ) 8002304: 6f1b ldr r3, [r3, #112] @ 0x70 8002306: 4a53 ldr r2, [pc, #332] @ (8002454 ) 8002308: f023 0304 bic.w r3, r3, #4 800230c: 6713 str r3, [r2, #112] @ 0x70 800230e: 4b51 ldr r3, [pc, #324] @ (8002454 ) 8002310: 6f1b ldr r3, [r3, #112] @ 0x70 8002312: 4a50 ldr r2, [pc, #320] @ (8002454 ) 8002314: f023 0380 bic.w r3, r3, #128 @ 0x80 8002318: 6713 str r3, [r2, #112] @ 0x70 /* Check the LSE State */ if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 800231a: 687b ldr r3, [r7, #4] 800231c: 689b ldr r3, [r3, #8] 800231e: 2b00 cmp r3, #0 8002320: d015 beq.n 800234e { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002322: f7fe fce5 bl 8000cf0 8002326: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 8002328: e00a b.n 8002340 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800232a: f7fe fce1 bl 8000cf0 800232e: 4602 mov r2, r0 8002330: 693b ldr r3, [r7, #16] 8002332: 1ad3 subs r3, r2, r3 8002334: f241 3288 movw r2, #5000 @ 0x1388 8002338: 4293 cmp r3, r2 800233a: d901 bls.n 8002340 { return HAL_TIMEOUT; 800233c: 2303 movs r3, #3 800233e: e085 b.n 800244c while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 8002340: 4b44 ldr r3, [pc, #272] @ (8002454 ) 8002342: 6f1b ldr r3, [r3, #112] @ 0x70 8002344: f003 0302 and.w r3, r3, #2 8002348: 2b00 cmp r3, #0 800234a: d0ee beq.n 800232a 800234c: e014 b.n 8002378 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800234e: f7fe fccf bl 8000cf0 8002352: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) 8002354: e00a b.n 800236c { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8002356: f7fe fccb bl 8000cf0 800235a: 4602 mov r2, r0 800235c: 693b ldr r3, [r7, #16] 800235e: 1ad3 subs r3, r2, r3 8002360: f241 3288 movw r2, #5000 @ 0x1388 8002364: 4293 cmp r3, r2 8002366: d901 bls.n 800236c { return HAL_TIMEOUT; 8002368: 2303 movs r3, #3 800236a: e06f b.n 800244c while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) 800236c: 4b39 ldr r3, [pc, #228] @ (8002454 ) 800236e: 6f1b ldr r3, [r3, #112] @ 0x70 8002370: f003 0302 and.w r3, r3, #2 8002374: 2b00 cmp r3, #0 8002376: d1ee bne.n 8002356 /*-------------------------------- PLL1 Configuration ----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL1.PLLState)); if (RCC_OscInitStruct->PLL1.PLLState != RCC_PLL_NONE) 8002378: 687b ldr r3, [r7, #4] 800237a: 6a5b ldr r3, [r3, #36] @ 0x24 800237c: 2b00 cmp r3, #0 800237e: d042 beq.n 8002406 { /* Check if the PLL is used as system clock or not */ if (sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8002380: 69fb ldr r3, [r7, #28] 8002382: 2b18 cmp r3, #24 8002384: d131 bne.n 80023ea { /* No PLL off possible */ if (RCC_OscInitStruct->PLL1.PLLState == RCC_PLL_OFF) 8002386: 687b ldr r3, [r7, #4] 8002388: 6a5b ldr r3, [r3, #36] @ 0x24 800238a: 2b01 cmp r3, #1 800238c: d101 bne.n 8002392 { return HAL_ERROR; 800238e: 2301 movs r3, #1 8002390: e05c b.n 800244c } else { /* Check if only fractional part needs to be updated */ tmpreg1 = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN) >> RCC_PLL1FRACR_FRACN_Pos); 8002392: 4b30 ldr r3, [pc, #192] @ (8002454 ) 8002394: 6b5b ldr r3, [r3, #52] @ 0x34 8002396: 08db lsrs r3, r3, #3 8002398: f3c3 030c ubfx r3, r3, #0, #13 800239c: 60fb str r3, [r7, #12] if (RCC_OscInitStruct->PLL1.PLLFractional != tmpreg1) 800239e: 687b ldr r3, [r7, #4] 80023a0: 6c9b ldr r3, [r3, #72] @ 0x48 80023a2: 68fa ldr r2, [r7, #12] 80023a4: 429a cmp r2, r3 80023a6: d02e beq.n 8002406 { assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL1.PLLFractional)); /* Disable PLL1FRACLE */ __HAL_RCC_PLL1_FRACN_DISABLE(); 80023a8: 4b2a ldr r3, [pc, #168] @ (8002454 ) 80023aa: 6adb ldr r3, [r3, #44] @ 0x2c 80023ac: 4a29 ldr r2, [pc, #164] @ (8002454 ) 80023ae: f023 0301 bic.w r3, r3, #1 80023b2: 62d3 str r3, [r2, #44] @ 0x2c /* Get Start Tick*/ tickstart = HAL_GetTick(); 80023b4: f7fe fc9c bl 8000cf0 80023b8: 6138 str r0, [r7, #16] /* Wait at least 2 CK_REF (PLL input source divided by M) period to make sure next latched value will be taken into account. */ while ((HAL_GetTick() - tickstart) < RCC_PLL_FRAC_WAIT_VALUE) 80023ba: bf00 nop 80023bc: f7fe fc98 bl 8000cf0 80023c0: 4602 mov r2, r0 80023c2: 693b ldr r3, [r7, #16] 80023c4: 4293 cmp r3, r2 80023c6: d0f9 beq.n 80023bc { /* Do nothing */ } /* Configure PLL1FRACN */ __HAL_RCC_PLL1_FRACN_CONFIG(RCC_OscInitStruct->PLL1.PLLFractional); 80023c8: 4b22 ldr r3, [pc, #136] @ (8002454 ) 80023ca: 6b5a ldr r2, [r3, #52] @ 0x34 80023cc: 4b22 ldr r3, [pc, #136] @ (8002458 ) 80023ce: 4013 ands r3, r2 80023d0: 687a ldr r2, [r7, #4] 80023d2: 6c92 ldr r2, [r2, #72] @ 0x48 80023d4: 00d2 lsls r2, r2, #3 80023d6: 491f ldr r1, [pc, #124] @ (8002454 ) 80023d8: 4313 orrs r3, r2 80023da: 634b str r3, [r1, #52] @ 0x34 /* Enable PLL1FRACLE to latch new value . */ __HAL_RCC_PLL1_FRACN_ENABLE(); 80023dc: 4b1d ldr r3, [pc, #116] @ (8002454 ) 80023de: 6adb ldr r3, [r3, #44] @ 0x2c 80023e0: 4a1c ldr r2, [pc, #112] @ (8002454 ) 80023e2: f043 0301 orr.w r3, r3, #1 80023e6: 62d3 str r3, [r2, #44] @ 0x2c 80023e8: e00d b.n 8002406 } } else { /* Initialize PLL1T to 1 to use common PLL initialization function */ RCC_OscInitStruct->PLL1.PLLT = 1U; 80023ea: 687b ldr r3, [r7, #4] 80023ec: 2201 movs r2, #1 80023ee: 645a str r2, [r3, #68] @ 0x44 if (RCC_PLL_Config(RCC_PLL1_CONFIG, &(RCC_OscInitStruct->PLL1)) != HAL_OK) 80023f0: 687b ldr r3, [r7, #4] 80023f2: 3324 adds r3, #36 @ 0x24 80023f4: 4619 mov r1, r3 80023f6: 2000 movs r0, #0 80023f8: f000 fc88 bl 8002d0c 80023fc: 4603 mov r3, r0 80023fe: 2b00 cmp r3, #0 8002400: d001 beq.n 8002406 { return HAL_ERROR; 8002402: 2301 movs r3, #1 8002404: e022 b.n 800244c /*-------------------------------- PLL2 Configuration ----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL2.PLLState)); if (RCC_OscInitStruct->PLL2.PLLState != RCC_PLL_NONE) 8002406: 687b ldr r3, [r7, #4] 8002408: 6cdb ldr r3, [r3, #76] @ 0x4c 800240a: 2b00 cmp r3, #0 800240c: d00a beq.n 8002424 { if (RCC_PLL_Config(RCC_PLL2_CONFIG, &(RCC_OscInitStruct->PLL2)) != HAL_OK) 800240e: 687b ldr r3, [r7, #4] 8002410: 334c adds r3, #76 @ 0x4c 8002412: 4619 mov r1, r3 8002414: 2001 movs r0, #1 8002416: f000 fc79 bl 8002d0c 800241a: 4603 mov r3, r0 800241c: 2b00 cmp r3, #0 800241e: d001 beq.n 8002424 { return HAL_ERROR; 8002420: 2301 movs r3, #1 8002422: e013 b.n 800244c /*-------------------------------- PLL3 Configuration ----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL3.PLLState)); if (RCC_OscInitStruct->PLL3.PLLState != RCC_PLL_NONE) 8002424: 687b ldr r3, [r7, #4] 8002426: 6f5b ldr r3, [r3, #116] @ 0x74 8002428: 2b00 cmp r3, #0 800242a: d00e beq.n 800244a { /* Initialize PLL3T to 1 to use common PLL initialization function */ RCC_OscInitStruct->PLL3.PLLT = 1U; 800242c: 687b ldr r3, [r7, #4] 800242e: 2201 movs r2, #1 8002430: f8c3 2094 str.w r2, [r3, #148] @ 0x94 if (RCC_PLL_Config(RCC_PLL3_CONFIG, &(RCC_OscInitStruct->PLL3)) != HAL_OK) 8002434: 687b ldr r3, [r7, #4] 8002436: 3374 adds r3, #116 @ 0x74 8002438: 4619 mov r1, r3 800243a: 2002 movs r0, #2 800243c: f000 fc66 bl 8002d0c 8002440: 4603 mov r3, r0 8002442: 2b00 cmp r3, #0 8002444: d001 beq.n 800244a { return HAL_ERROR; 8002446: 2301 movs r3, #1 8002448: e000 b.n 800244c } } return HAL_OK; 800244a: 2300 movs r3, #0 } 800244c: 4618 mov r0, r3 800244e: 3720 adds r7, #32 8002450: 46bd mov sp, r7 8002452: bd80 pop {r7, pc} 8002454: 58024400 .word 0x58024400 8002458: ffff0007 .word 0xffff0007 0800245c : * currently used as system clock source. * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 800245c: b580 push {r7, lr} 800245e: b084 sub sp, #16 8002460: af00 add r7, sp, #0 8002462: 6078 str r0, [r7, #4] 8002464: 6039 str r1, [r7, #0] HAL_StatusTypeDef halstatus; uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 8002466: 687b ldr r3, [r7, #4] 8002468: 2b00 cmp r3, #0 800246a: d101 bne.n 8002470 { return HAL_ERROR; 800246c: 2301 movs r3, #1 800246e: e182 b.n 8002776 /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8002470: 4b8a ldr r3, [pc, #552] @ (800269c ) 8002472: 681b ldr r3, [r3, #0] 8002474: f003 033f and.w r3, r3, #63 @ 0x3f 8002478: 683a ldr r2, [r7, #0] 800247a: 429a cmp r2, r3 800247c: d910 bls.n 80024a0 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800247e: 4b87 ldr r3, [pc, #540] @ (800269c ) 8002480: 681b ldr r3, [r3, #0] 8002482: f023 023f bic.w r2, r3, #63 @ 0x3f 8002486: 4985 ldr r1, [pc, #532] @ (800269c ) 8002488: 683b ldr r3, [r7, #0] 800248a: 4313 orrs r3, r2 800248c: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 800248e: 4b83 ldr r3, [pc, #524] @ (800269c ) 8002490: 681b ldr r3, [r3, #0] 8002492: f003 033f and.w r3, r3, #63 @ 0x3f 8002496: 683a ldr r2, [r7, #0] 8002498: 429a cmp r2, r3 800249a: d001 beq.n 80024a0 { return HAL_ERROR; 800249c: 2301 movs r3, #1 800249e: e16a b.n 8002776 } /* Increasing the BUS frequency divider ? */ /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80024a0: 687b ldr r3, [r7, #4] 80024a2: 681b ldr r3, [r3, #0] 80024a4: f003 0304 and.w r3, r3, #4 80024a8: 2b00 cmp r3, #0 80024aa: d010 beq.n 80024ce { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->APBCFGR & RCC_APBCFGR_PPRE1)) 80024ac: 687b ldr r3, [r7, #4] 80024ae: 691a ldr r2, [r3, #16] 80024b0: 4b7b ldr r3, [pc, #492] @ (80026a0 ) 80024b2: 6a1b ldr r3, [r3, #32] 80024b4: f003 0307 and.w r3, r3, #7 80024b8: 429a cmp r2, r3 80024ba: d908 bls.n 80024ce { MODIFY_REG(RCC->APBCFGR, RCC_APBCFGR_PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 80024bc: 4b78 ldr r3, [pc, #480] @ (80026a0 ) 80024be: 6a1b ldr r3, [r3, #32] 80024c0: f023 0207 bic.w r2, r3, #7 80024c4: 687b ldr r3, [r7, #4] 80024c6: 691b ldr r3, [r3, #16] 80024c8: 4975 ldr r1, [pc, #468] @ (80026a0 ) 80024ca: 4313 orrs r3, r2 80024cc: 620b str r3, [r1, #32] } } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 80024ce: 687b ldr r3, [r7, #4] 80024d0: 681b ldr r3, [r3, #0] 80024d2: f003 0308 and.w r3, r3, #8 80024d6: 2b00 cmp r3, #0 80024d8: d010 beq.n 80024fc { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->APBCFGR & RCC_APBCFGR_PPRE2)) 80024da: 687b ldr r3, [r7, #4] 80024dc: 695a ldr r2, [r3, #20] 80024de: 4b70 ldr r3, [pc, #448] @ (80026a0 ) 80024e0: 6a1b ldr r3, [r3, #32] 80024e2: f003 0370 and.w r3, r3, #112 @ 0x70 80024e6: 429a cmp r2, r3 80024e8: d908 bls.n 80024fc { MODIFY_REG(RCC->APBCFGR, RCC_APBCFGR_PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 80024ea: 4b6d ldr r3, [pc, #436] @ (80026a0 ) 80024ec: 6a1b ldr r3, [r3, #32] 80024ee: f023 0270 bic.w r2, r3, #112 @ 0x70 80024f2: 687b ldr r3, [r7, #4] 80024f4: 695b ldr r3, [r3, #20] 80024f6: 496a ldr r1, [pc, #424] @ (80026a0 ) 80024f8: 4313 orrs r3, r2 80024fa: 620b str r3, [r1, #32] } } /*-------------------------- PCLK4 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK4) == RCC_CLOCKTYPE_PCLK4) 80024fc: 687b ldr r3, [r7, #4] 80024fe: 681b ldr r3, [r3, #0] 8002500: f003 0310 and.w r3, r3, #16 8002504: 2b00 cmp r3, #0 8002506: d010 beq.n 800252a { assert_param(IS_RCC_PCLK4(RCC_ClkInitStruct->APB4CLKDivider)); if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->APBCFGR & RCC_APBCFGR_PPRE4)) 8002508: 687b ldr r3, [r7, #4] 800250a: 699a ldr r2, [r3, #24] 800250c: 4b64 ldr r3, [pc, #400] @ (80026a0 ) 800250e: 6a1b ldr r3, [r3, #32] 8002510: f403 63e0 and.w r3, r3, #1792 @ 0x700 8002514: 429a cmp r2, r3 8002516: d908 bls.n 800252a { MODIFY_REG(RCC->APBCFGR, RCC_APBCFGR_PPRE4, (RCC_ClkInitStruct->APB4CLKDivider)); 8002518: 4b61 ldr r3, [pc, #388] @ (80026a0 ) 800251a: 6a1b ldr r3, [r3, #32] 800251c: f423 62e0 bic.w r2, r3, #1792 @ 0x700 8002520: 687b ldr r3, [r7, #4] 8002522: 699b ldr r3, [r3, #24] 8002524: 495e ldr r1, [pc, #376] @ (80026a0 ) 8002526: 4313 orrs r3, r2 8002528: 620b str r3, [r1, #32] } } /*-------------------------- PCLK5 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK5) == RCC_CLOCKTYPE_PCLK5) 800252a: 687b ldr r3, [r7, #4] 800252c: 681b ldr r3, [r3, #0] 800252e: f003 0320 and.w r3, r3, #32 8002532: 2b00 cmp r3, #0 8002534: d010 beq.n 8002558 { assert_param(IS_RCC_PCLK5(RCC_ClkInitStruct->APB5CLKDivider)); if ((RCC_ClkInitStruct->APB5CLKDivider) > (RCC->APBCFGR & RCC_APBCFGR_PPRE5)) 8002536: 687b ldr r3, [r7, #4] 8002538: 69da ldr r2, [r3, #28] 800253a: 4b59 ldr r3, [pc, #356] @ (80026a0 ) 800253c: 6a1b ldr r3, [r3, #32] 800253e: f403 43e0 and.w r3, r3, #28672 @ 0x7000 8002542: 429a cmp r2, r3 8002544: d908 bls.n 8002558 { MODIFY_REG(RCC->APBCFGR, RCC_APBCFGR_PPRE5, (RCC_ClkInitStruct->APB5CLKDivider)); 8002546: 4b56 ldr r3, [pc, #344] @ (80026a0 ) 8002548: 6a1b ldr r3, [r3, #32] 800254a: f423 42e0 bic.w r2, r3, #28672 @ 0x7000 800254e: 687b ldr r3, [r7, #4] 8002550: 69db ldr r3, [r3, #28] 8002552: 4953 ldr r1, [pc, #332] @ (80026a0 ) 8002554: 4313 orrs r3, r2 8002556: 620b str r3, [r1, #32] } } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8002558: 687b ldr r3, [r7, #4] 800255a: 681b ldr r3, [r3, #0] 800255c: f003 0302 and.w r3, r3, #2 8002560: 2b00 cmp r3, #0 8002562: d010 beq.n 8002586 { assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->BMCFGR & RCC_BMCFGR_BMPRE)) 8002564: 687b ldr r3, [r7, #4] 8002566: 68da ldr r2, [r3, #12] 8002568: 4b4d ldr r3, [pc, #308] @ (80026a0 ) 800256a: 69db ldr r3, [r3, #28] 800256c: f003 030f and.w r3, r3, #15 8002570: 429a cmp r2, r3 8002572: d908 bls.n 8002586 { /* Set the new HCLK clock divider */ MODIFY_REG(RCC->BMCFGR, RCC_BMCFGR_BMPRE, RCC_ClkInitStruct->AHBCLKDivider); 8002574: 4b4a ldr r3, [pc, #296] @ (80026a0 ) 8002576: 69db ldr r3, [r3, #28] 8002578: f023 020f bic.w r2, r3, #15 800257c: 687b ldr r3, [r7, #4] 800257e: 68db ldr r3, [r3, #12] 8002580: 4947 ldr r1, [pc, #284] @ (80026a0 ) 8002582: 4313 orrs r3, r2 8002584: 61cb str r3, [r1, #28] } } /*------------------------- SYSCLK Configuration -------------------------*/ if ((RCC_ClkInitStruct->ClockType & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8002586: 687b ldr r3, [r7, #4] 8002588: 681b ldr r3, [r3, #0] 800258a: f003 0301 and.w r3, r3, #1 800258e: 2b00 cmp r3, #0 8002590: d055 beq.n 800263e { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider)); MODIFY_REG(RCC->CDCFGR, RCC_CDCFGR_CPRE, RCC_ClkInitStruct->SYSCLKDivider); 8002592: 4b43 ldr r3, [pc, #268] @ (80026a0 ) 8002594: 699b ldr r3, [r3, #24] 8002596: f023 020f bic.w r2, r3, #15 800259a: 687b ldr r3, [r7, #4] 800259c: 689b ldr r3, [r3, #8] 800259e: 4940 ldr r1, [pc, #256] @ (80026a0 ) 80025a0: 4313 orrs r3, r2 80025a2: 618b str r3, [r1, #24] /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 80025a4: 687b ldr r3, [r7, #4] 80025a6: 685b ldr r3, [r3, #4] 80025a8: 2b02 cmp r3, #2 80025aa: d107 bne.n 80025bc { /* Check the HSE ready flag */ if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 80025ac: 4b3c ldr r3, [pc, #240] @ (80026a0 ) 80025ae: 681b ldr r3, [r3, #0] 80025b0: f403 3300 and.w r3, r3, #131072 @ 0x20000 80025b4: 2b00 cmp r3, #0 80025b6: d121 bne.n 80025fc { return HAL_ERROR; 80025b8: 2301 movs r3, #1 80025ba: e0dc b.n 8002776 } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 80025bc: 687b ldr r3, [r7, #4] 80025be: 685b ldr r3, [r3, #4] 80025c0: 2b03 cmp r3, #3 80025c2: d107 bne.n 80025d4 { /* Check the PLL ready flag */ if (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == 0U) 80025c4: 4b36 ldr r3, [pc, #216] @ (80026a0 ) 80025c6: 681b ldr r3, [r3, #0] 80025c8: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80025cc: 2b00 cmp r3, #0 80025ce: d115 bne.n 80025fc { return HAL_ERROR; 80025d0: 2301 movs r3, #1 80025d2: e0d0 b.n 8002776 } } /* CSI is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI) 80025d4: 687b ldr r3, [r7, #4] 80025d6: 685b ldr r3, [r3, #4] 80025d8: 2b01 cmp r3, #1 80025da: d107 bne.n 80025ec { /* Check the PLL ready flag */ if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) == 0U) 80025dc: 4b30 ldr r3, [pc, #192] @ (80026a0 ) 80025de: 681b ldr r3, [r3, #0] 80025e0: f403 7380 and.w r3, r3, #256 @ 0x100 80025e4: 2b00 cmp r3, #0 80025e6: d109 bne.n 80025fc { return HAL_ERROR; 80025e8: 2301 movs r3, #1 80025ea: e0c4 b.n 8002776 } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 80025ec: 4b2c ldr r3, [pc, #176] @ (80026a0 ) 80025ee: 681b ldr r3, [r3, #0] 80025f0: f003 0304 and.w r3, r3, #4 80025f4: 2b00 cmp r3, #0 80025f6: d101 bne.n 80025fc { return HAL_ERROR; 80025f8: 2301 movs r3, #1 80025fa: e0bc b.n 8002776 } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 80025fc: 4b28 ldr r3, [pc, #160] @ (80026a0 ) 80025fe: 691b ldr r3, [r3, #16] 8002600: f023 0207 bic.w r2, r3, #7 8002604: 687b ldr r3, [r7, #4] 8002606: 685b ldr r3, [r3, #4] 8002608: 4925 ldr r1, [pc, #148] @ (80026a0 ) 800260a: 4313 orrs r3, r2 800260c: 610b str r3, [r1, #16] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800260e: f7fe fb6f bl 8000cf0 8002612: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8002614: e00a b.n 800262c { if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) 8002616: f7fe fb6b bl 8000cf0 800261a: 4602 mov r2, r0 800261c: 68fb ldr r3, [r7, #12] 800261e: 1ad3 subs r3, r2, r3 8002620: f241 3288 movw r2, #5000 @ 0x1388 8002624: 4293 cmp r3, r2 8002626: d901 bls.n 800262c { return HAL_TIMEOUT; 8002628: 2303 movs r3, #3 800262a: e0a4 b.n 8002776 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800262c: 4b1c ldr r3, [pc, #112] @ (80026a0 ) 800262e: 691b ldr r3, [r3, #16] 8002630: f003 0238 and.w r2, r3, #56 @ 0x38 8002634: 687b ldr r3, [r7, #4] 8002636: 685b ldr r3, [r3, #4] 8002638: 00db lsls r3, r3, #3 800263a: 429a cmp r2, r3 800263c: d1eb bne.n 8002616 } /* Decreasing the BUS frequency divider ? */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800263e: 687b ldr r3, [r7, #4] 8002640: 681b ldr r3, [r3, #0] 8002642: f003 0302 and.w r3, r3, #2 8002646: 2b00 cmp r3, #0 8002648: d010 beq.n 800266c { assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->BMCFGR & RCC_BMCFGR_BMPRE)) 800264a: 687b ldr r3, [r7, #4] 800264c: 68da ldr r2, [r3, #12] 800264e: 4b14 ldr r3, [pc, #80] @ (80026a0 ) 8002650: 69db ldr r3, [r3, #28] 8002652: f003 030f and.w r3, r3, #15 8002656: 429a cmp r2, r3 8002658: d208 bcs.n 800266c { /* Set the new HCLK clock divider */ MODIFY_REG(RCC->BMCFGR, RCC_BMCFGR_BMPRE, RCC_ClkInitStruct->AHBCLKDivider); 800265a: 4b11 ldr r3, [pc, #68] @ (80026a0 ) 800265c: 69db ldr r3, [r3, #28] 800265e: f023 020f bic.w r2, r3, #15 8002662: 687b ldr r3, [r7, #4] 8002664: 68db ldr r3, [r3, #12] 8002666: 490e ldr r1, [pc, #56] @ (80026a0 ) 8002668: 4313 orrs r3, r2 800266a: 61cb str r3, [r1, #28] } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 800266c: 4b0b ldr r3, [pc, #44] @ (800269c ) 800266e: 681b ldr r3, [r3, #0] 8002670: f003 033f and.w r3, r3, #63 @ 0x3f 8002674: 683a ldr r2, [r7, #0] 8002676: 429a cmp r2, r3 8002678: d214 bcs.n 80026a4 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800267a: 4b08 ldr r3, [pc, #32] @ (800269c ) 800267c: 681b ldr r3, [r3, #0] 800267e: f023 023f bic.w r2, r3, #63 @ 0x3f 8002682: 4906 ldr r1, [pc, #24] @ (800269c ) 8002684: 683b ldr r3, [r7, #0] 8002686: 4313 orrs r3, r2 8002688: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 800268a: 4b04 ldr r3, [pc, #16] @ (800269c ) 800268c: 681b ldr r3, [r3, #0] 800268e: f003 033f and.w r3, r3, #63 @ 0x3f 8002692: 683a ldr r2, [r7, #0] 8002694: 429a cmp r2, r3 8002696: d005 beq.n 80026a4 { return HAL_ERROR; 8002698: 2301 movs r3, #1 800269a: e06c b.n 8002776 800269c: 52002000 .word 0x52002000 80026a0: 58024400 .word 0x58024400 } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80026a4: 687b ldr r3, [r7, #4] 80026a6: 681b ldr r3, [r3, #0] 80026a8: f003 0304 and.w r3, r3, #4 80026ac: 2b00 cmp r3, #0 80026ae: d010 beq.n 80026d2 { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->APBCFGR & RCC_APBCFGR_PPRE1)) 80026b0: 687b ldr r3, [r7, #4] 80026b2: 691a ldr r2, [r3, #16] 80026b4: 4b32 ldr r3, [pc, #200] @ (8002780 ) 80026b6: 6a1b ldr r3, [r3, #32] 80026b8: f003 0307 and.w r3, r3, #7 80026bc: 429a cmp r2, r3 80026be: d208 bcs.n 80026d2 { MODIFY_REG(RCC->APBCFGR, RCC_APBCFGR_PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 80026c0: 4b2f ldr r3, [pc, #188] @ (8002780 ) 80026c2: 6a1b ldr r3, [r3, #32] 80026c4: f023 0207 bic.w r2, r3, #7 80026c8: 687b ldr r3, [r7, #4] 80026ca: 691b ldr r3, [r3, #16] 80026cc: 492c ldr r1, [pc, #176] @ (8002780 ) 80026ce: 4313 orrs r3, r2 80026d0: 620b str r3, [r1, #32] } } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 80026d2: 687b ldr r3, [r7, #4] 80026d4: 681b ldr r3, [r3, #0] 80026d6: f003 0308 and.w r3, r3, #8 80026da: 2b00 cmp r3, #0 80026dc: d010 beq.n 8002700 { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->APBCFGR & RCC_APBCFGR_PPRE2)) 80026de: 687b ldr r3, [r7, #4] 80026e0: 695a ldr r2, [r3, #20] 80026e2: 4b27 ldr r3, [pc, #156] @ (8002780 ) 80026e4: 6a1b ldr r3, [r3, #32] 80026e6: f003 0370 and.w r3, r3, #112 @ 0x70 80026ea: 429a cmp r2, r3 80026ec: d208 bcs.n 8002700 { MODIFY_REG(RCC->APBCFGR, RCC_APBCFGR_PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 80026ee: 4b24 ldr r3, [pc, #144] @ (8002780 ) 80026f0: 6a1b ldr r3, [r3, #32] 80026f2: f023 0270 bic.w r2, r3, #112 @ 0x70 80026f6: 687b ldr r3, [r7, #4] 80026f8: 695b ldr r3, [r3, #20] 80026fa: 4921 ldr r1, [pc, #132] @ (8002780 ) 80026fc: 4313 orrs r3, r2 80026fe: 620b str r3, [r1, #32] } } /*-------------------------- PCLK4 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK4) == RCC_CLOCKTYPE_PCLK4) 8002700: 687b ldr r3, [r7, #4] 8002702: 681b ldr r3, [r3, #0] 8002704: f003 0310 and.w r3, r3, #16 8002708: 2b00 cmp r3, #0 800270a: d010 beq.n 800272e { assert_param(IS_RCC_PCLK4(RCC_ClkInitStruct->APB4CLKDivider)); if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->APBCFGR & RCC_APBCFGR_PPRE4)) 800270c: 687b ldr r3, [r7, #4] 800270e: 699a ldr r2, [r3, #24] 8002710: 4b1b ldr r3, [pc, #108] @ (8002780 ) 8002712: 6a1b ldr r3, [r3, #32] 8002714: f403 63e0 and.w r3, r3, #1792 @ 0x700 8002718: 429a cmp r2, r3 800271a: d208 bcs.n 800272e { MODIFY_REG(RCC->APBCFGR, RCC_APBCFGR_PPRE4, (RCC_ClkInitStruct->APB4CLKDivider)); 800271c: 4b18 ldr r3, [pc, #96] @ (8002780 ) 800271e: 6a1b ldr r3, [r3, #32] 8002720: f423 62e0 bic.w r2, r3, #1792 @ 0x700 8002724: 687b ldr r3, [r7, #4] 8002726: 699b ldr r3, [r3, #24] 8002728: 4915 ldr r1, [pc, #84] @ (8002780 ) 800272a: 4313 orrs r3, r2 800272c: 620b str r3, [r1, #32] } } /*-------------------------- PCLK5 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK5) == RCC_CLOCKTYPE_PCLK5) 800272e: 687b ldr r3, [r7, #4] 8002730: 681b ldr r3, [r3, #0] 8002732: f003 0320 and.w r3, r3, #32 8002736: 2b00 cmp r3, #0 8002738: d010 beq.n 800275c { assert_param(IS_RCC_PCLK5(RCC_ClkInitStruct->APB5CLKDivider)); if ((RCC_ClkInitStruct->APB5CLKDivider) < (RCC->APBCFGR & RCC_APBCFGR_PPRE5)) 800273a: 687b ldr r3, [r7, #4] 800273c: 69da ldr r2, [r3, #28] 800273e: 4b10 ldr r3, [pc, #64] @ (8002780 ) 8002740: 6a1b ldr r3, [r3, #32] 8002742: f403 43e0 and.w r3, r3, #28672 @ 0x7000 8002746: 429a cmp r2, r3 8002748: d208 bcs.n 800275c { MODIFY_REG(RCC->APBCFGR, RCC_APBCFGR_PPRE5, (RCC_ClkInitStruct->APB5CLKDivider)); 800274a: 4b0d ldr r3, [pc, #52] @ (8002780 ) 800274c: 6a1b ldr r3, [r3, #32] 800274e: f423 42e0 bic.w r2, r3, #28672 @ 0x7000 8002752: 687b ldr r3, [r7, #4] 8002754: 69db ldr r3, [r3, #28] 8002756: 490a ldr r1, [pc, #40] @ (8002780 ) 8002758: 4313 orrs r3, r2 800275a: 620b str r3, [r1, #32] } } /* Update the SystemCoreClock global variable with the System CPU clock */ SystemCoreClock = HAL_RCC_GetSysClockFreq(); 800275c: f000 f816 bl 800278c 8002760: 4603 mov r3, r0 8002762: 4a08 ldr r2, [pc, #32] @ (8002784 ) 8002764: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ halstatus = HAL_InitTick(uwTickPrio); 8002766: 4b08 ldr r3, [pc, #32] @ (8002788 ) 8002768: 681b ldr r3, [r3, #0] 800276a: 4618 mov r0, r3 800276c: f7fe fa70 bl 8000c50 8002770: 4603 mov r3, r0 8002772: 72fb strb r3, [r7, #11] return halstatus; 8002774: 7afb ldrb r3, [r7, #11] } 8002776: 4618 mov r0, r3 8002778: 3710 adds r7, #16 800277a: 46bd mov sp, r7 800277c: bd80 pop {r7, pc} 800277e: bf00 nop 8002780: 58024400 .word 0x58024400 8002784: 24000000 .word 0x24000000 8002788: 24000004 .word 0x24000004 0800278c : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 800278c: b480 push {r7} 800278e: b08b sub sp, #44 @ 0x2c 8002790: af00 add r7, sp, #0 uint32_t sysclockfreq; uint32_t prescaler; /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 8002792: 4baa ldr r3, [pc, #680] @ (8002a3c ) 8002794: 691b ldr r3, [r3, #16] 8002796: f003 0338 and.w r3, r3, #56 @ 0x38 800279a: 2b18 cmp r3, #24 800279c: f200 8136 bhi.w 8002a0c 80027a0: a201 add r2, pc, #4 @ (adr r2, 80027a8 ) 80027a2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80027a6: bf00 nop 80027a8: 0800280d .word 0x0800280d 80027ac: 08002a0d .word 0x08002a0d 80027b0: 08002a0d .word 0x08002a0d 80027b4: 08002a0d .word 0x08002a0d 80027b8: 08002a0d .word 0x08002a0d 80027bc: 08002a0d .word 0x08002a0d 80027c0: 08002a0d .word 0x08002a0d 80027c4: 08002a0d .word 0x08002a0d 80027c8: 08002833 .word 0x08002833 80027cc: 08002a0d .word 0x08002a0d 80027d0: 08002a0d .word 0x08002a0d 80027d4: 08002a0d .word 0x08002a0d 80027d8: 08002a0d .word 0x08002a0d 80027dc: 08002a0d .word 0x08002a0d 80027e0: 08002a0d .word 0x08002a0d 80027e4: 08002a0d .word 0x08002a0d 80027e8: 08002839 .word 0x08002839 80027ec: 08002a0d .word 0x08002a0d 80027f0: 08002a0d .word 0x08002a0d 80027f4: 08002a0d .word 0x08002a0d 80027f8: 08002a0d .word 0x08002a0d 80027fc: 08002a0d .word 0x08002a0d 8002800: 08002a0d .word 0x08002a0d 8002804: 08002a0d .word 0x08002a0d 8002808: 0800283f .word 0x0800283f { case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) 800280c: 4b8b ldr r3, [pc, #556] @ (8002a3c ) 800280e: 681b ldr r3, [r3, #0] 8002810: f003 0320 and.w r3, r3, #32 8002814: 2b00 cmp r3, #0 8002816: d009 beq.n 800282c { sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); 8002818: 4b88 ldr r3, [pc, #544] @ (8002a3c ) 800281a: 681b ldr r3, [r3, #0] 800281c: 08db lsrs r3, r3, #3 800281e: f003 0303 and.w r3, r3, #3 8002822: 4a87 ldr r2, [pc, #540] @ (8002a40 ) 8002824: fa22 f303 lsr.w r3, r2, r3 8002828: 623b str r3, [r7, #32] { /* Can't retrieve HSIDIV value */ sysclockfreq = 0U; } break; 800282a: e0f2 b.n 8002a12 sysclockfreq = 0U; 800282c: 2300 movs r3, #0 800282e: 623b str r3, [r7, #32] break; 8002830: e0ef b.n 8002a12 case RCC_SYSCLKSOURCE_STATUS_CSI: /* CSI used as system clock source */ sysclockfreq = CSI_VALUE; 8002832: 4b84 ldr r3, [pc, #528] @ (8002a44 ) 8002834: 623b str r3, [r7, #32] break; 8002836: e0ec b.n 8002a12 case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; 8002838: 4b83 ldr r3, [pc, #524] @ (8002a48 ) 800283a: 623b str r3, [r7, #32] break; 800283c: e0e9 b.n 8002a12 case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL1 used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800283e: 4b7f ldr r3, [pc, #508] @ (8002a3c ) 8002840: 6a9b ldr r3, [r3, #40] @ 0x28 8002842: f003 0303 and.w r3, r3, #3 8002846: 61fb str r3, [r7, #28] pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) ; 8002848: 4b7c ldr r3, [pc, #496] @ (8002a3c ) 800284a: 6a9b ldr r3, [r3, #40] @ 0x28 800284c: 091b lsrs r3, r3, #4 800284e: f003 033f and.w r3, r3, #63 @ 0x3f 8002852: 61bb str r3, [r7, #24] pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos); 8002854: 4b79 ldr r3, [pc, #484] @ (8002a3c ) 8002856: 6adb ldr r3, [r3, #44] @ 0x2c 8002858: f003 0301 and.w r3, r3, #1 800285c: 617b str r3, [r7, #20] fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN) >> 3)); 800285e: 4b77 ldr r3, [pc, #476] @ (8002a3c ) 8002860: 6b5b ldr r3, [r3, #52] @ 0x34 8002862: 08db lsrs r3, r3, #3 8002864: f3c3 030c ubfx r3, r3, #0, #13 8002868: 697a ldr r2, [r7, #20] 800286a: fb02 f303 mul.w r3, r2, r3 800286e: ee07 3a90 vmov s15, r3 8002872: eef8 7a67 vcvt.f32.u32 s15, s15 8002876: edc7 7a04 vstr s15, [r7, #16] if (pllm != 0U) 800287a: 69bb ldr r3, [r7, #24] 800287c: 2b00 cmp r3, #0 800287e: f000 80c2 beq.w 8002a06 { switch (pllsource) 8002882: 69fb ldr r3, [r7, #28] 8002884: 2b02 cmp r3, #2 8002886: d064 beq.n 8002952 8002888: 69fb ldr r3, [r7, #28] 800288a: 2b02 cmp r3, #2 800288c: f200 8083 bhi.w 8002996 8002890: 69fb ldr r3, [r7, #28] 8002892: 2b00 cmp r3, #0 8002894: d003 beq.n 800289e 8002896: 69fb ldr r3, [r7, #28] 8002898: 2b01 cmp r3, #1 800289a: d038 beq.n 800290e 800289c: e07b b.n 8002996 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) 800289e: 4b67 ldr r3, [pc, #412] @ (8002a3c ) 80028a0: 681b ldr r3, [r3, #0] 80028a2: f003 0320 and.w r3, r3, #32 80028a6: 2b00 cmp r3, #0 80028a8: d02d beq.n 8002906 { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); 80028aa: 4b64 ldr r3, [pc, #400] @ (8002a3c ) 80028ac: 681b ldr r3, [r3, #0] 80028ae: 08db lsrs r3, r3, #3 80028b0: f003 0303 and.w r3, r3, #3 80028b4: 4a62 ldr r2, [pc, #392] @ (8002a40 ) 80028b6: fa22 f303 lsr.w r3, r2, r3 80028ba: 60fb str r3, [r7, #12] pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) + (fracn1 / (float_t)0x2000) + (float_t)1); 80028bc: 68fb ldr r3, [r7, #12] 80028be: ee07 3a90 vmov s15, r3 80028c2: eef8 6a67 vcvt.f32.u32 s13, s15 80028c6: 69bb ldr r3, [r7, #24] 80028c8: ee07 3a90 vmov s15, r3 80028cc: eef8 7a67 vcvt.f32.u32 s15, s15 80028d0: ee86 7aa7 vdiv.f32 s14, s13, s15 80028d4: 4b59 ldr r3, [pc, #356] @ (8002a3c ) 80028d6: 6b1b ldr r3, [r3, #48] @ 0x30 80028d8: f3c3 0308 ubfx r3, r3, #0, #9 80028dc: ee07 3a90 vmov s15, r3 80028e0: eef8 6a67 vcvt.f32.u32 s13, s15 80028e4: ed97 6a04 vldr s12, [r7, #16] 80028e8: eddf 5a58 vldr s11, [pc, #352] @ 8002a4c 80028ec: eec6 7a25 vdiv.f32 s15, s12, s11 80028f0: ee76 7aa7 vadd.f32 s15, s13, s15 80028f4: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 80028f8: ee77 7aa6 vadd.f32 s15, s15, s13 80028fc: ee67 7a27 vmul.f32 s15, s14, s15 8002900: edc7 7a09 vstr s15, [r7, #36] @ 0x24 else { /* Can't retrieve HSIDIV value */ pllvco = (float_t)0; } break; 8002904: e069 b.n 80029da pllvco = (float_t)0; 8002906: f04f 0300 mov.w r3, #0 800290a: 627b str r3, [r7, #36] @ 0x24 break; 800290c: e065 b.n 80029da case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) + (fracn1 / (float_t)0x2000) + (float_t)1); 800290e: 69bb ldr r3, [r7, #24] 8002910: ee07 3a90 vmov s15, r3 8002914: eef8 7a67 vcvt.f32.u32 s15, s15 8002918: eddf 6a4d vldr s13, [pc, #308] @ 8002a50 800291c: ee86 7aa7 vdiv.f32 s14, s13, s15 8002920: 4b46 ldr r3, [pc, #280] @ (8002a3c ) 8002922: 6b1b ldr r3, [r3, #48] @ 0x30 8002924: f3c3 0308 ubfx r3, r3, #0, #9 8002928: ee07 3a90 vmov s15, r3 800292c: eef8 6a67 vcvt.f32.u32 s13, s15 8002930: ed97 6a04 vldr s12, [r7, #16] 8002934: eddf 5a45 vldr s11, [pc, #276] @ 8002a4c 8002938: eec6 7a25 vdiv.f32 s15, s12, s11 800293c: ee76 7aa7 vadd.f32 s15, s13, s15 8002940: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8002944: ee77 7aa6 vadd.f32 s15, s15, s13 8002948: ee67 7a27 vmul.f32 s15, s14, s15 800294c: edc7 7a09 vstr s15, [r7, #36] @ 0x24 break; 8002950: e043 b.n 80029da case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) + (fracn1 / (float_t)0x2000) + (float_t)1); 8002952: 69bb ldr r3, [r7, #24] 8002954: ee07 3a90 vmov s15, r3 8002958: eef8 7a67 vcvt.f32.u32 s15, s15 800295c: eddf 6a3d vldr s13, [pc, #244] @ 8002a54 8002960: ee86 7aa7 vdiv.f32 s14, s13, s15 8002964: 4b35 ldr r3, [pc, #212] @ (8002a3c ) 8002966: 6b1b ldr r3, [r3, #48] @ 0x30 8002968: f3c3 0308 ubfx r3, r3, #0, #9 800296c: ee07 3a90 vmov s15, r3 8002970: eef8 6a67 vcvt.f32.u32 s13, s15 8002974: ed97 6a04 vldr s12, [r7, #16] 8002978: eddf 5a34 vldr s11, [pc, #208] @ 8002a4c 800297c: eec6 7a25 vdiv.f32 s15, s12, s11 8002980: ee76 7aa7 vadd.f32 s15, s13, s15 8002984: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8002988: ee77 7aa6 vadd.f32 s15, s15, s13 800298c: ee67 7a27 vmul.f32 s15, s14, s15 8002990: edc7 7a09 vstr s15, [r7, #36] @ 0x24 break; 8002994: e021 b.n 80029da default: pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) + (fracn1 / (float_t)0x2000) + (float_t)1); 8002996: 69bb ldr r3, [r7, #24] 8002998: ee07 3a90 vmov s15, r3 800299c: eef8 7a67 vcvt.f32.u32 s15, s15 80029a0: eddf 6a2b vldr s13, [pc, #172] @ 8002a50 80029a4: ee86 7aa7 vdiv.f32 s14, s13, s15 80029a8: 4b24 ldr r3, [pc, #144] @ (8002a3c ) 80029aa: 6b1b ldr r3, [r3, #48] @ 0x30 80029ac: f3c3 0308 ubfx r3, r3, #0, #9 80029b0: ee07 3a90 vmov s15, r3 80029b4: eef8 6a67 vcvt.f32.u32 s13, s15 80029b8: ed97 6a04 vldr s12, [r7, #16] 80029bc: eddf 5a23 vldr s11, [pc, #140] @ 8002a4c 80029c0: eec6 7a25 vdiv.f32 s15, s12, s11 80029c4: ee76 7aa7 vadd.f32 s15, s13, s15 80029c8: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 80029cc: ee77 7aa6 vadd.f32 s15, s15, s13 80029d0: ee67 7a27 vmul.f32 s15, s14, s15 80029d4: edc7 7a09 vstr s15, [r7, #36] @ 0x24 break; 80029d8: bf00 nop } pllp = (((RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVP) >> RCC_PLL1DIVR1_DIVP_Pos) + 1U) ; 80029da: 4b18 ldr r3, [pc, #96] @ (8002a3c ) 80029dc: 6b1b ldr r3, [r3, #48] @ 0x30 80029de: 0a5b lsrs r3, r3, #9 80029e0: f003 037f and.w r3, r3, #127 @ 0x7f 80029e4: 3301 adds r3, #1 80029e6: 60bb str r3, [r7, #8] sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp); 80029e8: 68bb ldr r3, [r7, #8] 80029ea: ee07 3a90 vmov s15, r3 80029ee: eeb8 7a67 vcvt.f32.u32 s14, s15 80029f2: edd7 6a09 vldr s13, [r7, #36] @ 0x24 80029f6: eec6 7a87 vdiv.f32 s15, s13, s14 80029fa: eefc 7ae7 vcvt.u32.f32 s15, s15 80029fe: ee17 3a90 vmov r3, s15 8002a02: 623b str r3, [r7, #32] } else { sysclockfreq = 0U; } break; 8002a04: e005 b.n 8002a12 sysclockfreq = 0U; 8002a06: 2300 movs r3, #0 8002a08: 623b str r3, [r7, #32] break; 8002a0a: e002 b.n 8002a12 default: sysclockfreq = CSI_VALUE; 8002a0c: 4b0d ldr r3, [pc, #52] @ (8002a44 ) 8002a0e: 623b str r3, [r7, #32] break; 8002a10: bf00 nop } prescaler = RCC->CDCFGR & RCC_CDCFGR_CPRE; 8002a12: 4b0a ldr r3, [pc, #40] @ (8002a3c ) 8002a14: 699b ldr r3, [r3, #24] 8002a16: f003 030f and.w r3, r3, #15 8002a1a: 607b str r3, [r7, #4] if (prescaler >= 8U) 8002a1c: 687b ldr r3, [r7, #4] 8002a1e: 2b07 cmp r3, #7 8002a20: d905 bls.n 8002a2e { sysclockfreq = sysclockfreq >> (prescaler - RCC_CDCFGR_CPRE_3 + 1U); 8002a22: 687b ldr r3, [r7, #4] 8002a24: 3b07 subs r3, #7 8002a26: 6a3a ldr r2, [r7, #32] 8002a28: fa22 f303 lsr.w r3, r2, r3 8002a2c: 623b str r3, [r7, #32] } return sysclockfreq; 8002a2e: 6a3b ldr r3, [r7, #32] } 8002a30: 4618 mov r0, r3 8002a32: 372c adds r7, #44 @ 0x2c 8002a34: 46bd mov sp, r7 8002a36: f85d 7b04 ldr.w r7, [sp], #4 8002a3a: 4770 bx lr 8002a3c: 58024400 .word 0x58024400 8002a40: 03d09000 .word 0x03d09000 8002a44: 003d0900 .word 0x003d0900 8002a48: 016e3600 .word 0x016e3600 8002a4c: 46000000 .word 0x46000000 8002a50: 4a742400 .word 0x4a742400 8002a54: 4bb71b00 .word 0x4bb71b00 08002a58 : /** * @brief Return the HCLK frequency. * @retval HCLK frequency in Hz */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8002a58: b580 push {r7, lr} 8002a5a: b084 sub sp, #16 8002a5c: af00 add r7, sp, #0 uint32_t clock; uint32_t prescaler; const uint8_t AHBPrescTable[8] = {1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; 8002a5e: 4a10 ldr r2, [pc, #64] @ (8002aa0 ) 8002a60: 463b mov r3, r7 8002a62: e892 0003 ldmia.w r2, {r0, r1} 8002a66: e883 0003 stmia.w r3, {r0, r1} /* SysClk */ clock = HAL_RCC_GetSysClockFreq(); 8002a6a: f7ff fe8f bl 800278c 8002a6e: 60f8 str r0, [r7, #12] /* Bus matrix divider */ prescaler = (RCC->BMCFGR & RCC_BMCFGR_BMPRE) >> RCC_BMCFGR_BMPRE_Pos; 8002a70: 4b0c ldr r3, [pc, #48] @ (8002aa4 ) 8002a72: 69db ldr r3, [r3, #28] 8002a74: f003 030f and.w r3, r3, #15 8002a78: 60bb str r3, [r7, #8] if (prescaler >= 8U) 8002a7a: 68bb ldr r3, [r7, #8] 8002a7c: 2b07 cmp r3, #7 8002a7e: d909 bls.n 8002a94 { clock = clock >> AHBPrescTable[prescaler - 8U]; 8002a80: 68bb ldr r3, [r7, #8] 8002a82: 3b08 subs r3, #8 8002a84: 3310 adds r3, #16 8002a86: 443b add r3, r7 8002a88: f813 3c10 ldrb.w r3, [r3, #-16] 8002a8c: 461a mov r2, r3 8002a8e: 68fb ldr r3, [r7, #12] 8002a90: 40d3 lsrs r3, r2 8002a92: 60fb str r3, [r7, #12] } return (clock); 8002a94: 68fb ldr r3, [r7, #12] } 8002a96: 4618 mov r0, r3 8002a98: 3710 adds r7, #16 8002a9a: 46bd mov sp, r7 8002a9c: bd80 pop {r7, pc} 8002a9e: bf00 nop 8002aa0: 0800a120 .word 0x0800a120 8002aa4: 58024400 .word 0x58024400 08002aa8 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency in Hz */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8002aa8: b580 push {r7, lr} 8002aaa: b082 sub sp, #8 8002aac: af00 add r7, sp, #0 uint32_t clock; uint32_t prescaler; /* Get HCLK source and compute PCLK1 frequency ---------------------------*/ clock = HAL_RCC_GetHCLKFreq(); 8002aae: f7ff ffd3 bl 8002a58 8002ab2: 6078 str r0, [r7, #4] /* APB1 prescaler */ prescaler = (RCC->APBCFGR & RCC_APBCFGR_PPRE1) >> RCC_APBCFGR_PPRE1_Pos; 8002ab4: 4b09 ldr r3, [pc, #36] @ (8002adc ) 8002ab6: 6a1b ldr r3, [r3, #32] 8002ab8: f003 0307 and.w r3, r3, #7 8002abc: 603b str r3, [r7, #0] if (prescaler >= 4U) 8002abe: 683b ldr r3, [r7, #0] 8002ac0: 2b03 cmp r3, #3 8002ac2: d905 bls.n 8002ad0 { clock = clock >> (prescaler - 3U); 8002ac4: 683b ldr r3, [r7, #0] 8002ac6: 3b03 subs r3, #3 8002ac8: 687a ldr r2, [r7, #4] 8002aca: fa22 f303 lsr.w r3, r2, r3 8002ace: 607b str r3, [r7, #4] } return (clock); 8002ad0: 687b ldr r3, [r7, #4] } 8002ad2: 4618 mov r0, r3 8002ad4: 3708 adds r7, #8 8002ad6: 46bd mov sp, r7 8002ad8: bd80 pop {r7, pc} 8002ada: bf00 nop 8002adc: 58024400 .word 0x58024400 08002ae0 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency in Hz */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8002ae0: b580 push {r7, lr} 8002ae2: b082 sub sp, #8 8002ae4: af00 add r7, sp, #0 uint32_t clock; uint32_t prescaler; /* Get HCLK source and compute PCLK2 frequency ---------------------------*/ clock = HAL_RCC_GetHCLKFreq(); 8002ae6: f7ff ffb7 bl 8002a58 8002aea: 6078 str r0, [r7, #4] /* APB2 prescaler */ prescaler = (RCC->APBCFGR & RCC_APBCFGR_PPRE2) >> RCC_APBCFGR_PPRE2_Pos; 8002aec: 4b09 ldr r3, [pc, #36] @ (8002b14 ) 8002aee: 6a1b ldr r3, [r3, #32] 8002af0: 091b lsrs r3, r3, #4 8002af2: f003 0307 and.w r3, r3, #7 8002af6: 603b str r3, [r7, #0] if (prescaler >= 4U) 8002af8: 683b ldr r3, [r7, #0] 8002afa: 2b03 cmp r3, #3 8002afc: d905 bls.n 8002b0a { clock = clock >> (prescaler - 3U); 8002afe: 683b ldr r3, [r7, #0] 8002b00: 3b03 subs r3, #3 8002b02: 687a ldr r2, [r7, #4] 8002b04: fa22 f303 lsr.w r3, r2, r3 8002b08: 607b str r3, [r7, #4] } return (clock); 8002b0a: 687b ldr r3, [r7, #4] } 8002b0c: 4618 mov r0, r3 8002b0e: 3708 adds r7, #8 8002b10: 46bd mov sp, r7 8002b12: bd80 pop {r7, pc} 8002b14: 58024400 .word 0x58024400 08002b18 : * @note Each time PCLK4 changes, this function must be called to update the * right PCLK4 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK4 frequency in Hz */ uint32_t HAL_RCC_GetPCLK4Freq(void) { 8002b18: b580 push {r7, lr} 8002b1a: b082 sub sp, #8 8002b1c: af00 add r7, sp, #0 uint32_t clock; uint32_t prescaler; /* Get HCLK source and compute PCLK4 frequency ---------------------------*/ clock = HAL_RCC_GetHCLKFreq(); 8002b1e: f7ff ff9b bl 8002a58 8002b22: 6078 str r0, [r7, #4] /* APB4 prescaler */ prescaler = (RCC->APBCFGR & RCC_APBCFGR_PPRE4) >> RCC_APBCFGR_PPRE4_Pos; 8002b24: 4b09 ldr r3, [pc, #36] @ (8002b4c ) 8002b26: 6a1b ldr r3, [r3, #32] 8002b28: 0a1b lsrs r3, r3, #8 8002b2a: f003 0307 and.w r3, r3, #7 8002b2e: 603b str r3, [r7, #0] if (prescaler >= 4U) 8002b30: 683b ldr r3, [r7, #0] 8002b32: 2b03 cmp r3, #3 8002b34: d905 bls.n 8002b42 { clock = clock >> (prescaler - 3U); 8002b36: 683b ldr r3, [r7, #0] 8002b38: 3b03 subs r3, #3 8002b3a: 687a ldr r2, [r7, #4] 8002b3c: fa22 f303 lsr.w r3, r2, r3 8002b40: 607b str r3, [r7, #4] } return (clock); 8002b42: 687b ldr r3, [r7, #4] } 8002b44: 4618 mov r0, r3 8002b46: 3708 adds r7, #8 8002b48: 46bd mov sp, r7 8002b4a: bd80 pop {r7, pc} 8002b4c: 58024400 .word 0x58024400 08002b50 : /** * @brief Return the PLL1Q frequency. * @retval PLL1Q frequency in Hz */ uint32_t HAL_RCC_GetPLL1QFreq(void) { 8002b50: b580 push {r7, lr} 8002b52: b082 sub sp, #8 8002b54: af00 add r7, sp, #0 uint32_t pllq; /* PLL1Q divider */ pllq = ((RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVQ) >> RCC_PLL1DIVR1_DIVQ_Pos) + 1U; 8002b56: 4b08 ldr r3, [pc, #32] @ (8002b78 ) 8002b58: 6b1b ldr r3, [r3, #48] @ 0x30 8002b5a: 0c1b lsrs r3, r3, #16 8002b5c: f003 037f and.w r3, r3, #127 @ 0x7f 8002b60: 3301 adds r3, #1 8002b62: 607b str r3, [r7, #4] /* Compute VCO output frequency and return PLL1Q one */ return ((uint32_t)RCC_PLL1_GetVCOOutputFreq() / pllq); 8002b64: f000 fa28 bl 8002fb8 8002b68: 4602 mov r2, r0 8002b6a: 687b ldr r3, [r7, #4] 8002b6c: fbb2 f3f3 udiv r3, r2, r3 } 8002b70: 4618 mov r0, r3 8002b72: 3708 adds r7, #8 8002b74: 46bd mov sp, r7 8002b76: bd80 pop {r7, pc} 8002b78: 58024400 .word 0x58024400 08002b7c : /** * @brief Return the PLL2P frequency. * @retval PLL2P frequency in Hz */ uint32_t HAL_RCC_GetPLL2PFreq(void) { 8002b7c: b580 push {r7, lr} 8002b7e: b082 sub sp, #8 8002b80: af00 add r7, sp, #0 uint32_t pllp; /* PLL2P divider */ pllp = ((RCC->PLL2DIVR1 & RCC_PLL2DIVR1_DIVP) >> RCC_PLL2DIVR1_DIVP_Pos) + 1U; 8002b82: 4b08 ldr r3, [pc, #32] @ (8002ba4 ) 8002b84: 6b9b ldr r3, [r3, #56] @ 0x38 8002b86: 0a5b lsrs r3, r3, #9 8002b88: f003 037f and.w r3, r3, #127 @ 0x7f 8002b8c: 3301 adds r3, #1 8002b8e: 607b str r3, [r7, #4] /* Compute VCO output frequency and return PLL2P one */ return ((uint32_t)RCC_PLL2_GetVCOOutputFreq() / pllp); 8002b90: f000 fa98 bl 80030c4 8002b94: 4602 mov r2, r0 8002b96: 687b ldr r3, [r7, #4] 8002b98: fbb2 f3f3 udiv r3, r2, r3 } 8002b9c: 4618 mov r0, r3 8002b9e: 3708 adds r7, #8 8002ba0: 46bd mov sp, r7 8002ba2: bd80 pop {r7, pc} 8002ba4: 58024400 .word 0x58024400 08002ba8 : /** * @brief Return the PLL2Q frequency. * @retval PLL2Q frequency in Hz */ uint32_t HAL_RCC_GetPLL2QFreq(void) { 8002ba8: b580 push {r7, lr} 8002baa: b082 sub sp, #8 8002bac: af00 add r7, sp, #0 uint32_t pllq; /* PLL2Q divider */ pllq = ((RCC->PLL2DIVR1 & RCC_PLL2DIVR1_DIVQ) >> RCC_PLL2DIVR1_DIVQ_Pos) + 1U; 8002bae: 4b08 ldr r3, [pc, #32] @ (8002bd0 ) 8002bb0: 6b9b ldr r3, [r3, #56] @ 0x38 8002bb2: 0c1b lsrs r3, r3, #16 8002bb4: f003 037f and.w r3, r3, #127 @ 0x7f 8002bb8: 3301 adds r3, #1 8002bba: 607b str r3, [r7, #4] /* Compute VCO output frequency and return PLL2Q one */ return ((uint32_t)RCC_PLL2_GetVCOOutputFreq() / pllq); 8002bbc: f000 fa82 bl 80030c4 8002bc0: 4602 mov r2, r0 8002bc2: 687b ldr r3, [r7, #4] 8002bc4: fbb2 f3f3 udiv r3, r2, r3 } 8002bc8: 4618 mov r0, r3 8002bca: 3708 adds r7, #8 8002bcc: 46bd mov sp, r7 8002bce: bd80 pop {r7, pc} 8002bd0: 58024400 .word 0x58024400 08002bd4 : /** * @brief Return the PLL2R frequency. * @retval PLL2R frequency in Hz */ uint32_t HAL_RCC_GetPLL2RFreq(void) { 8002bd4: b580 push {r7, lr} 8002bd6: b082 sub sp, #8 8002bd8: af00 add r7, sp, #0 uint32_t pllr; /* PLL2R divider */ pllr = ((RCC->PLL2DIVR1 & RCC_PLL2DIVR1_DIVR) >> RCC_PLL2DIVR1_DIVR_Pos) + 1U; 8002bda: 4b08 ldr r3, [pc, #32] @ (8002bfc ) 8002bdc: 6b9b ldr r3, [r3, #56] @ 0x38 8002bde: 0e1b lsrs r3, r3, #24 8002be0: f003 037f and.w r3, r3, #127 @ 0x7f 8002be4: 3301 adds r3, #1 8002be6: 607b str r3, [r7, #4] /* Compute VCO output frequency and return PLL2R one */ return ((uint32_t)RCC_PLL2_GetVCOOutputFreq() / pllr); 8002be8: f000 fa6c bl 80030c4 8002bec: 4602 mov r2, r0 8002bee: 687b ldr r3, [r7, #4] 8002bf0: fbb2 f3f3 udiv r3, r2, r3 } 8002bf4: 4618 mov r0, r3 8002bf6: 3708 adds r7, #8 8002bf8: 46bd mov sp, r7 8002bfa: bd80 pop {r7, pc} 8002bfc: 58024400 .word 0x58024400 08002c00 : /** * @brief Return the PLL2S frequency. * @retval PLL2S frequency in Hz */ uint32_t HAL_RCC_GetPLL2SFreq(void) { 8002c00: b580 push {r7, lr} 8002c02: b082 sub sp, #8 8002c04: af00 add r7, sp, #0 uint32_t plls; /* PLL2S divider */ plls = ((RCC->PLL2DIVR2 & RCC_PLL2DIVR2_DIVS) >> RCC_PLL2DIVR2_DIVS_Pos) + 1U; 8002c06: 4b08 ldr r3, [pc, #32] @ (8002c28 ) 8002c08: f8d3 30c4 ldr.w r3, [r3, #196] @ 0xc4 8002c0c: f003 0307 and.w r3, r3, #7 8002c10: 3301 adds r3, #1 8002c12: 607b str r3, [r7, #4] /* Compute VCO output frequency and return PLL2R one */ return ((uint32_t)RCC_PLL2_GetVCOOutputFreq() / plls); 8002c14: f000 fa56 bl 80030c4 8002c18: 4602 mov r2, r0 8002c1a: 687b ldr r3, [r7, #4] 8002c1c: fbb2 f3f3 udiv r3, r2, r3 } 8002c20: 4618 mov r0, r3 8002c22: 3708 adds r7, #8 8002c24: 46bd mov sp, r7 8002c26: bd80 pop {r7, pc} 8002c28: 58024400 .word 0x58024400 08002c2c : /** * @brief Return the PLL2T frequency. * @retval PLL2T frequency in Hz */ uint32_t HAL_RCC_GetPLL2TFreq(void) { 8002c2c: b580 push {r7, lr} 8002c2e: b082 sub sp, #8 8002c30: af00 add r7, sp, #0 uint32_t pllt; /* PLL2T divider */ pllt = ((RCC->PLL2DIVR2 & RCC_PLL2DIVR2_DIVT) >> RCC_PLL2DIVR2_DIVT_Pos) + 1U; 8002c32: 4b09 ldr r3, [pc, #36] @ (8002c58 ) 8002c34: f8d3 30c4 ldr.w r3, [r3, #196] @ 0xc4 8002c38: 0a1b lsrs r3, r3, #8 8002c3a: f003 0307 and.w r3, r3, #7 8002c3e: 3301 adds r3, #1 8002c40: 607b str r3, [r7, #4] /* Compute VCO output frequency and return PLL2T one */ return ((uint32_t)RCC_PLL2_GetVCOOutputFreq() / pllt); 8002c42: f000 fa3f bl 80030c4 8002c46: 4602 mov r2, r0 8002c48: 687b ldr r3, [r7, #4] 8002c4a: fbb2 f3f3 udiv r3, r2, r3 } 8002c4e: 4618 mov r0, r3 8002c50: 3708 adds r7, #8 8002c52: 46bd mov sp, r7 8002c54: bd80 pop {r7, pc} 8002c56: bf00 nop 8002c58: 58024400 .word 0x58024400 08002c5c : /** * @brief Return the PLL3P frequency. * @retval PLL3P frequency in Hz */ uint32_t HAL_RCC_GetPLL3PFreq(void) { 8002c5c: b580 push {r7, lr} 8002c5e: b082 sub sp, #8 8002c60: af00 add r7, sp, #0 uint32_t pllp; /* PLL3P divider */ pllp = ((RCC->PLL3DIVR1 & RCC_PLL3DIVR1_DIVP) >> RCC_PLL3DIVR1_DIVP_Pos) + 1U; 8002c62: 4b08 ldr r3, [pc, #32] @ (8002c84 ) 8002c64: 6c1b ldr r3, [r3, #64] @ 0x40 8002c66: 0a5b lsrs r3, r3, #9 8002c68: f003 037f and.w r3, r3, #127 @ 0x7f 8002c6c: 3301 adds r3, #1 8002c6e: 607b str r3, [r7, #4] /* Compute VCO output frequency and return PLL3P one */ return ((uint32_t)RCC_PLL3_GetVCOOutputFreq() / pllp); 8002c70: f000 faae bl 80031d0 8002c74: 4602 mov r2, r0 8002c76: 687b ldr r3, [r7, #4] 8002c78: fbb2 f3f3 udiv r3, r2, r3 } 8002c7c: 4618 mov r0, r3 8002c7e: 3708 adds r7, #8 8002c80: 46bd mov sp, r7 8002c82: bd80 pop {r7, pc} 8002c84: 58024400 .word 0x58024400 08002c88 : /** * @brief Return the PLL3Q frequency. * @retval PLL3Q frequency in Hz */ uint32_t HAL_RCC_GetPLL3QFreq(void) { 8002c88: b580 push {r7, lr} 8002c8a: b082 sub sp, #8 8002c8c: af00 add r7, sp, #0 uint32_t pllq; /* PLL3Q divider */ pllq = ((RCC->PLL3DIVR1 & RCC_PLL3DIVR1_DIVQ) >> RCC_PLL3DIVR1_DIVQ_Pos) + 1U; 8002c8e: 4b08 ldr r3, [pc, #32] @ (8002cb0 ) 8002c90: 6c1b ldr r3, [r3, #64] @ 0x40 8002c92: 0c1b lsrs r3, r3, #16 8002c94: f003 037f and.w r3, r3, #127 @ 0x7f 8002c98: 3301 adds r3, #1 8002c9a: 607b str r3, [r7, #4] /* Compute VCO output frequency and return PLL3Q one */ return ((uint32_t)RCC_PLL3_GetVCOOutputFreq() / pllq); 8002c9c: f000 fa98 bl 80031d0 8002ca0: 4602 mov r2, r0 8002ca2: 687b ldr r3, [r7, #4] 8002ca4: fbb2 f3f3 udiv r3, r2, r3 } 8002ca8: 4618 mov r0, r3 8002caa: 3708 adds r7, #8 8002cac: 46bd mov sp, r7 8002cae: bd80 pop {r7, pc} 8002cb0: 58024400 .word 0x58024400 08002cb4 : /** * @brief Return the PLL3R frequency. * @retval PLL3R frequency in Hz */ uint32_t HAL_RCC_GetPLL3RFreq(void) { 8002cb4: b580 push {r7, lr} 8002cb6: b082 sub sp, #8 8002cb8: af00 add r7, sp, #0 uint32_t pllr; /* PLL3R divider */ pllr = ((RCC->PLL3DIVR1 & RCC_PLL3DIVR1_DIVR) >> RCC_PLL3DIVR1_DIVR_Pos) + 1U; 8002cba: 4b08 ldr r3, [pc, #32] @ (8002cdc ) 8002cbc: 6c1b ldr r3, [r3, #64] @ 0x40 8002cbe: 0e1b lsrs r3, r3, #24 8002cc0: f003 037f and.w r3, r3, #127 @ 0x7f 8002cc4: 3301 adds r3, #1 8002cc6: 607b str r3, [r7, #4] /* Compute VCO output frequency and return PLL3R one */ return ((uint32_t)RCC_PLL3_GetVCOOutputFreq() / pllr); 8002cc8: f000 fa82 bl 80031d0 8002ccc: 4602 mov r2, r0 8002cce: 687b ldr r3, [r7, #4] 8002cd0: fbb2 f3f3 udiv r3, r2, r3 } 8002cd4: 4618 mov r0, r3 8002cd6: 3708 adds r7, #8 8002cd8: 46bd mov sp, r7 8002cda: bd80 pop {r7, pc} 8002cdc: 58024400 .word 0x58024400 08002ce0 : /** * @brief Return the PLL3S frequency. * @retval PLL3S frequency in Hz */ uint32_t HAL_RCC_GetPLL3SFreq(void) { 8002ce0: b580 push {r7, lr} 8002ce2: b082 sub sp, #8 8002ce4: af00 add r7, sp, #0 uint32_t plls; /* PLL3S divider */ plls = ((RCC->PLL3DIVR2 & RCC_PLL3DIVR2_DIVS) >> RCC_PLL3DIVR2_DIVS_Pos) + 1U; 8002ce6: 4b08 ldr r3, [pc, #32] @ (8002d08 ) 8002ce8: f8d3 30c8 ldr.w r3, [r3, #200] @ 0xc8 8002cec: f003 0307 and.w r3, r3, #7 8002cf0: 3301 adds r3, #1 8002cf2: 607b str r3, [r7, #4] /* Compute VCO output frequency and return PLL3S one */ return ((uint32_t)RCC_PLL3_GetVCOOutputFreq() / plls); 8002cf4: f000 fa6c bl 80031d0 8002cf8: 4602 mov r2, r0 8002cfa: 687b ldr r3, [r7, #4] 8002cfc: fbb2 f3f3 udiv r3, r2, r3 } 8002d00: 4618 mov r0, r3 8002d02: 3708 adds r7, #8 8002d04: 46bd mov sp, r7 8002d06: bd80 pop {r7, pc} 8002d08: 58024400 .word 0x58024400 08002d0c : * @note PLL is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCC_PLL_Config(uint32_t PLLnumber, const RCC_PLLInitTypeDef *pPLLInit) { 8002d0c: b580 push {r7, lr} 8002d0e: b08a sub sp, #40 @ 0x28 8002d10: af00 add r7, sp, #0 8002d12: 6078 str r0, [r7, #4] 8002d14: 6039 str r1, [r7, #0] __IO uint32_t *p_rcc_pll_divr1_reg; __IO uint32_t *p_rcc_pll_divr2_reg; __IO uint32_t *p_rcc_pll_fracr_reg; HAL_StatusTypeDef ret = HAL_OK; 8002d16: 2300 movs r3, #0 8002d18: f887 3023 strb.w r3, [r7, #35] @ 0x23 uint32_t tickstart; uint32_t pllsrc; uint32_t pllvco; p_rcc_pll_divr1_reg = &(RCC->PLL1DIVR1) + (((uint32_t)0x02) * PLLnumber); 8002d1c: 687b ldr r3, [r7, #4] 8002d1e: 00da lsls r2, r3, #3 8002d20: 4b9a ldr r3, [pc, #616] @ (8002f8c ) 8002d22: 4413 add r3, r2 8002d24: 61fb str r3, [r7, #28] p_rcc_pll_divr2_reg = &(RCC->PLL1DIVR2) + (((uint32_t)0x01) * PLLnumber); 8002d26: 687b ldr r3, [r7, #4] 8002d28: 009a lsls r2, r3, #2 8002d2a: 4b99 ldr r3, [pc, #612] @ (8002f90 ) 8002d2c: 4413 add r3, r2 8002d2e: 61bb str r3, [r7, #24] /* Disable the post-dividers */ CLEAR_BIT(RCC->PLLCFGR, (RCC_PLLCFGR_PLL1PEN | RCC_PLLCFGR_PLL1QEN | RCC_PLLCFGR_PLL1REN | RCC_PLLCFGR_PLL1SEN | 8002d30: 4b98 ldr r3, [pc, #608] @ (8002f94 ) 8002d32: 6ad9 ldr r1, [r3, #44] @ 0x2c 8002d34: 687a ldr r2, [r7, #4] 8002d36: 4613 mov r3, r2 8002d38: 009b lsls r3, r3, #2 8002d3a: 4413 add r3, r2 8002d3c: 005b lsls r3, r3, #1 8002d3e: 4413 add r3, r2 8002d40: f44f 7278 mov.w r2, #992 @ 0x3e0 8002d44: fa02 f303 lsl.w r3, r2, r3 8002d48: 43db mvns r3, r3 8002d4a: 4a92 ldr r2, [pc, #584] @ (8002f94 ) 8002d4c: 400b ands r3, r1 8002d4e: 62d3 str r3, [r2, #44] @ 0x2c 0x00000200U) /* Hardcoded because no definition in CMSIS */ << ((RCC_PLLCFGR_PLL2PEN_Pos - RCC_PLLCFGR_PLL1PEN_Pos)*PLLnumber)); /* Ensure PLLx is disabled */ CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON << ((RCC_CR_PLL2ON_Pos - RCC_CR_PLL1ON_Pos)*PLLnumber)); 8002d50: 4b90 ldr r3, [pc, #576] @ (8002f94 ) 8002d52: 681a ldr r2, [r3, #0] 8002d54: 687b ldr r3, [r7, #4] 8002d56: 005b lsls r3, r3, #1 8002d58: f04f 7180 mov.w r1, #16777216 @ 0x1000000 8002d5c: fa01 f303 lsl.w r3, r1, r3 8002d60: 43db mvns r3, r3 8002d62: 498c ldr r1, [pc, #560] @ (8002f94 ) 8002d64: 4013 ands r3, r2 8002d66: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002d68: f7fd ffc2 bl 8000cf0 8002d6c: 6178 str r0, [r7, #20] /* Wait till PLLx is disabled */ while (READ_BIT(RCC->CR, (RCC_CR_PLL1RDY << ((RCC_CR_PLL2RDY_Pos - RCC_CR_PLL1RDY_Pos)*PLLnumber))) != 0U) 8002d6e: e008 b.n 8002d82 { if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE) 8002d70: f7fd ffbe bl 8000cf0 8002d74: 4602 mov r2, r0 8002d76: 697b ldr r3, [r7, #20] 8002d78: 1ad3 subs r3, r2, r3 8002d7a: 2b32 cmp r3, #50 @ 0x32 8002d7c: d901 bls.n 8002d82 { return HAL_TIMEOUT; 8002d7e: 2303 movs r3, #3 8002d80: e0ff b.n 8002f82 while (READ_BIT(RCC->CR, (RCC_CR_PLL1RDY << ((RCC_CR_PLL2RDY_Pos - RCC_CR_PLL1RDY_Pos)*PLLnumber))) != 0U) 8002d82: 4b84 ldr r3, [pc, #528] @ (8002f94 ) 8002d84: 681a ldr r2, [r3, #0] 8002d86: 687b ldr r3, [r7, #4] 8002d88: 005b lsls r3, r3, #1 8002d8a: f04f 7100 mov.w r1, #33554432 @ 0x2000000 8002d8e: fa01 f303 lsl.w r3, r1, r3 8002d92: 4013 ands r3, r2 8002d94: 2b00 cmp r3, #0 8002d96: d1eb bne.n 8002d70 } } if (pPLLInit->PLLState == RCC_PLL_ON) 8002d98: 683b ldr r3, [r7, #0] 8002d9a: 681b ldr r3, [r3, #0] 8002d9c: 2b02 cmp r3, #2 8002d9e: f040 80dd bne.w 8002f5c assert_param(IS_RCC_PLLQ_VALUE(pPLLInit->PLLQ)); assert_param(IS_RCC_PLLR_VALUE(pPLLInit->PLLR)); assert_param(IS_RCC_PLLS_VALUE(pPLLInit->PLLS)); assert_param(IS_RCC_PLLT_VALUE(pPLLInit->PLLT)); pllsrc = pPLLInit->PLLSource; 8002da2: 683b ldr r3, [r7, #0] 8002da4: 685b ldr r3, [r3, #4] 8002da6: 613b str r3, [r7, #16] /* Compute VCO input frequency and define range accordingly. First check clock source frequency */ if (pllsrc == RCC_PLLSOURCE_HSI) 8002da8: 693b ldr r3, [r7, #16] 8002daa: 2b00 cmp r3, #0 8002dac: d109 bne.n 8002dc2 { /* Clock source is HSI or HSI/HSIDIV */ pllvco = HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos); 8002dae: 4b79 ldr r3, [pc, #484] @ (8002f94 ) 8002db0: 681b ldr r3, [r3, #0] 8002db2: 08db lsrs r3, r3, #3 8002db4: f003 0303 and.w r3, r3, #3 8002db8: 4a77 ldr r2, [pc, #476] @ (8002f98 ) 8002dba: fa22 f303 lsr.w r3, r2, r3 8002dbe: 627b str r3, [r7, #36] @ 0x24 8002dc0: e007 b.n 8002dd2 } else if (pllsrc == RCC_PLLSOURCE_HSE) 8002dc2: 693b ldr r3, [r7, #16] 8002dc4: 2b02 cmp r3, #2 8002dc6: d102 bne.n 8002dce { /* Clock source is HSE */ pllvco = HSE_VALUE; 8002dc8: 4b74 ldr r3, [pc, #464] @ (8002f9c ) 8002dca: 627b str r3, [r7, #36] @ 0x24 8002dcc: e001 b.n 8002dd2 } else { /* Clock source is CSI */ pllvco = CSI_VALUE; 8002dce: 4b74 ldr r3, [pc, #464] @ (8002fa0 ) 8002dd0: 627b str r3, [r7, #36] @ 0x24 } /* Compute VCO input frequency depending on M divider */ pllvco = (pllvco / pPLLInit->PLLM); 8002dd2: 683b ldr r3, [r7, #0] 8002dd4: 689b ldr r3, [r3, #8] 8002dd6: 6a7a ldr r2, [r7, #36] @ 0x24 8002dd8: fbb2 f3f3 udiv r3, r2, r3 8002ddc: 627b str r3, [r7, #36] @ 0x24 assert_param(IS_RCC_PLL_VCOINPUTFREQ(pllvco)); if (pllvco >= RCC_PLL_INPUTRANGE2_FREQMAX) 8002dde: 6a7b ldr r3, [r7, #36] @ 0x24 8002de0: 4a70 ldr r2, [pc, #448] @ (8002fa4 ) 8002de2: 4293 cmp r3, r2 8002de4: d302 bcc.n 8002dec { pllvco = RCC_PLL_VCOINPUT_RANGE3 | RCC_PLL_VCO_HIGH; 8002de6: 2318 movs r3, #24 8002de8: 627b str r3, [r7, #36] @ 0x24 8002dea: e00f b.n 8002e0c } else if (pllvco >= RCC_PLL_INPUTRANGE1_FREQMAX) 8002dec: 6a7b ldr r3, [r7, #36] @ 0x24 8002dee: 4a6e ldr r2, [pc, #440] @ (8002fa8 ) 8002df0: 4293 cmp r3, r2 8002df2: d902 bls.n 8002dfa { pllvco = RCC_PLL_VCOINPUT_RANGE2 | RCC_PLL_VCO_HIGH; 8002df4: 2310 movs r3, #16 8002df6: 627b str r3, [r7, #36] @ 0x24 8002df8: e008 b.n 8002e0c } else if (pllvco >= RCC_PLL_INPUTRANGE0_FREQMAX) 8002dfa: 6a7b ldr r3, [r7, #36] @ 0x24 8002dfc: 4a6b ldr r2, [pc, #428] @ (8002fac ) 8002dfe: 4293 cmp r3, r2 8002e00: d902 bls.n 8002e08 { pllvco = RCC_PLL_VCOINPUT_RANGE1 | RCC_PLL_VCO_HIGH; 8002e02: 2308 movs r3, #8 8002e04: 627b str r3, [r7, #36] @ 0x24 8002e06: e001 b.n 8002e0c } else { pllvco = RCC_PLL_VCOINPUT_RANGE0 | RCC_PLL_VCO_LOW; 8002e08: 2302 movs r3, #2 8002e0a: 627b str r3, [r7, #36] @ 0x24 } pllvco = (pllvco << ((RCC_PLLCFGR_PLL2RGE_Pos - RCC_PLLCFGR_PLL1RGE_Pos) * PLLnumber)); 8002e0c: 687a ldr r2, [r7, #4] 8002e0e: 4613 mov r3, r2 8002e10: 009b lsls r3, r3, #2 8002e12: 4413 add r3, r2 8002e14: 005b lsls r3, r3, #1 8002e16: 4413 add r3, r2 8002e18: 6a7a ldr r2, [r7, #36] @ 0x24 8002e1a: fa02 f303 lsl.w r3, r2, r3 8002e1e: 627b str r3, [r7, #36] @ 0x24 /* Configure PLL source and PLLM divider */ MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_PLLSRC | (RCC_PLLCKSELR_DIVM1 << ((RCC_PLLCKSELR_DIVM2_Pos - RCC_PLLCKSELR_DIVM1_Pos)*PLLnumber))), \ 8002e20: 4b5c ldr r3, [pc, #368] @ (8002f94 ) 8002e22: 6a9a ldr r2, [r3, #40] @ 0x28 8002e24: 687b ldr r3, [r7, #4] 8002e26: 00db lsls r3, r3, #3 8002e28: f44f 717c mov.w r1, #1008 @ 0x3f0 8002e2c: fa01 f303 lsl.w r3, r1, r3 8002e30: f043 0303 orr.w r3, r3, #3 8002e34: 43db mvns r3, r3 8002e36: 401a ands r2, r3 8002e38: 683b ldr r3, [r7, #0] 8002e3a: 6899 ldr r1, [r3, #8] 8002e3c: 687b ldr r3, [r7, #4] 8002e3e: 00db lsls r3, r3, #3 8002e40: 3304 adds r3, #4 8002e42: 4099 lsls r1, r3 8002e44: 693b ldr r3, [r7, #16] 8002e46: 430b orrs r3, r1 8002e48: 4952 ldr r1, [pc, #328] @ (8002f94 ) 8002e4a: 4313 orrs r3, r2 8002e4c: 628b str r3, [r1, #40] @ 0x28 pllsrc | (pPLLInit->PLLM << (RCC_PLLCKSELR_DIVM1_Pos + ((RCC_PLLCKSELR_DIVM2_Pos - RCC_PLLCKSELR_DIVM1_Pos)*PLLnumber)))); if ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) != pllsrc) 8002e4e: 4b51 ldr r3, [pc, #324] @ (8002f94 ) 8002e50: 6a9b ldr r3, [r3, #40] @ 0x28 8002e52: f003 0303 and.w r3, r3, #3 8002e56: 693a ldr r2, [r7, #16] 8002e58: 429a cmp r2, r3 8002e5a: d001 beq.n 8002e60 { /* There is another PLL activated with another source */ return HAL_ERROR; 8002e5c: 2301 movs r3, #1 8002e5e: e090 b.n 8002f82 } /* Configure VCO input range, VCO selection and clear FRACEN */ MODIFY_REG(RCC->PLLCFGR, (RCC_PLLCFGR_PLL1RGE | RCC_PLLCFGR_PLL1VCOSEL | RCC_PLLCFGR_PLL1FRACEN) << (((RCC_PLLCFGR_PLL2RGE_Pos - RCC_PLLCFGR_PLL1RGE_Pos)*PLLnumber)), \ 8002e60: 4b4c ldr r3, [pc, #304] @ (8002f94 ) 8002e62: 6ad9 ldr r1, [r3, #44] @ 0x2c 8002e64: 687a ldr r2, [r7, #4] 8002e66: 4613 mov r3, r2 8002e68: 009b lsls r3, r3, #2 8002e6a: 4413 add r3, r2 8002e6c: 005b lsls r3, r3, #1 8002e6e: 4413 add r3, r2 8002e70: 221b movs r2, #27 8002e72: fa02 f303 lsl.w r3, r2, r3 8002e76: 43db mvns r3, r3 8002e78: ea01 0203 and.w r2, r1, r3 8002e7c: 4945 ldr r1, [pc, #276] @ (8002f94 ) 8002e7e: 6a7b ldr r3, [r7, #36] @ 0x24 8002e80: 4313 orrs r3, r2 8002e82: 62cb str r3, [r1, #44] @ 0x2c pllvco); /* Configure PLLN, PLLP, PLLQ, PLLR, PLLS and PLLT dividers */ WRITE_REG(*p_rcc_pll_divr1_reg, ((pPLLInit->PLLN - 1U) | 8002e84: 683b ldr r3, [r7, #0] 8002e86: 68db ldr r3, [r3, #12] 8002e88: 1e5a subs r2, r3, #1 8002e8a: 683b ldr r3, [r7, #0] 8002e8c: 691b ldr r3, [r3, #16] 8002e8e: 3b01 subs r3, #1 8002e90: 025b lsls r3, r3, #9 8002e92: 431a orrs r2, r3 8002e94: 683b ldr r3, [r7, #0] 8002e96: 695b ldr r3, [r3, #20] 8002e98: 3b01 subs r3, #1 8002e9a: 041b lsls r3, r3, #16 8002e9c: 431a orrs r2, r3 8002e9e: 683b ldr r3, [r7, #0] 8002ea0: 699b ldr r3, [r3, #24] 8002ea2: 3b01 subs r3, #1 8002ea4: 061b lsls r3, r3, #24 8002ea6: 431a orrs r2, r3 8002ea8: 69fb ldr r3, [r7, #28] 8002eaa: 601a str r2, [r3, #0] ((pPLLInit->PLLP - 1U) << RCC_PLL1DIVR1_DIVP_Pos) | ((pPLLInit->PLLQ - 1U) << RCC_PLL1DIVR1_DIVQ_Pos) | ((pPLLInit->PLLR - 1U) << RCC_PLL1DIVR1_DIVR_Pos))); WRITE_REG(*p_rcc_pll_divr2_reg, ((pPLLInit->PLLS - 1U) | 8002eac: 683b ldr r3, [r7, #0] 8002eae: 69db ldr r3, [r3, #28] 8002eb0: 1e5a subs r2, r3, #1 8002eb2: 683b ldr r3, [r7, #0] 8002eb4: 6a1b ldr r3, [r3, #32] 8002eb6: 3b01 subs r3, #1 8002eb8: 021b lsls r3, r3, #8 8002eba: 431a orrs r2, r3 8002ebc: 69bb ldr r3, [r7, #24] 8002ebe: 601a str r2, [r3, #0] ((pPLLInit->PLLT - 1U) << RCC_PLL2DIVR2_DIVT_Pos))); if (PLLnumber == RCC_PLL1_CONFIG) 8002ec0: 687b ldr r3, [r7, #4] 8002ec2: 2b00 cmp r3, #0 8002ec4: d105 bne.n 8002ed2 { SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1PEN); 8002ec6: 4b33 ldr r3, [pc, #204] @ (8002f94 ) 8002ec8: 6adb ldr r3, [r3, #44] @ 0x2c 8002eca: 4a32 ldr r2, [pc, #200] @ (8002f94 ) 8002ecc: f043 0320 orr.w r3, r3, #32 8002ed0: 62d3 str r3, [r2, #44] @ 0x2c } if (pPLLInit->PLLFractional != 0U) 8002ed2: 683b ldr r3, [r7, #0] 8002ed4: 6a5b ldr r3, [r3, #36] @ 0x24 8002ed6: 2b00 cmp r3, #0 8002ed8: d01c beq.n 8002f14 { assert_param(IS_RCC_PLLFRACN_VALUE(pPLLInit->PLLFractional)); p_rcc_pll_fracr_reg = &(RCC->PLL1FRACR) + (((uint32_t)0x02) * PLLnumber); 8002eda: 687b ldr r3, [r7, #4] 8002edc: 00da lsls r2, r3, #3 8002ede: 4b34 ldr r3, [pc, #208] @ (8002fb0 ) 8002ee0: 4413 add r3, r2 8002ee2: 60fb str r3, [r7, #12] /* Configure PLLFRACN */ MODIFY_REG(*p_rcc_pll_fracr_reg, RCC_PLL1FRACR_FRACN, pPLLInit->PLLFractional << RCC_PLL1FRACR_FRACN_Pos); 8002ee4: 68fb ldr r3, [r7, #12] 8002ee6: 681a ldr r2, [r3, #0] 8002ee8: 4b32 ldr r3, [pc, #200] @ (8002fb4 ) 8002eea: 4013 ands r3, r2 8002eec: 683a ldr r2, [r7, #0] 8002eee: 6a52 ldr r2, [r2, #36] @ 0x24 8002ef0: 00d2 lsls r2, r2, #3 8002ef2: 431a orrs r2, r3 8002ef4: 68fb ldr r3, [r7, #12] 8002ef6: 601a str r2, [r3, #0] /* Enable PLLFRACLE */ SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN << ((RCC_PLLCFGR_PLL2FRACEN_Pos - RCC_PLLCFGR_PLL1FRACEN_Pos)*PLLnumber)); 8002ef8: 4b26 ldr r3, [pc, #152] @ (8002f94 ) 8002efa: 6ad9 ldr r1, [r3, #44] @ 0x2c 8002efc: 687a ldr r2, [r7, #4] 8002efe: 4613 mov r3, r2 8002f00: 009b lsls r3, r3, #2 8002f02: 4413 add r3, r2 8002f04: 005b lsls r3, r3, #1 8002f06: 4413 add r3, r2 8002f08: 2201 movs r2, #1 8002f0a: fa02 f303 lsl.w r3, r2, r3 8002f0e: 4a21 ldr r2, [pc, #132] @ (8002f94 ) 8002f10: 430b orrs r3, r1 8002f12: 62d3 str r3, [r2, #44] @ 0x2c } /* Enable the PLLx */ SET_BIT(RCC->CR, RCC_CR_PLL1ON << ((RCC_CR_PLL2ON_Pos - RCC_CR_PLL1ON_Pos)*PLLnumber)); 8002f14: 4b1f ldr r3, [pc, #124] @ (8002f94 ) 8002f16: 681a ldr r2, [r3, #0] 8002f18: 687b ldr r3, [r7, #4] 8002f1a: 005b lsls r3, r3, #1 8002f1c: f04f 7180 mov.w r1, #16777216 @ 0x1000000 8002f20: fa01 f303 lsl.w r3, r1, r3 8002f24: 491b ldr r1, [pc, #108] @ (8002f94 ) 8002f26: 4313 orrs r3, r2 8002f28: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002f2a: f7fd fee1 bl 8000cf0 8002f2e: 6178 str r0, [r7, #20] /* Wait till PLLx is ready */ while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY << ((RCC_CR_PLL2RDY_Pos - RCC_CR_PLL1RDY_Pos)*PLLnumber)) == 0U) 8002f30: e008 b.n 8002f44 { if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE) 8002f32: f7fd fedd bl 8000cf0 8002f36: 4602 mov r2, r0 8002f38: 697b ldr r3, [r7, #20] 8002f3a: 1ad3 subs r3, r2, r3 8002f3c: 2b32 cmp r3, #50 @ 0x32 8002f3e: d901 bls.n 8002f44 { return HAL_TIMEOUT; 8002f40: 2303 movs r3, #3 8002f42: e01e b.n 8002f82 while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY << ((RCC_CR_PLL2RDY_Pos - RCC_CR_PLL1RDY_Pos)*PLLnumber)) == 0U) 8002f44: 4b13 ldr r3, [pc, #76] @ (8002f94 ) 8002f46: 681a ldr r2, [r3, #0] 8002f48: 687b ldr r3, [r7, #4] 8002f4a: 005b lsls r3, r3, #1 8002f4c: f04f 7100 mov.w r1, #33554432 @ 0x2000000 8002f50: fa01 f303 lsl.w r3, r1, r3 8002f54: 4013 ands r3, r2 8002f56: 2b00 cmp r3, #0 8002f58: d0eb beq.n 8002f32 8002f5a: e010 b.n 8002f7e } } else { /* Disable outputs to save power when PLLx is off */ MODIFY_REG(RCC->PLLCKSELR, ((RCC_PLLCKSELR_DIVM1 << (RCC_PLLCKSELR_DIVM1_Pos + ((RCC_PLLCKSELR_DIVM2_Pos - RCC_PLLCKSELR_DIVM1_Pos)*PLLnumber))) 8002f5c: 4b0d ldr r3, [pc, #52] @ (8002f94 ) 8002f5e: 6a9a ldr r2, [r3, #40] @ 0x28 8002f60: 687b ldr r3, [r7, #4] 8002f62: 00db lsls r3, r3, #3 8002f64: 3304 adds r3, #4 8002f66: f44f 717c mov.w r1, #1008 @ 0x3f0 8002f6a: fa01 f303 lsl.w r3, r1, r3 8002f6e: f043 0303 orr.w r3, r3, #3 8002f72: 43db mvns r3, r3 8002f74: 4013 ands r3, r2 8002f76: 4a07 ldr r2, [pc, #28] @ (8002f94 ) 8002f78: f043 0303 orr.w r3, r3, #3 8002f7c: 6293 str r3, [r2, #40] @ 0x28 | RCC_PLLCKSELR_PLLSRC), RCC_PLLSOURCE_NONE); } return ret; 8002f7e: f897 3023 ldrb.w r3, [r7, #35] @ 0x23 } 8002f82: 4618 mov r0, r3 8002f84: 3728 adds r7, #40 @ 0x28 8002f86: 46bd mov sp, r7 8002f88: bd80 pop {r7, pc} 8002f8a: bf00 nop 8002f8c: 58024430 .word 0x58024430 8002f90: 580244c0 .word 0x580244c0 8002f94: 58024400 .word 0x58024400 8002f98: 03d09000 .word 0x03d09000 8002f9c: 016e3600 .word 0x016e3600 8002fa0: 003d0900 .word 0x003d0900 8002fa4: 007a1200 .word 0x007a1200 8002fa8: 003d08ff .word 0x003d08ff 8002fac: 001e847f .word 0x001e847f 8002fb0: 58024434 .word 0x58024434 8002fb4: ffff0007 .word 0xffff0007 08002fb8 : /** * @brief Compute PLL1 VCO output frequency * @retval Value of PLL1 VCO output frequency */ static uint32_t RCC_PLL1_GetVCOOutputFreq(void) { 8002fb8: b480 push {r7} 8002fba: b089 sub sp, #36 @ 0x24 8002fbc: af00 add r7, sp, #0 uint32_t plln; uint32_t pllfracn; float_t frequency; /* Get PLL1 CKSELR and DIVR register values */ tmpreg1 = RCC->PLLCKSELR; 8002fbe: 4b3c ldr r3, [pc, #240] @ (80030b0 ) 8002fc0: 6a9b ldr r3, [r3, #40] @ 0x28 8002fc2: 617b str r3, [r7, #20] tmpreg2 = RCC->PLL1DIVR1; 8002fc4: 4b3a ldr r3, [pc, #232] @ (80030b0 ) 8002fc6: 6b1b ldr r3, [r3, #48] @ 0x30 8002fc8: 613b str r3, [r7, #16] /* Retrieve PLL1 multiplication factor and divider */ pllm = (tmpreg1 & RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos; 8002fca: 697b ldr r3, [r7, #20] 8002fcc: 091b lsrs r3, r3, #4 8002fce: f003 033f and.w r3, r3, #63 @ 0x3f 8002fd2: 60fb str r3, [r7, #12] plln = (tmpreg2 & RCC_PLL1DIVR1_DIVN) + 1U; 8002fd4: 693b ldr r3, [r7, #16] 8002fd6: f3c3 0308 ubfx r3, r3, #0, #9 8002fda: 3301 adds r3, #1 8002fdc: 60bb str r3, [r7, #8] if (pllm == 0U) 8002fde: 68fb ldr r3, [r7, #12] 8002fe0: 2b00 cmp r3, #0 8002fe2: d101 bne.n 8002fe8 { /* Prescaler disabled */ return 0U; 8002fe4: 2300 movs r3, #0 8002fe6: e05c b.n 80030a2 } /* Check if fractional part is enable */ if ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) != 0U) 8002fe8: 4b31 ldr r3, [pc, #196] @ (80030b0 ) 8002fea: 6adb ldr r3, [r3, #44] @ 0x2c 8002fec: f003 0301 and.w r3, r3, #1 8002ff0: 2b00 cmp r3, #0 8002ff2: d006 beq.n 8003002 { pllfracn = (RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN) >> RCC_PLL1FRACR_FRACN_Pos; 8002ff4: 4b2e ldr r3, [pc, #184] @ (80030b0 ) 8002ff6: 6b5b ldr r3, [r3, #52] @ 0x34 8002ff8: 08db lsrs r3, r3, #3 8002ffa: f3c3 030c ubfx r3, r3, #0, #13 8002ffe: 61bb str r3, [r7, #24] 8003000: e001 b.n 8003006 } else { pllfracn = 0U; 8003002: 2300 movs r3, #0 8003004: 61bb str r3, [r7, #24] } /* determine PLL source */ switch (tmpreg1 & RCC_PLLCKSELR_PLLSRC) 8003006: 697b ldr r3, [r7, #20] 8003008: f003 0303 and.w r3, r3, #3 800300c: 2b02 cmp r3, #2 800300e: d019 beq.n 8003044 8003010: 2b02 cmp r3, #2 8003012: d81d bhi.n 8003050 8003014: 2b00 cmp r3, #0 8003016: d002 beq.n 800301e 8003018: 2b01 cmp r3, #1 800301a: d016 beq.n 800304a 800301c: e018 b.n 8003050 { /* HSI used as PLL1 clock source */ case RCC_PLLSOURCE_HSI: if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) 800301e: 4b24 ldr r3, [pc, #144] @ (80030b0 ) 8003020: 681b ldr r3, [r3, #0] 8003022: f003 0320 and.w r3, r3, #32 8003026: 2b00 cmp r3, #0 8003028: d009 beq.n 800303e { pllsrc = HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos); 800302a: 4b21 ldr r3, [pc, #132] @ (80030b0 ) 800302c: 681b ldr r3, [r3, #0] 800302e: 08db lsrs r3, r3, #3 8003030: f003 0303 and.w r3, r3, #3 8003034: 4a1f ldr r2, [pc, #124] @ (80030b4 ) 8003036: fa22 f303 lsr.w r3, r2, r3 800303a: 61fb str r3, [r7, #28] else { /* Can't retrieve HSIDIV value */ pllsrc = 0U; } break; 800303c: e00b b.n 8003056 pllsrc = 0U; 800303e: 2300 movs r3, #0 8003040: 61fb str r3, [r7, #28] break; 8003042: e008 b.n 8003056 /* HSE used as PLL1 clock source */ case RCC_PLLSOURCE_HSE: pllsrc = HSE_VALUE; 8003044: 4b1c ldr r3, [pc, #112] @ (80030b8 ) 8003046: 61fb str r3, [r7, #28] break; 8003048: e005 b.n 8003056 /* CSI used as PLL1 clock source */ case RCC_PLLSOURCE_CSI: pllsrc = CSI_VALUE; 800304a: 4b1c ldr r3, [pc, #112] @ (80030bc ) 800304c: 61fb str r3, [r7, #28] break; 800304e: e002 b.n 8003056 default: pllsrc = 0U; 8003050: 2300 movs r3, #0 8003052: 61fb str r3, [r7, #28] break; 8003054: bf00 nop } /* Compute VCO output frequency */ frequency = ((float_t)pllsrc / (float_t)pllm) * ((float_t)plln + ((float_t)pllfracn / (float_t)0x2000U)); 8003056: 69fb ldr r3, [r7, #28] 8003058: ee07 3a90 vmov s15, r3 800305c: eef8 6a67 vcvt.f32.u32 s13, s15 8003060: 68fb ldr r3, [r7, #12] 8003062: ee07 3a90 vmov s15, r3 8003066: eef8 7a67 vcvt.f32.u32 s15, s15 800306a: ee86 7aa7 vdiv.f32 s14, s13, s15 800306e: 68bb ldr r3, [r7, #8] 8003070: ee07 3a90 vmov s15, r3 8003074: eef8 6a67 vcvt.f32.u32 s13, s15 8003078: 69bb ldr r3, [r7, #24] 800307a: ee07 3a90 vmov s15, r3 800307e: eeb8 6a67 vcvt.f32.u32 s12, s15 8003082: eddf 5a0f vldr s11, [pc, #60] @ 80030c0 8003086: eec6 7a25 vdiv.f32 s15, s12, s11 800308a: ee76 7aa7 vadd.f32 s15, s13, s15 800308e: ee67 7a27 vmul.f32 s15, s14, s15 8003092: edc7 7a01 vstr s15, [r7, #4] return (uint32_t)frequency; 8003096: edd7 7a01 vldr s15, [r7, #4] 800309a: eefc 7ae7 vcvt.u32.f32 s15, s15 800309e: ee17 3a90 vmov r3, s15 } 80030a2: 4618 mov r0, r3 80030a4: 3724 adds r7, #36 @ 0x24 80030a6: 46bd mov sp, r7 80030a8: f85d 7b04 ldr.w r7, [sp], #4 80030ac: 4770 bx lr 80030ae: bf00 nop 80030b0: 58024400 .word 0x58024400 80030b4: 03d09000 .word 0x03d09000 80030b8: 016e3600 .word 0x016e3600 80030bc: 003d0900 .word 0x003d0900 80030c0: 46000000 .word 0x46000000 080030c4 : /** * @brief Compute PLL2 VCO output frequency * @retval Value of PLL2 VCO output frequency */ static uint32_t RCC_PLL2_GetVCOOutputFreq(void) { 80030c4: b480 push {r7} 80030c6: b089 sub sp, #36 @ 0x24 80030c8: af00 add r7, sp, #0 uint32_t plln; uint32_t pllfracn; float_t frequency; /* Get PLL2 CKSELR and DIVR register values */ tmpreg1 = RCC->PLLCKSELR; 80030ca: 4b3c ldr r3, [pc, #240] @ (80031bc ) 80030cc: 6a9b ldr r3, [r3, #40] @ 0x28 80030ce: 617b str r3, [r7, #20] tmpreg2 = RCC->PLL2DIVR1; 80030d0: 4b3a ldr r3, [pc, #232] @ (80031bc ) 80030d2: 6b9b ldr r3, [r3, #56] @ 0x38 80030d4: 613b str r3, [r7, #16] /* Retrieve PLL2 multiplication factor and divider */ pllm = (tmpreg1 & RCC_PLLCKSELR_DIVM2) >> RCC_PLLCKSELR_DIVM2_Pos; 80030d6: 697b ldr r3, [r7, #20] 80030d8: 0b1b lsrs r3, r3, #12 80030da: f003 033f and.w r3, r3, #63 @ 0x3f 80030de: 60fb str r3, [r7, #12] plln = (tmpreg2 & RCC_PLL2DIVR1_DIVN) + 1U; 80030e0: 693b ldr r3, [r7, #16] 80030e2: f3c3 0308 ubfx r3, r3, #0, #9 80030e6: 3301 adds r3, #1 80030e8: 60bb str r3, [r7, #8] if (pllm == 0U) 80030ea: 68fb ldr r3, [r7, #12] 80030ec: 2b00 cmp r3, #0 80030ee: d101 bne.n 80030f4 { /* Prescaler disabled */ return 0U; 80030f0: 2300 movs r3, #0 80030f2: e05c b.n 80031ae } /* Check if fractional part is enable */ if ((RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) != 0U) 80030f4: 4b31 ldr r3, [pc, #196] @ (80031bc ) 80030f6: 6adb ldr r3, [r3, #44] @ 0x2c 80030f8: f403 6300 and.w r3, r3, #2048 @ 0x800 80030fc: 2b00 cmp r3, #0 80030fe: d006 beq.n 800310e { pllfracn = (RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN) >> RCC_PLL2FRACR_FRACN_Pos; 8003100: 4b2e ldr r3, [pc, #184] @ (80031bc ) 8003102: 6bdb ldr r3, [r3, #60] @ 0x3c 8003104: 08db lsrs r3, r3, #3 8003106: f3c3 030c ubfx r3, r3, #0, #13 800310a: 61bb str r3, [r7, #24] 800310c: e001 b.n 8003112 } else { pllfracn = 0U; 800310e: 2300 movs r3, #0 8003110: 61bb str r3, [r7, #24] } /* determine PLL source */ switch (tmpreg1 & RCC_PLLCKSELR_PLLSRC) 8003112: 697b ldr r3, [r7, #20] 8003114: f003 0303 and.w r3, r3, #3 8003118: 2b02 cmp r3, #2 800311a: d019 beq.n 8003150 800311c: 2b02 cmp r3, #2 800311e: d81d bhi.n 800315c 8003120: 2b00 cmp r3, #0 8003122: d002 beq.n 800312a 8003124: 2b01 cmp r3, #1 8003126: d016 beq.n 8003156 8003128: e018 b.n 800315c { /* HSI used as PLL2 clock source */ case RCC_PLLSOURCE_HSI: if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) 800312a: 4b24 ldr r3, [pc, #144] @ (80031bc ) 800312c: 681b ldr r3, [r3, #0] 800312e: f003 0320 and.w r3, r3, #32 8003132: 2b00 cmp r3, #0 8003134: d009 beq.n 800314a { pllsrc = HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos); 8003136: 4b21 ldr r3, [pc, #132] @ (80031bc ) 8003138: 681b ldr r3, [r3, #0] 800313a: 08db lsrs r3, r3, #3 800313c: f003 0303 and.w r3, r3, #3 8003140: 4a1f ldr r2, [pc, #124] @ (80031c0 ) 8003142: fa22 f303 lsr.w r3, r2, r3 8003146: 61fb str r3, [r7, #28] else { /* Can't retrieve HSIDIV value */ pllsrc = 0U; } break; 8003148: e00b b.n 8003162 pllsrc = 0U; 800314a: 2300 movs r3, #0 800314c: 61fb str r3, [r7, #28] break; 800314e: e008 b.n 8003162 /* HSE used as PLL2 clock source */ case RCC_PLLSOURCE_HSE: pllsrc = HSE_VALUE; 8003150: 4b1c ldr r3, [pc, #112] @ (80031c4 ) 8003152: 61fb str r3, [r7, #28] break; 8003154: e005 b.n 8003162 /* CSI used as PLL2 clock source */ case RCC_PLLSOURCE_CSI: pllsrc = CSI_VALUE; 8003156: 4b1c ldr r3, [pc, #112] @ (80031c8 ) 8003158: 61fb str r3, [r7, #28] break; 800315a: e002 b.n 8003162 default: pllsrc = 0U; 800315c: 2300 movs r3, #0 800315e: 61fb str r3, [r7, #28] break; 8003160: bf00 nop } /* Compute VCO output frequency */ frequency = ((float_t)pllsrc / (float_t)pllm) * ((float_t)plln + ((float_t)pllfracn / (float_t)0x2000U)); 8003162: 69fb ldr r3, [r7, #28] 8003164: ee07 3a90 vmov s15, r3 8003168: eef8 6a67 vcvt.f32.u32 s13, s15 800316c: 68fb ldr r3, [r7, #12] 800316e: ee07 3a90 vmov s15, r3 8003172: eef8 7a67 vcvt.f32.u32 s15, s15 8003176: ee86 7aa7 vdiv.f32 s14, s13, s15 800317a: 68bb ldr r3, [r7, #8] 800317c: ee07 3a90 vmov s15, r3 8003180: eef8 6a67 vcvt.f32.u32 s13, s15 8003184: 69bb ldr r3, [r7, #24] 8003186: ee07 3a90 vmov s15, r3 800318a: eeb8 6a67 vcvt.f32.u32 s12, s15 800318e: eddf 5a0f vldr s11, [pc, #60] @ 80031cc 8003192: eec6 7a25 vdiv.f32 s15, s12, s11 8003196: ee76 7aa7 vadd.f32 s15, s13, s15 800319a: ee67 7a27 vmul.f32 s15, s14, s15 800319e: edc7 7a01 vstr s15, [r7, #4] return (uint32_t)frequency; 80031a2: edd7 7a01 vldr s15, [r7, #4] 80031a6: eefc 7ae7 vcvt.u32.f32 s15, s15 80031aa: ee17 3a90 vmov r3, s15 } 80031ae: 4618 mov r0, r3 80031b0: 3724 adds r7, #36 @ 0x24 80031b2: 46bd mov sp, r7 80031b4: f85d 7b04 ldr.w r7, [sp], #4 80031b8: 4770 bx lr 80031ba: bf00 nop 80031bc: 58024400 .word 0x58024400 80031c0: 03d09000 .word 0x03d09000 80031c4: 016e3600 .word 0x016e3600 80031c8: 003d0900 .word 0x003d0900 80031cc: 46000000 .word 0x46000000 080031d0 : /** * @brief Compute PLL3 VCO output frequency * @retval Value of PLL3 VCO output frequency */ static uint32_t RCC_PLL3_GetVCOOutputFreq(void) { 80031d0: b480 push {r7} 80031d2: b089 sub sp, #36 @ 0x24 80031d4: af00 add r7, sp, #0 uint32_t plln; uint32_t pllfracn; float_t frequency; /* Get PLL3 CKSELR and DIVR register values */ tmpreg1 = RCC->PLLCKSELR; 80031d6: 4b3c ldr r3, [pc, #240] @ (80032c8 ) 80031d8: 6a9b ldr r3, [r3, #40] @ 0x28 80031da: 617b str r3, [r7, #20] tmpreg2 = RCC->PLL3DIVR1; 80031dc: 4b3a ldr r3, [pc, #232] @ (80032c8 ) 80031de: 6c1b ldr r3, [r3, #64] @ 0x40 80031e0: 613b str r3, [r7, #16] /* Retrieve PLL3 multiplication factor and divider */ pllm = (tmpreg1 & RCC_PLLCKSELR_DIVM3) >> RCC_PLLCKSELR_DIVM3_Pos; 80031e2: 697b ldr r3, [r7, #20] 80031e4: 0d1b lsrs r3, r3, #20 80031e6: f003 033f and.w r3, r3, #63 @ 0x3f 80031ea: 60fb str r3, [r7, #12] plln = (tmpreg2 & RCC_PLL3DIVR1_DIVN) + 1U; 80031ec: 693b ldr r3, [r7, #16] 80031ee: f3c3 0308 ubfx r3, r3, #0, #9 80031f2: 3301 adds r3, #1 80031f4: 60bb str r3, [r7, #8] if (pllm == 0U) 80031f6: 68fb ldr r3, [r7, #12] 80031f8: 2b00 cmp r3, #0 80031fa: d101 bne.n 8003200 { /* Prescaler disabled */ return 0U; 80031fc: 2300 movs r3, #0 80031fe: e05c b.n 80032ba } /* Check if fractional part is enable */ if ((RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) != 0U) 8003200: 4b31 ldr r3, [pc, #196] @ (80032c8 ) 8003202: 6adb ldr r3, [r3, #44] @ 0x2c 8003204: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8003208: 2b00 cmp r3, #0 800320a: d006 beq.n 800321a { pllfracn = (RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN) >> RCC_PLL3FRACR_FRACN_Pos; 800320c: 4b2e ldr r3, [pc, #184] @ (80032c8 ) 800320e: 6c5b ldr r3, [r3, #68] @ 0x44 8003210: 08db lsrs r3, r3, #3 8003212: f3c3 030c ubfx r3, r3, #0, #13 8003216: 61bb str r3, [r7, #24] 8003218: e001 b.n 800321e } else { pllfracn = 0U; 800321a: 2300 movs r3, #0 800321c: 61bb str r3, [r7, #24] } /* determine PLL source */ switch (tmpreg1 & RCC_PLLCKSELR_PLLSRC) 800321e: 697b ldr r3, [r7, #20] 8003220: f003 0303 and.w r3, r3, #3 8003224: 2b02 cmp r3, #2 8003226: d019 beq.n 800325c 8003228: 2b02 cmp r3, #2 800322a: d81d bhi.n 8003268 800322c: 2b00 cmp r3, #0 800322e: d002 beq.n 8003236 8003230: 2b01 cmp r3, #1 8003232: d016 beq.n 8003262 8003234: e018 b.n 8003268 { /* HSI used as PLL3 clock source */ case RCC_PLLSOURCE_HSI: if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) 8003236: 4b24 ldr r3, [pc, #144] @ (80032c8 ) 8003238: 681b ldr r3, [r3, #0] 800323a: f003 0320 and.w r3, r3, #32 800323e: 2b00 cmp r3, #0 8003240: d009 beq.n 8003256 { pllsrc = HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos); 8003242: 4b21 ldr r3, [pc, #132] @ (80032c8 ) 8003244: 681b ldr r3, [r3, #0] 8003246: 08db lsrs r3, r3, #3 8003248: f003 0303 and.w r3, r3, #3 800324c: 4a1f ldr r2, [pc, #124] @ (80032cc ) 800324e: fa22 f303 lsr.w r3, r2, r3 8003252: 61fb str r3, [r7, #28] else { /* Can't retrieve HSIDIV value */ pllsrc = 0U; } break; 8003254: e00b b.n 800326e pllsrc = 0U; 8003256: 2300 movs r3, #0 8003258: 61fb str r3, [r7, #28] break; 800325a: e008 b.n 800326e /* HSE used as PLL3 clock source */ case RCC_PLLSOURCE_HSE: pllsrc = HSE_VALUE; 800325c: 4b1c ldr r3, [pc, #112] @ (80032d0 ) 800325e: 61fb str r3, [r7, #28] break; 8003260: e005 b.n 800326e /* CSI used as PLL3 clock source */ case RCC_PLLSOURCE_CSI: pllsrc = CSI_VALUE; 8003262: 4b1c ldr r3, [pc, #112] @ (80032d4 ) 8003264: 61fb str r3, [r7, #28] break; 8003266: e002 b.n 800326e default: pllsrc = 0U; 8003268: 2300 movs r3, #0 800326a: 61fb str r3, [r7, #28] break; 800326c: bf00 nop } /* Compute VCO output frequency */ frequency = ((float_t)pllsrc / (float_t)pllm) * ((float_t)plln + ((float_t)pllfracn / (float_t)0x2000U)); 800326e: 69fb ldr r3, [r7, #28] 8003270: ee07 3a90 vmov s15, r3 8003274: eef8 6a67 vcvt.f32.u32 s13, s15 8003278: 68fb ldr r3, [r7, #12] 800327a: ee07 3a90 vmov s15, r3 800327e: eef8 7a67 vcvt.f32.u32 s15, s15 8003282: ee86 7aa7 vdiv.f32 s14, s13, s15 8003286: 68bb ldr r3, [r7, #8] 8003288: ee07 3a90 vmov s15, r3 800328c: eef8 6a67 vcvt.f32.u32 s13, s15 8003290: 69bb ldr r3, [r7, #24] 8003292: ee07 3a90 vmov s15, r3 8003296: eeb8 6a67 vcvt.f32.u32 s12, s15 800329a: eddf 5a0f vldr s11, [pc, #60] @ 80032d8 800329e: eec6 7a25 vdiv.f32 s15, s12, s11 80032a2: ee76 7aa7 vadd.f32 s15, s13, s15 80032a6: ee67 7a27 vmul.f32 s15, s14, s15 80032aa: edc7 7a01 vstr s15, [r7, #4] return (uint32_t)frequency; 80032ae: edd7 7a01 vldr s15, [r7, #4] 80032b2: eefc 7ae7 vcvt.u32.f32 s15, s15 80032b6: ee17 3a90 vmov r3, s15 } 80032ba: 4618 mov r0, r3 80032bc: 3724 adds r7, #36 @ 0x24 80032be: 46bd mov sp, r7 80032c0: f85d 7b04 ldr.w r7, [sp], #4 80032c4: 4770 bx lr 80032c6: bf00 nop 80032c8: 58024400 .word 0x58024400 80032cc: 03d09000 .word 0x03d09000 80032d0: 016e3600 .word 0x016e3600 80032d4: 003d0900 .word 0x003d0900 80032d8: 46000000 .word 0x46000000 080032dc : * the backup registers) are set to their reset values. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 80032dc: b580 push {r7, lr} 80032de: b086 sub sp, #24 80032e0: af00 add r7, sp, #0 80032e2: 6078 str r0, [r7, #4] uint32_t tmpreg; uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 80032e4: 2300 movs r3, #0 80032e6: 75fb strb r3, [r7, #23] HAL_StatusTypeDef status = HAL_OK; /* Final status */ 80032e8: 2300 movs r3, #0 80032ea: 75bb strb r3, [r7, #22] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*---------------------------- RTC configuration -------------------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 80032ec: 687b ldr r3, [r7, #4] 80032ee: 681b ldr r3, [r3, #0] 80032f0: f403 2380 and.w r3, r3, #262144 @ 0x40000 80032f4: 2b00 cmp r3, #0 80032f6: f000 8081 beq.w 80033fc /* check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* As the RTC clock source selection can be changed only if the Backup Domain is reset */ /* reset the Backup domain only if the RTC Clock source selection is modified from default reset value */ tmpreg = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); 80032fa: 4b8c ldr r3, [pc, #560] @ (800352c ) 80032fc: 6f1b ldr r3, [r3, #112] @ 0x70 80032fe: f403 7340 and.w r3, r3, #768 @ 0x300 8003302: 613b str r3, [r7, #16] if ((tmpreg != RCC_RTCCLKSOURCE_DISABLE) && (tmpreg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 8003304: 693b ldr r3, [r7, #16] 8003306: 2b00 cmp r3, #0 8003308: d029 beq.n 800335e 800330a: 687b ldr r3, [r7, #4] 800330c: 6fdb ldr r3, [r3, #124] @ 0x7c 800330e: f403 7340 and.w r3, r3, #768 @ 0x300 8003312: 693a ldr r2, [r7, #16] 8003314: 429a cmp r2, r3 8003316: d022 beq.n 800335e { /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 8003318: 4b85 ldr r3, [pc, #532] @ (8003530 ) 800331a: 681b ldr r3, [r3, #0] 800331c: 4a84 ldr r2, [pc, #528] @ (8003530 ) 800331e: f443 7380 orr.w r3, r3, #256 @ 0x100 8003322: 6013 str r3, [r2, #0] /* Read back to check Backup domain enabled */ if (READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U) 8003324: 4b82 ldr r3, [pc, #520] @ (8003530 ) 8003326: 681b ldr r3, [r3, #0] 8003328: f403 7380 and.w r3, r3, #256 @ 0x100 800332c: 2b00 cmp r3, #0 800332e: d102 bne.n 8003336 { ret = HAL_ERROR; 8003330: 2301 movs r3, #1 8003332: 75fb strb r3, [r7, #23] 8003334: e013 b.n 800335e } else { /* Store the content of BDCR register before the reset of Backup Domain */ /* excepted the RTC clock source selection that will be changed */ tmpreg = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); 8003336: 4b7d ldr r3, [pc, #500] @ (800352c ) 8003338: 6f1b ldr r3, [r3, #112] @ 0x70 800333a: f423 7340 bic.w r3, r3, #768 @ 0x300 800333e: 613b str r3, [r7, #16] __HAL_RCC_BACKUPRESET_FORCE(); 8003340: 4b7a ldr r3, [pc, #488] @ (800352c ) 8003342: 6f1b ldr r3, [r3, #112] @ 0x70 8003344: 4a79 ldr r2, [pc, #484] @ (800352c ) 8003346: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800334a: 6713 str r3, [r2, #112] @ 0x70 __HAL_RCC_BACKUPRESET_RELEASE(); 800334c: 4b77 ldr r3, [pc, #476] @ (800352c ) 800334e: 6f1b ldr r3, [r3, #112] @ 0x70 8003350: 4a76 ldr r2, [pc, #472] @ (800352c ) 8003352: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8003356: 6713 str r3, [r2, #112] @ 0x70 /* Restore the content of BDCR register */ WRITE_REG(RCC->BDCR, tmpreg); 8003358: 4a74 ldr r2, [pc, #464] @ (800352c ) 800335a: 693b ldr r3, [r7, #16] 800335c: 6713 str r3, [r2, #112] @ 0x70 } } if (ret == HAL_OK) 800335e: 7dfb ldrb r3, [r7, #23] 8003360: 2b00 cmp r3, #0 8003362: d149 bne.n 80033f8 { /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */ if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) 8003364: 687b ldr r3, [r7, #4] 8003366: 6fdb ldr r3, [r3, #124] @ 0x7c 8003368: f5b3 7f80 cmp.w r3, #256 @ 0x100 800336c: d115 bne.n 800339a { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800336e: f7fd fcbf bl 8000cf0 8003372: 60f8 str r0, [r7, #12] /* Wait till LSE is ready */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 8003374: e00b b.n 800338e { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8003376: f7fd fcbb bl 8000cf0 800337a: 4602 mov r2, r0 800337c: 68fb ldr r3, [r7, #12] 800337e: 1ad3 subs r3, r2, r3 8003380: f241 3288 movw r2, #5000 @ 0x1388 8003384: 4293 cmp r3, r2 8003386: d902 bls.n 800338e { ret = HAL_TIMEOUT; 8003388: 2303 movs r3, #3 800338a: 75fb strb r3, [r7, #23] break; 800338c: e005 b.n 800339a while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 800338e: 4b67 ldr r3, [pc, #412] @ (800352c ) 8003390: 6f1b ldr r3, [r3, #112] @ 0x70 8003392: f003 0302 and.w r3, r3, #2 8003396: 2b00 cmp r3, #0 8003398: d0ed beq.n 8003376 } } } if (ret == HAL_OK) 800339a: 7dfb ldrb r3, [r7, #23] 800339c: 2b00 cmp r3, #0 800339e: d128 bne.n 80033f2 { __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 80033a0: 687b ldr r3, [r7, #4] 80033a2: 6fdb ldr r3, [r3, #124] @ 0x7c 80033a4: f403 337c and.w r3, r3, #258048 @ 0x3f000 80033a8: 2b00 cmp r3, #0 80033aa: d00c beq.n 80033c6 80033ac: 4b5f ldr r3, [pc, #380] @ (800352c ) 80033ae: 691b ldr r3, [r3, #16] 80033b0: f423 527c bic.w r2, r3, #16128 @ 0x3f00 80033b4: 687b ldr r3, [r7, #4] 80033b6: 6fdb ldr r3, [r3, #124] @ 0x7c 80033b8: 0919 lsrs r1, r3, #4 80033ba: 4b5e ldr r3, [pc, #376] @ (8003534 ) 80033bc: 400b ands r3, r1 80033be: 495b ldr r1, [pc, #364] @ (800352c ) 80033c0: 4313 orrs r3, r2 80033c2: 610b str r3, [r1, #16] 80033c4: e005 b.n 80033d2 80033c6: 4b59 ldr r3, [pc, #356] @ (800352c ) 80033c8: 691b ldr r3, [r3, #16] 80033ca: 4a58 ldr r2, [pc, #352] @ (800352c ) 80033cc: f423 537c bic.w r3, r3, #16128 @ 0x3f00 80033d0: 6113 str r3, [r2, #16] 80033d2: 4b56 ldr r3, [pc, #344] @ (800352c ) 80033d4: 6f1a ldr r2, [r3, #112] @ 0x70 80033d6: 687b ldr r3, [r7, #4] 80033d8: 6fdb ldr r3, [r3, #124] @ 0x7c 80033da: f403 7340 and.w r3, r3, #768 @ 0x300 80033de: 4953 ldr r1, [pc, #332] @ (800352c ) 80033e0: 4313 orrs r3, r2 80033e2: 670b str r3, [r1, #112] @ 0x70 __HAL_RCC_RTC_ENABLE(); 80033e4: 4b51 ldr r3, [pc, #324] @ (800352c ) 80033e6: 6f1b ldr r3, [r3, #112] @ 0x70 80033e8: 4a50 ldr r2, [pc, #320] @ (800352c ) 80033ea: f443 4300 orr.w r3, r3, #32768 @ 0x8000 80033ee: 6713 str r3, [r2, #112] @ 0x70 80033f0: e004 b.n 80033fc } else { /* set overall return value */ status = ret; 80033f2: 7dfb ldrb r3, [r7, #23] 80033f4: 75bb strb r3, [r7, #22] 80033f6: e001 b.n 80033fc } } else { /* set overall return value */ status = ret; 80033f8: 7dfb ldrb r3, [r7, #23] 80033fa: 75bb strb r3, [r7, #22] } } /*---------------------------- FMC configuration -------------------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) 80033fc: 687b ldr r3, [r7, #4] 80033fe: 681b ldr r3, [r3, #0] 8003400: f003 0301 and.w r3, r3, #1 8003404: 2b00 cmp r3, #0 8003406: d030 beq.n 800346a { /* Check the parameters */ assert_param(IS_RCC_FMCCLKSOURCE(PeriphClkInit->FmcClockSelection)); switch (PeriphClkInit->FmcClockSelection) 8003408: 687b ldr r3, [r7, #4] 800340a: 685b ldr r3, [r3, #4] 800340c: 2b03 cmp r3, #3 800340e: d819 bhi.n 8003444 8003410: a201 add r2, pc, #4 @ (adr r2, 8003418 ) 8003412: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8003416: bf00 nop 8003418: 0800344b .word 0x0800344b 800341c: 08003429 .word 0x08003429 8003420: 08003437 .word 0x08003437 8003424: 0800344b .word 0x0800344b case RCC_FMCCLKSOURCE_HCLK: /* HCLK clock selected as FMC kernel peripheral clock */ break; case RCC_FMCCLKSOURCE_PLL1Q: /* PLL1_Q is used as clock source for FMC kernel */ /* Enable FMC kernel clock output generated form System PLL . */ __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL_QCLK); 8003428: 4b40 ldr r3, [pc, #256] @ (800352c ) 800342a: 6adb ldr r3, [r3, #44] @ 0x2c 800342c: 4a3f ldr r2, [pc, #252] @ (800352c ) 800342e: f043 0340 orr.w r3, r3, #64 @ 0x40 8003432: 62d3 str r3, [r2, #44] @ 0x2c /* FMC kernel clock source configuration done later after clock selection check */ break; 8003434: e00a b.n 800344c case RCC_FMCCLKSOURCE_PLL2R: /* PLL2_R is used as clock source for FMC kernel */ __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_RCLK); 8003436: 4b3d ldr r3, [pc, #244] @ (800352c ) 8003438: 6adb ldr r3, [r3, #44] @ 0x2c 800343a: 4a3c ldr r2, [pc, #240] @ (800352c ) 800343c: f443 2380 orr.w r3, r3, #262144 @ 0x40000 8003440: 62d3 str r3, [r2, #44] @ 0x2c /* FMC kernel clock source configuration done later after clock selection check */ break; 8003442: e003 b.n 800344c case RCC_FMCCLKSOURCE_HSI: /* HSI oscillator is used as clock source for FMC kernel */ /* FMC kernel clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8003444: 2301 movs r3, #1 8003446: 75fb strb r3, [r7, #23] break; 8003448: e000 b.n 800344c break; 800344a: bf00 nop } if (ret == HAL_OK) 800344c: 7dfb ldrb r3, [r7, #23] 800344e: 2b00 cmp r3, #0 8003450: d109 bne.n 8003466 { /* Set the source of FMC kernel clock*/ __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection); 8003452: 4b36 ldr r3, [pc, #216] @ (800352c ) 8003454: 6cdb ldr r3, [r3, #76] @ 0x4c 8003456: f023 0203 bic.w r2, r3, #3 800345a: 687b ldr r3, [r7, #4] 800345c: 685b ldr r3, [r3, #4] 800345e: 4933 ldr r1, [pc, #204] @ (800352c ) 8003460: 4313 orrs r3, r2 8003462: 64cb str r3, [r1, #76] @ 0x4c 8003464: e001 b.n 800346a } else { /* set overall return value */ status = ret; 8003466: 7dfb ldrb r3, [r7, #23] 8003468: 75bb strb r3, [r7, #22] } } /*-------------------------- XSPI1 clock source configuration ----------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_XSPI1) == RCC_PERIPHCLK_XSPI1) 800346a: 687b ldr r3, [r7, #4] 800346c: 681b ldr r3, [r3, #0] 800346e: f003 0302 and.w r3, r3, #2 8003472: 2b00 cmp r3, #0 8003474: d02a beq.n 80034cc { /* Check the parameters */ assert_param(IS_RCC_XSPI1CLKSOURCE(PeriphClkInit->Xspi1ClockSelection)); switch (PeriphClkInit->Xspi1ClockSelection) 8003476: 687b ldr r3, [r7, #4] 8003478: 689b ldr r3, [r3, #8] 800347a: 2b20 cmp r3, #32 800347c: d00c beq.n 8003498 800347e: 2b20 cmp r3, #32 8003480: d811 bhi.n 80034a6 8003482: 2b00 cmp r3, #0 8003484: d012 beq.n 80034ac 8003486: 2b10 cmp r3, #16 8003488: d10d bne.n 80034a6 case RCC_XSPI1CLKSOURCE_HCLK: /* HCLK is used as clock source for Xspi1 */ /* Nothing to do */ break; case RCC_XSPI1CLKSOURCE_PLL2S: /* PLL2_S is used as clock source for Xspi1 */ __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_SCLK); 800348a: 4b28 ldr r3, [pc, #160] @ (800352c ) 800348c: 6adb ldr r3, [r3, #44] @ 0x2c 800348e: 4a27 ldr r2, [pc, #156] @ (800352c ) 8003490: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8003494: 62d3 str r3, [r2, #44] @ 0x2c /* XSPI1 clock source configuration done later after clock selection check */ break; 8003496: e00a b.n 80034ae case RCC_XSPI1CLKSOURCE_PLL2T: /* PLL2_T is used as clock source for Xspi1 */ __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_TCLK); 8003498: 4b24 ldr r3, [pc, #144] @ (800352c ) 800349a: 6adb ldr r3, [r3, #44] @ 0x2c 800349c: 4a23 ldr r2, [pc, #140] @ (800352c ) 800349e: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 80034a2: 62d3 str r3, [r2, #44] @ 0x2c /* XSPI1 clock source configuration done later after clock selection check */ break; 80034a4: e003 b.n 80034ae default: ret = HAL_ERROR; 80034a6: 2301 movs r3, #1 80034a8: 75fb strb r3, [r7, #23] break; 80034aa: e000 b.n 80034ae break; 80034ac: bf00 nop } if (ret == HAL_OK) 80034ae: 7dfb ldrb r3, [r7, #23] 80034b0: 2b00 cmp r3, #0 80034b2: d109 bne.n 80034c8 { /* Configure the XSPI1 clock source */ __HAL_RCC_XSPI1_CONFIG(PeriphClkInit->Xspi1ClockSelection); 80034b4: 4b1d ldr r3, [pc, #116] @ (800352c ) 80034b6: 6cdb ldr r3, [r3, #76] @ 0x4c 80034b8: f023 0230 bic.w r2, r3, #48 @ 0x30 80034bc: 687b ldr r3, [r7, #4] 80034be: 689b ldr r3, [r3, #8] 80034c0: 491a ldr r1, [pc, #104] @ (800352c ) 80034c2: 4313 orrs r3, r2 80034c4: 64cb str r3, [r1, #76] @ 0x4c 80034c6: e001 b.n 80034cc } else { /* set overall return value */ status = ret; 80034c8: 7dfb ldrb r3, [r7, #23] 80034ca: 75bb strb r3, [r7, #22] } } /*-------------------------- XSPI2 clock source configuration ----------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_XSPI2) == RCC_PERIPHCLK_XSPI2) 80034cc: 687b ldr r3, [r7, #4] 80034ce: 681b ldr r3, [r3, #0] 80034d0: f003 0304 and.w r3, r3, #4 80034d4: 2b00 cmp r3, #0 80034d6: d031 beq.n 800353c { /* Check the parameters */ assert_param(IS_RCC_XSPI2CLKSOURCE(PeriphClkInit->Xspi2ClockSelection)); switch (PeriphClkInit->Xspi2ClockSelection) 80034d8: 687b ldr r3, [r7, #4] 80034da: 68db ldr r3, [r3, #12] 80034dc: 2b80 cmp r3, #128 @ 0x80 80034de: d00c beq.n 80034fa 80034e0: 2b80 cmp r3, #128 @ 0x80 80034e2: d811 bhi.n 8003508 80034e4: 2b00 cmp r3, #0 80034e6: d012 beq.n 800350e 80034e8: 2b40 cmp r3, #64 @ 0x40 80034ea: d10d bne.n 8003508 case RCC_XSPI2CLKSOURCE_HCLK: /* HCLK is used as clock source for Xspi2 */ /* Nothing to do */ break; case RCC_XSPI2CLKSOURCE_PLL2S: /* PLL2_S is used as clock source for Xspi2 */ __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_SCLK); 80034ec: 4b0f ldr r3, [pc, #60] @ (800352c ) 80034ee: 6adb ldr r3, [r3, #44] @ 0x2c 80034f0: 4a0e ldr r2, [pc, #56] @ (800352c ) 80034f2: f443 2300 orr.w r3, r3, #524288 @ 0x80000 80034f6: 62d3 str r3, [r2, #44] @ 0x2c /* XSPI2 clock source configuration done later after clock selection check */ break; 80034f8: e00a b.n 8003510 case RCC_XSPI2CLKSOURCE_PLL2T: /* PLL2_T is used as clock source for Xspi2 */ __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_TCLK); 80034fa: 4b0c ldr r3, [pc, #48] @ (800352c ) 80034fc: 6adb ldr r3, [r3, #44] @ 0x2c 80034fe: 4a0b ldr r2, [pc, #44] @ (800352c ) 8003500: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8003504: 62d3 str r3, [r2, #44] @ 0x2c /* XSPI2 clock source configuration done later after clock selection check */ break; 8003506: e003 b.n 8003510 default: ret = HAL_ERROR; 8003508: 2301 movs r3, #1 800350a: 75fb strb r3, [r7, #23] break; 800350c: e000 b.n 8003510 break; 800350e: bf00 nop } if (ret == HAL_OK) 8003510: 7dfb ldrb r3, [r7, #23] 8003512: 2b00 cmp r3, #0 8003514: d110 bne.n 8003538 { /* Configure the XSPI2 clock source */ __HAL_RCC_XSPI2_CONFIG(PeriphClkInit->Xspi2ClockSelection); 8003516: 4b05 ldr r3, [pc, #20] @ (800352c ) 8003518: 6cdb ldr r3, [r3, #76] @ 0x4c 800351a: f023 02c0 bic.w r2, r3, #192 @ 0xc0 800351e: 687b ldr r3, [r7, #4] 8003520: 68db ldr r3, [r3, #12] 8003522: 4902 ldr r1, [pc, #8] @ (800352c ) 8003524: 4313 orrs r3, r2 8003526: 64cb str r3, [r1, #76] @ 0x4c 8003528: e008 b.n 800353c 800352a: bf00 nop 800352c: 58024400 .word 0x58024400 8003530: 58024800 .word 0x58024800 8003534: 0fffffcf .word 0x0fffffcf } else { /* set overall return value */ status = ret; 8003538: 7dfb ldrb r3, [r7, #23] 800353a: 75bb strb r3, [r7, #22] } } /*------------------------------------ CKPER configuration --------------------------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) 800353c: 687b ldr r3, [r7, #4] 800353e: 681b ldr r3, [r3, #0] 8003540: f003 0308 and.w r3, r3, #8 8003544: 2b00 cmp r3, #0 8003546: d008 beq.n 800355a { /* Check the parameters */ assert_param(IS_RCC_CKPERCLKSOURCE(PeriphClkInit->CkperClockSelection)); /* Configure the CKPER clock source */ __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection); 8003548: 4b93 ldr r3, [pc, #588] @ (8003798 ) 800354a: 6cdb ldr r3, [r3, #76] @ 0x4c 800354c: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000 8003550: 687b ldr r3, [r7, #4] 8003552: 691b ldr r3, [r3, #16] 8003554: 4990 ldr r1, [pc, #576] @ (8003798 ) 8003556: 4313 orrs r3, r2 8003558: 64cb str r3, [r1, #76] @ 0x4c } /*------------------------------------- SDMMC12 Configuration ------------------------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SDMMC12) == RCC_PERIPHCLK_SDMMC12) 800355a: 687b ldr r3, [r7, #4] 800355c: 681b ldr r3, [r3, #0] 800355e: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8003562: 2b00 cmp r3, #0 8003564: d026 beq.n 80035b4 { /* Check the parameters */ assert_param(IS_RCC_SDMMC12CLKSOURCE(PeriphClkInit->Sdmmc12ClockSelection)); switch (PeriphClkInit->Sdmmc12ClockSelection) 8003566: 687b ldr r3, [r7, #4] 8003568: 6d5b ldr r3, [r3, #84] @ 0x54 800356a: 2b00 cmp r3, #0 800356c: d002 beq.n 8003574 800356e: 2b04 cmp r3, #4 8003570: d007 beq.n 8003582 8003572: e00d b.n 8003590 { case RCC_SDMMC12CLKSOURCE_PLL2S: /* PLL2_S is used as clock source for SDMMC12 kernel */ __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_SCLK); 8003574: 4b88 ldr r3, [pc, #544] @ (8003798 ) 8003576: 6adb ldr r3, [r3, #44] @ 0x2c 8003578: 4a87 ldr r2, [pc, #540] @ (8003798 ) 800357a: f443 2300 orr.w r3, r3, #524288 @ 0x80000 800357e: 62d3 str r3, [r2, #44] @ 0x2c /* SDMMC12 kernel clock source configuration done later after clock selection check */ break; 8003580: e009 b.n 8003596 case RCC_SDMMC12CLKSOURCE_PLL2T: /* PLL2_T is used as clock source for SDMMC12 kernel */ __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_TCLK); 8003582: 4b85 ldr r3, [pc, #532] @ (8003798 ) 8003584: 6adb ldr r3, [r3, #44] @ 0x2c 8003586: 4a84 ldr r2, [pc, #528] @ (8003798 ) 8003588: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 800358c: 62d3 str r3, [r2, #44] @ 0x2c /* SDMMC12 kernel clock source configuration done later after clock selection check */ break; 800358e: e002 b.n 8003596 default: ret = HAL_ERROR; 8003590: 2301 movs r3, #1 8003592: 75fb strb r3, [r7, #23] break; 8003594: bf00 nop } if (ret == HAL_OK) 8003596: 7dfb ldrb r3, [r7, #23] 8003598: 2b00 cmp r3, #0 800359a: d109 bne.n 80035b0 { /* Set the source of SDMMC12 clock*/ __HAL_RCC_SDMMC12_CONFIG(PeriphClkInit->Sdmmc12ClockSelection); 800359c: 4b7e ldr r3, [pc, #504] @ (8003798 ) 800359e: 6cdb ldr r3, [r3, #76] @ 0x4c 80035a0: f023 0204 bic.w r2, r3, #4 80035a4: 687b ldr r3, [r7, #4] 80035a6: 6d5b ldr r3, [r3, #84] @ 0x54 80035a8: 497b ldr r1, [pc, #492] @ (8003798 ) 80035aa: 4313 orrs r3, r2 80035ac: 64cb str r3, [r1, #76] @ 0x4c 80035ae: e001 b.n 80035b4 } else { /* set overall return value */ status = ret; 80035b0: 7dfb ldrb r3, [r7, #23] 80035b2: 75bb strb r3, [r7, #22] } } /*---------------------------- ADC configuration -------------------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 80035b4: 687b ldr r3, [r7, #4] 80035b6: 681b ldr r3, [r3, #0] 80035b8: f003 0310 and.w r3, r3, #16 80035bc: 2b00 cmp r3, #0 80035be: d02e beq.n 800361e { /* Check the parameters */ assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); switch (PeriphClkInit->AdcClockSelection) 80035c0: 687b ldr r3, [r7, #4] 80035c2: 695b ldr r3, [r3, #20] 80035c4: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 80035c8: d019 beq.n 80035fe 80035ca: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 80035ce: d813 bhi.n 80035f8 80035d0: 2b00 cmp r3, #0 80035d2: d003 beq.n 80035dc 80035d4: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 80035d8: d007 beq.n 80035ea 80035da: e00d b.n 80035f8 { case RCC_ADCCLKSOURCE_PLL2P: /* PLL2_P is used as clock source for ADC */ __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_PCLK); 80035dc: 4b6e ldr r3, [pc, #440] @ (8003798 ) 80035de: 6adb ldr r3, [r3, #44] @ 0x2c 80035e0: 4a6d ldr r2, [pc, #436] @ (8003798 ) 80035e2: f443 3380 orr.w r3, r3, #65536 @ 0x10000 80035e6: 62d3 str r3, [r2, #44] @ 0x2c /* ADC clock source configuration done later after clock selection check */ break; 80035e8: e00a b.n 8003600 case RCC_ADCCLKSOURCE_PLL3R: /* PLL3_R is used as clock source for ADC */ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_RCLK); 80035ea: 4b6b ldr r3, [pc, #428] @ (8003798 ) 80035ec: 6adb ldr r3, [r3, #44] @ 0x2c 80035ee: 4a6a ldr r2, [pc, #424] @ (8003798 ) 80035f0: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 80035f4: 62d3 str r3, [r2, #44] @ 0x2c /* ADC clock source configuration done later after clock selection check */ break; 80035f6: e003 b.n 8003600 /* HSI, HSE, or CSI oscillator is used as source of ADC clock */ /* ADC clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80035f8: 2301 movs r3, #1 80035fa: 75fb strb r3, [r7, #23] break; 80035fc: e000 b.n 8003600 break; 80035fe: bf00 nop } if (ret == HAL_OK) 8003600: 7dfb ldrb r3, [r7, #23] 8003602: 2b00 cmp r3, #0 8003604: d109 bne.n 800361a { /* Set the source of ADC clock*/ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 8003606: 4b64 ldr r3, [pc, #400] @ (8003798 ) 8003608: 6cdb ldr r3, [r3, #76] @ 0x4c 800360a: f023 7240 bic.w r2, r3, #50331648 @ 0x3000000 800360e: 687b ldr r3, [r7, #4] 8003610: 695b ldr r3, [r3, #20] 8003612: 4961 ldr r1, [pc, #388] @ (8003798 ) 8003614: 4313 orrs r3, r2 8003616: 64cb str r3, [r1, #76] @ 0x4c 8003618: e001 b.n 800361e } else { /* set overall return value */ status = ret; 800361a: 7dfb ldrb r3, [r7, #23] 800361c: 75bb strb r3, [r7, #22] } } /*---------------------------- ADF1 configuration --------------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ADF1) == RCC_PERIPHCLK_ADF1) 800361e: 687b ldr r3, [r7, #4] 8003620: 681b ldr r3, [r3, #0] 8003622: f003 0320 and.w r3, r3, #32 8003626: 2b00 cmp r3, #0 8003628: d03f beq.n 80036aa { /* Check the parameters */ assert_param(IS_RCC_ADF1CLKSOURCE(PeriphClkInit->Adf1ClockSelection)); switch (PeriphClkInit->Adf1ClockSelection) 800362a: 687b ldr r3, [r7, #4] 800362c: 699b ldr r3, [r3, #24] 800362e: f5b3 0fa0 cmp.w r3, #5242880 @ 0x500000 8003632: d02a beq.n 800368a 8003634: f5b3 0fa0 cmp.w r3, #5242880 @ 0x500000 8003638: d824 bhi.n 8003684 800363a: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800363e: d024 beq.n 800368a 8003640: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8003644: d81e bhi.n 8003684 8003646: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800364a: d01e beq.n 800368a 800364c: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 8003650: d818 bhi.n 8003684 8003652: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 8003656: d00e beq.n 8003676 8003658: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800365c: d812 bhi.n 8003684 800365e: 2b00 cmp r3, #0 8003660: d013 beq.n 800368a 8003662: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8003666: d10d bne.n 8003684 { case RCC_ADF1CLKSOURCE_PLL2P: /* PLL2_P is used as clock source for ADF1 */ __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_PCLK); 8003668: 4b4b ldr r3, [pc, #300] @ (8003798 ) 800366a: 6adb ldr r3, [r3, #44] @ 0x2c 800366c: 4a4a ldr r2, [pc, #296] @ (8003798 ) 800366e: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8003672: 62d3 str r3, [r2, #44] @ 0x2c /* ADF1 clock source configuration done later after clock selection check */ break; 8003674: e00a b.n 800368c case RCC_ADF1CLKSOURCE_PLL3P: /* PLL3_P is used as clock source for ADF1 */ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_PCLK); 8003676: 4b48 ldr r3, [pc, #288] @ (8003798 ) 8003678: 6adb ldr r3, [r3, #44] @ 0x2c 800367a: 4a47 ldr r2, [pc, #284] @ (8003798 ) 800367c: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 8003680: 62d3 str r3, [r2, #44] @ 0x2c /* ADF1 clock source configuration done later after clock selection check */ break; 8003682: e003 b.n 800368c case RCC_ADF1CLKSOURCE_HSI: /* HSI is used as clock source for ADF1 */ /* ADF1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8003684: 2301 movs r3, #1 8003686: 75fb strb r3, [r7, #23] break; 8003688: e000 b.n 800368c break; 800368a: bf00 nop } if (ret == HAL_OK) 800368c: 7dfb ldrb r3, [r7, #23] 800368e: 2b00 cmp r3, #0 8003690: d109 bne.n 80036a6 { /* Set the source of ADF1 clock*/ __HAL_RCC_ADF1_CONFIG(PeriphClkInit->Adf1ClockSelection); 8003692: 4b41 ldr r3, [pc, #260] @ (8003798 ) 8003694: 6cdb ldr r3, [r3, #76] @ 0x4c 8003696: f423 02e0 bic.w r2, r3, #7340032 @ 0x700000 800369a: 687b ldr r3, [r7, #4] 800369c: 699b ldr r3, [r3, #24] 800369e: 493e ldr r1, [pc, #248] @ (8003798 ) 80036a0: 4313 orrs r3, r2 80036a2: 64cb str r3, [r1, #76] @ 0x4c 80036a4: e001 b.n 80036aa } else { /* set overall return value */ status = ret; 80036a6: 7dfb ldrb r3, [r7, #23] 80036a8: 75bb strb r3, [r7, #22] } } /*---------------------- CEC configuration ---------------------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 80036aa: 687b ldr r3, [r7, #4] 80036ac: 681b ldr r3, [r3, #0] 80036ae: f003 0340 and.w r3, r3, #64 @ 0x40 80036b2: 2b00 cmp r3, #0 80036b4: d008 beq.n 80036c8 { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 80036b6: 4b38 ldr r3, [pc, #224] @ (8003798 ) 80036b8: 6d1b ldr r3, [r3, #80] @ 0x50 80036ba: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000 80036be: 687b ldr r3, [r7, #4] 80036c0: 69db ldr r3, [r3, #28] 80036c2: 4935 ldr r1, [pc, #212] @ (8003798 ) 80036c4: 4313 orrs r3, r2 80036c6: 650b str r3, [r1, #80] @ 0x50 } /*---------------------- ETH1 REF configuration --------------------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ETH1REF) == RCC_PERIPHCLK_ETH1REF) 80036c8: 687b ldr r3, [r7, #4] 80036ca: 681b ldr r3, [r3, #0] 80036cc: f003 0380 and.w r3, r3, #128 @ 0x80 80036d0: 2b00 cmp r3, #0 80036d2: d008 beq.n 80036e6 { /* Check the parameters */ assert_param(IS_RCC_ETH1REFCLKSOURCE(PeriphClkInit->Eth1RefClockSelection)); /* Configure the ETH1 REF clock source */ __HAL_RCC_ETH1REF_CONFIG(PeriphClkInit->Eth1RefClockSelection); 80036d4: 4b30 ldr r3, [pc, #192] @ (8003798 ) 80036d6: 6cdb ldr r3, [r3, #76] @ 0x4c 80036d8: f423 3240 bic.w r2, r3, #196608 @ 0x30000 80036dc: 687b ldr r3, [r7, #4] 80036de: 6a1b ldr r3, [r3, #32] 80036e0: 492d ldr r1, [pc, #180] @ (8003798 ) 80036e2: 4313 orrs r3, r2 80036e4: 64cb str r3, [r1, #76] @ 0x4c } /*---------------------- ETH1PHY configuration --------------------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ETH1PHY) == RCC_PERIPHCLK_ETH1PHY) 80036e6: 687b ldr r3, [r7, #4] 80036e8: 681b ldr r3, [r3, #0] 80036ea: f403 7380 and.w r3, r3, #256 @ 0x100 80036ee: 2b00 cmp r3, #0 80036f0: d020 beq.n 8003734 { /* Check the parameters */ assert_param(IS_RCC_ETH1PHYCLKSOURCE(PeriphClkInit->Eth1PhyClockSelection)); switch (PeriphClkInit->Eth1PhyClockSelection) 80036f2: 687b ldr r3, [r7, #4] 80036f4: 6a5b ldr r3, [r3, #36] @ 0x24 80036f6: 2b00 cmp r3, #0 80036f8: d00c beq.n 8003714 80036fa: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 80036fe: d106 bne.n 800370e case RCC_ETH1PHYCLKSOURCE_HSE: /* HSE is used as clock source for ETH PHY */ /* ETH PHY clock source configuration done later after clock selection check */ break; case RCC_ETH1PHYCLKSOURCE_PLL3S: /* PLL3_S is used as clock source for ETH PHY */ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_SCLK); 8003700: 4b25 ldr r3, [pc, #148] @ (8003798 ) 8003702: 6adb ldr r3, [r3, #44] @ 0x2c 8003704: 4a24 ldr r2, [pc, #144] @ (8003798 ) 8003706: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 800370a: 62d3 str r3, [r2, #44] @ 0x2c /* ETH PHY clock source configuration done later after clock selection check */ break; 800370c: e003 b.n 8003716 default: ret = HAL_ERROR; 800370e: 2301 movs r3, #1 8003710: 75fb strb r3, [r7, #23] break; 8003712: e000 b.n 8003716 break; 8003714: bf00 nop } if (ret == HAL_OK) 8003716: 7dfb ldrb r3, [r7, #23] 8003718: 2b00 cmp r3, #0 800371a: d109 bne.n 8003730 { /* Set the source of ETH PHY clock*/ __HAL_RCC_ETH1PHY_CONFIG(PeriphClkInit->Eth1PhyClockSelection); 800371c: 4b1e ldr r3, [pc, #120] @ (8003798 ) 800371e: 6cdb ldr r3, [r3, #76] @ 0x4c 8003720: f423 2280 bic.w r2, r3, #262144 @ 0x40000 8003724: 687b ldr r3, [r7, #4] 8003726: 6a5b ldr r3, [r3, #36] @ 0x24 8003728: 491b ldr r1, [pc, #108] @ (8003798 ) 800372a: 4313 orrs r3, r2 800372c: 64cb str r3, [r1, #76] @ 0x4c 800372e: e001 b.n 8003734 } else { /* set overall return value */ status = ret; 8003730: 7dfb ldrb r3, [r7, #23] 8003732: 75bb strb r3, [r7, #22] } } /*---------------------- FDCAN configuration -------------------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) 8003734: 687b ldr r3, [r7, #4] 8003736: 681b ldr r3, [r3, #0] 8003738: f403 7300 and.w r3, r3, #512 @ 0x200 800373c: 2b00 cmp r3, #0 800373e: d02f beq.n 80037a0 { /* Check the parameters */ assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection)); switch (PeriphClkInit->FdcanClockSelection) 8003740: 687b ldr r3, [r7, #4] 8003742: 6a9b ldr r3, [r3, #40] @ 0x28 8003744: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 8003748: d00e beq.n 8003768 800374a: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800374e: d812 bhi.n 8003776 8003750: 2b00 cmp r3, #0 8003752: d013 beq.n 800377c 8003754: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8003758: d10d bne.n 8003776 { case RCC_FDCANCLKSOURCE_PLL1Q: /* PLL1_Q is used as clock source for FDCAN kernel */ /* Enable FDCAN Clock output generated form System PLL . */ __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL_QCLK); 800375a: 4b0f ldr r3, [pc, #60] @ (8003798 ) 800375c: 6adb ldr r3, [r3, #44] @ 0x2c 800375e: 4a0e ldr r2, [pc, #56] @ (8003798 ) 8003760: f043 0340 orr.w r3, r3, #64 @ 0x40 8003764: 62d3 str r3, [r2, #44] @ 0x2c /* FDCAN clock source configuration done later after clock selection check */ break; 8003766: e00a b.n 800377e case RCC_FDCANCLKSOURCE_PLL2P: /* PLL2_P is used as clock source for FDCAN kernel */ __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_PCLK); 8003768: 4b0b ldr r3, [pc, #44] @ (8003798 ) 800376a: 6adb ldr r3, [r3, #44] @ 0x2c 800376c: 4a0a ldr r2, [pc, #40] @ (8003798 ) 800376e: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8003772: 62d3 str r3, [r2, #44] @ 0x2c /* FDCAN clock source configuration done later after clock selection check */ break; 8003774: e003 b.n 800377e case RCC_FDCANCLKSOURCE_HSE: /* HSE is used as clock source for FDCAN kernel */ /* FDCAN clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8003776: 2301 movs r3, #1 8003778: 75fb strb r3, [r7, #23] break; 800377a: e000 b.n 800377e break; 800377c: bf00 nop } if (ret == HAL_OK) 800377e: 7dfb ldrb r3, [r7, #23] 8003780: 2b00 cmp r3, #0 8003782: d10b bne.n 800379c { /* Set the source of FDCAN clock*/ __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); 8003784: 4b04 ldr r3, [pc, #16] @ (8003798 ) 8003786: 6d1b ldr r3, [r3, #80] @ 0x50 8003788: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 800378c: 687b ldr r3, [r7, #4] 800378e: 6a9b ldr r3, [r3, #40] @ 0x28 8003790: 4901 ldr r1, [pc, #4] @ (8003798 ) 8003792: 4313 orrs r3, r2 8003794: 650b str r3, [r1, #80] @ 0x50 8003796: e003 b.n 80037a0 8003798: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 800379c: 7dfb ldrb r3, [r7, #23] 800379e: 75bb strb r3, [r7, #22] } } /*------------------------------ I2C1/I3C1 Configuration ------------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_I2C1_I3C1) == RCC_PERIPHCLK_I2C1_I3C1) 80037a0: 687b ldr r3, [r7, #4] 80037a2: 681b ldr r3, [r3, #0] 80037a4: f403 6300 and.w r3, r3, #2048 @ 0x800 80037a8: 2b00 cmp r3, #0 80037aa: d02c beq.n 8003806 { /* Check the parameters */ assert_param(IS_RCC_I2C1_I3C1CLKSOURCE(PeriphClkInit->I2c1_I3c1ClockSelection)); switch (PeriphClkInit->I2c1_I3c1ClockSelection) 80037ac: 687b ldr r3, [r7, #4] 80037ae: 6adb ldr r3, [r3, #44] @ 0x2c 80037b0: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 80037b4: d017 beq.n 80037e6 80037b6: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 80037ba: d811 bhi.n 80037e0 80037bc: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 80037c0: d011 beq.n 80037e6 80037c2: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 80037c6: d80b bhi.n 80037e0 80037c8: 2b00 cmp r3, #0 80037ca: d00c beq.n 80037e6 80037cc: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80037d0: d106 bne.n 80037e0 { case RCC_I2C1_I3C1CLKSOURCE_PLL3R: /* PLL3_R is used as clock source for I2C1/I3C1*/ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_RCLK); 80037d2: 4b97 ldr r3, [pc, #604] @ (8003a30 ) 80037d4: 6adb ldr r3, [r3, #44] @ 0x2c 80037d6: 4a96 ldr r2, [pc, #600] @ (8003a30 ) 80037d8: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 80037dc: 62d3 str r3, [r2, #44] @ 0x2c /* I2C1/I3C1 clock source configuration done later after clock selection check */ break; 80037de: e003 b.n 80037e8 case RCC_I2C1_I3C1CLKSOURCE_CSI: /* CSI is used as clock source for I2C1/I3C1*/ /* I2C1/I3C1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80037e0: 2301 movs r3, #1 80037e2: 75fb strb r3, [r7, #23] break; 80037e4: e000 b.n 80037e8 break; 80037e6: bf00 nop } if (ret == HAL_OK) 80037e8: 7dfb ldrb r3, [r7, #23] 80037ea: 2b00 cmp r3, #0 80037ec: d109 bne.n 8003802 { /* Set the source of I2C1/I3C1 clock*/ __HAL_RCC_I2C1_I3C1_CONFIG(PeriphClkInit->I2c1_I3c1ClockSelection); 80037ee: 4b90 ldr r3, [pc, #576] @ (8003a30 ) 80037f0: 6d1b ldr r3, [r3, #80] @ 0x50 80037f2: f423 5240 bic.w r2, r3, #12288 @ 0x3000 80037f6: 687b ldr r3, [r7, #4] 80037f8: 6adb ldr r3, [r3, #44] @ 0x2c 80037fa: 498d ldr r1, [pc, #564] @ (8003a30 ) 80037fc: 4313 orrs r3, r2 80037fe: 650b str r3, [r1, #80] @ 0x50 8003800: e001 b.n 8003806 } else { /* set overall return value */ status = ret; 8003802: 7dfb ldrb r3, [r7, #23] 8003804: 75bb strb r3, [r7, #22] } } /*------------------------------ I2C2/I2C3 Configuration -------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_I2C23) == RCC_PERIPHCLK_I2C23) 8003806: 687b ldr r3, [r7, #4] 8003808: 681b ldr r3, [r3, #0] 800380a: f403 6380 and.w r3, r3, #1024 @ 0x400 800380e: 2b00 cmp r3, #0 8003810: d02c beq.n 800386c { /* Check the parameters */ assert_param(IS_RCC_I2C23CLKSOURCE(PeriphClkInit->I2c23ClockSelection)); switch (PeriphClkInit->I2c23ClockSelection) 8003812: 687b ldr r3, [r7, #4] 8003814: 6b1b ldr r3, [r3, #48] @ 0x30 8003816: f5b3 7f40 cmp.w r3, #768 @ 0x300 800381a: d017 beq.n 800384c 800381c: f5b3 7f40 cmp.w r3, #768 @ 0x300 8003820: d811 bhi.n 8003846 8003822: f5b3 7f00 cmp.w r3, #512 @ 0x200 8003826: d011 beq.n 800384c 8003828: f5b3 7f00 cmp.w r3, #512 @ 0x200 800382c: d80b bhi.n 8003846 800382e: 2b00 cmp r3, #0 8003830: d00c beq.n 800384c 8003832: f5b3 7f80 cmp.w r3, #256 @ 0x100 8003836: d106 bne.n 8003846 { case RCC_I2C23CLKSOURCE_PLL3R: /* PLL3_R is used as clock source for I2C2/I2C3 */ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_RCLK); 8003838: 4b7d ldr r3, [pc, #500] @ (8003a30 ) 800383a: 6adb ldr r3, [r3, #44] @ 0x2c 800383c: 4a7c ldr r2, [pc, #496] @ (8003a30 ) 800383e: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8003842: 62d3 str r3, [r2, #44] @ 0x2c /* I2C2/I2C3 clock source configuration done later after clock selection check */ break; 8003844: e003 b.n 800384e case RCC_I2C23CLKSOURCE_CSI: /* CSI is used as clock source for I2C2/I2C3 */ /* I2C2/I2C3 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8003846: 2301 movs r3, #1 8003848: 75fb strb r3, [r7, #23] break; 800384a: e000 b.n 800384e break; 800384c: bf00 nop } if (ret == HAL_OK) 800384e: 7dfb ldrb r3, [r7, #23] 8003850: 2b00 cmp r3, #0 8003852: d109 bne.n 8003868 { /* Set the source of I2C2/I2C3 clock*/ __HAL_RCC_I2C23_CONFIG(PeriphClkInit->I2c23ClockSelection); 8003854: 4b76 ldr r3, [pc, #472] @ (8003a30 ) 8003856: 6d1b ldr r3, [r3, #80] @ 0x50 8003858: f423 7240 bic.w r2, r3, #768 @ 0x300 800385c: 687b ldr r3, [r7, #4] 800385e: 6b1b ldr r3, [r3, #48] @ 0x30 8003860: 4973 ldr r1, [pc, #460] @ (8003a30 ) 8003862: 4313 orrs r3, r2 8003864: 650b str r3, [r1, #80] @ 0x50 8003866: e001 b.n 800386c } else { /* set overall return value */ status = ret; 8003868: 7dfb ldrb r3, [r7, #23] 800386a: 75bb strb r3, [r7, #22] } } /*---------------------------- LPTIM1 configuration -------------------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) 800386c: 687b ldr r3, [r7, #4] 800386e: 681b ldr r3, [r3, #0] 8003870: f403 5380 and.w r3, r3, #4096 @ 0x1000 8003874: 2b00 cmp r3, #0 8003876: d045 beq.n 8003904 { /* Check the parameters */ assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); switch (PeriphClkInit->Lptim1ClockSelection) 8003878: 687b ldr r3, [r7, #4] 800387a: 6b5b ldr r3, [r3, #52] @ 0x34 800387c: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8003880: d02a beq.n 80038d8 8003882: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8003886: d824 bhi.n 80038d2 8003888: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800388c: d026 beq.n 80038dc 800388e: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8003892: d81e bhi.n 80038d2 8003894: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 8003898: d022 beq.n 80038e0 800389a: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800389e: d818 bhi.n 80038d2 80038a0: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 80038a4: d00e beq.n 80038c4 80038a6: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 80038aa: d812 bhi.n 80038d2 80038ac: 2b00 cmp r3, #0 80038ae: d019 beq.n 80038e4 80038b0: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80038b4: d10d bne.n 80038d2 case RCC_LPTIM1CLKSOURCE_PCLK1: /* PCLK1 as clock source for LPTIM1 */ /* LPTIM1 clock source configuration done later after clock selection check */ break; case RCC_LPTIM1CLKSOURCE_PLL2P: /* PLL2_P is used as clock source for LPTIM1 */ __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_PCLK); 80038b6: 4b5e ldr r3, [pc, #376] @ (8003a30 ) 80038b8: 6adb ldr r3, [r3, #44] @ 0x2c 80038ba: 4a5d ldr r2, [pc, #372] @ (8003a30 ) 80038bc: f443 3380 orr.w r3, r3, #65536 @ 0x10000 80038c0: 62d3 str r3, [r2, #44] @ 0x2c /* LPTIM1 clock source configuration done later after clock selection check */ break; 80038c2: e010 b.n 80038e6 case RCC_LPTIM1CLKSOURCE_PLL3R: /* PLL3_R is used as clock source for LPTIM1 */ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_RCLK); 80038c4: 4b5a ldr r3, [pc, #360] @ (8003a30 ) 80038c6: 6adb ldr r3, [r3, #44] @ 0x2c 80038c8: 4a59 ldr r2, [pc, #356] @ (8003a30 ) 80038ca: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 80038ce: 62d3 str r3, [r2, #44] @ 0x2c /* LPTIM1 clock source configuration done later after clock selection check */ break; 80038d0: e009 b.n 80038e6 /* HSI, HSE, or CSI oscillator is used as clock source for LPTIM1 */ /* LPTIM1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80038d2: 2301 movs r3, #1 80038d4: 75fb strb r3, [r7, #23] break; 80038d6: e006 b.n 80038e6 break; 80038d8: bf00 nop 80038da: e004 b.n 80038e6 break; 80038dc: bf00 nop 80038de: e002 b.n 80038e6 break; 80038e0: bf00 nop 80038e2: e000 b.n 80038e6 break; 80038e4: bf00 nop } if (ret == HAL_OK) 80038e6: 7dfb ldrb r3, [r7, #23] 80038e8: 2b00 cmp r3, #0 80038ea: d109 bne.n 8003900 { /* Set the source of LPTIM1 clock*/ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 80038ec: 4b50 ldr r3, [pc, #320] @ (8003a30 ) 80038ee: 6d1b ldr r3, [r3, #80] @ 0x50 80038f0: f423 22e0 bic.w r2, r3, #458752 @ 0x70000 80038f4: 687b ldr r3, [r7, #4] 80038f6: 6b5b ldr r3, [r3, #52] @ 0x34 80038f8: 494d ldr r1, [pc, #308] @ (8003a30 ) 80038fa: 4313 orrs r3, r2 80038fc: 650b str r3, [r1, #80] @ 0x50 80038fe: e001 b.n 8003904 } else { /* set overall return value */ status = ret; 8003900: 7dfb ldrb r3, [r7, #23] 8003902: 75bb strb r3, [r7, #22] } } /*---------------------------- LPTIM2/LPTIM3 configuration -----------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LPTIM23) == RCC_PERIPHCLK_LPTIM23) 8003904: 687b ldr r3, [r7, #4] 8003906: 681b ldr r3, [r3, #0] 8003908: f403 5300 and.w r3, r3, #8192 @ 0x2000 800390c: 2b00 cmp r3, #0 800390e: d045 beq.n 800399c { switch (PeriphClkInit->Lptim23ClockSelection) 8003910: 687b ldr r3, [r7, #4] 8003912: 6b9b ldr r3, [r3, #56] @ 0x38 8003914: f5b3 6fa0 cmp.w r3, #1280 @ 0x500 8003918: d02a beq.n 8003970 800391a: f5b3 6fa0 cmp.w r3, #1280 @ 0x500 800391e: d824 bhi.n 800396a 8003920: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8003924: d026 beq.n 8003974 8003926: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800392a: d81e bhi.n 800396a 800392c: f5b3 7f40 cmp.w r3, #768 @ 0x300 8003930: d022 beq.n 8003978 8003932: f5b3 7f40 cmp.w r3, #768 @ 0x300 8003936: d818 bhi.n 800396a 8003938: f5b3 7f00 cmp.w r3, #512 @ 0x200 800393c: d00e beq.n 800395c 800393e: f5b3 7f00 cmp.w r3, #512 @ 0x200 8003942: d812 bhi.n 800396a 8003944: 2b00 cmp r3, #0 8003946: d019 beq.n 800397c 8003948: f5b3 7f80 cmp.w r3, #256 @ 0x100 800394c: d10d bne.n 800396a case RCC_LPTIM23CLKSOURCE_PCLK4: /* PCLK4 as clock source for LPTIM2/LPTIM3 */ /* LPTIM2/LPTIM3 clock source configuration done later after clock selection check */ break; case RCC_LPTIM23CLKSOURCE_PLL2P: /* PLL2_P is used as clock source for LPTIM2/LPTIM3 */ __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_PCLK); 800394e: 4b38 ldr r3, [pc, #224] @ (8003a30 ) 8003950: 6adb ldr r3, [r3, #44] @ 0x2c 8003952: 4a37 ldr r2, [pc, #220] @ (8003a30 ) 8003954: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8003958: 62d3 str r3, [r2, #44] @ 0x2c /* LPTIM2/LPTIM3 clock source configuration done later after clock selection check */ break; 800395a: e010 b.n 800397e case RCC_LPTIM23CLKSOURCE_PLL3R: /* PLL3_R is used as clock source for LPTIM2/LPTIM3 */ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_RCLK); 800395c: 4b34 ldr r3, [pc, #208] @ (8003a30 ) 800395e: 6adb ldr r3, [r3, #44] @ 0x2c 8003960: 4a33 ldr r2, [pc, #204] @ (8003a30 ) 8003962: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8003966: 62d3 str r3, [r2, #44] @ 0x2c /* LPTIM2/LPTIM3 clock source configuration done later after clock selection check */ break; 8003968: e009 b.n 800397e /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */ /* LPTIM2/LPTIM3 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800396a: 2301 movs r3, #1 800396c: 75fb strb r3, [r7, #23] break; 800396e: e006 b.n 800397e break; 8003970: bf00 nop 8003972: e004 b.n 800397e break; 8003974: bf00 nop 8003976: e002 b.n 800397e break; 8003978: bf00 nop 800397a: e000 b.n 800397e break; 800397c: bf00 nop } if (ret == HAL_OK) 800397e: 7dfb ldrb r3, [r7, #23] 8003980: 2b00 cmp r3, #0 8003982: d109 bne.n 8003998 { /* Set the source of LPTIM2/LPTIM3 clock*/ __HAL_RCC_LPTIM23_CONFIG(PeriphClkInit->Lptim23ClockSelection); 8003984: 4b2a ldr r3, [pc, #168] @ (8003a30 ) 8003986: 6d9b ldr r3, [r3, #88] @ 0x58 8003988: f423 62e0 bic.w r2, r3, #1792 @ 0x700 800398c: 687b ldr r3, [r7, #4] 800398e: 6b9b ldr r3, [r3, #56] @ 0x38 8003990: 4927 ldr r1, [pc, #156] @ (8003a30 ) 8003992: 4313 orrs r3, r2 8003994: 658b str r3, [r1, #88] @ 0x58 8003996: e001 b.n 800399c } else { /* set overall return value */ status = ret; 8003998: 7dfb ldrb r3, [r7, #23] 800399a: 75bb strb r3, [r7, #22] } } /*---------------------------- LPTIM4/LPTIM5 configuration -----------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LPTIM45) == RCC_PERIPHCLK_LPTIM45) 800399c: 687b ldr r3, [r7, #4] 800399e: 681b ldr r3, [r3, #0] 80039a0: f403 4380 and.w r3, r3, #16384 @ 0x4000 80039a4: 2b00 cmp r3, #0 80039a6: d047 beq.n 8003a38 { switch (PeriphClkInit->Lptim45ClockSelection) 80039a8: 687b ldr r3, [r7, #4] 80039aa: 6bdb ldr r3, [r3, #60] @ 0x3c 80039ac: f5b3 4fa0 cmp.w r3, #20480 @ 0x5000 80039b0: d02a beq.n 8003a08 80039b2: f5b3 4fa0 cmp.w r3, #20480 @ 0x5000 80039b6: d824 bhi.n 8003a02 80039b8: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 80039bc: d026 beq.n 8003a0c 80039be: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 80039c2: d81e bhi.n 8003a02 80039c4: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 80039c8: d022 beq.n 8003a10 80039ca: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 80039ce: d818 bhi.n 8003a02 80039d0: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 80039d4: d00e beq.n 80039f4 80039d6: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 80039da: d812 bhi.n 8003a02 80039dc: 2b00 cmp r3, #0 80039de: d019 beq.n 8003a14 80039e0: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80039e4: d10d bne.n 8003a02 case RCC_LPTIM45CLKSOURCE_PCLK4: /* PCLK4 as clock source for LPTIM4/LPTIM5 */ /* LPTIM4/LPTIM5 clock source configuration done later after clock selection check */ break; case RCC_LPTIM45CLKSOURCE_PLL2P: /* PLL2 is used as clock source for LPTIM4/LPTIM5 */ __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_PCLK); 80039e6: 4b12 ldr r3, [pc, #72] @ (8003a30 ) 80039e8: 6adb ldr r3, [r3, #44] @ 0x2c 80039ea: 4a11 ldr r2, [pc, #68] @ (8003a30 ) 80039ec: f443 3380 orr.w r3, r3, #65536 @ 0x10000 80039f0: 62d3 str r3, [r2, #44] @ 0x2c /* LPTIM4/LPTIM5 clock source configuration done later after clock selection check */ break; 80039f2: e010 b.n 8003a16 case RCC_LPTIM45CLKSOURCE_PLL3R: /* PLL3 is used as clock source for LPTIM4/LPTIM5 */ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_RCLK); 80039f4: 4b0e ldr r3, [pc, #56] @ (8003a30 ) 80039f6: 6adb ldr r3, [r3, #44] @ 0x2c 80039f8: 4a0d ldr r2, [pc, #52] @ (8003a30 ) 80039fa: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 80039fe: 62d3 str r3, [r2, #44] @ 0x2c /* LPTIM4/LPTIM5 clock source configuration done later after clock selection check */ break; 8003a00: e009 b.n 8003a16 /* HSI, HSE, or CSI oscillator is used as source of LPTIM4/LPTIM5 clock */ /* LPTIM4/LPTIM5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8003a02: 2301 movs r3, #1 8003a04: 75fb strb r3, [r7, #23] break; 8003a06: e006 b.n 8003a16 break; 8003a08: bf00 nop 8003a0a: e004 b.n 8003a16 break; 8003a0c: bf00 nop 8003a0e: e002 b.n 8003a16 break; 8003a10: bf00 nop 8003a12: e000 b.n 8003a16 break; 8003a14: bf00 nop } if (ret == HAL_OK) 8003a16: 7dfb ldrb r3, [r7, #23] 8003a18: 2b00 cmp r3, #0 8003a1a: d10b bne.n 8003a34 { /* Set the source of LPTIM4/LPTIM5 clock */ __HAL_RCC_LPTIM45_CONFIG(PeriphClkInit->Lptim45ClockSelection); 8003a1c: 4b04 ldr r3, [pc, #16] @ (8003a30 ) 8003a1e: 6d9b ldr r3, [r3, #88] @ 0x58 8003a20: f423 42e0 bic.w r2, r3, #28672 @ 0x7000 8003a24: 687b ldr r3, [r7, #4] 8003a26: 6bdb ldr r3, [r3, #60] @ 0x3c 8003a28: 4901 ldr r1, [pc, #4] @ (8003a30 ) 8003a2a: 4313 orrs r3, r2 8003a2c: 658b str r3, [r1, #88] @ 0x58 8003a2e: e003 b.n 8003a38 8003a30: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 8003a34: 7dfb ldrb r3, [r7, #23] 8003a36: 75bb strb r3, [r7, #22] } } /*-------------------------- LPUART1 Configuration -------------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 8003a38: 687b ldr r3, [r7, #4] 8003a3a: 681b ldr r3, [r3, #0] 8003a3c: f403 4300 and.w r3, r3, #32768 @ 0x8000 8003a40: 2b00 cmp r3, #0 8003a42: d034 beq.n 8003aae { /* Check the parameters */ assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); switch (PeriphClkInit->Lpuart1ClockSelection) 8003a44: 687b ldr r3, [r7, #4] 8003a46: 6c1b ldr r3, [r3, #64] @ 0x40 8003a48: 2b05 cmp r3, #5 8003a4a: d81d bhi.n 8003a88 8003a4c: a201 add r2, pc, #4 @ (adr r2, 8003a54 ) 8003a4e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8003a52: bf00 nop 8003a54: 08003a8f .word 0x08003a8f 8003a58: 08003a6d .word 0x08003a6d 8003a5c: 08003a7b .word 0x08003a7b 8003a60: 08003a8f .word 0x08003a8f 8003a64: 08003a8f .word 0x08003a8f 8003a68: 08003a8f .word 0x08003a8f case RCC_LPUART1CLKSOURCE_PCLK4: /* PCLK4 selected as clock source for LPUART1 */ /* LPUART1 clock source configuration done later after clock selection check */ break; case RCC_LPUART1CLKSOURCE_PLL2Q: /* PLL2_Q is used as clock source for LPUART1 */ __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_QCLK); 8003a6c: 4b91 ldr r3, [pc, #580] @ (8003cb4 ) 8003a6e: 6adb ldr r3, [r3, #44] @ 0x2c 8003a70: 4a90 ldr r2, [pc, #576] @ (8003cb4 ) 8003a72: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8003a76: 62d3 str r3, [r2, #44] @ 0x2c /* LPUART1 clock source configuration done later after clock selection check */ break; 8003a78: e00a b.n 8003a90 case RCC_LPUART1CLKSOURCE_PLL3Q: /* PLL3_Q is used as clock source for LPUART1 */ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_QCLK); 8003a7a: 4b8e ldr r3, [pc, #568] @ (8003cb4 ) 8003a7c: 6adb ldr r3, [r3, #44] @ 0x2c 8003a7e: 4a8d ldr r2, [pc, #564] @ (8003cb4 ) 8003a80: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8003a84: 62d3 str r3, [r2, #44] @ 0x2c /* LPUART1 clock source configuration done later after clock selection check */ break; 8003a86: e003 b.n 8003a90 /* LSE, oscillator is used as source of LPUART1 clock */ /* LPUART1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8003a88: 2301 movs r3, #1 8003a8a: 75fb strb r3, [r7, #23] break; 8003a8c: e000 b.n 8003a90 break; 8003a8e: bf00 nop } if (ret == HAL_OK) 8003a90: 7dfb ldrb r3, [r7, #23] 8003a92: 2b00 cmp r3, #0 8003a94: d109 bne.n 8003aaa { /* Set the source of LPUART1 clock */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 8003a96: 4b87 ldr r3, [pc, #540] @ (8003cb4 ) 8003a98: 6d9b ldr r3, [r3, #88] @ 0x58 8003a9a: f023 0207 bic.w r2, r3, #7 8003a9e: 687b ldr r3, [r7, #4] 8003aa0: 6c1b ldr r3, [r3, #64] @ 0x40 8003aa2: 4984 ldr r1, [pc, #528] @ (8003cb4 ) 8003aa4: 4313 orrs r3, r2 8003aa6: 658b str r3, [r1, #88] @ 0x58 8003aa8: e001 b.n 8003aae } else { /* set overall return value */ status = ret; 8003aaa: 7dfb ldrb r3, [r7, #23] 8003aac: 75bb strb r3, [r7, #22] } } /*-------------------------- LTDC Configuration ----------------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) 8003aae: 687b ldr r3, [r7, #4] 8003ab0: 681b ldr r3, [r3, #0] 8003ab2: f403 3380 and.w r3, r3, #65536 @ 0x10000 8003ab6: 2b00 cmp r3, #0 8003ab8: d005 beq.n 8003ac6 { /* LTDC internally connected to PLL3_R output clock */ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_RCLK); 8003aba: 4b7e ldr r3, [pc, #504] @ (8003cb4 ) 8003abc: 6adb ldr r3, [r3, #44] @ 0x2c 8003abe: 4a7d ldr r2, [pc, #500] @ (8003cb4 ) 8003ac0: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8003ac4: 62d3 str r3, [r2, #44] @ 0x2c } /*---------------------------- PSSI configuration --------------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PSSI) == RCC_PERIPHCLK_PSSI) 8003ac6: 687b ldr r3, [r7, #4] 8003ac8: 681b ldr r3, [r3, #0] 8003aca: f403 3300 and.w r3, r3, #131072 @ 0x20000 8003ace: 2b00 cmp r3, #0 8003ad0: d021 beq.n 8003b16 { /* Check the parameters */ assert_param(IS_RCC_PSSICLKSOURCE(PeriphClkInit->PssiClockSelection)); switch (PeriphClkInit->PssiClockSelection) 8003ad2: 687b ldr r3, [r7, #4] 8003ad4: 6c9b ldr r3, [r3, #72] @ 0x48 8003ad6: 2b00 cmp r3, #0 8003ad8: d003 beq.n 8003ae2 8003ada: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 8003ade: d00a beq.n 8003af6 8003ae0: e006 b.n 8003af0 { case RCC_PSSICLKSOURCE_PLL3R: /* PLL3_R is used as clock source for PSSI */ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_RCLK); 8003ae2: 4b74 ldr r3, [pc, #464] @ (8003cb4 ) 8003ae4: 6adb ldr r3, [r3, #44] @ 0x2c 8003ae6: 4a73 ldr r2, [pc, #460] @ (8003cb4 ) 8003ae8: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8003aec: 62d3 str r3, [r2, #44] @ 0x2c /* PSSI clock source configuration done later after clock selection check */ break; 8003aee: e003 b.n 8003af8 /* HSI, HSE, or CSI oscillator is used as source of PSSI clock */ /* PSSI clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8003af0: 2301 movs r3, #1 8003af2: 75fb strb r3, [r7, #23] break; 8003af4: e000 b.n 8003af8 break; 8003af6: bf00 nop } if (ret == HAL_OK) 8003af8: 7dfb ldrb r3, [r7, #23] 8003afa: 2b00 cmp r3, #0 8003afc: d109 bne.n 8003b12 { /* Set the source of PSSI clock*/ __HAL_RCC_PSSI_CONFIG(PeriphClkInit->PssiClockSelection); 8003afe: 4b6d ldr r3, [pc, #436] @ (8003cb4 ) 8003b00: 6cdb ldr r3, [r3, #76] @ 0x4c 8003b02: f023 6200 bic.w r2, r3, #134217728 @ 0x8000000 8003b06: 687b ldr r3, [r7, #4] 8003b08: 6c9b ldr r3, [r3, #72] @ 0x48 8003b0a: 496a ldr r1, [pc, #424] @ (8003cb4 ) 8003b0c: 4313 orrs r3, r2 8003b0e: 64cb str r3, [r1, #76] @ 0x4c 8003b10: e001 b.n 8003b16 } else { /* set overall return value */ status = ret; 8003b12: 7dfb ldrb r3, [r7, #23] 8003b14: 75bb strb r3, [r7, #22] } } /*---------------------------- SAI1 configuration --------------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 8003b16: 687b ldr r3, [r7, #4] 8003b18: 681b ldr r3, [r3, #0] 8003b1a: f403 2300 and.w r3, r3, #524288 @ 0x80000 8003b1e: 2b00 cmp r3, #0 8003b20: d043 beq.n 8003baa { /* Check the parameters */ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); switch (PeriphClkInit->Sai1ClockSelection) 8003b22: 687b ldr r3, [r7, #4] 8003b24: 6cdb ldr r3, [r3, #76] @ 0x4c 8003b26: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8003b2a: d02c beq.n 8003b86 8003b2c: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8003b30: d826 bhi.n 8003b80 8003b32: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 8003b36: d028 beq.n 8003b8a 8003b38: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 8003b3c: d820 bhi.n 8003b80 8003b3e: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8003b42: d016 beq.n 8003b72 8003b44: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8003b48: d81a bhi.n 8003b80 8003b4a: 2b00 cmp r3, #0 8003b4c: d003 beq.n 8003b56 8003b4e: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8003b52: d007 beq.n 8003b64 8003b54: e014 b.n 8003b80 { case RCC_SAI1CLKSOURCE_PLL1Q: /* PLL1_Q is used as clock source for SAI1 */ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL_QCLK); 8003b56: 4b57 ldr r3, [pc, #348] @ (8003cb4 ) 8003b58: 6adb ldr r3, [r3, #44] @ 0x2c 8003b5a: 4a56 ldr r2, [pc, #344] @ (8003cb4 ) 8003b5c: f043 0340 orr.w r3, r3, #64 @ 0x40 8003b60: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 8003b62: e013 b.n 8003b8c case RCC_SAI1CLKSOURCE_PLL2P: /* PLL2_P is used as clock source for SAI1 */ __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_PCLK); 8003b64: 4b53 ldr r3, [pc, #332] @ (8003cb4 ) 8003b66: 6adb ldr r3, [r3, #44] @ 0x2c 8003b68: 4a52 ldr r2, [pc, #328] @ (8003cb4 ) 8003b6a: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8003b6e: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 8003b70: e00c b.n 8003b8c case RCC_SAI1CLKSOURCE_PLL3P: /* PLL3_P is used as clock source for SAI1 */ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_PCLK); 8003b72: 4b50 ldr r3, [pc, #320] @ (8003cb4 ) 8003b74: 6adb ldr r3, [r3, #44] @ 0x2c 8003b76: 4a4f ldr r2, [pc, #316] @ (8003cb4 ) 8003b78: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 8003b7c: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 8003b7e: e005 b.n 8003b8c /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */ /* SAI1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8003b80: 2301 movs r3, #1 8003b82: 75fb strb r3, [r7, #23] break; 8003b84: e002 b.n 8003b8c break; 8003b86: bf00 nop 8003b88: e000 b.n 8003b8c break; 8003b8a: bf00 nop } if (ret == HAL_OK) 8003b8c: 7dfb ldrb r3, [r7, #23] 8003b8e: 2b00 cmp r3, #0 8003b90: d109 bne.n 8003ba6 { /* Set the source of SAI1 clock*/ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 8003b92: 4b48 ldr r3, [pc, #288] @ (8003cb4 ) 8003b94: 6d5b ldr r3, [r3, #84] @ 0x54 8003b96: f423 22e0 bic.w r2, r3, #458752 @ 0x70000 8003b9a: 687b ldr r3, [r7, #4] 8003b9c: 6cdb ldr r3, [r3, #76] @ 0x4c 8003b9e: 4945 ldr r1, [pc, #276] @ (8003cb4 ) 8003ba0: 4313 orrs r3, r2 8003ba2: 654b str r3, [r1, #84] @ 0x54 8003ba4: e001 b.n 8003baa } else { /* set overall return value */ status = ret; 8003ba6: 7dfb ldrb r3, [r7, #23] 8003ba8: 75bb strb r3, [r7, #22] } } /*---------------------------- SAI2 configuration --------------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) 8003baa: 687b ldr r3, [r7, #4] 8003bac: 681b ldr r3, [r3, #0] 8003bae: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8003bb2: 2b00 cmp r3, #0 8003bb4: d04b beq.n 8003c4e { /* Check the parameters */ assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); switch (PeriphClkInit->Sai2ClockSelection) 8003bb6: 687b ldr r3, [r7, #4] 8003bb8: 6d1b ldr r3, [r3, #80] @ 0x50 8003bba: f5b3 0fa0 cmp.w r3, #5242880 @ 0x500000 8003bbe: d032 beq.n 8003c26 8003bc0: f5b3 0fa0 cmp.w r3, #5242880 @ 0x500000 8003bc4: d82c bhi.n 8003c20 8003bc6: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8003bca: d02e beq.n 8003c2a 8003bcc: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8003bd0: d826 bhi.n 8003c20 8003bd2: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 8003bd6: d02a beq.n 8003c2e 8003bd8: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 8003bdc: d820 bhi.n 8003c20 8003bde: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 8003be2: d016 beq.n 8003c12 8003be4: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 8003be8: d81a bhi.n 8003c20 8003bea: 2b00 cmp r3, #0 8003bec: d003 beq.n 8003bf6 8003bee: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8003bf2: d007 beq.n 8003c04 8003bf4: e014 b.n 8003c20 { case RCC_SAI2CLKSOURCE_PLL1Q: /* PLL1_Q is used as clock source for SAI2 */ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL_QCLK); 8003bf6: 4b2f ldr r3, [pc, #188] @ (8003cb4 ) 8003bf8: 6adb ldr r3, [r3, #44] @ 0x2c 8003bfa: 4a2e ldr r2, [pc, #184] @ (8003cb4 ) 8003bfc: f043 0340 orr.w r3, r3, #64 @ 0x40 8003c00: 62d3 str r3, [r2, #44] @ 0x2c /* SAI2 clock source configuration done later after clock selection check */ break; 8003c02: e015 b.n 8003c30 case RCC_SAI2CLKSOURCE_PLL2P: /* PLL2_P is used as clock source for SAI2 */ __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_PCLK); 8003c04: 4b2b ldr r3, [pc, #172] @ (8003cb4 ) 8003c06: 6adb ldr r3, [r3, #44] @ 0x2c 8003c08: 4a2a ldr r2, [pc, #168] @ (8003cb4 ) 8003c0a: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8003c0e: 62d3 str r3, [r2, #44] @ 0x2c /* SAI2 clock source configuration done later after clock selection check */ break; 8003c10: e00e b.n 8003c30 case RCC_SAI2CLKSOURCE_PLL3P: /* PLL3_P is used as clock source for SAI2 */ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_PCLK); 8003c12: 4b28 ldr r3, [pc, #160] @ (8003cb4 ) 8003c14: 6adb ldr r3, [r3, #44] @ 0x2c 8003c16: 4a27 ldr r2, [pc, #156] @ (8003cb4 ) 8003c18: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 8003c1c: 62d3 str r3, [r2, #44] @ 0x2c /* SAI2 clock source configuration done later after clock selection check */ break; 8003c1e: e007 b.n 8003c30 case RCC_SAI2CLKSOURCE_SPDIF: /* SPDIF clock is used as source of SAI2 clock */ /* SAI2 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8003c20: 2301 movs r3, #1 8003c22: 75fb strb r3, [r7, #23] break; 8003c24: e004 b.n 8003c30 break; 8003c26: bf00 nop 8003c28: e002 b.n 8003c30 break; 8003c2a: bf00 nop 8003c2c: e000 b.n 8003c30 break; 8003c2e: bf00 nop } if (ret == HAL_OK) 8003c30: 7dfb ldrb r3, [r7, #23] 8003c32: 2b00 cmp r3, #0 8003c34: d109 bne.n 8003c4a { /* Set the source of SAI2 clock*/ __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); 8003c36: 4b1f ldr r3, [pc, #124] @ (8003cb4 ) 8003c38: 6d5b ldr r3, [r3, #84] @ 0x54 8003c3a: f423 02e0 bic.w r2, r3, #7340032 @ 0x700000 8003c3e: 687b ldr r3, [r7, #4] 8003c40: 6d1b ldr r3, [r3, #80] @ 0x50 8003c42: 491c ldr r1, [pc, #112] @ (8003cb4 ) 8003c44: 4313 orrs r3, r2 8003c46: 654b str r3, [r1, #84] @ 0x54 8003c48: e001 b.n 8003c4e } else { /* set overall return value */ status = ret; 8003c4a: 7dfb ldrb r3, [r7, #23] 8003c4c: 75bb strb r3, [r7, #22] } } /*---------------------------- SPDIFRX configuration -------------------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 8003c4e: 687b ldr r3, [r7, #4] 8003c50: 681b ldr r3, [r3, #0] 8003c52: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8003c56: 2b00 cmp r3, #0 8003c58: d03e beq.n 8003cd8 { /* Check the parameters */ assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifrxClockSelection)); switch (PeriphClkInit->SpdifrxClockSelection) 8003c5a: 687b ldr r3, [r7, #4] 8003c5c: 6e9b ldr r3, [r3, #104] @ 0x68 8003c5e: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 8003c62: d029 beq.n 8003cb8 8003c64: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 8003c68: d820 bhi.n 8003cac 8003c6a: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 8003c6e: d016 beq.n 8003c9e 8003c70: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 8003c74: d81a bhi.n 8003cac 8003c76: 2b00 cmp r3, #0 8003c78: d003 beq.n 8003c82 8003c7a: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8003c7e: d007 beq.n 8003c90 8003c80: e014 b.n 8003cac { case RCC_SPDIFRXCLKSOURCE_PLL1Q: /* PLL1_Q is used as clock source for SPDIFRX */ /* Enable PLL1Q Clock output generated form System PLL . */ __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL_QCLK); 8003c82: 4b0c ldr r3, [pc, #48] @ (8003cb4 ) 8003c84: 6adb ldr r3, [r3, #44] @ 0x2c 8003c86: 4a0b ldr r2, [pc, #44] @ (8003cb4 ) 8003c88: f043 0340 orr.w r3, r3, #64 @ 0x40 8003c8c: 62d3 str r3, [r2, #44] @ 0x2c /* SPDIFRX clock source configuration done later after clock selection check */ break; 8003c8e: e014 b.n 8003cba case RCC_SPDIFRXCLKSOURCE_PLL2R: /* PLL2_R is used as clock source for SPDIFRX */ __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_RCLK); 8003c90: 4b08 ldr r3, [pc, #32] @ (8003cb4 ) 8003c92: 6adb ldr r3, [r3, #44] @ 0x2c 8003c94: 4a07 ldr r2, [pc, #28] @ (8003cb4 ) 8003c96: f443 2380 orr.w r3, r3, #262144 @ 0x40000 8003c9a: 62d3 str r3, [r2, #44] @ 0x2c /* SPDIFRX clock source configuration done later after clock selection check */ break; 8003c9c: e00d b.n 8003cba case RCC_SPDIFRXCLKSOURCE_PLL3R: /* PLL3_R is used as clock source for SPDIFRX */ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_RCLK); 8003c9e: 4b05 ldr r3, [pc, #20] @ (8003cb4 ) 8003ca0: 6adb ldr r3, [r3, #44] @ 0x2c 8003ca2: 4a04 ldr r2, [pc, #16] @ (8003cb4 ) 8003ca4: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8003ca8: 62d3 str r3, [r2, #44] @ 0x2c /* SPDIFRX clock source configuration done later after clock selection check */ break; 8003caa: e006 b.n 8003cba /* Internal OSC clock is used as source of SPDIFRX clock*/ /* SPDIFRX clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8003cac: 2301 movs r3, #1 8003cae: 75fb strb r3, [r7, #23] break; 8003cb0: e003 b.n 8003cba 8003cb2: bf00 nop 8003cb4: 58024400 .word 0x58024400 break; 8003cb8: bf00 nop } if (ret == HAL_OK) 8003cba: 7dfb ldrb r3, [r7, #23] 8003cbc: 2b00 cmp r3, #0 8003cbe: d109 bne.n 8003cd4 { /* Set the source of SPDIFRX clock */ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection); 8003cc0: 4b8e ldr r3, [pc, #568] @ (8003efc ) 8003cc2: 6d1b ldr r3, [r3, #80] @ 0x50 8003cc4: f023 7240 bic.w r2, r3, #50331648 @ 0x3000000 8003cc8: 687b ldr r3, [r7, #4] 8003cca: 6e9b ldr r3, [r3, #104] @ 0x68 8003ccc: 498b ldr r1, [pc, #556] @ (8003efc ) 8003cce: 4313 orrs r3, r2 8003cd0: 650b str r3, [r1, #80] @ 0x50 8003cd2: e001 b.n 8003cd8 } else { /* set overall return value */ status = ret; 8003cd4: 7dfb ldrb r3, [r7, #23] 8003cd6: 75bb strb r3, [r7, #22] } } /*---------------------------- SPI1 configuration --------------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPI1) == RCC_PERIPHCLK_SPI1) 8003cd8: 687b ldr r3, [r7, #4] 8003cda: 681b ldr r3, [r3, #0] 8003cdc: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8003ce0: 2b00 cmp r3, #0 8003ce2: d043 beq.n 8003d6c { /* Check the parameters */ assert_param(IS_RCC_SPI1CLKSOURCE(PeriphClkInit->Spi1ClockSelection)); switch (PeriphClkInit->Spi1ClockSelection) 8003ce4: 687b ldr r3, [r7, #4] 8003ce6: 6d9b ldr r3, [r3, #88] @ 0x58 8003ce8: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8003cec: d02c beq.n 8003d48 8003cee: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8003cf2: d826 bhi.n 8003d42 8003cf4: f5b3 7f40 cmp.w r3, #768 @ 0x300 8003cf8: d028 beq.n 8003d4c 8003cfa: f5b3 7f40 cmp.w r3, #768 @ 0x300 8003cfe: d820 bhi.n 8003d42 8003d00: f5b3 7f00 cmp.w r3, #512 @ 0x200 8003d04: d016 beq.n 8003d34 8003d06: f5b3 7f00 cmp.w r3, #512 @ 0x200 8003d0a: d81a bhi.n 8003d42 8003d0c: 2b00 cmp r3, #0 8003d0e: d003 beq.n 8003d18 8003d10: f5b3 7f80 cmp.w r3, #256 @ 0x100 8003d14: d007 beq.n 8003d26 8003d16: e014 b.n 8003d42 { case RCC_SPI1CLKSOURCE_PLL1Q: /* PLL1_Q is used as clock source for SPI1 */ /* Enable SPI Clock output generated form System PLL . */ __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL_QCLK); 8003d18: 4b78 ldr r3, [pc, #480] @ (8003efc ) 8003d1a: 6adb ldr r3, [r3, #44] @ 0x2c 8003d1c: 4a77 ldr r2, [pc, #476] @ (8003efc ) 8003d1e: f043 0340 orr.w r3, r3, #64 @ 0x40 8003d22: 62d3 str r3, [r2, #44] @ 0x2c /* SPI1 clock source configuration done later after clock selection check */ break; 8003d24: e013 b.n 8003d4e case RCC_SPI1CLKSOURCE_PLL2P: /* PLL2_P is used as clock source for SPI1 */ __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_PCLK); 8003d26: 4b75 ldr r3, [pc, #468] @ (8003efc ) 8003d28: 6adb ldr r3, [r3, #44] @ 0x2c 8003d2a: 4a74 ldr r2, [pc, #464] @ (8003efc ) 8003d2c: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8003d30: 62d3 str r3, [r2, #44] @ 0x2c /* SPI1 clock source configuration done later after clock selection check */ break; 8003d32: e00c b.n 8003d4e case RCC_SPI1CLKSOURCE_PLL3P: /* PLL3_P is used as clock source for SPI1 */ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_PCLK); 8003d34: 4b71 ldr r3, [pc, #452] @ (8003efc ) 8003d36: 6adb ldr r3, [r3, #44] @ 0x2c 8003d38: 4a70 ldr r2, [pc, #448] @ (8003efc ) 8003d3a: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 8003d3e: 62d3 str r3, [r2, #44] @ 0x2c /* SPI1 clock source configuration done later after clock selection check */ break; 8003d40: e005 b.n 8003d4e case RCC_SPI1CLKSOURCE_CLKP: /* HSI, HSE, or CSI oscillator is used as source of SPI1 clock */ /* SPI1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8003d42: 2301 movs r3, #1 8003d44: 75fb strb r3, [r7, #23] break; 8003d46: e002 b.n 8003d4e break; 8003d48: bf00 nop 8003d4a: e000 b.n 8003d4e break; 8003d4c: bf00 nop } if (ret == HAL_OK) 8003d4e: 7dfb ldrb r3, [r7, #23] 8003d50: 2b00 cmp r3, #0 8003d52: d109 bne.n 8003d68 { /* Set the source of SPI1 clock*/ __HAL_RCC_SPI1_CONFIG(PeriphClkInit->Spi1ClockSelection); 8003d54: 4b69 ldr r3, [pc, #420] @ (8003efc ) 8003d56: 6d5b ldr r3, [r3, #84] @ 0x54 8003d58: f423 62e0 bic.w r2, r3, #1792 @ 0x700 8003d5c: 687b ldr r3, [r7, #4] 8003d5e: 6d9b ldr r3, [r3, #88] @ 0x58 8003d60: 4966 ldr r1, [pc, #408] @ (8003efc ) 8003d62: 4313 orrs r3, r2 8003d64: 654b str r3, [r1, #84] @ 0x54 8003d66: e001 b.n 8003d6c } else { /* set overall return value */ status = ret; 8003d68: 7dfb ldrb r3, [r7, #23] 8003d6a: 75bb strb r3, [r7, #22] } } /*---------------------------- SPI2/SPI3 configuration ---------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPI23) == RCC_PERIPHCLK_SPI23) 8003d6c: 687b ldr r3, [r7, #4] 8003d6e: 681b ldr r3, [r3, #0] 8003d70: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8003d74: 2b00 cmp r3, #0 8003d76: d03c beq.n 8003df2 { /* Check the parameters */ assert_param(IS_RCC_SPI23CLKSOURCE(PeriphClkInit->Spi23ClockSelection)); switch (PeriphClkInit->Spi23ClockSelection) 8003d78: 687b ldr r3, [r7, #4] 8003d7a: 6ddb ldr r3, [r3, #92] @ 0x5c 8003d7c: 2b40 cmp r3, #64 @ 0x40 8003d7e: d026 beq.n 8003dce 8003d80: 2b40 cmp r3, #64 @ 0x40 8003d82: d821 bhi.n 8003dc8 8003d84: 2b30 cmp r3, #48 @ 0x30 8003d86: d024 beq.n 8003dd2 8003d88: 2b30 cmp r3, #48 @ 0x30 8003d8a: d81d bhi.n 8003dc8 8003d8c: 2b20 cmp r3, #32 8003d8e: d014 beq.n 8003dba 8003d90: 2b20 cmp r3, #32 8003d92: d819 bhi.n 8003dc8 8003d94: 2b00 cmp r3, #0 8003d96: d002 beq.n 8003d9e 8003d98: 2b10 cmp r3, #16 8003d9a: d007 beq.n 8003dac 8003d9c: e014 b.n 8003dc8 { case RCC_SPI23CLKSOURCE_PLL1Q: /* PLL1_Q is used as clock source for SPI2/SPI3 */ /* Enable SPI Clock output generated form System PLL . */ __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL_QCLK); 8003d9e: 4b57 ldr r3, [pc, #348] @ (8003efc ) 8003da0: 6adb ldr r3, [r3, #44] @ 0x2c 8003da2: 4a56 ldr r2, [pc, #344] @ (8003efc ) 8003da4: f043 0340 orr.w r3, r3, #64 @ 0x40 8003da8: 62d3 str r3, [r2, #44] @ 0x2c /* SPI2/SPI3 clock source configuration done later after clock selection check */ break; 8003daa: e013 b.n 8003dd4 case RCC_SPI23CLKSOURCE_PLL2P: /* PLL2_P is used as clock source for SPI2/SPI3 */ __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_PCLK); 8003dac: 4b53 ldr r3, [pc, #332] @ (8003efc ) 8003dae: 6adb ldr r3, [r3, #44] @ 0x2c 8003db0: 4a52 ldr r2, [pc, #328] @ (8003efc ) 8003db2: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8003db6: 62d3 str r3, [r2, #44] @ 0x2c /* SPI2/SPI3 clock source configuration done later after clock selection check */ break; 8003db8: e00c b.n 8003dd4 case RCC_SPI23CLKSOURCE_PLL3P: /* PLL3_P is used as clock source for SPI2/SPI3 */ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_PCLK); 8003dba: 4b50 ldr r3, [pc, #320] @ (8003efc ) 8003dbc: 6adb ldr r3, [r3, #44] @ 0x2c 8003dbe: 4a4f ldr r2, [pc, #316] @ (8003efc ) 8003dc0: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 8003dc4: 62d3 str r3, [r2, #44] @ 0x2c /* SPI2/SPI3 clock source configuration done later after clock selection check */ break; 8003dc6: e005 b.n 8003dd4 case RCC_SPI23CLKSOURCE_CLKP: /* HSI, HSE, or CSI oscillator is used as source of SPI2/SPI3 clock */ /* SPI2/SPI3 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8003dc8: 2301 movs r3, #1 8003dca: 75fb strb r3, [r7, #23] break; 8003dcc: e002 b.n 8003dd4 break; 8003dce: bf00 nop 8003dd0: e000 b.n 8003dd4 break; 8003dd2: bf00 nop } if (ret == HAL_OK) 8003dd4: 7dfb ldrb r3, [r7, #23] 8003dd6: 2b00 cmp r3, #0 8003dd8: d109 bne.n 8003dee { /* Set the source of SPI2/SPI3 clock*/ __HAL_RCC_SPI23_CONFIG(PeriphClkInit->Spi23ClockSelection); 8003dda: 4b48 ldr r3, [pc, #288] @ (8003efc ) 8003ddc: 6d1b ldr r3, [r3, #80] @ 0x50 8003dde: f023 0270 bic.w r2, r3, #112 @ 0x70 8003de2: 687b ldr r3, [r7, #4] 8003de4: 6ddb ldr r3, [r3, #92] @ 0x5c 8003de6: 4945 ldr r1, [pc, #276] @ (8003efc ) 8003de8: 4313 orrs r3, r2 8003dea: 650b str r3, [r1, #80] @ 0x50 8003dec: e001 b.n 8003df2 } else { /* set overall return value */ status = ret; 8003dee: 7dfb ldrb r3, [r7, #23] 8003df0: 75bb strb r3, [r7, #22] } } /*---------------------------- SPI4/5 configuration -------------------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) 8003df2: 687b ldr r3, [r7, #4] 8003df4: 681b ldr r3, [r3, #0] 8003df6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8003dfa: 2b00 cmp r3, #0 8003dfc: d03c beq.n 8003e78 { /* Check the parameters */ assert_param(IS_RCC_SPI45CLKSOURCE(PeriphClkInit->Spi45ClockSelection)); switch (PeriphClkInit->Spi45ClockSelection) 8003dfe: 687b ldr r3, [r7, #4] 8003e00: 6e1b ldr r3, [r3, #96] @ 0x60 8003e02: 2b50 cmp r3, #80 @ 0x50 8003e04: d022 beq.n 8003e4c 8003e06: 2b50 cmp r3, #80 @ 0x50 8003e08: d81d bhi.n 8003e46 8003e0a: 2b40 cmp r3, #64 @ 0x40 8003e0c: d020 beq.n 8003e50 8003e0e: 2b40 cmp r3, #64 @ 0x40 8003e10: d819 bhi.n 8003e46 8003e12: 2b30 cmp r3, #48 @ 0x30 8003e14: d01e beq.n 8003e54 8003e16: 2b30 cmp r3, #48 @ 0x30 8003e18: d815 bhi.n 8003e46 8003e1a: 2b20 cmp r3, #32 8003e1c: d00c beq.n 8003e38 8003e1e: 2b20 cmp r3, #32 8003e20: d811 bhi.n 8003e46 8003e22: 2b00 cmp r3, #0 8003e24: d018 beq.n 8003e58 8003e26: 2b10 cmp r3, #16 8003e28: d10d bne.n 8003e46 case RCC_SPI45CLKSOURCE_PCLK2: /* PCLK2 as clock source for SPI4/SPI5 */ /* SPI4/SPI5 clock source configuration done later after clock selection check */ break; case RCC_SPI45CLKSOURCE_PLL2Q: /* PLL2_Q is used as clock source for SPI4/SPI5 */ __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_QCLK); 8003e2a: 4b34 ldr r3, [pc, #208] @ (8003efc ) 8003e2c: 6adb ldr r3, [r3, #44] @ 0x2c 8003e2e: 4a33 ldr r2, [pc, #204] @ (8003efc ) 8003e30: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8003e34: 62d3 str r3, [r2, #44] @ 0x2c /* SPI4/SPI5 clock source configuration done later after clock selection check */ break; 8003e36: e010 b.n 8003e5a case RCC_SPI45CLKSOURCE_PLL3Q: /* PLL3_Q is used as clock source for SPI4/SPI5 */ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_QCLK); 8003e38: 4b30 ldr r3, [pc, #192] @ (8003efc ) 8003e3a: 6adb ldr r3, [r3, #44] @ 0x2c 8003e3c: 4a2f ldr r2, [pc, #188] @ (8003efc ) 8003e3e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8003e42: 62d3 str r3, [r2, #44] @ 0x2c /* SPI4/SPI5 clock source configuration done later after clock selection check */ break; 8003e44: e009 b.n 8003e5a case RCC_SPI45CLKSOURCE_HSE: /* HSE oscillator clock is used as source of SPI4/SPI5 */ /* SPI4/SPI5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8003e46: 2301 movs r3, #1 8003e48: 75fb strb r3, [r7, #23] break; 8003e4a: e006 b.n 8003e5a break; 8003e4c: bf00 nop 8003e4e: e004 b.n 8003e5a break; 8003e50: bf00 nop 8003e52: e002 b.n 8003e5a break; 8003e54: bf00 nop 8003e56: e000 b.n 8003e5a break; 8003e58: bf00 nop } if (ret == HAL_OK) 8003e5a: 7dfb ldrb r3, [r7, #23] 8003e5c: 2b00 cmp r3, #0 8003e5e: d109 bne.n 8003e74 { /* Set the source of SPI4/SPI5 clock */ __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection); 8003e60: 4b26 ldr r3, [pc, #152] @ (8003efc ) 8003e62: 6d5b ldr r3, [r3, #84] @ 0x54 8003e64: f023 0270 bic.w r2, r3, #112 @ 0x70 8003e68: 687b ldr r3, [r7, #4] 8003e6a: 6e1b ldr r3, [r3, #96] @ 0x60 8003e6c: 4923 ldr r1, [pc, #140] @ (8003efc ) 8003e6e: 4313 orrs r3, r2 8003e70: 654b str r3, [r1, #84] @ 0x54 8003e72: e001 b.n 8003e78 } else { /* set overall return value */ status = ret; 8003e74: 7dfb ldrb r3, [r7, #23] 8003e76: 75bb strb r3, [r7, #22] } } /*---------------------------- SPI6 configuration --------------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) 8003e78: 687b ldr r3, [r7, #4] 8003e7a: 681b ldr r3, [r3, #0] 8003e7c: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8003e80: 2b00 cmp r3, #0 8003e82: d03f beq.n 8003f04 { /* Check the parameters */ assert_param(IS_RCC_SPI6CLKSOURCE(PeriphClkInit->Spi6ClockSelection)); switch (PeriphClkInit->Spi6ClockSelection) 8003e84: 687b ldr r3, [r7, #4] 8003e86: 6e5b ldr r3, [r3, #100] @ 0x64 8003e88: 2b50 cmp r3, #80 @ 0x50 8003e8a: d022 beq.n 8003ed2 8003e8c: 2b50 cmp r3, #80 @ 0x50 8003e8e: d81d bhi.n 8003ecc 8003e90: 2b40 cmp r3, #64 @ 0x40 8003e92: d020 beq.n 8003ed6 8003e94: 2b40 cmp r3, #64 @ 0x40 8003e96: d819 bhi.n 8003ecc 8003e98: 2b30 cmp r3, #48 @ 0x30 8003e9a: d01e beq.n 8003eda 8003e9c: 2b30 cmp r3, #48 @ 0x30 8003e9e: d815 bhi.n 8003ecc 8003ea0: 2b20 cmp r3, #32 8003ea2: d00c beq.n 8003ebe 8003ea4: 2b20 cmp r3, #32 8003ea6: d811 bhi.n 8003ecc 8003ea8: 2b00 cmp r3, #0 8003eaa: d018 beq.n 8003ede 8003eac: 2b10 cmp r3, #16 8003eae: d10d bne.n 8003ecc case RCC_SPI6CLKSOURCE_PCLK4: /* PCLK4 as clock source for SPI6 */ /* SPI6 clock source configuration done later after clock selection check */ break; case RCC_SPI6CLKSOURCE_PLL2Q: /* PLL2_Q is used as clock source for SPI6 */ __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_QCLK); 8003eb0: 4b12 ldr r3, [pc, #72] @ (8003efc ) 8003eb2: 6adb ldr r3, [r3, #44] @ 0x2c 8003eb4: 4a11 ldr r2, [pc, #68] @ (8003efc ) 8003eb6: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8003eba: 62d3 str r3, [r2, #44] @ 0x2c /* SPI6 clock source configuration done later after clock selection check */ break; 8003ebc: e010 b.n 8003ee0 case RCC_SPI6CLKSOURCE_PLL3Q: /* PLL3_Q is used as clock source for SPI6 */ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_QCLK); 8003ebe: 4b0f ldr r3, [pc, #60] @ (8003efc ) 8003ec0: 6adb ldr r3, [r3, #44] @ 0x2c 8003ec2: 4a0e ldr r2, [pc, #56] @ (8003efc ) 8003ec4: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8003ec8: 62d3 str r3, [r2, #44] @ 0x2c /* SPI6 clock source configuration done later after clock selection check */ break; 8003eca: e009 b.n 8003ee0 case RCC_SPI6CLKSOURCE_HSE: /* HSE oscillator is used as source for SPI6 */ /* SPI6 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8003ecc: 2301 movs r3, #1 8003ece: 75fb strb r3, [r7, #23] break; 8003ed0: e006 b.n 8003ee0 break; 8003ed2: bf00 nop 8003ed4: e004 b.n 8003ee0 break; 8003ed6: bf00 nop 8003ed8: e002 b.n 8003ee0 break; 8003eda: bf00 nop 8003edc: e000 b.n 8003ee0 break; 8003ede: bf00 nop } if (ret == HAL_OK) 8003ee0: 7dfb ldrb r3, [r7, #23] 8003ee2: 2b00 cmp r3, #0 8003ee4: d10c bne.n 8003f00 { /* Set the source of SPI6 clock*/ __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection); 8003ee6: 4b05 ldr r3, [pc, #20] @ (8003efc ) 8003ee8: 6d9b ldr r3, [r3, #88] @ 0x58 8003eea: f023 0270 bic.w r2, r3, #112 @ 0x70 8003eee: 687b ldr r3, [r7, #4] 8003ef0: 6e5b ldr r3, [r3, #100] @ 0x64 8003ef2: 4902 ldr r1, [pc, #8] @ (8003efc ) 8003ef4: 4313 orrs r3, r2 8003ef6: 658b str r3, [r1, #88] @ 0x58 8003ef8: e004 b.n 8003f04 8003efa: bf00 nop 8003efc: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 8003f00: 7dfb ldrb r3, [r7, #23] 8003f02: 75bb strb r3, [r7, #22] } } /*-------------------------- USART1 configuration --------------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) 8003f04: 687b ldr r3, [r7, #4] 8003f06: 681b ldr r3, [r3, #0] 8003f08: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8003f0c: 2b00 cmp r3, #0 8003f0e: d034 beq.n 8003f7a { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); switch (PeriphClkInit->Usart1ClockSelection) 8003f10: 687b ldr r3, [r7, #4] 8003f12: 6edb ldr r3, [r3, #108] @ 0x6c 8003f14: 2b05 cmp r3, #5 8003f16: d81d bhi.n 8003f54 8003f18: a201 add r2, pc, #4 @ (adr r2, 8003f20 ) 8003f1a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8003f1e: bf00 nop 8003f20: 08003f5b .word 0x08003f5b 8003f24: 08003f39 .word 0x08003f39 8003f28: 08003f47 .word 0x08003f47 8003f2c: 08003f5b .word 0x08003f5b 8003f30: 08003f5b .word 0x08003f5b 8003f34: 08003f5b .word 0x08003f5b case RCC_USART1CLKSOURCE_PCLK2: /* PCLK2 as clock source for USART1 */ /* USART1 clock source configuration done later after clock selection check */ break; case RCC_USART1CLKSOURCE_PLL2Q: /* PLL2_Q is used as clock source for USART1 */ __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_QCLK); 8003f38: 4b69 ldr r3, [pc, #420] @ (80040e0 ) 8003f3a: 6adb ldr r3, [r3, #44] @ 0x2c 8003f3c: 4a68 ldr r2, [pc, #416] @ (80040e0 ) 8003f3e: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8003f42: 62d3 str r3, [r2, #44] @ 0x2c /* USART1 clock source configuration done later after clock selection check */ break; 8003f44: e00a b.n 8003f5c case RCC_USART1CLKSOURCE_PLL3Q: /* PLL3_Q is used as clock source for USART1 */ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_QCLK); 8003f46: 4b66 ldr r3, [pc, #408] @ (80040e0 ) 8003f48: 6adb ldr r3, [r3, #44] @ 0x2c 8003f4a: 4a65 ldr r2, [pc, #404] @ (80040e0 ) 8003f4c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8003f50: 62d3 str r3, [r2, #44] @ 0x2c /* USART1 clock source configuration done later after clock selection check */ break; 8003f52: e003 b.n 8003f5c case RCC_USART1CLKSOURCE_LSE: /* LSE oscillator is used as source for USART1 */ /* USART1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8003f54: 2301 movs r3, #1 8003f56: 75fb strb r3, [r7, #23] break; 8003f58: e000 b.n 8003f5c break; 8003f5a: bf00 nop } if (ret == HAL_OK) 8003f5c: 7dfb ldrb r3, [r7, #23] 8003f5e: 2b00 cmp r3, #0 8003f60: d109 bne.n 8003f76 { /* Set the source of USART1 clock */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); 8003f62: 4b5f ldr r3, [pc, #380] @ (80040e0 ) 8003f64: 6d5b ldr r3, [r3, #84] @ 0x54 8003f66: f023 0207 bic.w r2, r3, #7 8003f6a: 687b ldr r3, [r7, #4] 8003f6c: 6edb ldr r3, [r3, #108] @ 0x6c 8003f6e: 495c ldr r1, [pc, #368] @ (80040e0 ) 8003f70: 4313 orrs r3, r2 8003f72: 654b str r3, [r1, #84] @ 0x54 8003f74: e001 b.n 8003f7a } else { /* set overall return value */ status = ret; 8003f76: 7dfb ldrb r3, [r7, #23] 8003f78: 75bb strb r3, [r7, #22] } } /*------------- USART2/USART3/UART4/UART5/UART7/UART8 Configuration --------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578) 8003f7a: 687b ldr r3, [r7, #4] 8003f7c: 681b ldr r3, [r3, #0] 8003f7e: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8003f82: 2b00 cmp r3, #0 8003f84: d033 beq.n 8003fee { /* Check the parameters */ assert_param(IS_RCC_USART234578CLKSOURCE(PeriphClkInit->Usart234578ClockSelection)); switch (PeriphClkInit->Usart234578ClockSelection) 8003f86: 687b ldr r3, [r7, #4] 8003f88: 6f1b ldr r3, [r3, #112] @ 0x70 8003f8a: 2b05 cmp r3, #5 8003f8c: d81c bhi.n 8003fc8 8003f8e: a201 add r2, pc, #4 @ (adr r2, 8003f94 ) 8003f90: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8003f94: 08003fcf .word 0x08003fcf 8003f98: 08003fad .word 0x08003fad 8003f9c: 08003fbb .word 0x08003fbb 8003fa0: 08003fcf .word 0x08003fcf 8003fa4: 08003fcf .word 0x08003fcf 8003fa8: 08003fcf .word 0x08003fcf case RCC_USART234578CLKSOURCE_PCLK1: /* PCLK1 as clock source for USART2/USART3/UART4/UART5/UART7/UART8 */ /* USART2/USART3/UART4/UART5/UART7/UART8 clock source configuration done later after clock selection check */ break; case RCC_USART234578CLKSOURCE_PLL2Q: /* PLL2_Q is used as clock source for USART2/USART3/UART4/UART5/UART7/UART8 */ __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_QCLK); 8003fac: 4b4c ldr r3, [pc, #304] @ (80040e0 ) 8003fae: 6adb ldr r3, [r3, #44] @ 0x2c 8003fb0: 4a4b ldr r2, [pc, #300] @ (80040e0 ) 8003fb2: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8003fb6: 62d3 str r3, [r2, #44] @ 0x2c /* USART2/USART3/UART4/UART5/UART7/UART8 clock source configuration done later after clock selection check */ break; 8003fb8: e00a b.n 8003fd0 case RCC_USART234578CLKSOURCE_PLL3Q: /* PLL3_Q is used as clock source for USART2/USART3/UART4/UART5/UART7/UART8 */ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_QCLK); 8003fba: 4b49 ldr r3, [pc, #292] @ (80040e0 ) 8003fbc: 6adb ldr r3, [r3, #44] @ 0x2c 8003fbe: 4a48 ldr r2, [pc, #288] @ (80040e0 ) 8003fc0: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8003fc4: 62d3 str r3, [r2, #44] @ 0x2c /* USART2/USART3/UART4/UART5/UART7/UART8 clock source configuration done later after clock selection check */ break; 8003fc6: e003 b.n 8003fd0 /* LSE, oscillator is used as source of USART2/USART3/UART4/UART5/UART7/UART8 clock */ /* USART2/USART3/UART4/UART5/UART7/UART8 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8003fc8: 2301 movs r3, #1 8003fca: 75fb strb r3, [r7, #23] break; 8003fcc: e000 b.n 8003fd0 break; 8003fce: bf00 nop } if (ret == HAL_OK) 8003fd0: 7dfb ldrb r3, [r7, #23] 8003fd2: 2b00 cmp r3, #0 8003fd4: d109 bne.n 8003fea { /* Set the source of USART2/USART3/UART4/UART5/UART7/UART8 clock */ __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection); 8003fd6: 4b42 ldr r3, [pc, #264] @ (80040e0 ) 8003fd8: 6d1b ldr r3, [r3, #80] @ 0x50 8003fda: f023 0207 bic.w r2, r3, #7 8003fde: 687b ldr r3, [r7, #4] 8003fe0: 6f1b ldr r3, [r3, #112] @ 0x70 8003fe2: 493f ldr r1, [pc, #252] @ (80040e0 ) 8003fe4: 4313 orrs r3, r2 8003fe6: 650b str r3, [r1, #80] @ 0x50 8003fe8: e001 b.n 8003fee } else { /* set overall return value */ status = ret; 8003fea: 7dfb ldrb r3, [r7, #23] 8003fec: 75bb strb r3, [r7, #22] } } /*------------------------------ USBPHYC Configuration ---------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USBPHYC) == RCC_PERIPHCLK_USBPHYC) 8003fee: 687b ldr r3, [r7, #4] 8003ff0: 681b ldr r3, [r3, #0] 8003ff2: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 8003ff6: 2b00 cmp r3, #0 8003ff8: d027 beq.n 800404a { /* Check the parameters */ assert_param(IS_RCC_USBPHYCCLKSOURCE(PeriphClkInit->UsbPhycClockSelection)); switch (PeriphClkInit->UsbPhycClockSelection) 8003ffa: 687b ldr r3, [r7, #4] 8003ffc: 6f5b ldr r3, [r3, #116] @ 0x74 8003ffe: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8004002: d008 beq.n 8004016 8004004: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8004008: d80c bhi.n 8004024 800400a: 2b00 cmp r3, #0 800400c: d00d beq.n 800402a 800400e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8004012: d00a beq.n 800402a 8004014: e006 b.n 8004024 { case RCC_USBPHYCCLKSOURCE_PLL3Q: /* PLL3_Q is used as clock source for USBPHYC */ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_QCLK); 8004016: 4b32 ldr r3, [pc, #200] @ (80040e0 ) 8004018: 6adb ldr r3, [r3, #44] @ 0x2c 800401a: 4a31 ldr r2, [pc, #196] @ (80040e0 ) 800401c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8004020: 62d3 str r3, [r2, #44] @ 0x2c /* USBPHYC clock source configuration done later after clock selection check */ break; 8004022: e003 b.n 800402c case RCC_USBPHYCCLKSOURCE_HSE_DIV2: /* HSE divided by 2 is used as clock source for USBPHYC */ /* USBPHYC clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8004024: 2301 movs r3, #1 8004026: 75fb strb r3, [r7, #23] break; 8004028: e000 b.n 800402c break; 800402a: bf00 nop } if (ret == HAL_OK) 800402c: 7dfb ldrb r3, [r7, #23] 800402e: 2b00 cmp r3, #0 8004030: d109 bne.n 8004046 { /* Set the source of USBPHYC clock*/ __HAL_RCC_USBPHYC_CONFIG(PeriphClkInit->UsbPhycClockSelection); 8004032: 4b2b ldr r3, [pc, #172] @ (80040e0 ) 8004034: 6cdb ldr r3, [r3, #76] @ 0x4c 8004036: f423 5240 bic.w r2, r3, #12288 @ 0x3000 800403a: 687b ldr r3, [r7, #4] 800403c: 6f5b ldr r3, [r3, #116] @ 0x74 800403e: 4928 ldr r1, [pc, #160] @ (80040e0 ) 8004040: 4313 orrs r3, r2 8004042: 64cb str r3, [r1, #76] @ 0x4c 8004044: e001 b.n 800404a } else { /* set overall return value */ status = ret; 8004046: 7dfb ldrb r3, [r7, #23] 8004048: 75bb strb r3, [r7, #22] } } /*------------------------------ USBOTGFS Configuration ---------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USBOTGFS) == RCC_PERIPHCLK_USBOTGFS) 800404a: 687b ldr r3, [r7, #4] 800404c: 681b ldr r3, [r3, #0] 800404e: 2b00 cmp r3, #0 8004050: da2c bge.n 80040ac { /* Check the parameters */ assert_param(IS_RCC_USBOTGFSCLKSOURCE(PeriphClkInit->UsbOtgFsClockSelection)); switch (PeriphClkInit->UsbOtgFsClockSelection) 8004052: 687b ldr r3, [r7, #4] 8004054: 6f9b ldr r3, [r3, #120] @ 0x78 8004056: f5b3 4f40 cmp.w r3, #49152 @ 0xc000 800405a: d017 beq.n 800408c 800405c: f5b3 4f40 cmp.w r3, #49152 @ 0xc000 8004060: d811 bhi.n 8004086 8004062: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 8004066: d011 beq.n 800408c 8004068: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800406c: d80b bhi.n 8004086 800406e: 2b00 cmp r3, #0 8004070: d00c beq.n 800408c 8004072: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 8004076: d106 bne.n 8004086 { case RCC_USBOTGFSCLKSOURCE_PLL3Q: /* PLL3_Q is used as clock source for USB OTG FS */ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_QCLK); 8004078: 4b19 ldr r3, [pc, #100] @ (80040e0 ) 800407a: 6adb ldr r3, [r3, #44] @ 0x2c 800407c: 4a18 ldr r2, [pc, #96] @ (80040e0 ) 800407e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8004082: 62d3 str r3, [r2, #44] @ 0x2c /* USB OTG FS clock source configuration done later after clock selection check */ break; 8004084: e003 b.n 800408e case RCC_USBOTGFSCLKSOURCE_CLK48: /* USBPHYC CLK48 is used as clock source for USB OTG FS */ /* USB OTG FS clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8004086: 2301 movs r3, #1 8004088: 75fb strb r3, [r7, #23] break; 800408a: e000 b.n 800408e break; 800408c: bf00 nop } if (ret == HAL_OK) 800408e: 7dfb ldrb r3, [r7, #23] 8004090: 2b00 cmp r3, #0 8004092: d109 bne.n 80040a8 { /* Set the source of USBPHYC clock*/ __HAL_RCC_USBOTGFS_CONFIG(PeriphClkInit->UsbOtgFsClockSelection); 8004094: 4b12 ldr r3, [pc, #72] @ (80040e0 ) 8004096: 6cdb ldr r3, [r3, #76] @ 0x4c 8004098: f423 4240 bic.w r2, r3, #49152 @ 0xc000 800409c: 687b ldr r3, [r7, #4] 800409e: 6f9b ldr r3, [r3, #120] @ 0x78 80040a0: 490f ldr r1, [pc, #60] @ (80040e0 ) 80040a2: 4313 orrs r3, r2 80040a4: 64cb str r3, [r1, #76] @ 0x4c 80040a6: e001 b.n 80040ac } else { /* set overall return value */ status = ret; 80040a8: 7dfb ldrb r3, [r7, #23] 80040aa: 75bb strb r3, [r7, #22] } } /*------------------------------------ TIM configuration --------------------------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) 80040ac: 687b ldr r3, [r7, #4] 80040ae: 681b ldr r3, [r3, #0] 80040b0: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 80040b4: 2b00 cmp r3, #0 80040b6: d009 beq.n 80040cc { /* Check the parameters */ assert_param(IS_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection)); /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER_CONFIG(PeriphClkInit->TIMPresSelection); 80040b8: 4b09 ldr r3, [pc, #36] @ (80040e0 ) 80040ba: 691b ldr r3, [r3, #16] 80040bc: f423 4200 bic.w r2, r3, #32768 @ 0x8000 80040c0: 687b ldr r3, [r7, #4] 80040c2: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80040c6: 4906 ldr r1, [pc, #24] @ (80040e0 ) 80040c8: 4313 orrs r3, r2 80040ca: 610b str r3, [r1, #16] } if (status == HAL_OK) 80040cc: 7dbb ldrb r3, [r7, #22] 80040ce: 2b00 cmp r3, #0 80040d0: d101 bne.n 80040d6 { return HAL_OK; 80040d2: 2300 movs r3, #0 80040d4: e000 b.n 80040d8 } return HAL_ERROR; 80040d6: 2301 movs r3, #1 } 80040d8: 4618 mov r0, r3 80040da: 3718 adds r7, #24 80040dc: 46bd mov sp, r7 80040de: bd80 pop {r7, pc} 80040e0: 58024400 .word 0x58024400 080040e4 : * @arg RCC_PERIPHCLK_USART234578 : USART2/3/5/7/8 peripheral clock * @arg RCC_PERIPHCLK_USBOTGFS : USBOTGFS peripheral clock * @retval Frequency in KHz */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { 80040e4: b580 push {r7, lr} 80040e6: b086 sub sp, #24 80040e8: af00 add r7, sp, #0 80040ea: 6078 str r0, [r7, #4] uint32_t frequency = 0; /* Set to 0 for returned value if no source clock */ 80040ec: 2300 movs r3, #0 80040ee: 617b str r3, [r7, #20] uint32_t clocksource; uint32_t ethclocksource; uint32_t prescaler; switch (PeriphClk) 80040f0: 687b ldr r3, [r7, #4] 80040f2: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80040f6: f001 82db beq.w 80056b0 80040fa: 687b ldr r3, [r7, #4] 80040fc: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8004100: f201 8326 bhi.w 8005750 8004104: 687b ldr r3, [r7, #4] 8004106: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800410a: f001 8298 beq.w 800563e 800410e: 687b ldr r3, [r7, #4] 8004110: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8004114: f201 831c bhi.w 8005750 8004118: 687b ldr r3, [r7, #4] 800411a: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800411e: f001 822a beq.w 8005576 8004122: 687b ldr r3, [r7, #4] 8004124: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004128: f201 8312 bhi.w 8005750 800412c: 687b ldr r3, [r7, #4] 800412e: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8004132: f001 81bb beq.w 80054ac 8004136: 687b ldr r3, [r7, #4] 8004138: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800413c: f201 8308 bhi.w 8005750 8004140: 687b ldr r3, [r7, #4] 8004142: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 8004146: f001 8139 beq.w 80053bc 800414a: 687b ldr r3, [r7, #4] 800414c: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 8004150: f201 82fe bhi.w 8005750 8004154: 687b ldr r3, [r7, #4] 8004156: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800415a: f001 80bf beq.w 80052dc 800415e: 687b ldr r3, [r7, #4] 8004160: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 8004164: f201 82f4 bhi.w 8005750 8004168: 687b ldr r3, [r7, #4] 800416a: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800416e: f001 8069 beq.w 8005244 8004172: 687b ldr r3, [r7, #4] 8004174: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8004178: f201 82ea bhi.w 8005750 800417c: 687b ldr r3, [r7, #4] 800417e: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 8004182: f001 8007 beq.w 8005194 8004186: 687b ldr r3, [r7, #4] 8004188: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800418c: f201 82e0 bhi.w 8005750 8004190: 687b ldr r3, [r7, #4] 8004192: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8004196: f000 87a2 beq.w 80050de 800419a: 687b ldr r3, [r7, #4] 800419c: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 80041a0: f201 82d6 bhi.w 8005750 80041a4: 687b ldr r3, [r7, #4] 80041a6: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 80041aa: f000 877a beq.w 80050a2 80041ae: 687b ldr r3, [r7, #4] 80041b0: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 80041b4: f201 82cc bhi.w 8005750 80041b8: 687b ldr r3, [r7, #4] 80041ba: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 80041be: f000 8713 beq.w 8004fe8 80041c2: 687b ldr r3, [r7, #4] 80041c4: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 80041c8: f201 82c2 bhi.w 8005750 80041cc: 687b ldr r3, [r7, #4] 80041ce: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 80041d2: f000 86ad beq.w 8004f30 80041d6: 687b ldr r3, [r7, #4] 80041d8: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 80041dc: f201 82b8 bhi.w 8005750 80041e0: 687b ldr r3, [r7, #4] 80041e2: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 80041e6: f000 8644 beq.w 8004e72 80041ea: 687b ldr r3, [r7, #4] 80041ec: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 80041f0: f201 82ae bhi.w 8005750 80041f4: 687b ldr r3, [r7, #4] 80041f6: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 80041fa: f000 861c beq.w 8004e36 80041fe: 687b ldr r3, [r7, #4] 8004200: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8004204: f201 82a4 bhi.w 8005750 8004208: 687b ldr r3, [r7, #4] 800420a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800420e: f000 8606 beq.w 8004e1e 8004212: 687b ldr r3, [r7, #4] 8004214: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8004218: f201 829a bhi.w 8005750 800421c: 687b ldr r3, [r7, #4] 800421e: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 8004222: f000 8592 beq.w 8004d4a 8004226: 687b ldr r3, [r7, #4] 8004228: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800422c: f201 8290 bhi.w 8005750 8004230: 687b ldr r3, [r7, #4] 8004232: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 8004236: f000 8519 beq.w 8004c6c 800423a: 687b ldr r3, [r7, #4] 800423c: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 8004240: f201 8286 bhi.w 8005750 8004244: 687b ldr r3, [r7, #4] 8004246: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800424a: f000 84a3 beq.w 8004b94 800424e: 687b ldr r3, [r7, #4] 8004250: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8004254: f201 827c bhi.w 8005750 8004258: 687b ldr r3, [r7, #4] 800425a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800425e: f000 842d beq.w 8004abc 8004262: 687b ldr r3, [r7, #4] 8004264: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8004268: f201 8272 bhi.w 8005750 800426c: 687b ldr r3, [r7, #4] 800426e: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8004272: f000 83c5 beq.w 8004a00 8004276: 687b ldr r3, [r7, #4] 8004278: f5b3 6f00 cmp.w r3, #2048 @ 0x800 800427c: f201 8268 bhi.w 8005750 8004280: 687b ldr r3, [r7, #4] 8004282: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8004286: f000 8365 beq.w 8004954 800428a: 687b ldr r3, [r7, #4] 800428c: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8004290: f201 825e bhi.w 8005750 8004294: 687b ldr r3, [r7, #4] 8004296: f5b3 7f00 cmp.w r3, #512 @ 0x200 800429a: f000 831d beq.w 80048d8 800429e: 687b ldr r3, [r7, #4] 80042a0: f5b3 7f00 cmp.w r3, #512 @ 0x200 80042a4: f201 8254 bhi.w 8005750 80042a8: 687b ldr r3, [r7, #4] 80042aa: f5b3 7f80 cmp.w r3, #256 @ 0x100 80042ae: f000 82ed beq.w 800488c 80042b2: 687b ldr r3, [r7, #4] 80042b4: f5b3 7f80 cmp.w r3, #256 @ 0x100 80042b8: f201 824a bhi.w 8005750 80042bc: 687b ldr r3, [r7, #4] 80042be: 2b80 cmp r3, #128 @ 0x80 80042c0: f000 8291 beq.w 80047e6 80042c4: 687b ldr r3, [r7, #4] 80042c6: 2b80 cmp r3, #128 @ 0x80 80042c8: f201 8242 bhi.w 8005750 80042cc: 687b ldr r3, [r7, #4] 80042ce: 2b20 cmp r3, #32 80042d0: d84c bhi.n 800436c 80042d2: 687b ldr r3, [r7, #4] 80042d4: 2b00 cmp r3, #0 80042d6: f001 823b beq.w 8005750 80042da: 687b ldr r3, [r7, #4] 80042dc: 3b01 subs r3, #1 80042de: 2b1f cmp r3, #31 80042e0: f201 8236 bhi.w 8005750 80042e4: a201 add r2, pc, #4 @ (adr r2, 80042ec ) 80042e6: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80042ea: bf00 nop 80042ec: 08004379 .word 0x08004379 80042f0: 08004447 .word 0x08004447 80042f4: 08005751 .word 0x08005751 80042f8: 080044d7 .word 0x080044d7 80042fc: 08005751 .word 0x08005751 8004300: 08005751 .word 0x08005751 8004304: 08005751 .word 0x08005751 8004308: 0800456f .word 0x0800456f 800430c: 08005751 .word 0x08005751 8004310: 08005751 .word 0x08005751 8004314: 08005751 .word 0x08005751 8004318: 08005751 .word 0x08005751 800431c: 08005751 .word 0x08005751 8004320: 08005751 .word 0x08005751 8004324: 08005751 .word 0x08005751 8004328: 08004611 .word 0x08004611 800432c: 08005751 .word 0x08005751 8004330: 08005751 .word 0x08005751 8004334: 08005751 .word 0x08005751 8004338: 08005751 .word 0x08005751 800433c: 08005751 .word 0x08005751 8004340: 08005751 .word 0x08005751 8004344: 08005751 .word 0x08005751 8004348: 08005751 .word 0x08005751 800434c: 08005751 .word 0x08005751 8004350: 08005751 .word 0x08005751 8004354: 08005751 .word 0x08005751 8004358: 08005751 .word 0x08005751 800435c: 08005751 .word 0x08005751 8004360: 08005751 .word 0x08005751 8004364: 08005751 .word 0x08005751 8004368: 0800467d .word 0x0800467d 800436c: 687b ldr r3, [r7, #4] 800436e: 2b40 cmp r3, #64 @ 0x40 8004370: f000 81fb beq.w 800476a } break; default: /* Nothing to do, frequency is by default set to 0 */ break; 8004374: f001 b9ec b.w 8005750 clocksource = __HAL_RCC_GET_FMC_SOURCE(); 8004378: 4ba1 ldr r3, [pc, #644] @ (8004600 ) 800437a: f8d3 3100 ldr.w r3, [r3, #256] @ 0x100 800437e: f403 43e0 and.w r3, r3, #28672 @ 0x7000 8004382: f5b3 4fa0 cmp.w r3, #20480 @ 0x5000 8004386: d004 beq.n 8004392 8004388: 4b9d ldr r3, [pc, #628] @ (8004600 ) 800438a: 6cdb ldr r3, [r3, #76] @ 0x4c 800438c: f003 0303 and.w r3, r3, #3 8004390: e001 b.n 8004396 8004392: f44f 43a0 mov.w r3, #20480 @ 0x5000 8004396: 613b str r3, [r7, #16] switch (clocksource) 8004398: 693b ldr r3, [r7, #16] 800439a: 2b03 cmp r3, #3 800439c: d80e bhi.n 80043bc 800439e: 693b ldr r3, [r7, #16] 80043a0: 2b03 cmp r3, #3 80043a2: d844 bhi.n 800442e 80043a4: a201 add r2, pc, #4 @ (adr r2, 80043ac ) 80043a6: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80043aa: bf00 nop 80043ac: 080043c7 .word 0x080043c7 80043b0: 080043cf .word 0x080043cf 80043b4: 080043e3 .word 0x080043e3 80043b8: 080043f7 .word 0x080043f7 80043bc: 693b ldr r3, [r7, #16] 80043be: f5b3 4fa0 cmp.w r3, #20480 @ 0x5000 80043c2: d02e beq.n 8004422 break; 80043c4: e033 b.n 800442e frequency = HAL_RCC_GetHCLKFreq(); 80043c6: f7fe fb47 bl 8002a58 80043ca: 6178 str r0, [r7, #20] break; 80043cc: e039 b.n 8004442 if (__HAL_RCC_GET_PLL1CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) 80043ce: 4b8c ldr r3, [pc, #560] @ (8004600 ) 80043d0: 6adb ldr r3, [r3, #44] @ 0x2c 80043d2: f003 0340 and.w r3, r3, #64 @ 0x40 80043d6: 2b00 cmp r3, #0 80043d8: d02c beq.n 8004434 frequency = HAL_RCC_GetPLL1QFreq(); 80043da: f7fe fbb9 bl 8002b50 80043de: 6178 str r0, [r7, #20] break; 80043e0: e028 b.n 8004434 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U) 80043e2: 4b87 ldr r3, [pc, #540] @ (8004600 ) 80043e4: 6adb ldr r3, [r3, #44] @ 0x2c 80043e6: f403 2380 and.w r3, r3, #262144 @ 0x40000 80043ea: 2b00 cmp r3, #0 80043ec: d025 beq.n 800443a frequency = HAL_RCC_GetPLL2RFreq(); 80043ee: f7fe fbf1 bl 8002bd4 80043f2: 6178 str r0, [r7, #20] break; 80043f4: e021 b.n 800443a if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 80043f6: 4b82 ldr r3, [pc, #520] @ (8004600 ) 80043f8: 681b ldr r3, [r3, #0] 80043fa: f003 0304 and.w r3, r3, #4 80043fe: 2b00 cmp r3, #0 8004400: d01e beq.n 8004440 if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) 8004402: 4b7f ldr r3, [pc, #508] @ (8004600 ) 8004404: 681b ldr r3, [r3, #0] 8004406: f003 0320 and.w r3, r3, #32 800440a: 2b00 cmp r3, #0 800440c: d018 beq.n 8004440 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); 800440e: 4b7c ldr r3, [pc, #496] @ (8004600 ) 8004410: 681b ldr r3, [r3, #0] 8004412: 08db lsrs r3, r3, #3 8004414: f003 0303 and.w r3, r3, #3 8004418: 4a7a ldr r2, [pc, #488] @ (8004604 ) 800441a: fa22 f303 lsr.w r3, r2, r3 800441e: 617b str r3, [r7, #20] break; 8004420: e00e b.n 8004440 frequency = (HAL_RCC_GetHCLKFreq() / 4U); 8004422: f7fe fb19 bl 8002a58 8004426: 4603 mov r3, r0 8004428: 089b lsrs r3, r3, #2 800442a: 617b str r3, [r7, #20] break; 800442c: e009 b.n 8004442 break; 800442e: bf00 nop 8004430: f001 b993 b.w 800575a break; 8004434: bf00 nop 8004436: f001 b990 b.w 800575a break; 800443a: bf00 nop 800443c: f001 b98d b.w 800575a break; 8004440: bf00 nop break; 8004442: f001 b98a b.w 800575a clocksource = __HAL_RCC_GET_XSPI1_SOURCE(); 8004446: 4b6e ldr r3, [pc, #440] @ (8004600 ) 8004448: f8d3 3100 ldr.w r3, [r3, #256] @ 0x100 800444c: f003 0370 and.w r3, r3, #112 @ 0x70 8004450: 2b40 cmp r3, #64 @ 0x40 8004452: d004 beq.n 800445e 8004454: 4b6a ldr r3, [pc, #424] @ (8004600 ) 8004456: 6cdb ldr r3, [r3, #76] @ 0x4c 8004458: f003 0330 and.w r3, r3, #48 @ 0x30 800445c: e000 b.n 8004460 800445e: 2340 movs r3, #64 @ 0x40 8004460: 613b str r3, [r7, #16] switch (clocksource) 8004462: 693b ldr r3, [r7, #16] 8004464: 2b40 cmp r3, #64 @ 0x40 8004466: d027 beq.n 80044b8 8004468: 693b ldr r3, [r7, #16] 800446a: 2b40 cmp r3, #64 @ 0x40 800446c: d82a bhi.n 80044c4 800446e: 693b ldr r3, [r7, #16] 8004470: 2b20 cmp r3, #32 8004472: d017 beq.n 80044a4 8004474: 693b ldr r3, [r7, #16] 8004476: 2b20 cmp r3, #32 8004478: d824 bhi.n 80044c4 800447a: 693b ldr r3, [r7, #16] 800447c: 2b00 cmp r3, #0 800447e: d003 beq.n 8004488 8004480: 693b ldr r3, [r7, #16] 8004482: 2b10 cmp r3, #16 8004484: d004 beq.n 8004490 break; 8004486: e01d b.n 80044c4 frequency = HAL_RCC_GetHCLKFreq(); 8004488: f7fe fae6 bl 8002a58 800448c: 6178 str r0, [r7, #20] break; 800448e: e020 b.n 80044d2 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_SCLK) != 0U) 8004490: 4b5b ldr r3, [pc, #364] @ (8004600 ) 8004492: 6adb ldr r3, [r3, #44] @ 0x2c 8004494: f403 2300 and.w r3, r3, #524288 @ 0x80000 8004498: 2b00 cmp r3, #0 800449a: d016 beq.n 80044ca frequency = HAL_RCC_GetPLL2SFreq(); 800449c: f7fe fbb0 bl 8002c00 80044a0: 6178 str r0, [r7, #20] break; 80044a2: e012 b.n 80044ca if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_TCLK) != 0U) 80044a4: 4b56 ldr r3, [pc, #344] @ (8004600 ) 80044a6: 6adb ldr r3, [r3, #44] @ 0x2c 80044a8: f403 1380 and.w r3, r3, #1048576 @ 0x100000 80044ac: 2b00 cmp r3, #0 80044ae: d00f beq.n 80044d0 frequency = HAL_RCC_GetPLL2TFreq(); 80044b0: f7fe fbbc bl 8002c2c 80044b4: 6178 str r0, [r7, #20] break; 80044b6: e00b b.n 80044d0 frequency = (HAL_RCC_GetHCLKFreq() / 4U); 80044b8: f7fe face bl 8002a58 80044bc: 4603 mov r3, r0 80044be: 089b lsrs r3, r3, #2 80044c0: 617b str r3, [r7, #20] break; 80044c2: e006 b.n 80044d2 break; 80044c4: bf00 nop 80044c6: f001 b948 b.w 800575a break; 80044ca: bf00 nop 80044cc: f001 b945 b.w 800575a break; 80044d0: bf00 nop break; 80044d2: f001 b942 b.w 800575a clocksource = __HAL_RCC_GET_XSPI2_SOURCE(); 80044d6: 4b4a ldr r3, [pc, #296] @ (8004600 ) 80044d8: f8d3 3100 ldr.w r3, [r3, #256] @ 0x100 80044dc: f403 63e0 and.w r3, r3, #1792 @ 0x700 80044e0: f5b3 6f80 cmp.w r3, #1024 @ 0x400 80044e4: d004 beq.n 80044f0 80044e6: 4b46 ldr r3, [pc, #280] @ (8004600 ) 80044e8: 6cdb ldr r3, [r3, #76] @ 0x4c 80044ea: f003 03c0 and.w r3, r3, #192 @ 0xc0 80044ee: e001 b.n 80044f4 80044f0: f44f 6380 mov.w r3, #1024 @ 0x400 80044f4: 613b str r3, [r7, #16] switch (clocksource) 80044f6: 693b ldr r3, [r7, #16] 80044f8: f5b3 6f80 cmp.w r3, #1024 @ 0x400 80044fc: d028 beq.n 8004550 80044fe: 693b ldr r3, [r7, #16] 8004500: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8004504: d82a bhi.n 800455c 8004506: 693b ldr r3, [r7, #16] 8004508: 2b80 cmp r3, #128 @ 0x80 800450a: d017 beq.n 800453c 800450c: 693b ldr r3, [r7, #16] 800450e: 2b80 cmp r3, #128 @ 0x80 8004510: d824 bhi.n 800455c 8004512: 693b ldr r3, [r7, #16] 8004514: 2b00 cmp r3, #0 8004516: d003 beq.n 8004520 8004518: 693b ldr r3, [r7, #16] 800451a: 2b40 cmp r3, #64 @ 0x40 800451c: d004 beq.n 8004528 break; 800451e: e01d b.n 800455c frequency = HAL_RCC_GetHCLKFreq(); 8004520: f7fe fa9a bl 8002a58 8004524: 6178 str r0, [r7, #20] break; 8004526: e020 b.n 800456a if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_SCLK) != 0U) 8004528: 4b35 ldr r3, [pc, #212] @ (8004600 ) 800452a: 6adb ldr r3, [r3, #44] @ 0x2c 800452c: f403 2300 and.w r3, r3, #524288 @ 0x80000 8004530: 2b00 cmp r3, #0 8004532: d016 beq.n 8004562 frequency = HAL_RCC_GetPLL2SFreq(); 8004534: f7fe fb64 bl 8002c00 8004538: 6178 str r0, [r7, #20] break; 800453a: e012 b.n 8004562 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_TCLK) != 0U) 800453c: 4b30 ldr r3, [pc, #192] @ (8004600 ) 800453e: 6adb ldr r3, [r3, #44] @ 0x2c 8004540: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8004544: 2b00 cmp r3, #0 8004546: d00f beq.n 8004568 frequency = HAL_RCC_GetPLL2TFreq(); 8004548: f7fe fb70 bl 8002c2c 800454c: 6178 str r0, [r7, #20] break; 800454e: e00b b.n 8004568 frequency = (HAL_RCC_GetHCLKFreq() / 4U); 8004550: f7fe fa82 bl 8002a58 8004554: 4603 mov r3, r0 8004556: 089b lsrs r3, r3, #2 8004558: 617b str r3, [r7, #20] break; 800455a: e006 b.n 800456a break; 800455c: bf00 nop 800455e: f001 b8fc b.w 800575a break; 8004562: bf00 nop 8004564: f001 b8f9 b.w 800575a break; 8004568: bf00 nop break; 800456a: f001 b8f6 b.w 800575a clocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800456e: 4b24 ldr r3, [pc, #144] @ (8004600 ) 8004570: 6cdb ldr r3, [r3, #76] @ 0x4c 8004572: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 8004576: 613b str r3, [r7, #16] switch (clocksource) 8004578: 693b ldr r3, [r7, #16] 800457a: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800457e: d02a beq.n 80045d6 8004580: 693b ldr r3, [r7, #16] 8004582: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004586: d82f bhi.n 80045e8 8004588: 693b ldr r3, [r7, #16] 800458a: 2b00 cmp r3, #0 800458c: d004 beq.n 8004598 800458e: 693b ldr r3, [r7, #16] 8004590: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8004594: d016 beq.n 80045c4 break; 8004596: e027 b.n 80045e8 if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 8004598: 4b19 ldr r3, [pc, #100] @ (8004600 ) 800459a: 681b ldr r3, [r3, #0] 800459c: f003 0304 and.w r3, r3, #4 80045a0: 2b00 cmp r3, #0 80045a2: d024 beq.n 80045ee if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) 80045a4: 4b16 ldr r3, [pc, #88] @ (8004600 ) 80045a6: 681b ldr r3, [r3, #0] 80045a8: f003 0320 and.w r3, r3, #32 80045ac: 2b00 cmp r3, #0 80045ae: d01e beq.n 80045ee frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); 80045b0: 4b13 ldr r3, [pc, #76] @ (8004600 ) 80045b2: 681b ldr r3, [r3, #0] 80045b4: 08db lsrs r3, r3, #3 80045b6: f003 0303 and.w r3, r3, #3 80045ba: 4a12 ldr r2, [pc, #72] @ (8004604 ) 80045bc: fa22 f303 lsr.w r3, r2, r3 80045c0: 617b str r3, [r7, #20] break; 80045c2: e014 b.n 80045ee if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U) 80045c4: 4b0e ldr r3, [pc, #56] @ (8004600 ) 80045c6: 681b ldr r3, [r3, #0] 80045c8: f403 7380 and.w r3, r3, #256 @ 0x100 80045cc: 2b00 cmp r3, #0 80045ce: d011 beq.n 80045f4 frequency = CSI_VALUE; 80045d0: 4b0d ldr r3, [pc, #52] @ (8004608 ) 80045d2: 617b str r3, [r7, #20] break; 80045d4: e00e b.n 80045f4 if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 80045d6: 4b0a ldr r3, [pc, #40] @ (8004600 ) 80045d8: 681b ldr r3, [r3, #0] 80045da: f403 3300 and.w r3, r3, #131072 @ 0x20000 80045de: 2b00 cmp r3, #0 80045e0: d00b beq.n 80045fa frequency = HSE_VALUE; 80045e2: 4b0a ldr r3, [pc, #40] @ (800460c ) 80045e4: 617b str r3, [r7, #20] break; 80045e6: e008 b.n 80045fa break; 80045e8: bf00 nop 80045ea: f001 b8b6 b.w 800575a break; 80045ee: bf00 nop 80045f0: f001 b8b3 b.w 800575a break; 80045f4: bf00 nop 80045f6: f001 b8b0 b.w 800575a break; 80045fa: bf00 nop break; 80045fc: f001 b8ad b.w 800575a 8004600: 58024400 .word 0x58024400 8004604: 03d09000 .word 0x03d09000 8004608: 003d0900 .word 0x003d0900 800460c: 016e3600 .word 0x016e3600 clocksource = __HAL_RCC_GET_ADC_SOURCE(); 8004610: 4b9a ldr r3, [pc, #616] @ (800487c ) 8004612: 6cdb ldr r3, [r3, #76] @ 0x4c 8004614: f003 7340 and.w r3, r3, #50331648 @ 0x3000000 8004618: 613b str r3, [r7, #16] switch (clocksource) 800461a: 693b ldr r3, [r7, #16] 800461c: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 8004620: d01f beq.n 8004662 8004622: 693b ldr r3, [r7, #16] 8004624: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 8004628: d81f bhi.n 800466a 800462a: 693b ldr r3, [r7, #16] 800462c: 2b00 cmp r3, #0 800462e: d004 beq.n 800463a 8004630: 693b ldr r3, [r7, #16] 8004632: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8004636: d00a beq.n 800464e break; 8004638: e017 b.n 800466a if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U) 800463a: 4b90 ldr r3, [pc, #576] @ (800487c ) 800463c: 6adb ldr r3, [r3, #44] @ 0x2c 800463e: f403 3380 and.w r3, r3, #65536 @ 0x10000 8004642: 2b00 cmp r3, #0 8004644: d014 beq.n 8004670 frequency = HAL_RCC_GetPLL2PFreq(); 8004646: f7fe fa99 bl 8002b7c 800464a: 6178 str r0, [r7, #20] break; 800464c: e010 b.n 8004670 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U) 800464e: 4b8b ldr r3, [pc, #556] @ (800487c ) 8004650: 6adb ldr r3, [r3, #44] @ 0x2c 8004652: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8004656: 2b00 cmp r3, #0 8004658: d00d beq.n 8004676 frequency = HAL_RCC_GetPLL3RFreq(); 800465a: f7fe fb2b bl 8002cb4 800465e: 6178 str r0, [r7, #20] break; 8004660: e009 b.n 8004676 frequency = RCC_GetCLKPFreq(); 8004662: f001 f893 bl 800578c 8004666: 6178 str r0, [r7, #20] break; 8004668: e006 b.n 8004678 break; 800466a: bf00 nop 800466c: f001 b875 b.w 800575a break; 8004670: bf00 nop 8004672: f001 b872 b.w 800575a break; 8004676: bf00 nop break; 8004678: f001 b86f b.w 800575a clocksource = __HAL_RCC_GET_ADF1_SOURCE(); 800467c: 4b7f ldr r3, [pc, #508] @ (800487c ) 800467e: 6cdb ldr r3, [r3, #76] @ 0x4c 8004680: f403 03e0 and.w r3, r3, #7340032 @ 0x700000 8004684: 613b str r3, [r7, #16] switch (clocksource) 8004686: 693b ldr r3, [r7, #16] 8004688: f5b3 0fa0 cmp.w r3, #5242880 @ 0x500000 800468c: d048 beq.n 8004720 800468e: 693b ldr r3, [r7, #16] 8004690: f5b3 0fa0 cmp.w r3, #5242880 @ 0x500000 8004694: d85a bhi.n 800474c 8004696: 693b ldr r3, [r7, #16] 8004698: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800469c: d037 beq.n 800470e 800469e: 693b ldr r3, [r7, #16] 80046a0: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 80046a4: d852 bhi.n 800474c 80046a6: 693b ldr r3, [r7, #16] 80046a8: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 80046ac: d02b beq.n 8004706 80046ae: 693b ldr r3, [r7, #16] 80046b0: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 80046b4: d84a bhi.n 800474c 80046b6: 693b ldr r3, [r7, #16] 80046b8: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 80046bc: d019 beq.n 80046f2 80046be: 693b ldr r3, [r7, #16] 80046c0: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 80046c4: d842 bhi.n 800474c 80046c6: 693b ldr r3, [r7, #16] 80046c8: 2b00 cmp r3, #0 80046ca: d004 beq.n 80046d6 80046cc: 693b ldr r3, [r7, #16] 80046ce: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 80046d2: d004 beq.n 80046de break; 80046d4: e03a b.n 800474c frequency = HAL_RCC_GetHCLKFreq(); 80046d6: f7fe f9bf bl 8002a58 80046da: 6178 str r0, [r7, #20] break; 80046dc: e043 b.n 8004766 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U) 80046de: 4b67 ldr r3, [pc, #412] @ (800487c ) 80046e0: 6adb ldr r3, [r3, #44] @ 0x2c 80046e2: f403 3380 and.w r3, r3, #65536 @ 0x10000 80046e6: 2b00 cmp r3, #0 80046e8: d033 beq.n 8004752 frequency = HAL_RCC_GetPLL2PFreq(); 80046ea: f7fe fa47 bl 8002b7c 80046ee: 6178 str r0, [r7, #20] break; 80046f0: e02f b.n 8004752 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U) 80046f2: 4b62 ldr r3, [pc, #392] @ (800487c ) 80046f4: 6adb ldr r3, [r3, #44] @ 0x2c 80046f6: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 80046fa: 2b00 cmp r3, #0 80046fc: d02c beq.n 8004758 frequency = HAL_RCC_GetPLL3PFreq(); 80046fe: f7fe faad bl 8002c5c 8004702: 6178 str r0, [r7, #20] break; 8004704: e028 b.n 8004758 frequency = EXTERNAL_CLOCK_VALUE; 8004706: f64b 3380 movw r3, #48000 @ 0xbb80 800470a: 617b str r3, [r7, #20] break; 800470c: e02b b.n 8004766 if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U) 800470e: 4b5b ldr r3, [pc, #364] @ (800487c ) 8004710: 681b ldr r3, [r3, #0] 8004712: f403 7380 and.w r3, r3, #256 @ 0x100 8004716: 2b00 cmp r3, #0 8004718: d021 beq.n 800475e frequency = CSI_VALUE; 800471a: 4b59 ldr r3, [pc, #356] @ (8004880 ) 800471c: 617b str r3, [r7, #20] break; 800471e: e01e b.n 800475e if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 8004720: 4b56 ldr r3, [pc, #344] @ (800487c ) 8004722: 681b ldr r3, [r3, #0] 8004724: f003 0304 and.w r3, r3, #4 8004728: 2b00 cmp r3, #0 800472a: d01b beq.n 8004764 if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) 800472c: 4b53 ldr r3, [pc, #332] @ (800487c ) 800472e: 681b ldr r3, [r3, #0] 8004730: f003 0320 and.w r3, r3, #32 8004734: 2b00 cmp r3, #0 8004736: d015 beq.n 8004764 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); 8004738: 4b50 ldr r3, [pc, #320] @ (800487c ) 800473a: 681b ldr r3, [r3, #0] 800473c: 08db lsrs r3, r3, #3 800473e: f003 0303 and.w r3, r3, #3 8004742: 4a50 ldr r2, [pc, #320] @ (8004884 ) 8004744: fa22 f303 lsr.w r3, r2, r3 8004748: 617b str r3, [r7, #20] break; 800474a: e00b b.n 8004764 break; 800474c: bf00 nop 800474e: f001 b804 b.w 800575a break; 8004752: bf00 nop 8004754: f001 b801 b.w 800575a break; 8004758: bf00 nop 800475a: f000 bffe b.w 800575a break; 800475e: bf00 nop 8004760: f000 bffb b.w 800575a break; 8004764: bf00 nop break; 8004766: f000 bff8 b.w 800575a clocksource = __HAL_RCC_GET_CEC_SOURCE(); 800476a: 4b44 ldr r3, [pc, #272] @ (800487c ) 800476c: 6d1b ldr r3, [r3, #80] @ 0x50 800476e: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 8004772: 613b str r3, [r7, #16] switch (clocksource) 8004774: 693b ldr r3, [r7, #16] 8004776: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800477a: d01f beq.n 80047bc 800477c: 693b ldr r3, [r7, #16] 800477e: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004782: d824 bhi.n 80047ce 8004784: 693b ldr r3, [r7, #16] 8004786: 2b00 cmp r3, #0 8004788: d004 beq.n 8004794 800478a: 693b ldr r3, [r7, #16] 800478c: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8004790: d00a beq.n 80047a8 break; 8004792: e01c b.n 80047ce if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) 8004794: 4b39 ldr r3, [pc, #228] @ (800487c ) 8004796: 6f1b ldr r3, [r3, #112] @ 0x70 8004798: f003 0302 and.w r3, r3, #2 800479c: 2b00 cmp r3, #0 800479e: d019 beq.n 80047d4 frequency = LSE_VALUE; 80047a0: f44f 4300 mov.w r3, #32768 @ 0x8000 80047a4: 617b str r3, [r7, #20] break; 80047a6: e015 b.n 80047d4 if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) 80047a8: 4b34 ldr r3, [pc, #208] @ (800487c ) 80047aa: 6f5b ldr r3, [r3, #116] @ 0x74 80047ac: f003 0302 and.w r3, r3, #2 80047b0: 2b00 cmp r3, #0 80047b2: d012 beq.n 80047da frequency = LSI_VALUE; 80047b4: f44f 43fa mov.w r3, #32000 @ 0x7d00 80047b8: 617b str r3, [r7, #20] break; 80047ba: e00e b.n 80047da if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U) 80047bc: 4b2f ldr r3, [pc, #188] @ (800487c ) 80047be: 681b ldr r3, [r3, #0] 80047c0: f403 7380 and.w r3, r3, #256 @ 0x100 80047c4: 2b00 cmp r3, #0 80047c6: d00b beq.n 80047e0 frequency = CSI_VALUE; 80047c8: 4b2d ldr r3, [pc, #180] @ (8004880 ) 80047ca: 617b str r3, [r7, #20] break; 80047cc: e008 b.n 80047e0 break; 80047ce: bf00 nop 80047d0: f000 bfc3 b.w 800575a break; 80047d4: bf00 nop 80047d6: f000 bfc0 b.w 800575a break; 80047da: bf00 nop 80047dc: f000 bfbd b.w 800575a break; 80047e0: bf00 nop break; 80047e2: f000 bfba b.w 800575a clocksource = __HAL_RCC_GET_ETH1REF_SOURCE(); 80047e6: 4b25 ldr r3, [pc, #148] @ (800487c ) 80047e8: 6cdb ldr r3, [r3, #76] @ 0x4c 80047ea: f403 3340 and.w r3, r3, #196608 @ 0x30000 80047ee: 613b str r3, [r7, #16] switch (clocksource) 80047f0: 693b ldr r3, [r7, #16] 80047f2: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 80047f6: d014 beq.n 8004822 80047f8: 693b ldr r3, [r7, #16] 80047fa: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 80047fe: d834 bhi.n 800486a 8004800: 693b ldr r3, [r7, #16] 8004802: 2b00 cmp r3, #0 8004804: d034 beq.n 8004870 8004806: 693b ldr r3, [r7, #16] 8004808: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800480c: d000 beq.n 8004810 break; 800480e: e02c b.n 800486a if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 8004810: 4b1a ldr r3, [pc, #104] @ (800487c ) 8004812: 681b ldr r3, [r3, #0] 8004814: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004818: 2b00 cmp r3, #0 800481a: d02c beq.n 8004876 frequency = HSE_VALUE; 800481c: 4b1a ldr r3, [pc, #104] @ (8004888 ) 800481e: 617b str r3, [r7, #20] break; 8004820: e029 b.n 8004876 ethclocksource = __HAL_RCC_GET_ETH1PHY_SOURCE(); 8004822: 4b16 ldr r3, [pc, #88] @ (800487c ) 8004824: 6cdb ldr r3, [r3, #76] @ 0x4c 8004826: f403 2380 and.w r3, r3, #262144 @ 0x40000 800482a: 60bb str r3, [r7, #8] switch (ethclocksource) 800482c: 68bb ldr r3, [r7, #8] 800482e: 2b00 cmp r3, #0 8004830: d004 beq.n 800483c 8004832: 68bb ldr r3, [r7, #8] 8004834: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8004838: d009 beq.n 800484e break; 800483a: e015 b.n 8004868 if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 800483c: 4b0f ldr r3, [pc, #60] @ (800487c ) 800483e: 681b ldr r3, [r3, #0] 8004840: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004844: 2b00 cmp r3, #0 8004846: d00c beq.n 8004862 frequency = HSE_VALUE; 8004848: 4b0f ldr r3, [pc, #60] @ (8004888 ) 800484a: 617b str r3, [r7, #20] break; 800484c: e009 b.n 8004862 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_SCLK) != 0U) 800484e: 4b0b ldr r3, [pc, #44] @ (800487c ) 8004850: 6adb ldr r3, [r3, #44] @ 0x2c 8004852: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 8004856: 2b00 cmp r3, #0 8004858: d005 beq.n 8004866 frequency = HAL_RCC_GetPLL3SFreq(); 800485a: f7fe fa41 bl 8002ce0 800485e: 6178 str r0, [r7, #20] break; 8004860: e001 b.n 8004866 break; 8004862: bf00 nop 8004864: e008 b.n 8004878 break; 8004866: bf00 nop break; 8004868: e006 b.n 8004878 break; 800486a: bf00 nop 800486c: f000 bf75 b.w 800575a break; 8004870: bf00 nop 8004872: f000 bf72 b.w 800575a break; 8004876: bf00 nop break; 8004878: f000 bf6f b.w 800575a 800487c: 58024400 .word 0x58024400 8004880: 003d0900 .word 0x003d0900 8004884: 03d09000 .word 0x03d09000 8004888: 016e3600 .word 0x016e3600 clocksource = __HAL_RCC_GET_ETH1PHY_SOURCE(); 800488c: 4b87 ldr r3, [pc, #540] @ (8004aac ) 800488e: 6cdb ldr r3, [r3, #76] @ 0x4c 8004890: f403 2380 and.w r3, r3, #262144 @ 0x40000 8004894: 613b str r3, [r7, #16] switch (clocksource) 8004896: 693b ldr r3, [r7, #16] 8004898: 2b00 cmp r3, #0 800489a: d004 beq.n 80048a6 800489c: 693b ldr r3, [r7, #16] 800489e: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 80048a2: d009 beq.n 80048b8 break; 80048a4: e016 b.n 80048d4 if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 80048a6: 4b81 ldr r3, [pc, #516] @ (8004aac ) 80048a8: 681b ldr r3, [r3, #0] 80048aa: f403 3300 and.w r3, r3, #131072 @ 0x20000 80048ae: 2b00 cmp r3, #0 80048b0: d00c beq.n 80048cc frequency = HSE_VALUE; 80048b2: 4b7f ldr r3, [pc, #508] @ (8004ab0 ) 80048b4: 617b str r3, [r7, #20] break; 80048b6: e009 b.n 80048cc if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_SCLK) != 0U) 80048b8: 4b7c ldr r3, [pc, #496] @ (8004aac ) 80048ba: 6adb ldr r3, [r3, #44] @ 0x2c 80048bc: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 80048c0: 2b00 cmp r3, #0 80048c2: d006 beq.n 80048d2 frequency = HAL_RCC_GetPLL3SFreq(); 80048c4: f7fe fa0c bl 8002ce0 80048c8: 6178 str r0, [r7, #20] break; 80048ca: e002 b.n 80048d2 break; 80048cc: bf00 nop 80048ce: f000 bf44 b.w 800575a break; 80048d2: bf00 nop break; 80048d4: f000 bf41 b.w 800575a clocksource = __HAL_RCC_GET_FDCAN_SOURCE(); 80048d8: 4b74 ldr r3, [pc, #464] @ (8004aac ) 80048da: 6d1b ldr r3, [r3, #80] @ 0x50 80048dc: f403 0340 and.w r3, r3, #12582912 @ 0xc00000 80048e0: 613b str r3, [r7, #16] switch (clocksource) 80048e2: 693b ldr r3, [r7, #16] 80048e4: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 80048e8: d01e beq.n 8004928 80048ea: 693b ldr r3, [r7, #16] 80048ec: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 80048f0: d824 bhi.n 800493c 80048f2: 693b ldr r3, [r7, #16] 80048f4: 2b00 cmp r3, #0 80048f6: d004 beq.n 8004902 80048f8: 693b ldr r3, [r7, #16] 80048fa: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 80048fe: d009 beq.n 8004914 break; 8004900: e01c b.n 800493c if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 8004902: 4b6a ldr r3, [pc, #424] @ (8004aac ) 8004904: 681b ldr r3, [r3, #0] 8004906: f403 3300 and.w r3, r3, #131072 @ 0x20000 800490a: 2b00 cmp r3, #0 800490c: d019 beq.n 8004942 frequency = HSE_VALUE; 800490e: 4b68 ldr r3, [pc, #416] @ (8004ab0 ) 8004910: 617b str r3, [r7, #20] break; 8004912: e016 b.n 8004942 if (__HAL_RCC_GET_PLL1CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) 8004914: 4b65 ldr r3, [pc, #404] @ (8004aac ) 8004916: 6adb ldr r3, [r3, #44] @ 0x2c 8004918: f003 0340 and.w r3, r3, #64 @ 0x40 800491c: 2b00 cmp r3, #0 800491e: d013 beq.n 8004948 frequency = HAL_RCC_GetPLL1QFreq(); 8004920: f7fe f916 bl 8002b50 8004924: 6178 str r0, [r7, #20] break; 8004926: e00f b.n 8004948 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U) 8004928: 4b60 ldr r3, [pc, #384] @ (8004aac ) 800492a: 6adb ldr r3, [r3, #44] @ 0x2c 800492c: f403 3380 and.w r3, r3, #65536 @ 0x10000 8004930: 2b00 cmp r3, #0 8004932: d00c beq.n 800494e frequency = HAL_RCC_GetPLL2PFreq(); 8004934: f7fe f922 bl 8002b7c 8004938: 6178 str r0, [r7, #20] break; 800493a: e008 b.n 800494e break; 800493c: bf00 nop 800493e: f000 bf0c b.w 800575a break; 8004942: bf00 nop 8004944: f000 bf09 b.w 800575a break; 8004948: bf00 nop 800494a: f000 bf06 b.w 800575a break; 800494e: bf00 nop break; 8004950: f000 bf03 b.w 800575a clocksource = __HAL_RCC_GET_I2C23_SOURCE(); 8004954: 4b55 ldr r3, [pc, #340] @ (8004aac ) 8004956: 6d1b ldr r3, [r3, #80] @ 0x50 8004958: f403 7340 and.w r3, r3, #768 @ 0x300 800495c: 613b str r3, [r7, #16] switch (clocksource) 800495e: 693b ldr r3, [r7, #16] 8004960: f5b3 7f40 cmp.w r3, #768 @ 0x300 8004964: d037 beq.n 80049d6 8004966: 693b ldr r3, [r7, #16] 8004968: f5b3 7f40 cmp.w r3, #768 @ 0x300 800496c: d83c bhi.n 80049e8 800496e: 693b ldr r3, [r7, #16] 8004970: f5b3 7f00 cmp.w r3, #512 @ 0x200 8004974: d019 beq.n 80049aa 8004976: 693b ldr r3, [r7, #16] 8004978: f5b3 7f00 cmp.w r3, #512 @ 0x200 800497c: d834 bhi.n 80049e8 800497e: 693b ldr r3, [r7, #16] 8004980: 2b00 cmp r3, #0 8004982: d004 beq.n 800498e 8004984: 693b ldr r3, [r7, #16] 8004986: f5b3 7f80 cmp.w r3, #256 @ 0x100 800498a: d004 beq.n 8004996 break; 800498c: e02c b.n 80049e8 frequency = HAL_RCC_GetPCLK1Freq(); 800498e: f7fe f88b bl 8002aa8 8004992: 6178 str r0, [r7, #20] break; 8004994: e032 b.n 80049fc if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U) 8004996: 4b45 ldr r3, [pc, #276] @ (8004aac ) 8004998: 6adb ldr r3, [r3, #44] @ 0x2c 800499a: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800499e: 2b00 cmp r3, #0 80049a0: d025 beq.n 80049ee frequency = HAL_RCC_GetPLL3RFreq(); 80049a2: f7fe f987 bl 8002cb4 80049a6: 6178 str r0, [r7, #20] break; 80049a8: e021 b.n 80049ee if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 80049aa: 4b40 ldr r3, [pc, #256] @ (8004aac ) 80049ac: 681b ldr r3, [r3, #0] 80049ae: f003 0304 and.w r3, r3, #4 80049b2: 2b00 cmp r3, #0 80049b4: d01e beq.n 80049f4 if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) 80049b6: 4b3d ldr r3, [pc, #244] @ (8004aac ) 80049b8: 681b ldr r3, [r3, #0] 80049ba: f003 0320 and.w r3, r3, #32 80049be: 2b00 cmp r3, #0 80049c0: d018 beq.n 80049f4 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); 80049c2: 4b3a ldr r3, [pc, #232] @ (8004aac ) 80049c4: 681b ldr r3, [r3, #0] 80049c6: 08db lsrs r3, r3, #3 80049c8: f003 0303 and.w r3, r3, #3 80049cc: 4a39 ldr r2, [pc, #228] @ (8004ab4 ) 80049ce: fa22 f303 lsr.w r3, r2, r3 80049d2: 617b str r3, [r7, #20] break; 80049d4: e00e b.n 80049f4 if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U) 80049d6: 4b35 ldr r3, [pc, #212] @ (8004aac ) 80049d8: 681b ldr r3, [r3, #0] 80049da: f403 7380 and.w r3, r3, #256 @ 0x100 80049de: 2b00 cmp r3, #0 80049e0: d00b beq.n 80049fa frequency = CSI_VALUE; 80049e2: 4b35 ldr r3, [pc, #212] @ (8004ab8 ) 80049e4: 617b str r3, [r7, #20] break; 80049e6: e008 b.n 80049fa break; 80049e8: bf00 nop 80049ea: f000 beb6 b.w 800575a break; 80049ee: bf00 nop 80049f0: f000 beb3 b.w 800575a break; 80049f4: bf00 nop 80049f6: f000 beb0 b.w 800575a break; 80049fa: bf00 nop break; 80049fc: f000 bead b.w 800575a clocksource = __HAL_RCC_GET_I2C1_I3C1_SOURCE(); 8004a00: 4b2a ldr r3, [pc, #168] @ (8004aac ) 8004a02: 6d1b ldr r3, [r3, #80] @ 0x50 8004a04: f403 5340 and.w r3, r3, #12288 @ 0x3000 8004a08: 613b str r3, [r7, #16] switch (clocksource) 8004a0a: 693b ldr r3, [r7, #16] 8004a0c: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 8004a10: d037 beq.n 8004a82 8004a12: 693b ldr r3, [r7, #16] 8004a14: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 8004a18: d83c bhi.n 8004a94 8004a1a: 693b ldr r3, [r7, #16] 8004a1c: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8004a20: d019 beq.n 8004a56 8004a22: 693b ldr r3, [r7, #16] 8004a24: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8004a28: d834 bhi.n 8004a94 8004a2a: 693b ldr r3, [r7, #16] 8004a2c: 2b00 cmp r3, #0 8004a2e: d004 beq.n 8004a3a 8004a30: 693b ldr r3, [r7, #16] 8004a32: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8004a36: d004 beq.n 8004a42 break; 8004a38: e02c b.n 8004a94 frequency = HAL_RCC_GetPCLK1Freq(); 8004a3a: f7fe f835 bl 8002aa8 8004a3e: 6178 str r0, [r7, #20] break; 8004a40: e032 b.n 8004aa8 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U) 8004a42: 4b1a ldr r3, [pc, #104] @ (8004aac ) 8004a44: 6adb ldr r3, [r3, #44] @ 0x2c 8004a46: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8004a4a: 2b00 cmp r3, #0 8004a4c: d025 beq.n 8004a9a frequency = HAL_RCC_GetPLL3RFreq(); 8004a4e: f7fe f931 bl 8002cb4 8004a52: 6178 str r0, [r7, #20] break; 8004a54: e021 b.n 8004a9a if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 8004a56: 4b15 ldr r3, [pc, #84] @ (8004aac ) 8004a58: 681b ldr r3, [r3, #0] 8004a5a: f003 0304 and.w r3, r3, #4 8004a5e: 2b00 cmp r3, #0 8004a60: d01e beq.n 8004aa0 if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) 8004a62: 4b12 ldr r3, [pc, #72] @ (8004aac ) 8004a64: 681b ldr r3, [r3, #0] 8004a66: f003 0320 and.w r3, r3, #32 8004a6a: 2b00 cmp r3, #0 8004a6c: d018 beq.n 8004aa0 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); 8004a6e: 4b0f ldr r3, [pc, #60] @ (8004aac ) 8004a70: 681b ldr r3, [r3, #0] 8004a72: 08db lsrs r3, r3, #3 8004a74: f003 0303 and.w r3, r3, #3 8004a78: 4a0e ldr r2, [pc, #56] @ (8004ab4 ) 8004a7a: fa22 f303 lsr.w r3, r2, r3 8004a7e: 617b str r3, [r7, #20] break; 8004a80: e00e b.n 8004aa0 if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U) 8004a82: 4b0a ldr r3, [pc, #40] @ (8004aac ) 8004a84: 681b ldr r3, [r3, #0] 8004a86: f403 7380 and.w r3, r3, #256 @ 0x100 8004a8a: 2b00 cmp r3, #0 8004a8c: d00b beq.n 8004aa6 frequency = CSI_VALUE; 8004a8e: 4b0a ldr r3, [pc, #40] @ (8004ab8 ) 8004a90: 617b str r3, [r7, #20] break; 8004a92: e008 b.n 8004aa6 break; 8004a94: bf00 nop 8004a96: f000 be60 b.w 800575a break; 8004a9a: bf00 nop 8004a9c: f000 be5d b.w 800575a break; 8004aa0: bf00 nop 8004aa2: f000 be5a b.w 800575a break; 8004aa6: bf00 nop break; 8004aa8: f000 be57 b.w 800575a 8004aac: 58024400 .word 0x58024400 8004ab0: 016e3600 .word 0x016e3600 8004ab4: 03d09000 .word 0x03d09000 8004ab8: 003d0900 .word 0x003d0900 clocksource = __HAL_RCC_GET_LPTIM1_SOURCE(); 8004abc: 4ba0 ldr r3, [pc, #640] @ (8004d40 ) 8004abe: 6d1b ldr r3, [r3, #80] @ 0x50 8004ac0: f403 23e0 and.w r3, r3, #458752 @ 0x70000 8004ac4: 613b str r3, [r7, #16] switch (clocksource) 8004ac6: 693b ldr r3, [r7, #16] 8004ac8: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8004acc: d04f beq.n 8004b6e 8004ace: 693b ldr r3, [r7, #16] 8004ad0: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8004ad4: d84f bhi.n 8004b76 8004ad6: 693b ldr r3, [r7, #16] 8004ad8: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8004adc: d03d beq.n 8004b5a 8004ade: 693b ldr r3, [r7, #16] 8004ae0: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8004ae4: d847 bhi.n 8004b76 8004ae6: 693b ldr r3, [r7, #16] 8004ae8: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 8004aec: d02b beq.n 8004b46 8004aee: 693b ldr r3, [r7, #16] 8004af0: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 8004af4: d83f bhi.n 8004b76 8004af6: 693b ldr r3, [r7, #16] 8004af8: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8004afc: d019 beq.n 8004b32 8004afe: 693b ldr r3, [r7, #16] 8004b00: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8004b04: d837 bhi.n 8004b76 8004b06: 693b ldr r3, [r7, #16] 8004b08: 2b00 cmp r3, #0 8004b0a: d004 beq.n 8004b16 8004b0c: 693b ldr r3, [r7, #16] 8004b0e: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8004b12: d004 beq.n 8004b1e break; 8004b14: e02f b.n 8004b76 frequency = HAL_RCC_GetPCLK1Freq(); 8004b16: f7fd ffc7 bl 8002aa8 8004b1a: 6178 str r0, [r7, #20] break; 8004b1c: e038 b.n 8004b90 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U) 8004b1e: 4b88 ldr r3, [pc, #544] @ (8004d40 ) 8004b20: 6adb ldr r3, [r3, #44] @ 0x2c 8004b22: f403 3380 and.w r3, r3, #65536 @ 0x10000 8004b26: 2b00 cmp r3, #0 8004b28: d028 beq.n 8004b7c frequency = HAL_RCC_GetPLL2PFreq(); 8004b2a: f7fe f827 bl 8002b7c 8004b2e: 6178 str r0, [r7, #20] break; 8004b30: e024 b.n 8004b7c if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U) 8004b32: 4b83 ldr r3, [pc, #524] @ (8004d40 ) 8004b34: 6adb ldr r3, [r3, #44] @ 0x2c 8004b36: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8004b3a: 2b00 cmp r3, #0 8004b3c: d021 beq.n 8004b82 frequency = HAL_RCC_GetPLL3RFreq(); 8004b3e: f7fe f8b9 bl 8002cb4 8004b42: 6178 str r0, [r7, #20] break; 8004b44: e01d b.n 8004b82 if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) 8004b46: 4b7e ldr r3, [pc, #504] @ (8004d40 ) 8004b48: 6f1b ldr r3, [r3, #112] @ 0x70 8004b4a: f003 0302 and.w r3, r3, #2 8004b4e: 2b00 cmp r3, #0 8004b50: d01a beq.n 8004b88 frequency = LSE_VALUE; 8004b52: f44f 4300 mov.w r3, #32768 @ 0x8000 8004b56: 617b str r3, [r7, #20] break; 8004b58: e016 b.n 8004b88 if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) 8004b5a: 4b79 ldr r3, [pc, #484] @ (8004d40 ) 8004b5c: 6f5b ldr r3, [r3, #116] @ 0x74 8004b5e: f003 0302 and.w r3, r3, #2 8004b62: 2b00 cmp r3, #0 8004b64: d013 beq.n 8004b8e frequency = LSI_VALUE; 8004b66: f44f 43fa mov.w r3, #32000 @ 0x7d00 8004b6a: 617b str r3, [r7, #20] break; 8004b6c: e00f b.n 8004b8e frequency = RCC_GetCLKPFreq(); 8004b6e: f000 fe0d bl 800578c 8004b72: 6178 str r0, [r7, #20] break; 8004b74: e00c b.n 8004b90 break; 8004b76: bf00 nop 8004b78: f000 bdef b.w 800575a break; 8004b7c: bf00 nop 8004b7e: f000 bdec b.w 800575a break; 8004b82: bf00 nop 8004b84: f000 bde9 b.w 800575a break; 8004b88: bf00 nop 8004b8a: f000 bde6 b.w 800575a break; 8004b8e: bf00 nop break; 8004b90: f000 bde3 b.w 800575a clocksource = __HAL_RCC_GET_LPTIM23_SOURCE(); 8004b94: 4b6a ldr r3, [pc, #424] @ (8004d40 ) 8004b96: 6d9b ldr r3, [r3, #88] @ 0x58 8004b98: f403 63e0 and.w r3, r3, #1792 @ 0x700 8004b9c: 613b str r3, [r7, #16] switch (clocksource) 8004b9e: 693b ldr r3, [r7, #16] 8004ba0: f5b3 6fa0 cmp.w r3, #1280 @ 0x500 8004ba4: d04f beq.n 8004c46 8004ba6: 693b ldr r3, [r7, #16] 8004ba8: f5b3 6fa0 cmp.w r3, #1280 @ 0x500 8004bac: d84f bhi.n 8004c4e 8004bae: 693b ldr r3, [r7, #16] 8004bb0: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8004bb4: d03d beq.n 8004c32 8004bb6: 693b ldr r3, [r7, #16] 8004bb8: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8004bbc: d847 bhi.n 8004c4e 8004bbe: 693b ldr r3, [r7, #16] 8004bc0: f5b3 7f40 cmp.w r3, #768 @ 0x300 8004bc4: d02b beq.n 8004c1e 8004bc6: 693b ldr r3, [r7, #16] 8004bc8: f5b3 7f40 cmp.w r3, #768 @ 0x300 8004bcc: d83f bhi.n 8004c4e 8004bce: 693b ldr r3, [r7, #16] 8004bd0: f5b3 7f00 cmp.w r3, #512 @ 0x200 8004bd4: d019 beq.n 8004c0a 8004bd6: 693b ldr r3, [r7, #16] 8004bd8: f5b3 7f00 cmp.w r3, #512 @ 0x200 8004bdc: d837 bhi.n 8004c4e 8004bde: 693b ldr r3, [r7, #16] 8004be0: 2b00 cmp r3, #0 8004be2: d004 beq.n 8004bee 8004be4: 693b ldr r3, [r7, #16] 8004be6: f5b3 7f80 cmp.w r3, #256 @ 0x100 8004bea: d004 beq.n 8004bf6 break; 8004bec: e02f b.n 8004c4e frequency = HAL_RCC_GetPCLK4Freq(); 8004bee: f7fd ff93 bl 8002b18 8004bf2: 6178 str r0, [r7, #20] break; 8004bf4: e038 b.n 8004c68 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U) 8004bf6: 4b52 ldr r3, [pc, #328] @ (8004d40 ) 8004bf8: 6adb ldr r3, [r3, #44] @ 0x2c 8004bfa: f403 3380 and.w r3, r3, #65536 @ 0x10000 8004bfe: 2b00 cmp r3, #0 8004c00: d028 beq.n 8004c54 frequency = HAL_RCC_GetPLL2PFreq(); 8004c02: f7fd ffbb bl 8002b7c 8004c06: 6178 str r0, [r7, #20] break; 8004c08: e024 b.n 8004c54 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U) 8004c0a: 4b4d ldr r3, [pc, #308] @ (8004d40 ) 8004c0c: 6adb ldr r3, [r3, #44] @ 0x2c 8004c0e: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8004c12: 2b00 cmp r3, #0 8004c14: d021 beq.n 8004c5a frequency = HAL_RCC_GetPLL3RFreq(); 8004c16: f7fe f84d bl 8002cb4 8004c1a: 6178 str r0, [r7, #20] break; 8004c1c: e01d b.n 8004c5a if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) 8004c1e: 4b48 ldr r3, [pc, #288] @ (8004d40 ) 8004c20: 6f1b ldr r3, [r3, #112] @ 0x70 8004c22: f003 0302 and.w r3, r3, #2 8004c26: 2b00 cmp r3, #0 8004c28: d01a beq.n 8004c60 frequency = LSE_VALUE; 8004c2a: f44f 4300 mov.w r3, #32768 @ 0x8000 8004c2e: 617b str r3, [r7, #20] break; 8004c30: e016 b.n 8004c60 if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) 8004c32: 4b43 ldr r3, [pc, #268] @ (8004d40 ) 8004c34: 6f5b ldr r3, [r3, #116] @ 0x74 8004c36: f003 0302 and.w r3, r3, #2 8004c3a: 2b00 cmp r3, #0 8004c3c: d013 beq.n 8004c66 frequency = LSI_VALUE; 8004c3e: f44f 43fa mov.w r3, #32000 @ 0x7d00 8004c42: 617b str r3, [r7, #20] break; 8004c44: e00f b.n 8004c66 frequency = RCC_GetCLKPFreq(); 8004c46: f000 fda1 bl 800578c 8004c4a: 6178 str r0, [r7, #20] break; 8004c4c: e00c b.n 8004c68 break; 8004c4e: bf00 nop 8004c50: f000 bd83 b.w 800575a break; 8004c54: bf00 nop 8004c56: f000 bd80 b.w 800575a break; 8004c5a: bf00 nop 8004c5c: f000 bd7d b.w 800575a break; 8004c60: bf00 nop 8004c62: f000 bd7a b.w 800575a break; 8004c66: bf00 nop break; 8004c68: f000 bd77 b.w 800575a clocksource = __HAL_RCC_GET_LPTIM45_SOURCE(); 8004c6c: 4b34 ldr r3, [pc, #208] @ (8004d40 ) 8004c6e: 6d9b ldr r3, [r3, #88] @ 0x58 8004c70: f403 43e0 and.w r3, r3, #28672 @ 0x7000 8004c74: 613b str r3, [r7, #16] switch (clocksource) 8004c76: 693b ldr r3, [r7, #16] 8004c78: f5b3 4fa0 cmp.w r3, #20480 @ 0x5000 8004c7c: d04f beq.n 8004d1e 8004c7e: 693b ldr r3, [r7, #16] 8004c80: f5b3 4fa0 cmp.w r3, #20480 @ 0x5000 8004c84: d84f bhi.n 8004d26 8004c86: 693b ldr r3, [r7, #16] 8004c88: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 8004c8c: d03d beq.n 8004d0a 8004c8e: 693b ldr r3, [r7, #16] 8004c90: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 8004c94: d847 bhi.n 8004d26 8004c96: 693b ldr r3, [r7, #16] 8004c98: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 8004c9c: d02b beq.n 8004cf6 8004c9e: 693b ldr r3, [r7, #16] 8004ca0: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 8004ca4: d83f bhi.n 8004d26 8004ca6: 693b ldr r3, [r7, #16] 8004ca8: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8004cac: d019 beq.n 8004ce2 8004cae: 693b ldr r3, [r7, #16] 8004cb0: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8004cb4: d837 bhi.n 8004d26 8004cb6: 693b ldr r3, [r7, #16] 8004cb8: 2b00 cmp r3, #0 8004cba: d004 beq.n 8004cc6 8004cbc: 693b ldr r3, [r7, #16] 8004cbe: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8004cc2: d004 beq.n 8004cce break; 8004cc4: e02f b.n 8004d26 frequency = HAL_RCC_GetPCLK4Freq(); 8004cc6: f7fd ff27 bl 8002b18 8004cca: 6178 str r0, [r7, #20] break; 8004ccc: e03b b.n 8004d46 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U) 8004cce: 4b1c ldr r3, [pc, #112] @ (8004d40 ) 8004cd0: 6adb ldr r3, [r3, #44] @ 0x2c 8004cd2: f403 3380 and.w r3, r3, #65536 @ 0x10000 8004cd6: 2b00 cmp r3, #0 8004cd8: d028 beq.n 8004d2c frequency = HAL_RCC_GetPLL2PFreq(); 8004cda: f7fd ff4f bl 8002b7c 8004cde: 6178 str r0, [r7, #20] break; 8004ce0: e024 b.n 8004d2c if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U) 8004ce2: 4b17 ldr r3, [pc, #92] @ (8004d40 ) 8004ce4: 6adb ldr r3, [r3, #44] @ 0x2c 8004ce6: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8004cea: 2b00 cmp r3, #0 8004cec: d021 beq.n 8004d32 frequency = HAL_RCC_GetPLL3RFreq(); 8004cee: f7fd ffe1 bl 8002cb4 8004cf2: 6178 str r0, [r7, #20] break; 8004cf4: e01d b.n 8004d32 if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) 8004cf6: 4b12 ldr r3, [pc, #72] @ (8004d40 ) 8004cf8: 6f1b ldr r3, [r3, #112] @ 0x70 8004cfa: f003 0302 and.w r3, r3, #2 8004cfe: 2b00 cmp r3, #0 8004d00: d01a beq.n 8004d38 frequency = LSE_VALUE; 8004d02: f44f 4300 mov.w r3, #32768 @ 0x8000 8004d06: 617b str r3, [r7, #20] break; 8004d08: e016 b.n 8004d38 if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) 8004d0a: 4b0d ldr r3, [pc, #52] @ (8004d40 ) 8004d0c: 6f5b ldr r3, [r3, #116] @ 0x74 8004d0e: f003 0302 and.w r3, r3, #2 8004d12: 2b00 cmp r3, #0 8004d14: d016 beq.n 8004d44 frequency = LSI_VALUE; 8004d16: f44f 43fa mov.w r3, #32000 @ 0x7d00 8004d1a: 617b str r3, [r7, #20] break; 8004d1c: e012 b.n 8004d44 frequency = RCC_GetCLKPFreq(); 8004d1e: f000 fd35 bl 800578c 8004d22: 6178 str r0, [r7, #20] break; 8004d24: e00f b.n 8004d46 break; 8004d26: bf00 nop 8004d28: f000 bd17 b.w 800575a break; 8004d2c: bf00 nop 8004d2e: f000 bd14 b.w 800575a break; 8004d32: bf00 nop 8004d34: f000 bd11 b.w 800575a break; 8004d38: bf00 nop 8004d3a: f000 bd0e b.w 800575a 8004d3e: bf00 nop 8004d40: 58024400 .word 0x58024400 break; 8004d44: bf00 nop break; 8004d46: f000 bd08 b.w 800575a clocksource = __HAL_RCC_GET_LPUART1_SOURCE(); 8004d4a: 4ba3 ldr r3, [pc, #652] @ (8004fd8 ) 8004d4c: 6d9b ldr r3, [r3, #88] @ 0x58 8004d4e: f003 0307 and.w r3, r3, #7 8004d52: 613b str r3, [r7, #16] switch (clocksource) 8004d54: 693b ldr r3, [r7, #16] 8004d56: 2b05 cmp r3, #5 8004d58: d84f bhi.n 8004dfa 8004d5a: a201 add r2, pc, #4 @ (adr r2, 8004d60 ) 8004d5c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004d60: 08004d79 .word 0x08004d79 8004d64: 08004d81 .word 0x08004d81 8004d68: 08004d95 .word 0x08004d95 8004d6c: 08004da9 .word 0x08004da9 8004d70: 08004dd5 .word 0x08004dd5 8004d74: 08004de7 .word 0x08004de7 frequency = HAL_RCC_GetPCLK4Freq(); 8004d78: f7fd fece bl 8002b18 8004d7c: 6178 str r0, [r7, #20] break; 8004d7e: e04c b.n 8004e1a if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) 8004d80: 4b95 ldr r3, [pc, #596] @ (8004fd8 ) 8004d82: 6adb ldr r3, [r3, #44] @ 0x2c 8004d84: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004d88: 2b00 cmp r3, #0 8004d8a: d039 beq.n 8004e00 frequency = HAL_RCC_GetPLL2QFreq(); 8004d8c: f7fd ff0c bl 8002ba8 8004d90: 6178 str r0, [r7, #20] break; 8004d92: e035 b.n 8004e00 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) 8004d94: 4b90 ldr r3, [pc, #576] @ (8004fd8 ) 8004d96: 6adb ldr r3, [r3, #44] @ 0x2c 8004d98: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8004d9c: 2b00 cmp r3, #0 8004d9e: d032 beq.n 8004e06 frequency = HAL_RCC_GetPLL3QFreq(); 8004da0: f7fd ff72 bl 8002c88 8004da4: 6178 str r0, [r7, #20] break; 8004da6: e02e b.n 8004e06 if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 8004da8: 4b8b ldr r3, [pc, #556] @ (8004fd8 ) 8004daa: 681b ldr r3, [r3, #0] 8004dac: f003 0304 and.w r3, r3, #4 8004db0: 2b00 cmp r3, #0 8004db2: d02b beq.n 8004e0c if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) 8004db4: 4b88 ldr r3, [pc, #544] @ (8004fd8 ) 8004db6: 681b ldr r3, [r3, #0] 8004db8: f003 0320 and.w r3, r3, #32 8004dbc: 2b00 cmp r3, #0 8004dbe: d025 beq.n 8004e0c frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); 8004dc0: 4b85 ldr r3, [pc, #532] @ (8004fd8 ) 8004dc2: 681b ldr r3, [r3, #0] 8004dc4: 08db lsrs r3, r3, #3 8004dc6: f003 0303 and.w r3, r3, #3 8004dca: 4a84 ldr r2, [pc, #528] @ (8004fdc ) 8004dcc: fa22 f303 lsr.w r3, r2, r3 8004dd0: 617b str r3, [r7, #20] break; 8004dd2: e01b b.n 8004e0c if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U) 8004dd4: 4b80 ldr r3, [pc, #512] @ (8004fd8 ) 8004dd6: 681b ldr r3, [r3, #0] 8004dd8: f403 7380 and.w r3, r3, #256 @ 0x100 8004ddc: 2b00 cmp r3, #0 8004dde: d018 beq.n 8004e12 frequency = CSI_VALUE; 8004de0: 4b7f ldr r3, [pc, #508] @ (8004fe0 ) 8004de2: 617b str r3, [r7, #20] break; 8004de4: e015 b.n 8004e12 if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) 8004de6: 4b7c ldr r3, [pc, #496] @ (8004fd8 ) 8004de8: 6f1b ldr r3, [r3, #112] @ 0x70 8004dea: f003 0302 and.w r3, r3, #2 8004dee: 2b00 cmp r3, #0 8004df0: d012 beq.n 8004e18 frequency = LSE_VALUE; 8004df2: f44f 4300 mov.w r3, #32768 @ 0x8000 8004df6: 617b str r3, [r7, #20] break; 8004df8: e00e b.n 8004e18 break; 8004dfa: bf00 nop 8004dfc: f000 bcad b.w 800575a break; 8004e00: bf00 nop 8004e02: f000 bcaa b.w 800575a break; 8004e06: bf00 nop 8004e08: f000 bca7 b.w 800575a break; 8004e0c: bf00 nop 8004e0e: f000 bca4 b.w 800575a break; 8004e12: bf00 nop 8004e14: f000 bca1 b.w 800575a break; 8004e18: bf00 nop break; 8004e1a: f000 bc9e b.w 800575a if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U) 8004e1e: 4b6e ldr r3, [pc, #440] @ (8004fd8 ) 8004e20: 6adb ldr r3, [r3, #44] @ 0x2c 8004e22: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8004e26: 2b00 cmp r3, #0 8004e28: f000 8494 beq.w 8005754 frequency = HAL_RCC_GetPLL3RFreq(); 8004e2c: f7fd ff42 bl 8002cb4 8004e30: 6178 str r0, [r7, #20] break; 8004e32: f000 bc8f b.w 8005754 clocksource = __HAL_RCC_GET_PSSI_SOURCE(); 8004e36: 4b68 ldr r3, [pc, #416] @ (8004fd8 ) 8004e38: 6cdb ldr r3, [r3, #76] @ 0x4c 8004e3a: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8004e3e: 613b str r3, [r7, #16] switch (clocksource) 8004e40: 693b ldr r3, [r7, #16] 8004e42: 2b00 cmp r3, #0 8004e44: d004 beq.n 8004e50 8004e46: 693b ldr r3, [r7, #16] 8004e48: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 8004e4c: d00a beq.n 8004e64 break; 8004e4e: e00e b.n 8004e6e if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U) 8004e50: 4b61 ldr r3, [pc, #388] @ (8004fd8 ) 8004e52: 6adb ldr r3, [r3, #44] @ 0x2c 8004e54: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8004e58: 2b00 cmp r3, #0 8004e5a: d007 beq.n 8004e6c frequency = HAL_RCC_GetPLL3RFreq(); 8004e5c: f7fd ff2a bl 8002cb4 8004e60: 6178 str r0, [r7, #20] break; 8004e62: e003 b.n 8004e6c frequency = RCC_GetCLKPFreq(); 8004e64: f000 fc92 bl 800578c 8004e68: 6178 str r0, [r7, #20] break; 8004e6a: e000 b.n 8004e6e break; 8004e6c: bf00 nop break; 8004e6e: f000 bc74 b.w 800575a clocksource = __HAL_RCC_GET_RTC_SOURCE(); 8004e72: 4b59 ldr r3, [pc, #356] @ (8004fd8 ) 8004e74: 6f1b ldr r3, [r3, #112] @ 0x70 8004e76: f403 7340 and.w r3, r3, #768 @ 0x300 8004e7a: f5b3 7f40 cmp.w r3, #768 @ 0x300 8004e7e: d107 bne.n 8004e90 8004e80: 4b55 ldr r3, [pc, #340] @ (8004fd8 ) 8004e82: 691b ldr r3, [r3, #16] 8004e84: 011b lsls r3, r3, #4 8004e86: f403 337c and.w r3, r3, #258048 @ 0x3f000 8004e8a: f443 7340 orr.w r3, r3, #768 @ 0x300 8004e8e: e003 b.n 8004e98 8004e90: 4b51 ldr r3, [pc, #324] @ (8004fd8 ) 8004e92: 6f1b ldr r3, [r3, #112] @ 0x70 8004e94: f403 7340 and.w r3, r3, #768 @ 0x300 8004e98: 613b str r3, [r7, #16] switch (clocksource) 8004e9a: 693b ldr r3, [r7, #16] 8004e9c: f5b3 7f00 cmp.w r3, #512 @ 0x200 8004ea0: d014 beq.n 8004ecc 8004ea2: 693b ldr r3, [r7, #16] 8004ea4: f5b3 7f00 cmp.w r3, #512 @ 0x200 8004ea8: d81a bhi.n 8004ee0 8004eaa: 693b ldr r3, [r7, #16] 8004eac: 2b00 cmp r3, #0 8004eae: d033 beq.n 8004f18 8004eb0: 693b ldr r3, [r7, #16] 8004eb2: f5b3 7f80 cmp.w r3, #256 @ 0x100 8004eb6: d113 bne.n 8004ee0 if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) 8004eb8: 4b47 ldr r3, [pc, #284] @ (8004fd8 ) 8004eba: 6f1b ldr r3, [r3, #112] @ 0x70 8004ebc: f003 0302 and.w r3, r3, #2 8004ec0: 2b00 cmp r3, #0 8004ec2: d02c beq.n 8004f1e frequency = LSE_VALUE; 8004ec4: f44f 4300 mov.w r3, #32768 @ 0x8000 8004ec8: 617b str r3, [r7, #20] break; 8004eca: e028 b.n 8004f1e if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) 8004ecc: 4b42 ldr r3, [pc, #264] @ (8004fd8 ) 8004ece: 6f5b ldr r3, [r3, #116] @ 0x74 8004ed0: f003 0302 and.w r3, r3, #2 8004ed4: 2b00 cmp r3, #0 8004ed6: d025 beq.n 8004f24 frequency = LSI_VALUE; 8004ed8: f44f 43fa mov.w r3, #32000 @ 0x7d00 8004edc: 617b str r3, [r7, #20] break; 8004ede: e021 b.n 8004f24 if (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) /*!< HSE is the clock source for RTC */ 8004ee0: 4b3d ldr r3, [pc, #244] @ (8004fd8 ) 8004ee2: 6f1b ldr r3, [r3, #112] @ 0x70 8004ee4: f403 7340 and.w r3, r3, #768 @ 0x300 8004ee8: f5b3 7f40 cmp.w r3, #768 @ 0x300 8004eec: d11d bne.n 8004f2a if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 8004eee: 4b3a ldr r3, [pc, #232] @ (8004fd8 ) 8004ef0: 681b ldr r3, [r3, #0] 8004ef2: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004ef6: 2b00 cmp r3, #0 8004ef8: d017 beq.n 8004f2a prescaler = READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) >> RCC_CFGR_RTCPRE_Pos; 8004efa: 4b37 ldr r3, [pc, #220] @ (8004fd8 ) 8004efc: 691b ldr r3, [r3, #16] 8004efe: 0a1b lsrs r3, r3, #8 8004f00: f003 033f and.w r3, r3, #63 @ 0x3f 8004f04: 60fb str r3, [r7, #12] if (prescaler > 1U) 8004f06: 68fb ldr r3, [r7, #12] 8004f08: 2b01 cmp r3, #1 8004f0a: d90e bls.n 8004f2a frequency = HSE_VALUE / prescaler; 8004f0c: 4a35 ldr r2, [pc, #212] @ (8004fe4 ) 8004f0e: 68fb ldr r3, [r7, #12] 8004f10: fbb2 f3f3 udiv r3, r2, r3 8004f14: 617b str r3, [r7, #20] break; 8004f16: e008 b.n 8004f2a break; 8004f18: bf00 nop 8004f1a: f000 bc1e b.w 800575a break; 8004f1e: bf00 nop 8004f20: f000 bc1b b.w 800575a break; 8004f24: bf00 nop 8004f26: f000 bc18 b.w 800575a break; 8004f2a: bf00 nop break; 8004f2c: f000 bc15 b.w 800575a clocksource = __HAL_RCC_GET_SAI1_SOURCE(); 8004f30: 4b29 ldr r3, [pc, #164] @ (8004fd8 ) 8004f32: 6d5b ldr r3, [r3, #84] @ 0x54 8004f34: f403 23e0 and.w r3, r3, #458752 @ 0x70000 8004f38: 613b str r3, [r7, #16] switch (clocksource) 8004f3a: 693b ldr r3, [r7, #16] 8004f3c: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8004f40: d039 beq.n 8004fb6 8004f42: 693b ldr r3, [r7, #16] 8004f44: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8004f48: d83d bhi.n 8004fc6 8004f4a: 693b ldr r3, [r7, #16] 8004f4c: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 8004f50: d035 beq.n 8004fbe 8004f52: 693b ldr r3, [r7, #16] 8004f54: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 8004f58: d835 bhi.n 8004fc6 8004f5a: 693b ldr r3, [r7, #16] 8004f5c: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8004f60: d01f beq.n 8004fa2 8004f62: 693b ldr r3, [r7, #16] 8004f64: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8004f68: d82d bhi.n 8004fc6 8004f6a: 693b ldr r3, [r7, #16] 8004f6c: 2b00 cmp r3, #0 8004f6e: d004 beq.n 8004f7a 8004f70: 693b ldr r3, [r7, #16] 8004f72: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8004f76: d00a beq.n 8004f8e break; 8004f78: e025 b.n 8004fc6 if (__HAL_RCC_GET_PLL1CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) 8004f7a: 4b17 ldr r3, [pc, #92] @ (8004fd8 ) 8004f7c: 6adb ldr r3, [r3, #44] @ 0x2c 8004f7e: f003 0340 and.w r3, r3, #64 @ 0x40 8004f82: 2b00 cmp r3, #0 8004f84: d021 beq.n 8004fca frequency = HAL_RCC_GetPLL1QFreq(); 8004f86: f7fd fde3 bl 8002b50 8004f8a: 6178 str r0, [r7, #20] break; 8004f8c: e01d b.n 8004fca if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U) 8004f8e: 4b12 ldr r3, [pc, #72] @ (8004fd8 ) 8004f90: 6adb ldr r3, [r3, #44] @ 0x2c 8004f92: f403 3380 and.w r3, r3, #65536 @ 0x10000 8004f96: 2b00 cmp r3, #0 8004f98: d019 beq.n 8004fce frequency = HAL_RCC_GetPLL2PFreq(); 8004f9a: f7fd fdef bl 8002b7c 8004f9e: 6178 str r0, [r7, #20] break; 8004fa0: e015 b.n 8004fce if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U) 8004fa2: 4b0d ldr r3, [pc, #52] @ (8004fd8 ) 8004fa4: 6adb ldr r3, [r3, #44] @ 0x2c 8004fa6: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8004faa: 2b00 cmp r3, #0 8004fac: d011 beq.n 8004fd2 frequency = HAL_RCC_GetPLL3PFreq(); 8004fae: f7fd fe55 bl 8002c5c 8004fb2: 6178 str r0, [r7, #20] break; 8004fb4: e00d b.n 8004fd2 frequency = RCC_GetCLKPFreq(); 8004fb6: f000 fbe9 bl 800578c 8004fba: 6178 str r0, [r7, #20] break; 8004fbc: e00a b.n 8004fd4 frequency = EXTERNAL_CLOCK_VALUE; 8004fbe: f64b 3380 movw r3, #48000 @ 0xbb80 8004fc2: 617b str r3, [r7, #20] break; 8004fc4: e006 b.n 8004fd4 break; 8004fc6: bf00 nop 8004fc8: e3c7 b.n 800575a break; 8004fca: bf00 nop 8004fcc: e3c5 b.n 800575a break; 8004fce: bf00 nop 8004fd0: e3c3 b.n 800575a break; 8004fd2: bf00 nop break; 8004fd4: e3c1 b.n 800575a 8004fd6: bf00 nop 8004fd8: 58024400 .word 0x58024400 8004fdc: 03d09000 .word 0x03d09000 8004fe0: 003d0900 .word 0x003d0900 8004fe4: 016e3600 .word 0x016e3600 clocksource = __HAL_RCC_GET_SAI2_SOURCE(); 8004fe8: 4b94 ldr r3, [pc, #592] @ (800523c ) 8004fea: 6d5b ldr r3, [r3, #84] @ 0x54 8004fec: f403 03e0 and.w r3, r3, #7340032 @ 0x700000 8004ff0: 613b str r3, [r7, #16] switch (clocksource) 8004ff2: 693b ldr r3, [r7, #16] 8004ff4: f5b3 0fa0 cmp.w r3, #5242880 @ 0x500000 8004ff8: d049 beq.n 800508e 8004ffa: 693b ldr r3, [r7, #16] 8004ffc: f5b3 0fa0 cmp.w r3, #5242880 @ 0x500000 8005000: d847 bhi.n 8005092 8005002: 693b ldr r3, [r7, #16] 8005004: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8005008: d039 beq.n 800507e 800500a: 693b ldr r3, [r7, #16] 800500c: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8005010: d83f bhi.n 8005092 8005012: 693b ldr r3, [r7, #16] 8005014: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 8005018: d035 beq.n 8005086 800501a: 693b ldr r3, [r7, #16] 800501c: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 8005020: d837 bhi.n 8005092 8005022: 693b ldr r3, [r7, #16] 8005024: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 8005028: d01f beq.n 800506a 800502a: 693b ldr r3, [r7, #16] 800502c: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 8005030: d82f bhi.n 8005092 8005032: 693b ldr r3, [r7, #16] 8005034: 2b00 cmp r3, #0 8005036: d004 beq.n 8005042 8005038: 693b ldr r3, [r7, #16] 800503a: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800503e: d00a beq.n 8005056 break; 8005040: e027 b.n 8005092 if (__HAL_RCC_GET_PLL1CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) 8005042: 4b7e ldr r3, [pc, #504] @ (800523c ) 8005044: 6adb ldr r3, [r3, #44] @ 0x2c 8005046: f003 0340 and.w r3, r3, #64 @ 0x40 800504a: 2b00 cmp r3, #0 800504c: d023 beq.n 8005096 frequency = HAL_RCC_GetPLL1QFreq(); 800504e: f7fd fd7f bl 8002b50 8005052: 6178 str r0, [r7, #20] break; 8005054: e01f b.n 8005096 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U) 8005056: 4b79 ldr r3, [pc, #484] @ (800523c ) 8005058: 6adb ldr r3, [r3, #44] @ 0x2c 800505a: f403 3380 and.w r3, r3, #65536 @ 0x10000 800505e: 2b00 cmp r3, #0 8005060: d01b beq.n 800509a frequency = HAL_RCC_GetPLL2PFreq(); 8005062: f7fd fd8b bl 8002b7c 8005066: 6178 str r0, [r7, #20] break; 8005068: e017 b.n 800509a if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U) 800506a: 4b74 ldr r3, [pc, #464] @ (800523c ) 800506c: 6adb ldr r3, [r3, #44] @ 0x2c 800506e: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8005072: 2b00 cmp r3, #0 8005074: d013 beq.n 800509e frequency = HAL_RCC_GetPLL3PFreq(); 8005076: f7fd fdf1 bl 8002c5c 800507a: 6178 str r0, [r7, #20] break; 800507c: e00f b.n 800509e frequency = RCC_GetCLKPFreq(); 800507e: f000 fb85 bl 800578c 8005082: 6178 str r0, [r7, #20] break; 8005084: e00c b.n 80050a0 frequency = EXTERNAL_CLOCK_VALUE; 8005086: f64b 3380 movw r3, #48000 @ 0xbb80 800508a: 617b str r3, [r7, #20] break; 800508c: e008 b.n 80050a0 break; 800508e: bf00 nop 8005090: e363 b.n 800575a break; 8005092: bf00 nop 8005094: e361 b.n 800575a break; 8005096: bf00 nop 8005098: e35f b.n 800575a break; 800509a: bf00 nop 800509c: e35d b.n 800575a break; 800509e: bf00 nop break; 80050a0: e35b b.n 800575a clocksource = __HAL_RCC_GET_SDMMC12_SOURCE(); 80050a2: 4b66 ldr r3, [pc, #408] @ (800523c ) 80050a4: 6cdb ldr r3, [r3, #76] @ 0x4c 80050a6: f003 0304 and.w r3, r3, #4 80050aa: 613b str r3, [r7, #16] if (clocksource == 80050ac: 693b ldr r3, [r7, #16] 80050ae: 2b00 cmp r3, #0 80050b0: d10a bne.n 80050c8 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_SCLK) != 0U) 80050b2: 4b62 ldr r3, [pc, #392] @ (800523c ) 80050b4: 6adb ldr r3, [r3, #44] @ 0x2c 80050b6: f403 2300 and.w r3, r3, #524288 @ 0x80000 80050ba: 2b00 cmp r3, #0 80050bc: f000 834c beq.w 8005758 frequency = HAL_RCC_GetPLL2SFreq(); 80050c0: f7fd fd9e bl 8002c00 80050c4: 6178 str r0, [r7, #20] break; 80050c6: e347 b.n 8005758 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_TCLK) != 0U) 80050c8: 4b5c ldr r3, [pc, #368] @ (800523c ) 80050ca: 6adb ldr r3, [r3, #44] @ 0x2c 80050cc: f403 1380 and.w r3, r3, #1048576 @ 0x100000 80050d0: 2b00 cmp r3, #0 80050d2: f000 8341 beq.w 8005758 frequency = HAL_RCC_GetPLL2TFreq(); 80050d6: f7fd fda9 bl 8002c2c 80050da: 6178 str r0, [r7, #20] break; 80050dc: e33c b.n 8005758 clocksource = __HAL_RCC_GET_SPDIFRX_SOURCE(); 80050de: 4b57 ldr r3, [pc, #348] @ (800523c ) 80050e0: 6d1b ldr r3, [r3, #80] @ 0x50 80050e2: f003 7340 and.w r3, r3, #50331648 @ 0x3000000 80050e6: 613b str r3, [r7, #16] switch (clocksource) 80050e8: 693b ldr r3, [r7, #16] 80050ea: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 80050ee: d031 beq.n 8005154 80050f0: 693b ldr r3, [r7, #16] 80050f2: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 80050f6: d843 bhi.n 8005180 80050f8: 693b ldr r3, [r7, #16] 80050fa: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 80050fe: d01f beq.n 8005140 8005100: 693b ldr r3, [r7, #16] 8005102: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 8005106: d83b bhi.n 8005180 8005108: 693b ldr r3, [r7, #16] 800510a: 2b00 cmp r3, #0 800510c: d004 beq.n 8005118 800510e: 693b ldr r3, [r7, #16] 8005110: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8005114: d00a beq.n 800512c break; 8005116: e033 b.n 8005180 if (__HAL_RCC_GET_PLL1CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) 8005118: 4b48 ldr r3, [pc, #288] @ (800523c ) 800511a: 6adb ldr r3, [r3, #44] @ 0x2c 800511c: f003 0340 and.w r3, r3, #64 @ 0x40 8005120: 2b00 cmp r3, #0 8005122: d02f beq.n 8005184 frequency = HAL_RCC_GetPLL1QFreq(); 8005124: f7fd fd14 bl 8002b50 8005128: 6178 str r0, [r7, #20] break; 800512a: e02b b.n 8005184 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U) 800512c: 4b43 ldr r3, [pc, #268] @ (800523c ) 800512e: 6adb ldr r3, [r3, #44] @ 0x2c 8005130: f403 2380 and.w r3, r3, #262144 @ 0x40000 8005134: 2b00 cmp r3, #0 8005136: d027 beq.n 8005188 frequency = HAL_RCC_GetPLL2RFreq(); 8005138: f7fd fd4c bl 8002bd4 800513c: 6178 str r0, [r7, #20] break; 800513e: e023 b.n 8005188 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U) 8005140: 4b3e ldr r3, [pc, #248] @ (800523c ) 8005142: 6adb ldr r3, [r3, #44] @ 0x2c 8005144: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8005148: 2b00 cmp r3, #0 800514a: d01f beq.n 800518c frequency = HAL_RCC_GetPLL3RFreq(); 800514c: f7fd fdb2 bl 8002cb4 8005150: 6178 str r0, [r7, #20] break; 8005152: e01b b.n 800518c if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 8005154: 4b39 ldr r3, [pc, #228] @ (800523c ) 8005156: 681b ldr r3, [r3, #0] 8005158: f003 0304 and.w r3, r3, #4 800515c: 2b00 cmp r3, #0 800515e: d017 beq.n 8005190 if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) 8005160: 4b36 ldr r3, [pc, #216] @ (800523c ) 8005162: 681b ldr r3, [r3, #0] 8005164: f003 0320 and.w r3, r3, #32 8005168: 2b00 cmp r3, #0 800516a: d011 beq.n 8005190 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); 800516c: 4b33 ldr r3, [pc, #204] @ (800523c ) 800516e: 681b ldr r3, [r3, #0] 8005170: 08db lsrs r3, r3, #3 8005172: f003 0303 and.w r3, r3, #3 8005176: 4a32 ldr r2, [pc, #200] @ (8005240 ) 8005178: fa22 f303 lsr.w r3, r2, r3 800517c: 617b str r3, [r7, #20] break; 800517e: e007 b.n 8005190 break; 8005180: bf00 nop 8005182: e2ea b.n 800575a break; 8005184: bf00 nop 8005186: e2e8 b.n 800575a break; 8005188: bf00 nop 800518a: e2e6 b.n 800575a break; 800518c: bf00 nop 800518e: e2e4 b.n 800575a break; 8005190: bf00 nop break; 8005192: e2e2 b.n 800575a clocksource = __HAL_RCC_GET_SPI1_SOURCE(); 8005194: 4b29 ldr r3, [pc, #164] @ (800523c ) 8005196: 6d5b ldr r3, [r3, #84] @ 0x54 8005198: f403 63e0 and.w r3, r3, #1792 @ 0x700 800519c: 613b str r3, [r7, #16] switch (clocksource) 800519e: 693b ldr r3, [r7, #16] 80051a0: f5b3 6f80 cmp.w r3, #1024 @ 0x400 80051a4: d039 beq.n 800521a 80051a6: 693b ldr r3, [r7, #16] 80051a8: f5b3 6f80 cmp.w r3, #1024 @ 0x400 80051ac: d83d bhi.n 800522a 80051ae: 693b ldr r3, [r7, #16] 80051b0: f5b3 7f40 cmp.w r3, #768 @ 0x300 80051b4: d035 beq.n 8005222 80051b6: 693b ldr r3, [r7, #16] 80051b8: f5b3 7f40 cmp.w r3, #768 @ 0x300 80051bc: d835 bhi.n 800522a 80051be: 693b ldr r3, [r7, #16] 80051c0: f5b3 7f00 cmp.w r3, #512 @ 0x200 80051c4: d01f beq.n 8005206 80051c6: 693b ldr r3, [r7, #16] 80051c8: f5b3 7f00 cmp.w r3, #512 @ 0x200 80051cc: d82d bhi.n 800522a 80051ce: 693b ldr r3, [r7, #16] 80051d0: 2b00 cmp r3, #0 80051d2: d004 beq.n 80051de 80051d4: 693b ldr r3, [r7, #16] 80051d6: f5b3 7f80 cmp.w r3, #256 @ 0x100 80051da: d00a beq.n 80051f2 break; 80051dc: e025 b.n 800522a if (__HAL_RCC_GET_PLL1CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) 80051de: 4b17 ldr r3, [pc, #92] @ (800523c ) 80051e0: 6adb ldr r3, [r3, #44] @ 0x2c 80051e2: f003 0340 and.w r3, r3, #64 @ 0x40 80051e6: 2b00 cmp r3, #0 80051e8: d021 beq.n 800522e frequency = HAL_RCC_GetPLL1QFreq(); 80051ea: f7fd fcb1 bl 8002b50 80051ee: 6178 str r0, [r7, #20] break; 80051f0: e01d b.n 800522e if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U) 80051f2: 4b12 ldr r3, [pc, #72] @ (800523c ) 80051f4: 6adb ldr r3, [r3, #44] @ 0x2c 80051f6: f403 3380 and.w r3, r3, #65536 @ 0x10000 80051fa: 2b00 cmp r3, #0 80051fc: d019 beq.n 8005232 frequency = HAL_RCC_GetPLL2PFreq(); 80051fe: f7fd fcbd bl 8002b7c 8005202: 6178 str r0, [r7, #20] break; 8005204: e015 b.n 8005232 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U) 8005206: 4b0d ldr r3, [pc, #52] @ (800523c ) 8005208: 6adb ldr r3, [r3, #44] @ 0x2c 800520a: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800520e: 2b00 cmp r3, #0 8005210: d011 beq.n 8005236 frequency = HAL_RCC_GetPLL3PFreq(); 8005212: f7fd fd23 bl 8002c5c 8005216: 6178 str r0, [r7, #20] break; 8005218: e00d b.n 8005236 frequency = RCC_GetCLKPFreq(); 800521a: f000 fab7 bl 800578c 800521e: 6178 str r0, [r7, #20] break; 8005220: e00a b.n 8005238 frequency = EXTERNAL_CLOCK_VALUE; 8005222: f64b 3380 movw r3, #48000 @ 0xbb80 8005226: 617b str r3, [r7, #20] break; 8005228: e006 b.n 8005238 break; 800522a: bf00 nop 800522c: e295 b.n 800575a break; 800522e: bf00 nop 8005230: e293 b.n 800575a break; 8005232: bf00 nop 8005234: e291 b.n 800575a break; 8005236: bf00 nop break; 8005238: e28f b.n 800575a 800523a: bf00 nop 800523c: 58024400 .word 0x58024400 8005240: 03d09000 .word 0x03d09000 clocksource = __HAL_RCC_GET_SPI23_SOURCE(); 8005244: 4b92 ldr r3, [pc, #584] @ (8005490 ) 8005246: 6d1b ldr r3, [r3, #80] @ 0x50 8005248: f003 0370 and.w r3, r3, #112 @ 0x70 800524c: 613b str r3, [r7, #16] switch (clocksource) 800524e: 693b ldr r3, [r7, #16] 8005250: 2b40 cmp r3, #64 @ 0x40 8005252: d033 beq.n 80052bc 8005254: 693b ldr r3, [r7, #16] 8005256: 2b40 cmp r3, #64 @ 0x40 8005258: d838 bhi.n 80052cc 800525a: 693b ldr r3, [r7, #16] 800525c: 2b30 cmp r3, #48 @ 0x30 800525e: d031 beq.n 80052c4 8005260: 693b ldr r3, [r7, #16] 8005262: 2b30 cmp r3, #48 @ 0x30 8005264: d832 bhi.n 80052cc 8005266: 693b ldr r3, [r7, #16] 8005268: 2b20 cmp r3, #32 800526a: d01d beq.n 80052a8 800526c: 693b ldr r3, [r7, #16] 800526e: 2b20 cmp r3, #32 8005270: d82c bhi.n 80052cc 8005272: 693b ldr r3, [r7, #16] 8005274: 2b00 cmp r3, #0 8005276: d003 beq.n 8005280 8005278: 693b ldr r3, [r7, #16] 800527a: 2b10 cmp r3, #16 800527c: d00a beq.n 8005294 break; 800527e: e025 b.n 80052cc if (__HAL_RCC_GET_PLL1CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) 8005280: 4b83 ldr r3, [pc, #524] @ (8005490 ) 8005282: 6adb ldr r3, [r3, #44] @ 0x2c 8005284: f003 0340 and.w r3, r3, #64 @ 0x40 8005288: 2b00 cmp r3, #0 800528a: d021 beq.n 80052d0 frequency = HAL_RCC_GetPLL1QFreq(); 800528c: f7fd fc60 bl 8002b50 8005290: 6178 str r0, [r7, #20] break; 8005292: e01d b.n 80052d0 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U) 8005294: 4b7e ldr r3, [pc, #504] @ (8005490 ) 8005296: 6adb ldr r3, [r3, #44] @ 0x2c 8005298: f403 3380 and.w r3, r3, #65536 @ 0x10000 800529c: 2b00 cmp r3, #0 800529e: d019 beq.n 80052d4 frequency = HAL_RCC_GetPLL2PFreq(); 80052a0: f7fd fc6c bl 8002b7c 80052a4: 6178 str r0, [r7, #20] break; 80052a6: e015 b.n 80052d4 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U) 80052a8: 4b79 ldr r3, [pc, #484] @ (8005490 ) 80052aa: 6adb ldr r3, [r3, #44] @ 0x2c 80052ac: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 80052b0: 2b00 cmp r3, #0 80052b2: d011 beq.n 80052d8 frequency = HAL_RCC_GetPLL3PFreq(); 80052b4: f7fd fcd2 bl 8002c5c 80052b8: 6178 str r0, [r7, #20] break; 80052ba: e00d b.n 80052d8 frequency = RCC_GetCLKPFreq(); 80052bc: f000 fa66 bl 800578c 80052c0: 6178 str r0, [r7, #20] break; 80052c2: e00a b.n 80052da frequency = EXTERNAL_CLOCK_VALUE; 80052c4: f64b 3380 movw r3, #48000 @ 0xbb80 80052c8: 617b str r3, [r7, #20] break; 80052ca: e006 b.n 80052da break; 80052cc: bf00 nop 80052ce: e244 b.n 800575a break; 80052d0: bf00 nop 80052d2: e242 b.n 800575a break; 80052d4: bf00 nop 80052d6: e240 b.n 800575a break; 80052d8: bf00 nop break; 80052da: e23e b.n 800575a clocksource = __HAL_RCC_GET_SPI45_SOURCE(); 80052dc: 4b6c ldr r3, [pc, #432] @ (8005490 ) 80052de: 6d5b ldr r3, [r3, #84] @ 0x54 80052e0: f003 0370 and.w r3, r3, #112 @ 0x70 80052e4: 613b str r3, [r7, #16] switch (clocksource) 80052e6: 693b ldr r3, [r7, #16] 80052e8: 2b50 cmp r3, #80 @ 0x50 80052ea: d052 beq.n 8005392 80052ec: 693b ldr r3, [r7, #16] 80052ee: 2b50 cmp r3, #80 @ 0x50 80052f0: d858 bhi.n 80053a4 80052f2: 693b ldr r3, [r7, #16] 80052f4: 2b40 cmp r3, #64 @ 0x40 80052f6: d043 beq.n 8005380 80052f8: 693b ldr r3, [r7, #16] 80052fa: 2b40 cmp r3, #64 @ 0x40 80052fc: d852 bhi.n 80053a4 80052fe: 693b ldr r3, [r7, #16] 8005300: 2b30 cmp r3, #48 @ 0x30 8005302: d027 beq.n 8005354 8005304: 693b ldr r3, [r7, #16] 8005306: 2b30 cmp r3, #48 @ 0x30 8005308: d84c bhi.n 80053a4 800530a: 693b ldr r3, [r7, #16] 800530c: 2b20 cmp r3, #32 800530e: d017 beq.n 8005340 8005310: 693b ldr r3, [r7, #16] 8005312: 2b20 cmp r3, #32 8005314: d846 bhi.n 80053a4 8005316: 693b ldr r3, [r7, #16] 8005318: 2b00 cmp r3, #0 800531a: d003 beq.n 8005324 800531c: 693b ldr r3, [r7, #16] 800531e: 2b10 cmp r3, #16 8005320: d004 beq.n 800532c break; 8005322: e03f b.n 80053a4 frequency = HAL_RCC_GetPCLK2Freq(); 8005324: f7fd fbdc bl 8002ae0 8005328: 6178 str r0, [r7, #20] break; 800532a: e046 b.n 80053ba if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) 800532c: 4b58 ldr r3, [pc, #352] @ (8005490 ) 800532e: 6adb ldr r3, [r3, #44] @ 0x2c 8005330: f403 3300 and.w r3, r3, #131072 @ 0x20000 8005334: 2b00 cmp r3, #0 8005336: d037 beq.n 80053a8 frequency = HAL_RCC_GetPLL2QFreq(); 8005338: f7fd fc36 bl 8002ba8 800533c: 6178 str r0, [r7, #20] break; 800533e: e033 b.n 80053a8 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) 8005340: 4b53 ldr r3, [pc, #332] @ (8005490 ) 8005342: 6adb ldr r3, [r3, #44] @ 0x2c 8005344: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8005348: 2b00 cmp r3, #0 800534a: d02f beq.n 80053ac frequency = HAL_RCC_GetPLL3QFreq(); 800534c: f7fd fc9c bl 8002c88 8005350: 6178 str r0, [r7, #20] break; 8005352: e02b b.n 80053ac if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 8005354: 4b4e ldr r3, [pc, #312] @ (8005490 ) 8005356: 681b ldr r3, [r3, #0] 8005358: f003 0304 and.w r3, r3, #4 800535c: 2b00 cmp r3, #0 800535e: d027 beq.n 80053b0 if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) 8005360: 4b4b ldr r3, [pc, #300] @ (8005490 ) 8005362: 681b ldr r3, [r3, #0] 8005364: f003 0320 and.w r3, r3, #32 8005368: 2b00 cmp r3, #0 800536a: d021 beq.n 80053b0 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); 800536c: 4b48 ldr r3, [pc, #288] @ (8005490 ) 800536e: 681b ldr r3, [r3, #0] 8005370: 08db lsrs r3, r3, #3 8005372: f003 0303 and.w r3, r3, #3 8005376: 4a47 ldr r2, [pc, #284] @ (8005494 ) 8005378: fa22 f303 lsr.w r3, r2, r3 800537c: 617b str r3, [r7, #20] break; 800537e: e017 b.n 80053b0 if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U) 8005380: 4b43 ldr r3, [pc, #268] @ (8005490 ) 8005382: 681b ldr r3, [r3, #0] 8005384: f403 7380 and.w r3, r3, #256 @ 0x100 8005388: 2b00 cmp r3, #0 800538a: d013 beq.n 80053b4 frequency = CSI_VALUE; 800538c: 4b42 ldr r3, [pc, #264] @ (8005498 ) 800538e: 617b str r3, [r7, #20] break; 8005390: e010 b.n 80053b4 if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 8005392: 4b3f ldr r3, [pc, #252] @ (8005490 ) 8005394: 681b ldr r3, [r3, #0] 8005396: f403 3300 and.w r3, r3, #131072 @ 0x20000 800539a: 2b00 cmp r3, #0 800539c: d00c beq.n 80053b8 frequency = HSE_VALUE; 800539e: 4b3f ldr r3, [pc, #252] @ (800549c ) 80053a0: 617b str r3, [r7, #20] break; 80053a2: e009 b.n 80053b8 break; 80053a4: bf00 nop 80053a6: e1d8 b.n 800575a break; 80053a8: bf00 nop 80053aa: e1d6 b.n 800575a break; 80053ac: bf00 nop 80053ae: e1d4 b.n 800575a break; 80053b0: bf00 nop 80053b2: e1d2 b.n 800575a break; 80053b4: bf00 nop 80053b6: e1d0 b.n 800575a break; 80053b8: bf00 nop break; 80053ba: e1ce b.n 800575a clocksource = __HAL_RCC_GET_SPI6_SOURCE(); 80053bc: 4b34 ldr r3, [pc, #208] @ (8005490 ) 80053be: 6d9b ldr r3, [r3, #88] @ 0x58 80053c0: f003 0370 and.w r3, r3, #112 @ 0x70 80053c4: 613b str r3, [r7, #16] switch (clocksource) 80053c6: 693b ldr r3, [r7, #16] 80053c8: 2b50 cmp r3, #80 @ 0x50 80053ca: d052 beq.n 8005472 80053cc: 693b ldr r3, [r7, #16] 80053ce: 2b50 cmp r3, #80 @ 0x50 80053d0: d858 bhi.n 8005484 80053d2: 693b ldr r3, [r7, #16] 80053d4: 2b40 cmp r3, #64 @ 0x40 80053d6: d043 beq.n 8005460 80053d8: 693b ldr r3, [r7, #16] 80053da: 2b40 cmp r3, #64 @ 0x40 80053dc: d852 bhi.n 8005484 80053de: 693b ldr r3, [r7, #16] 80053e0: 2b30 cmp r3, #48 @ 0x30 80053e2: d027 beq.n 8005434 80053e4: 693b ldr r3, [r7, #16] 80053e6: 2b30 cmp r3, #48 @ 0x30 80053e8: d84c bhi.n 8005484 80053ea: 693b ldr r3, [r7, #16] 80053ec: 2b20 cmp r3, #32 80053ee: d017 beq.n 8005420 80053f0: 693b ldr r3, [r7, #16] 80053f2: 2b20 cmp r3, #32 80053f4: d846 bhi.n 8005484 80053f6: 693b ldr r3, [r7, #16] 80053f8: 2b00 cmp r3, #0 80053fa: d003 beq.n 8005404 80053fc: 693b ldr r3, [r7, #16] 80053fe: 2b10 cmp r3, #16 8005400: d004 beq.n 800540c break; 8005402: e03f b.n 8005484 frequency = HAL_RCC_GetPCLK4Freq(); 8005404: f7fd fb88 bl 8002b18 8005408: 6178 str r0, [r7, #20] break; 800540a: e04e b.n 80054aa if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) 800540c: 4b20 ldr r3, [pc, #128] @ (8005490 ) 800540e: 6adb ldr r3, [r3, #44] @ 0x2c 8005410: f403 3300 and.w r3, r3, #131072 @ 0x20000 8005414: 2b00 cmp r3, #0 8005416: d037 beq.n 8005488 frequency = HAL_RCC_GetPLL2QFreq(); 8005418: f7fd fbc6 bl 8002ba8 800541c: 6178 str r0, [r7, #20] break; 800541e: e033 b.n 8005488 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) 8005420: 4b1b ldr r3, [pc, #108] @ (8005490 ) 8005422: 6adb ldr r3, [r3, #44] @ 0x2c 8005424: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8005428: 2b00 cmp r3, #0 800542a: d02f beq.n 800548c frequency = HAL_RCC_GetPLL3QFreq(); 800542c: f7fd fc2c bl 8002c88 8005430: 6178 str r0, [r7, #20] break; 8005432: e02b b.n 800548c if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 8005434: 4b16 ldr r3, [pc, #88] @ (8005490 ) 8005436: 681b ldr r3, [r3, #0] 8005438: f003 0304 and.w r3, r3, #4 800543c: 2b00 cmp r3, #0 800543e: d02f beq.n 80054a0 if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) 8005440: 4b13 ldr r3, [pc, #76] @ (8005490 ) 8005442: 681b ldr r3, [r3, #0] 8005444: f003 0320 and.w r3, r3, #32 8005448: 2b00 cmp r3, #0 800544a: d029 beq.n 80054a0 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); 800544c: 4b10 ldr r3, [pc, #64] @ (8005490 ) 800544e: 681b ldr r3, [r3, #0] 8005450: 08db lsrs r3, r3, #3 8005452: f003 0303 and.w r3, r3, #3 8005456: 4a0f ldr r2, [pc, #60] @ (8005494 ) 8005458: fa22 f303 lsr.w r3, r2, r3 800545c: 617b str r3, [r7, #20] break; 800545e: e01f b.n 80054a0 if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U) 8005460: 4b0b ldr r3, [pc, #44] @ (8005490 ) 8005462: 681b ldr r3, [r3, #0] 8005464: f403 7380 and.w r3, r3, #256 @ 0x100 8005468: 2b00 cmp r3, #0 800546a: d01b beq.n 80054a4 frequency = CSI_VALUE; 800546c: 4b0a ldr r3, [pc, #40] @ (8005498 ) 800546e: 617b str r3, [r7, #20] break; 8005470: e018 b.n 80054a4 if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 8005472: 4b07 ldr r3, [pc, #28] @ (8005490 ) 8005474: 681b ldr r3, [r3, #0] 8005476: f403 3300 and.w r3, r3, #131072 @ 0x20000 800547a: 2b00 cmp r3, #0 800547c: d014 beq.n 80054a8 frequency = HSE_VALUE; 800547e: 4b07 ldr r3, [pc, #28] @ (800549c ) 8005480: 617b str r3, [r7, #20] break; 8005482: e011 b.n 80054a8 break; 8005484: bf00 nop 8005486: e168 b.n 800575a break; 8005488: bf00 nop 800548a: e166 b.n 800575a break; 800548c: bf00 nop 800548e: e164 b.n 800575a 8005490: 58024400 .word 0x58024400 8005494: 03d09000 .word 0x03d09000 8005498: 003d0900 .word 0x003d0900 800549c: 016e3600 .word 0x016e3600 break; 80054a0: bf00 nop 80054a2: e15a b.n 800575a break; 80054a4: bf00 nop 80054a6: e158 b.n 800575a break; 80054a8: bf00 nop break; 80054aa: e156 b.n 800575a clocksource = __HAL_RCC_GET_USART1_SOURCE(); 80054ac: 4b9e ldr r3, [pc, #632] @ (8005728 ) 80054ae: 6d5b ldr r3, [r3, #84] @ 0x54 80054b0: f003 0307 and.w r3, r3, #7 80054b4: 613b str r3, [r7, #16] switch (clocksource) 80054b6: 693b ldr r3, [r7, #16] 80054b8: 2b05 cmp r3, #5 80054ba: d850 bhi.n 800555e 80054bc: a201 add r2, pc, #4 @ (adr r2, 80054c4 ) 80054be: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80054c2: bf00 nop 80054c4: 080054dd .word 0x080054dd 80054c8: 080054e5 .word 0x080054e5 80054cc: 080054f9 .word 0x080054f9 80054d0: 0800550d .word 0x0800550d 80054d4: 08005539 .word 0x08005539 80054d8: 0800554b .word 0x0800554b frequency = HAL_RCC_GetPCLK2Freq(); 80054dc: f7fd fb00 bl 8002ae0 80054e0: 6178 str r0, [r7, #20] break; 80054e2: e047 b.n 8005574 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) 80054e4: 4b90 ldr r3, [pc, #576] @ (8005728 ) 80054e6: 6adb ldr r3, [r3, #44] @ 0x2c 80054e8: f403 3300 and.w r3, r3, #131072 @ 0x20000 80054ec: 2b00 cmp r3, #0 80054ee: d038 beq.n 8005562 frequency = HAL_RCC_GetPLL2QFreq(); 80054f0: f7fd fb5a bl 8002ba8 80054f4: 6178 str r0, [r7, #20] break; 80054f6: e034 b.n 8005562 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) 80054f8: 4b8b ldr r3, [pc, #556] @ (8005728 ) 80054fa: 6adb ldr r3, [r3, #44] @ 0x2c 80054fc: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8005500: 2b00 cmp r3, #0 8005502: d030 beq.n 8005566 frequency = HAL_RCC_GetPLL3QFreq(); 8005504: f7fd fbc0 bl 8002c88 8005508: 6178 str r0, [r7, #20] break; 800550a: e02c b.n 8005566 if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 800550c: 4b86 ldr r3, [pc, #536] @ (8005728 ) 800550e: 681b ldr r3, [r3, #0] 8005510: f003 0304 and.w r3, r3, #4 8005514: 2b00 cmp r3, #0 8005516: d028 beq.n 800556a if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) 8005518: 4b83 ldr r3, [pc, #524] @ (8005728 ) 800551a: 681b ldr r3, [r3, #0] 800551c: f003 0320 and.w r3, r3, #32 8005520: 2b00 cmp r3, #0 8005522: d022 beq.n 800556a frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); 8005524: 4b80 ldr r3, [pc, #512] @ (8005728 ) 8005526: 681b ldr r3, [r3, #0] 8005528: 08db lsrs r3, r3, #3 800552a: f003 0303 and.w r3, r3, #3 800552e: 4a7f ldr r2, [pc, #508] @ (800572c ) 8005530: fa22 f303 lsr.w r3, r2, r3 8005534: 617b str r3, [r7, #20] break; 8005536: e018 b.n 800556a if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U) 8005538: 4b7b ldr r3, [pc, #492] @ (8005728 ) 800553a: 681b ldr r3, [r3, #0] 800553c: f403 7380 and.w r3, r3, #256 @ 0x100 8005540: 2b00 cmp r3, #0 8005542: d014 beq.n 800556e frequency = CSI_VALUE; 8005544: 4b7a ldr r3, [pc, #488] @ (8005730 ) 8005546: 617b str r3, [r7, #20] break; 8005548: e011 b.n 800556e if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) 800554a: 4b77 ldr r3, [pc, #476] @ (8005728 ) 800554c: 6f1b ldr r3, [r3, #112] @ 0x70 800554e: f003 0302 and.w r3, r3, #2 8005552: 2b00 cmp r3, #0 8005554: d00d beq.n 8005572 frequency = LSE_VALUE; 8005556: f44f 4300 mov.w r3, #32768 @ 0x8000 800555a: 617b str r3, [r7, #20] break; 800555c: e009 b.n 8005572 break; 800555e: bf00 nop 8005560: e0fb b.n 800575a break; 8005562: bf00 nop 8005564: e0f9 b.n 800575a break; 8005566: bf00 nop 8005568: e0f7 b.n 800575a break; 800556a: bf00 nop 800556c: e0f5 b.n 800575a break; 800556e: bf00 nop 8005570: e0f3 b.n 800575a break; 8005572: bf00 nop break; 8005574: e0f1 b.n 800575a clocksource = __HAL_RCC_GET_USART234578_SOURCE(); 8005576: 4b6c ldr r3, [pc, #432] @ (8005728 ) 8005578: 6d1b ldr r3, [r3, #80] @ 0x50 800557a: f003 0307 and.w r3, r3, #7 800557e: 613b str r3, [r7, #16] switch (clocksource) 8005580: 693b ldr r3, [r7, #16] 8005582: 2b05 cmp r3, #5 8005584: d84f bhi.n 8005626 8005586: a201 add r2, pc, #4 @ (adr r2, 800558c ) 8005588: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800558c: 080055a5 .word 0x080055a5 8005590: 080055ad .word 0x080055ad 8005594: 080055c1 .word 0x080055c1 8005598: 080055d5 .word 0x080055d5 800559c: 08005601 .word 0x08005601 80055a0: 08005613 .word 0x08005613 frequency = HAL_RCC_GetPCLK1Freq(); 80055a4: f7fd fa80 bl 8002aa8 80055a8: 6178 str r0, [r7, #20] break; 80055aa: e047 b.n 800563c if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) 80055ac: 4b5e ldr r3, [pc, #376] @ (8005728 ) 80055ae: 6adb ldr r3, [r3, #44] @ 0x2c 80055b0: f403 3300 and.w r3, r3, #131072 @ 0x20000 80055b4: 2b00 cmp r3, #0 80055b6: d038 beq.n 800562a frequency = HAL_RCC_GetPLL2QFreq(); 80055b8: f7fd faf6 bl 8002ba8 80055bc: 6178 str r0, [r7, #20] break; 80055be: e034 b.n 800562a if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) 80055c0: 4b59 ldr r3, [pc, #356] @ (8005728 ) 80055c2: 6adb ldr r3, [r3, #44] @ 0x2c 80055c4: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80055c8: 2b00 cmp r3, #0 80055ca: d030 beq.n 800562e frequency = HAL_RCC_GetPLL3QFreq(); 80055cc: f7fd fb5c bl 8002c88 80055d0: 6178 str r0, [r7, #20] break; 80055d2: e02c b.n 800562e if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 80055d4: 4b54 ldr r3, [pc, #336] @ (8005728 ) 80055d6: 681b ldr r3, [r3, #0] 80055d8: f003 0304 and.w r3, r3, #4 80055dc: 2b00 cmp r3, #0 80055de: d028 beq.n 8005632 if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) 80055e0: 4b51 ldr r3, [pc, #324] @ (8005728 ) 80055e2: 681b ldr r3, [r3, #0] 80055e4: f003 0320 and.w r3, r3, #32 80055e8: 2b00 cmp r3, #0 80055ea: d022 beq.n 8005632 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); 80055ec: 4b4e ldr r3, [pc, #312] @ (8005728 ) 80055ee: 681b ldr r3, [r3, #0] 80055f0: 08db lsrs r3, r3, #3 80055f2: f003 0303 and.w r3, r3, #3 80055f6: 4a4d ldr r2, [pc, #308] @ (800572c ) 80055f8: fa22 f303 lsr.w r3, r2, r3 80055fc: 617b str r3, [r7, #20] break; 80055fe: e018 b.n 8005632 if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U) 8005600: 4b49 ldr r3, [pc, #292] @ (8005728 ) 8005602: 681b ldr r3, [r3, #0] 8005604: f403 7380 and.w r3, r3, #256 @ 0x100 8005608: 2b00 cmp r3, #0 800560a: d014 beq.n 8005636 frequency = CSI_VALUE; 800560c: 4b48 ldr r3, [pc, #288] @ (8005730 ) 800560e: 617b str r3, [r7, #20] break; 8005610: e011 b.n 8005636 if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) 8005612: 4b45 ldr r3, [pc, #276] @ (8005728 ) 8005614: 6f1b ldr r3, [r3, #112] @ 0x70 8005616: f003 0302 and.w r3, r3, #2 800561a: 2b00 cmp r3, #0 800561c: d00d beq.n 800563a frequency = LSE_VALUE; 800561e: f44f 4300 mov.w r3, #32768 @ 0x8000 8005622: 617b str r3, [r7, #20] break; 8005624: e009 b.n 800563a break; 8005626: bf00 nop 8005628: e097 b.n 800575a break; 800562a: bf00 nop 800562c: e095 b.n 800575a break; 800562e: bf00 nop 8005630: e093 b.n 800575a break; 8005632: bf00 nop 8005634: e091 b.n 800575a break; 8005636: bf00 nop 8005638: e08f b.n 800575a break; 800563a: bf00 nop break; 800563c: e08d b.n 800575a clocksource = __HAL_RCC_GET_USBPHYC_SOURCE(); 800563e: 4b3a ldr r3, [pc, #232] @ (8005728 ) 8005640: 6cdb ldr r3, [r3, #76] @ 0x4c 8005642: f403 5340 and.w r3, r3, #12288 @ 0x3000 8005646: 613b str r3, [r7, #16] switch (clocksource) 8005648: 693b ldr r3, [r7, #16] 800564a: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800564e: d01d beq.n 800568c 8005650: 693b ldr r3, [r7, #16] 8005652: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8005656: d823 bhi.n 80056a0 8005658: 693b ldr r3, [r7, #16] 800565a: 2b00 cmp r3, #0 800565c: d004 beq.n 8005668 800565e: 693b ldr r3, [r7, #16] 8005660: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8005664: d009 beq.n 800567a break; 8005666: e01b b.n 80056a0 if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 8005668: 4b2f ldr r3, [pc, #188] @ (8005728 ) 800566a: 681b ldr r3, [r3, #0] 800566c: f403 3300 and.w r3, r3, #131072 @ 0x20000 8005670: 2b00 cmp r3, #0 8005672: d017 beq.n 80056a4 frequency = HSE_VALUE; 8005674: 4b2f ldr r3, [pc, #188] @ (8005734 ) 8005676: 617b str r3, [r7, #20] break; 8005678: e014 b.n 80056a4 if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 800567a: 4b2b ldr r3, [pc, #172] @ (8005728 ) 800567c: 681b ldr r3, [r3, #0] 800567e: f403 3300 and.w r3, r3, #131072 @ 0x20000 8005682: 2b00 cmp r3, #0 8005684: d010 beq.n 80056a8 frequency = (HSE_VALUE >> 1UL); 8005686: 4b2c ldr r3, [pc, #176] @ (8005738 ) 8005688: 617b str r3, [r7, #20] break; 800568a: e00d b.n 80056a8 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) 800568c: 4b26 ldr r3, [pc, #152] @ (8005728 ) 800568e: 6adb ldr r3, [r3, #44] @ 0x2c 8005690: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8005694: 2b00 cmp r3, #0 8005696: d009 beq.n 80056ac frequency = HAL_RCC_GetPLL3QFreq(); 8005698: f7fd faf6 bl 8002c88 800569c: 6178 str r0, [r7, #20] break; 800569e: e005 b.n 80056ac break; 80056a0: bf00 nop 80056a2: e05a b.n 800575a break; 80056a4: bf00 nop 80056a6: e058 b.n 800575a break; 80056a8: bf00 nop 80056aa: e056 b.n 800575a break; 80056ac: bf00 nop break; 80056ae: e054 b.n 800575a clocksource = __HAL_RCC_GET_USBOTGFS_SOURCE(); 80056b0: 4b1d ldr r3, [pc, #116] @ (8005728 ) 80056b2: 6cdb ldr r3, [r3, #76] @ 0x4c 80056b4: f403 4340 and.w r3, r3, #49152 @ 0xc000 80056b8: 613b str r3, [r7, #16] switch (clocksource) 80056ba: 693b ldr r3, [r7, #16] 80056bc: f5b3 4f40 cmp.w r3, #49152 @ 0xc000 80056c0: d02f beq.n 8005722 80056c2: 693b ldr r3, [r7, #16] 80056c4: f5b3 4f40 cmp.w r3, #49152 @ 0xc000 80056c8: d83a bhi.n 8005740 80056ca: 693b ldr r3, [r7, #16] 80056cc: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 80056d0: d01e beq.n 8005710 80056d2: 693b ldr r3, [r7, #16] 80056d4: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 80056d8: d832 bhi.n 8005740 80056da: 693b ldr r3, [r7, #16] 80056dc: 2b00 cmp r3, #0 80056de: d004 beq.n 80056ea 80056e0: 693b ldr r3, [r7, #16] 80056e2: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 80056e6: d009 beq.n 80056fc break; 80056e8: e02a b.n 8005740 if (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) != 0U) 80056ea: 4b0f ldr r3, [pc, #60] @ (8005728 ) 80056ec: 681b ldr r3, [r3, #0] 80056ee: f403 5300 and.w r3, r3, #8192 @ 0x2000 80056f2: 2b00 cmp r3, #0 80056f4: d026 beq.n 8005744 frequency = HSI48_VALUE; 80056f6: 4b11 ldr r3, [pc, #68] @ (800573c ) 80056f8: 617b str r3, [r7, #20] break; 80056fa: e023 b.n 8005744 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) 80056fc: 4b0a ldr r3, [pc, #40] @ (8005728 ) 80056fe: 6adb ldr r3, [r3, #44] @ 0x2c 8005700: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8005704: 2b00 cmp r3, #0 8005706: d01f beq.n 8005748 frequency = HAL_RCC_GetPLL3QFreq(); 8005708: f7fd fabe bl 8002c88 800570c: 6178 str r0, [r7, #20] break; 800570e: e01b b.n 8005748 if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 8005710: 4b05 ldr r3, [pc, #20] @ (8005728 ) 8005712: 681b ldr r3, [r3, #0] 8005714: f403 3300 and.w r3, r3, #131072 @ 0x20000 8005718: 2b00 cmp r3, #0 800571a: d017 beq.n 800574c frequency = HSE_VALUE; 800571c: 4b05 ldr r3, [pc, #20] @ (8005734 ) 800571e: 617b str r3, [r7, #20] break; 8005720: e014 b.n 800574c break; 8005722: bf00 nop 8005724: e019 b.n 800575a 8005726: bf00 nop 8005728: 58024400 .word 0x58024400 800572c: 03d09000 .word 0x03d09000 8005730: 003d0900 .word 0x003d0900 8005734: 016e3600 .word 0x016e3600 8005738: 00b71b00 .word 0x00b71b00 800573c: 02dc6c00 .word 0x02dc6c00 break; 8005740: bf00 nop 8005742: e00a b.n 800575a break; 8005744: bf00 nop 8005746: e008 b.n 800575a break; 8005748: bf00 nop 800574a: e006 b.n 800575a break; 800574c: bf00 nop break; 800574e: e004 b.n 800575a break; 8005750: bf00 nop 8005752: e002 b.n 800575a break; 8005754: bf00 nop 8005756: e000 b.n 800575a break; 8005758: bf00 nop } return frequency; 800575a: 697b ldr r3, [r7, #20] } 800575c: 4618 mov r0, r3 800575e: 3718 adds r7, #24 8005760: 46bd mov sp, r7 8005762: bd80 pop {r7, pc} 08005764 : * @arg RCC_CLOCKPROTECT_FMC FMC clock protection * @arg RCC_CLOCKPROTECT_XSPI XSPIs clock protection * @retval None */ void HAL_RCCEx_EnableClockProtection(uint32_t ProtectClk) { 8005764: b480 push {r7} 8005766: b083 sub sp, #12 8005768: af00 add r7, sp, #0 800576a: 6078 str r0, [r7, #4] /* Check the parameter */ assert_param(IS_RCC_CLOCKPROTECTION(ProtectClk)); SET_BIT(RCC->CKPROTR, ProtectClk); 800576c: 4b06 ldr r3, [pc, #24] @ (8005788 ) 800576e: f8d3 2100 ldr.w r2, [r3, #256] @ 0x100 8005772: 4905 ldr r1, [pc, #20] @ (8005788 ) 8005774: 687b ldr r3, [r7, #4] 8005776: 4313 orrs r3, r2 8005778: f8c1 3100 str.w r3, [r1, #256] @ 0x100 } 800577c: bf00 nop 800577e: 370c adds r7, #12 8005780: 46bd mov sp, r7 8005782: f85d 7b04 ldr.w r7, [sp], #4 8005786: 4770 bx lr 8005788: 58024400 .word 0x58024400 0800578c : /** * @brief Compute PLL2 VCO output frequency * @retval Value of PLL2 VCO output frequency */ static uint32_t RCC_GetCLKPFreq(void) { 800578c: b480 push {r7} 800578e: b083 sub sp, #12 8005790: af00 add r7, sp, #0 uint32_t frequency = 0U; 8005792: 2300 movs r3, #0 8005794: 607b str r3, [r7, #4] uint32_t ckpclocksource; ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 8005796: 4b1f ldr r3, [pc, #124] @ (8005814 ) 8005798: 6cdb ldr r3, [r3, #76] @ 0x4c 800579a: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800579e: 603b str r3, [r7, #0] if (ckpclocksource == RCC_CLKPSOURCE_HSI) 80057a0: 683b ldr r3, [r7, #0] 80057a2: 2b00 cmp r3, #0 80057a4: d115 bne.n 80057d2 { if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 80057a6: 4b1b ldr r3, [pc, #108] @ (8005814 ) 80057a8: 681b ldr r3, [r3, #0] 80057aa: f003 0304 and.w r3, r3, #4 80057ae: 2b00 cmp r3, #0 80057b0: d028 beq.n 8005804 { if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) 80057b2: 4b18 ldr r3, [pc, #96] @ (8005814 ) 80057b4: 681b ldr r3, [r3, #0] 80057b6: f003 0320 and.w r3, r3, #32 80057ba: 2b00 cmp r3, #0 80057bc: d022 beq.n 8005804 { frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); 80057be: 4b15 ldr r3, [pc, #84] @ (8005814 ) 80057c0: 681b ldr r3, [r3, #0] 80057c2: 08db lsrs r3, r3, #3 80057c4: f003 0303 and.w r3, r3, #3 80057c8: 4a13 ldr r2, [pc, #76] @ (8005818 ) 80057ca: fa22 f303 lsr.w r3, r2, r3 80057ce: 607b str r3, [r7, #4] 80057d0: e018 b.n 8005804 { /* Can't retrieve HSIDIV value */ } } } else if (ckpclocksource == RCC_CLKPSOURCE_CSI) 80057d2: 683b ldr r3, [r7, #0] 80057d4: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 80057d8: d108 bne.n 80057ec { if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U) 80057da: 4b0e ldr r3, [pc, #56] @ (8005814 ) 80057dc: 681b ldr r3, [r3, #0] 80057de: f403 7380 and.w r3, r3, #256 @ 0x100 80057e2: 2b00 cmp r3, #0 80057e4: d00e beq.n 8005804 { frequency = CSI_VALUE; 80057e6: 4b0d ldr r3, [pc, #52] @ (800581c ) 80057e8: 607b str r3, [r7, #4] 80057ea: e00b b.n 8005804 } } else if (ckpclocksource == RCC_CLKPSOURCE_HSE) 80057ec: 683b ldr r3, [r7, #0] 80057ee: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 80057f2: d107 bne.n 8005804 { if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 80057f4: 4b07 ldr r3, [pc, #28] @ (8005814 ) 80057f6: 681b ldr r3, [r3, #0] 80057f8: f403 3300 and.w r3, r3, #131072 @ 0x20000 80057fc: 2b00 cmp r3, #0 80057fe: d001 beq.n 8005804 { frequency = HSE_VALUE; 8005800: 4b07 ldr r3, [pc, #28] @ (8005820 ) 8005802: 607b str r3, [r7, #4] { /* Nothing to do, case the CKPER is disabled */ /* frequency is by default set to 0 */ } return frequency; 8005804: 687b ldr r3, [r7, #4] } 8005806: 4618 mov r0, r3 8005808: 370c adds r7, #12 800580a: 46bd mov sp, r7 800580c: f85d 7b04 ldr.w r7, [sp], #4 8005810: 4770 bx lr 8005812: bf00 nop 8005814: 58024400 .word 0x58024400 8005818: 03d09000 .word 0x03d09000 800581c: 003d0900 .word 0x003d0900 8005820: 016e3600 .word 0x016e3600 08005824 : * in the XSPI_InitTypeDef and initialize the associated handle. * @param hxspi : XSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_XSPI_Init(XSPI_HandleTypeDef *hxspi) { 8005824: b580 push {r7, lr} 8005826: b086 sub sp, #24 8005828: af02 add r7, sp, #8 800582a: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800582c: 2300 movs r3, #0 800582e: 73fb strb r3, [r7, #15] uint32_t tickstart = HAL_GetTick(); 8005830: f7fb fa5e bl 8000cf0 8005834: 60b8 str r0, [r7, #8] /* Check the XSPI handle allocation */ if (hxspi == NULL) 8005836: 687b ldr r3, [r7, #4] 8005838: 2b00 cmp r3, #0 800583a: d102 bne.n 8005842 { status = HAL_ERROR; 800583c: 2301 movs r3, #1 800583e: 73fb strb r3, [r7, #15] 8005840: e0f3 b.n 8005a2a assert_param(IS_XSPI_CS_BOUND(hxspi->Init.ChipSelectBoundary)); assert_param(IS_XSPI_FIFO_THRESHOLD_BYTE(hxspi->Init.FifoThresholdByte)); assert_param(IS_XSPI_MAXTRAN(hxspi->Init.MaxTran)); assert_param(IS_XSPI_CSSEL(hxspi->Init.MemorySelect)); /* Initialize error code */ hxspi->ErrorCode = HAL_XSPI_ERROR_NONE; 8005842: 687b ldr r3, [r7, #4] 8005844: 2200 movs r2, #0 8005846: 659a str r2, [r3, #88] @ 0x58 /* Check if the state is the reset state */ if (hxspi->State == HAL_XSPI_STATE_RESET) 8005848: 687b ldr r3, [r7, #4] 800584a: 6d5b ldr r3, [r3, #84] @ 0x54 800584c: 2b00 cmp r3, #0 800584e: f040 80ec bne.w 8005a2a { #if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) /* Reset Callback pointers in HAL_XSPI_STATE_RESET only */ hxspi->ErrorCallback = HAL_XSPI_ErrorCallback; 8005852: 687b ldr r3, [r7, #4] 8005854: 4a77 ldr r2, [pc, #476] @ (8005a34 ) 8005856: 661a str r2, [r3, #96] @ 0x60 hxspi->AbortCpltCallback = HAL_XSPI_AbortCpltCallback; 8005858: 687b ldr r3, [r7, #4] 800585a: 4a77 ldr r2, [pc, #476] @ (8005a38 ) 800585c: 665a str r2, [r3, #100] @ 0x64 hxspi->FifoThresholdCallback = HAL_XSPI_FifoThresholdCallback; 800585e: 687b ldr r3, [r7, #4] 8005860: 4a76 ldr r2, [pc, #472] @ (8005a3c ) 8005862: 669a str r2, [r3, #104] @ 0x68 hxspi->CmdCpltCallback = HAL_XSPI_CmdCpltCallback; 8005864: 687b ldr r3, [r7, #4] 8005866: 4a76 ldr r2, [pc, #472] @ (8005a40 ) 8005868: 66da str r2, [r3, #108] @ 0x6c hxspi->RxCpltCallback = HAL_XSPI_RxCpltCallback; 800586a: 687b ldr r3, [r7, #4] 800586c: 4a75 ldr r2, [pc, #468] @ (8005a44 ) 800586e: 671a str r2, [r3, #112] @ 0x70 hxspi->TxCpltCallback = HAL_XSPI_TxCpltCallback; 8005870: 687b ldr r3, [r7, #4] 8005872: 4a75 ldr r2, [pc, #468] @ (8005a48 ) 8005874: 675a str r2, [r3, #116] @ 0x74 hxspi->RxHalfCpltCallback = HAL_XSPI_RxHalfCpltCallback; 8005876: 687b ldr r3, [r7, #4] 8005878: 4a74 ldr r2, [pc, #464] @ (8005a4c ) 800587a: 679a str r2, [r3, #120] @ 0x78 hxspi->TxHalfCpltCallback = HAL_XSPI_TxHalfCpltCallback; 800587c: 687b ldr r3, [r7, #4] 800587e: 4a74 ldr r2, [pc, #464] @ (8005a50 ) 8005880: 67da str r2, [r3, #124] @ 0x7c hxspi->StatusMatchCallback = HAL_XSPI_StatusMatchCallback; 8005882: 687b ldr r3, [r7, #4] 8005884: 4a73 ldr r2, [pc, #460] @ (8005a54 ) 8005886: f8c3 2080 str.w r2, [r3, #128] @ 0x80 hxspi->TimeOutCallback = HAL_XSPI_TimeOutCallback; 800588a: 687b ldr r3, [r7, #4] 800588c: 4a72 ldr r2, [pc, #456] @ (8005a58 ) 800588e: f8c3 2084 str.w r2, [r3, #132] @ 0x84 if (hxspi->MspInitCallback == NULL) 8005892: 687b ldr r3, [r7, #4] 8005894: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8005898: 2b00 cmp r3, #0 800589a: d103 bne.n 80058a4 { hxspi->MspInitCallback = HAL_XSPI_MspInit; 800589c: 687b ldr r3, [r7, #4] 800589e: 4a6f ldr r2, [pc, #444] @ (8005a5c ) 80058a0: f8c3 2088 str.w r2, [r3, #136] @ 0x88 } /* Init the low level hardware */ hxspi->MspInitCallback(hxspi); 80058a4: 687b ldr r3, [r7, #4] 80058a6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80058aa: 6878 ldr r0, [r7, #4] 80058ac: 4798 blx r3 /* Initialization of the low level hardware */ HAL_XSPI_MspInit(hxspi); #endif /* defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ /* Configure the default timeout for the XSPI memory access */ (void)HAL_XSPI_SetTimeout(hxspi, HAL_XSPI_TIMEOUT_DEFAULT_VALUE); 80058ae: f241 3188 movw r1, #5000 @ 0x1388 80058b2: 6878 ldr r0, [r7, #4] 80058b4: f000 fffe bl 80068b4 /* Configure memory type, device size, chip select high time, free running clock, clock mode */ MODIFY_REG(hxspi->Instance->DCR1, 80058b8: 687b ldr r3, [r7, #4] 80058ba: 681b ldr r3, [r3, #0] 80058bc: 689a ldr r2, [r3, #8] 80058be: 4b68 ldr r3, [pc, #416] @ (8005a60 ) 80058c0: 4013 ands r3, r2 80058c2: 687a ldr r2, [r7, #4] 80058c4: 68d1 ldr r1, [r2, #12] 80058c6: 687a ldr r2, [r7, #4] 80058c8: 6912 ldr r2, [r2, #16] 80058ca: 0412 lsls r2, r2, #16 80058cc: 4311 orrs r1, r2 80058ce: 687a ldr r2, [r7, #4] 80058d0: 6952 ldr r2, [r2, #20] 80058d2: 3a01 subs r2, #1 80058d4: 0212 lsls r2, r2, #8 80058d6: 4311 orrs r1, r2 80058d8: 687a ldr r2, [r7, #4] 80058da: 69d2 ldr r2, [r2, #28] 80058dc: 4311 orrs r1, r2 80058de: 687a ldr r2, [r7, #4] 80058e0: 6812 ldr r2, [r2, #0] 80058e2: 430b orrs r3, r1 80058e4: 6093 str r3, [r2, #8] (XSPI_DCR1_MTYP | XSPI_DCR1_DEVSIZE | XSPI_DCR1_CSHT | XSPI_DCR1_FRCK | XSPI_DCR1_CKMODE), (hxspi->Init.MemoryType | ((hxspi->Init.MemorySize) << XSPI_DCR1_DEVSIZE_Pos) | ((hxspi->Init.ChipSelectHighTimeCycle - 1U) << XSPI_DCR1_CSHT_Pos) | hxspi->Init.ClockMode)); /* Configure wrap size */ MODIFY_REG(hxspi->Instance->DCR2, XSPI_DCR2_WRAPSIZE, hxspi->Init.WrapSize); 80058e6: 687b ldr r3, [r7, #4] 80058e8: 681b ldr r3, [r3, #0] 80058ea: 68db ldr r3, [r3, #12] 80058ec: f423 21e0 bic.w r1, r3, #458752 @ 0x70000 80058f0: 687b ldr r3, [r7, #4] 80058f2: 6a1a ldr r2, [r3, #32] 80058f4: 687b ldr r3, [r7, #4] 80058f6: 681b ldr r3, [r3, #0] 80058f8: 430a orrs r2, r1 80058fa: 60da str r2, [r3, #12] /* Configure chip select boundary */ MODIFY_REG(hxspi->Instance->DCR3, XSPI_DCR3_CSBOUND, (hxspi->Init.ChipSelectBoundary << XSPI_DCR3_CSBOUND_Pos)); 80058fc: 687b ldr r3, [r7, #4] 80058fe: 681b ldr r3, [r3, #0] 8005900: 691b ldr r3, [r3, #16] 8005902: f423 11f8 bic.w r1, r3, #2031616 @ 0x1f0000 8005906: 687b ldr r3, [r7, #4] 8005908: 6b1b ldr r3, [r3, #48] @ 0x30 800590a: 041a lsls r2, r3, #16 800590c: 687b ldr r3, [r7, #4] 800590e: 681b ldr r3, [r3, #0] 8005910: 430a orrs r2, r1 8005912: 611a str r2, [r3, #16] /* Configure maximum transfer */ MODIFY_REG(hxspi->Instance->DCR3, XSPI_DCR3_MAXTRAN, \ 8005914: 687b ldr r3, [r7, #4] 8005916: 681b ldr r3, [r3, #0] 8005918: 691b ldr r3, [r3, #16] 800591a: f023 01ff bic.w r1, r3, #255 @ 0xff 800591e: 687b ldr r3, [r7, #4] 8005920: 6b5a ldr r2, [r3, #52] @ 0x34 8005922: 687b ldr r3, [r7, #4] 8005924: 681b ldr r3, [r3, #0] 8005926: 430a orrs r2, r1 8005928: 611a str r2, [r3, #16] (hxspi->Init.MaxTran << XSPI_DCR3_MAXTRAN_Pos)); /* Configure refresh */ hxspi->Instance->DCR4 = hxspi->Init.Refresh; 800592a: 687b ldr r3, [r7, #4] 800592c: 681b ldr r3, [r3, #0] 800592e: 687a ldr r2, [r7, #4] 8005930: 6b92 ldr r2, [r2, #56] @ 0x38 8005932: 615a str r2, [r3, #20] /* Configure FIFO threshold */ MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FTHRES, ((hxspi->Init.FifoThresholdByte - 1U) << XSPI_CR_FTHRES_Pos)); 8005934: 687b ldr r3, [r7, #4] 8005936: 681b ldr r3, [r3, #0] 8005938: 681b ldr r3, [r3, #0] 800593a: f423 51f8 bic.w r1, r3, #7936 @ 0x1f00 800593e: 687b ldr r3, [r7, #4] 8005940: 685b ldr r3, [r3, #4] 8005942: 3b01 subs r3, #1 8005944: 021a lsls r2, r3, #8 8005946: 687b ldr r3, [r7, #4] 8005948: 681b ldr r3, [r3, #0] 800594a: 430a orrs r2, r1 800594c: 601a str r2, [r3, #0] /* Wait till busy flag is reset */ status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeout); 800594e: 687b ldr r3, [r7, #4] 8005950: 6ddb ldr r3, [r3, #92] @ 0x5c 8005952: 9300 str r3, [sp, #0] 8005954: 68bb ldr r3, [r7, #8] 8005956: 2200 movs r2, #0 8005958: 2120 movs r1, #32 800595a: 6878 ldr r0, [r7, #4] 800595c: f001 f953 bl 8006c06 8005960: 4603 mov r3, r0 8005962: 73fb strb r3, [r7, #15] if (status == HAL_OK) 8005964: 7bfb ldrb r3, [r7, #15] 8005966: 2b00 cmp r3, #0 8005968: d15f bne.n 8005a2a { /* Configure clock prescaler */ MODIFY_REG(hxspi->Instance->DCR2, XSPI_DCR2_PRESCALER, 800596a: 687b ldr r3, [r7, #4] 800596c: 681b ldr r3, [r3, #0] 800596e: 68db ldr r3, [r3, #12] 8005970: f023 01ff bic.w r1, r3, #255 @ 0xff 8005974: 687b ldr r3, [r7, #4] 8005976: 6a5a ldr r2, [r3, #36] @ 0x24 8005978: 687b ldr r3, [r7, #4] 800597a: 681b ldr r3, [r3, #0] 800597c: 430a orrs r2, r1 800597e: 60da str r2, [r3, #12] ((hxspi->Init.ClockPrescaler) << XSPI_DCR2_PRESCALER_Pos)); if (IS_XSPI_ALL_INSTANCE(hxspi->Instance)) 8005980: 687b ldr r3, [r7, #4] 8005982: 681b ldr r3, [r3, #0] 8005984: 4a37 ldr r2, [pc, #220] @ (8005a64 ) 8005986: 4293 cmp r3, r2 8005988: d004 beq.n 8005994 800598a: 687b ldr r3, [r7, #4] 800598c: 681b ldr r3, [r3, #0] 800598e: 4a36 ldr r2, [pc, #216] @ (8005a68 ) 8005990: 4293 cmp r3, r2 8005992: d10f bne.n 80059b4 { /* The configuration of clock prescaler trigger automatically a calibration process. So it is necessary to wait the calibration is complete */ status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeout); 8005994: 687b ldr r3, [r7, #4] 8005996: 6ddb ldr r3, [r3, #92] @ 0x5c 8005998: 9300 str r3, [sp, #0] 800599a: 68bb ldr r3, [r7, #8] 800599c: 2200 movs r2, #0 800599e: 2120 movs r1, #32 80059a0: 6878 ldr r0, [r7, #4] 80059a2: f001 f930 bl 8006c06 80059a6: 4603 mov r3, r0 80059a8: 73fb strb r3, [r7, #15] if (status != HAL_OK) 80059aa: 7bfb ldrb r3, [r7, #15] 80059ac: 2b00 cmp r3, #0 80059ae: d001 beq.n 80059b4 { return status; 80059b0: 7bfb ldrb r3, [r7, #15] 80059b2: e03b b.n 8005a2c } } /* Configure Dual Memory mode and CS Selection */ MODIFY_REG(hxspi->Instance->CR, (XSPI_CR_DMM | XSPI_CR_CSSEL), 80059b4: 687b ldr r3, [r7, #4] 80059b6: 681b ldr r3, [r3, #0] 80059b8: 681a ldr r2, [r3, #0] 80059ba: 4b2c ldr r3, [pc, #176] @ (8005a6c ) 80059bc: 4013 ands r3, r2 80059be: 687a ldr r2, [r7, #4] 80059c0: 6891 ldr r1, [r2, #8] 80059c2: 687a ldr r2, [r7, #4] 80059c4: 6bd2 ldr r2, [r2, #60] @ 0x3c 80059c6: 4311 orrs r1, r2 80059c8: 687a ldr r2, [r7, #4] 80059ca: 6812 ldr r2, [r2, #0] 80059cc: 430b orrs r3, r1 80059ce: 6013 str r3, [r2, #0] (hxspi->Init.MemoryMode | hxspi->Init.MemorySelect)); /* Configure sample shifting */ MODIFY_REG(hxspi->Instance->TCR, (XSPI_TCR_SSHIFT), hxspi->Init.SampleShifting); 80059d0: 687b ldr r3, [r7, #4] 80059d2: 681b ldr r3, [r3, #0] 80059d4: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 80059d8: f023 4180 bic.w r1, r3, #1073741824 @ 0x40000000 80059dc: 687b ldr r3, [r7, #4] 80059de: 6a9a ldr r2, [r3, #40] @ 0x28 80059e0: 687b ldr r3, [r7, #4] 80059e2: 681b ldr r3, [r3, #0] 80059e4: 430a orrs r2, r1 80059e6: f8c3 2108 str.w r2, [r3, #264] @ 0x108 /* Enable XSPI */ HAL_XSPI_ENABLE(hxspi); 80059ea: 687b ldr r3, [r7, #4] 80059ec: 681b ldr r3, [r3, #0] 80059ee: 681a ldr r2, [r3, #0] 80059f0: 687b ldr r3, [r7, #4] 80059f2: 681b ldr r3, [r3, #0] 80059f4: f042 0201 orr.w r2, r2, #1 80059f8: 601a str r2, [r3, #0] /* Enable free running clock if needed : must be done after XSPI enable */ if (hxspi->Init.FreeRunningClock == HAL_XSPI_FREERUNCLK_ENABLE) 80059fa: 687b ldr r3, [r7, #4] 80059fc: 699b ldr r3, [r3, #24] 80059fe: 2b02 cmp r3, #2 8005a00: d107 bne.n 8005a12 { SET_BIT(hxspi->Instance->DCR1, XSPI_DCR1_FRCK); 8005a02: 687b ldr r3, [r7, #4] 8005a04: 681b ldr r3, [r3, #0] 8005a06: 689a ldr r2, [r3, #8] 8005a08: 687b ldr r3, [r7, #4] 8005a0a: 681b ldr r3, [r3, #0] 8005a0c: f042 0202 orr.w r2, r2, #2 8005a10: 609a str r2, [r3, #8] } /* Initialize the XSPI state */ if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) 8005a12: 687b ldr r3, [r7, #4] 8005a14: 68db ldr r3, [r3, #12] 8005a16: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 8005a1a: d103 bne.n 8005a24 { hxspi->State = HAL_XSPI_STATE_HYPERBUS_INIT; 8005a1c: 687b ldr r3, [r7, #4] 8005a1e: 2201 movs r2, #1 8005a20: 655a str r2, [r3, #84] @ 0x54 8005a22: e002 b.n 8005a2a } else { hxspi->State = HAL_XSPI_STATE_READY; 8005a24: 687b ldr r3, [r7, #4] 8005a26: 2202 movs r2, #2 8005a28: 655a str r2, [r3, #84] @ 0x54 } } } } return status; 8005a2a: 7bfb ldrb r3, [r7, #15] } 8005a2c: 4618 mov r0, r3 8005a2e: 3710 adds r7, #16 8005a30: 46bd mov sp, r7 8005a32: bd80 pop {r7, pc} 8005a34: 08006485 .word 0x08006485 8005a38: 08006499 .word 0x08006499 8005a3c: 080064ad .word 0x080064ad 8005a40: 080064c1 .word 0x080064c1 8005a44: 080064d5 .word 0x080064d5 8005a48: 080064e9 .word 0x080064e9 8005a4c: 080064fd .word 0x080064fd 8005a50: 08006511 .word 0x08006511 8005a54: 08006525 .word 0x08006525 8005a58: 08006539 .word 0x08006539 8005a5c: 08000955 .word 0x08000955 8005a60: f8e0c0fc .word 0xf8e0c0fc 8005a64: 52005000 .word 0x52005000 8005a68: 5200a000 .word 0x5200a000 8005a6c: feffffbf .word 0xfeffffbf 08005a70 : * @param pCmd : structure that contains the command configuration information * @param Timeout : Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_XSPI_Command(XSPI_HandleTypeDef *hxspi, const XSPI_RegularCmdTypeDef *pCmd, uint32_t Timeout) { 8005a70: b580 push {r7, lr} 8005a72: b08a sub sp, #40 @ 0x28 8005a74: af02 add r7, sp, #8 8005a76: 60f8 str r0, [r7, #12] 8005a78: 60b9 str r1, [r7, #8] 8005a7a: 607a str r2, [r7, #4] HAL_StatusTypeDef status; uint32_t state; uint32_t tickstart = HAL_GetTick(); 8005a7c: f7fb f938 bl 8000cf0 8005a80: 61b8 str r0, [r7, #24] assert_param(IS_XSPI_ALT_BYTES_DTR_MODE(pCmd->AlternateBytesDTRMode)); } assert_param(IS_XSPI_DATA_MODE(hxspi->Init.MemoryType, pCmd->DataMode)); if (pCmd->DataMode != HAL_XSPI_DATA_NONE) 8005a82: 68bb ldr r3, [r7, #8] 8005a84: 6b9b ldr r3, [r3, #56] @ 0x38 8005a86: 2b00 cmp r3, #0 } assert_param(IS_XSPI_DQS_MODE(pCmd->DQSMode)); /* Check the state of the driver */ state = hxspi->State; 8005a88: 68fb ldr r3, [r7, #12] 8005a8a: 6d5b ldr r3, [r3, #84] @ 0x54 8005a8c: 617b str r3, [r7, #20] if (((state == HAL_XSPI_STATE_READY) && (hxspi->Init.MemoryType != HAL_XSPI_MEMTYPE_HYPERBUS)) || 8005a8e: 697b ldr r3, [r7, #20] 8005a90: 2b02 cmp r3, #2 8005a92: d104 bne.n 8005a9e 8005a94: 68fb ldr r3, [r7, #12] 8005a96: 68db ldr r3, [r3, #12] 8005a98: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 8005a9c: d115 bne.n 8005aca 8005a9e: 697b ldr r3, [r7, #20] 8005aa0: 2b14 cmp r3, #20 8005aa2: d107 bne.n 8005ab4 ((state == HAL_XSPI_STATE_READ_CMD_CFG) && ((pCmd->OperationType == HAL_XSPI_OPTYPE_WRITE_CFG) || 8005aa4: 68bb ldr r3, [r7, #8] 8005aa6: 681b ldr r3, [r3, #0] 8005aa8: 2b02 cmp r3, #2 8005aaa: d00e beq.n 8005aca (pCmd->OperationType == HAL_XSPI_OPTYPE_WRAP_CFG))) || 8005aac: 68bb ldr r3, [r7, #8] 8005aae: 681b ldr r3, [r3, #0] ((state == HAL_XSPI_STATE_READ_CMD_CFG) && ((pCmd->OperationType == HAL_XSPI_OPTYPE_WRITE_CFG) || 8005ab0: 2b03 cmp r3, #3 8005ab2: d00a beq.n 8005aca (pCmd->OperationType == HAL_XSPI_OPTYPE_WRAP_CFG))) || 8005ab4: 697b ldr r3, [r7, #20] 8005ab6: 2b24 cmp r3, #36 @ 0x24 8005ab8: d15e bne.n 8005b78 ((state == HAL_XSPI_STATE_WRITE_CMD_CFG) && ((pCmd->OperationType == HAL_XSPI_OPTYPE_READ_CFG) || 8005aba: 68bb ldr r3, [r7, #8] 8005abc: 681b ldr r3, [r3, #0] ((state == HAL_XSPI_STATE_WRITE_CMD_CFG) && 8005abe: 2b01 cmp r3, #1 8005ac0: d003 beq.n 8005aca (pCmd->OperationType == HAL_XSPI_OPTYPE_WRAP_CFG)))) 8005ac2: 68bb ldr r3, [r7, #8] 8005ac4: 681b ldr r3, [r3, #0] ((pCmd->OperationType == HAL_XSPI_OPTYPE_READ_CFG) || 8005ac6: 2b03 cmp r3, #3 8005ac8: d156 bne.n 8005b78 { /* Wait till busy flag is reset */ status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); 8005aca: 687b ldr r3, [r7, #4] 8005acc: 9300 str r3, [sp, #0] 8005ace: 69bb ldr r3, [r7, #24] 8005ad0: 2200 movs r2, #0 8005ad2: 2120 movs r1, #32 8005ad4: 68f8 ldr r0, [r7, #12] 8005ad6: f001 f896 bl 8006c06 8005ada: 4603 mov r3, r0 8005adc: 77fb strb r3, [r7, #31] if (status == HAL_OK) 8005ade: 7ffb ldrb r3, [r7, #31] 8005ae0: 2b00 cmp r3, #0 8005ae2: d146 bne.n 8005b72 { /* Initialize error code */ hxspi->ErrorCode = HAL_XSPI_ERROR_NONE; 8005ae4: 68fb ldr r3, [r7, #12] 8005ae6: 2200 movs r2, #0 8005ae8: 659a str r2, [r3, #88] @ 0x58 /* Configure the registers */ status = XSPI_ConfigCmd(hxspi, pCmd); 8005aea: 68b9 ldr r1, [r7, #8] 8005aec: 68f8 ldr r0, [r7, #12] 8005aee: f001 f8c1 bl 8006c74 8005af2: 4603 mov r3, r0 8005af4: 77fb strb r3, [r7, #31] if (status == HAL_OK) 8005af6: 7ffb ldrb r3, [r7, #31] 8005af8: 2b00 cmp r3, #0 8005afa: d143 bne.n 8005b84 { if (pCmd->DataMode == HAL_XSPI_DATA_NONE) 8005afc: 68bb ldr r3, [r7, #8] 8005afe: 6b9b ldr r3, [r3, #56] @ 0x38 8005b00: 2b00 cmp r3, #0 8005b02: d10e bne.n 8005b22 { /* When there is no data phase, the transfer start as soon as the configuration is done so wait until BUSY flag is reset to go back in idle state. */ status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); 8005b04: 687b ldr r3, [r7, #4] 8005b06: 9300 str r3, [sp, #0] 8005b08: 69bb ldr r3, [r7, #24] 8005b0a: 2200 movs r2, #0 8005b0c: 2120 movs r1, #32 8005b0e: 68f8 ldr r0, [r7, #12] 8005b10: f001 f879 bl 8006c06 8005b14: 4603 mov r3, r0 8005b16: 77fb strb r3, [r7, #31] /* Clear TC flag */ HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); 8005b18: 68fb ldr r3, [r7, #12] 8005b1a: 681b ldr r3, [r3, #0] 8005b1c: 2202 movs r2, #2 8005b1e: 625a str r2, [r3, #36] @ 0x24 if (status == HAL_OK) 8005b20: e030 b.n 8005b84 } else { /* Update the state */ if (pCmd->OperationType == HAL_XSPI_OPTYPE_COMMON_CFG) 8005b22: 68bb ldr r3, [r7, #8] 8005b24: 681b ldr r3, [r3, #0] 8005b26: 2b00 cmp r3, #0 8005b28: d103 bne.n 8005b32 { hxspi->State = HAL_XSPI_STATE_CMD_CFG; 8005b2a: 68fb ldr r3, [r7, #12] 8005b2c: 2204 movs r2, #4 8005b2e: 655a str r2, [r3, #84] @ 0x54 if (status == HAL_OK) 8005b30: e028 b.n 8005b84 } else if (pCmd->OperationType == HAL_XSPI_OPTYPE_READ_CFG) 8005b32: 68bb ldr r3, [r7, #8] 8005b34: 681b ldr r3, [r3, #0] 8005b36: 2b01 cmp r3, #1 8005b38: d10b bne.n 8005b52 { if (hxspi->State == HAL_XSPI_STATE_WRITE_CMD_CFG) 8005b3a: 68fb ldr r3, [r7, #12] 8005b3c: 6d5b ldr r3, [r3, #84] @ 0x54 8005b3e: 2b24 cmp r3, #36 @ 0x24 8005b40: d103 bne.n 8005b4a { hxspi->State = HAL_XSPI_STATE_CMD_CFG; 8005b42: 68fb ldr r3, [r7, #12] 8005b44: 2204 movs r2, #4 8005b46: 655a str r2, [r3, #84] @ 0x54 if (status == HAL_OK) 8005b48: e01c b.n 8005b84 } else { hxspi->State = HAL_XSPI_STATE_READ_CMD_CFG; 8005b4a: 68fb ldr r3, [r7, #12] 8005b4c: 2214 movs r2, #20 8005b4e: 655a str r2, [r3, #84] @ 0x54 if (status == HAL_OK) 8005b50: e018 b.n 8005b84 } } else if (pCmd->OperationType == HAL_XSPI_OPTYPE_WRITE_CFG) 8005b52: 68bb ldr r3, [r7, #8] 8005b54: 681b ldr r3, [r3, #0] 8005b56: 2b02 cmp r3, #2 8005b58: d114 bne.n 8005b84 { if (hxspi->State == HAL_XSPI_STATE_READ_CMD_CFG) 8005b5a: 68fb ldr r3, [r7, #12] 8005b5c: 6d5b ldr r3, [r3, #84] @ 0x54 8005b5e: 2b14 cmp r3, #20 8005b60: d103 bne.n 8005b6a { hxspi->State = HAL_XSPI_STATE_CMD_CFG; 8005b62: 68fb ldr r3, [r7, #12] 8005b64: 2204 movs r2, #4 8005b66: 655a str r2, [r3, #84] @ 0x54 if (status == HAL_OK) 8005b68: e00c b.n 8005b84 } else { hxspi->State = HAL_XSPI_STATE_WRITE_CMD_CFG; 8005b6a: 68fb ldr r3, [r7, #12] 8005b6c: 2224 movs r2, #36 @ 0x24 8005b6e: 655a str r2, [r3, #84] @ 0x54 if (status == HAL_OK) 8005b70: e008 b.n 8005b84 } } } else { status = HAL_BUSY; 8005b72: 2302 movs r3, #2 8005b74: 77fb strb r3, [r7, #31] if (status == HAL_OK) 8005b76: e005 b.n 8005b84 } } else { status = HAL_ERROR; 8005b78: 2301 movs r3, #1 8005b7a: 77fb strb r3, [r7, #31] hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; 8005b7c: 68fb ldr r3, [r7, #12] 8005b7e: 2210 movs r2, #16 8005b80: 659a str r2, [r3, #88] @ 0x58 8005b82: e000 b.n 8005b86 if (status == HAL_OK) 8005b84: bf00 nop } return status; 8005b86: 7ffb ldrb r3, [r7, #31] } 8005b88: 4618 mov r0, r3 8005b8a: 3720 adds r7, #32 8005b8c: 46bd mov sp, r7 8005b8e: bd80 pop {r7, pc} 08005b90 : * @param Timeout : Timeout duration * @note This function is used only in Indirect Write Mode * @retval HAL status */ HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, const uint8_t *pData, uint32_t Timeout) { 8005b90: b580 push {r7, lr} 8005b92: b08a sub sp, #40 @ 0x28 8005b94: af02 add r7, sp, #8 8005b96: 60f8 str r0, [r7, #12] 8005b98: 60b9 str r1, [r7, #8] 8005b9a: 607a str r2, [r7, #4] HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); 8005b9c: f7fb f8a8 bl 8000cf0 8005ba0: 61b8 str r0, [r7, #24] __IO uint32_t *data_reg = &hxspi->Instance->DR; 8005ba2: 68fb ldr r3, [r7, #12] 8005ba4: 681b ldr r3, [r3, #0] 8005ba6: 3350 adds r3, #80 @ 0x50 8005ba8: 617b str r3, [r7, #20] /* Check the data pointer allocation */ if (pData == NULL) 8005baa: 68bb ldr r3, [r7, #8] 8005bac: 2b00 cmp r3, #0 8005bae: d105 bne.n 8005bbc { status = HAL_ERROR; 8005bb0: 2301 movs r3, #1 8005bb2: 77fb strb r3, [r7, #31] hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; 8005bb4: 68fb ldr r3, [r7, #12] 8005bb6: 2208 movs r2, #8 8005bb8: 659a str r2, [r3, #88] @ 0x58 8005bba: e057 b.n 8005c6c } else { /* Check the state */ if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) 8005bbc: 68fb ldr r3, [r7, #12] 8005bbe: 6d5b ldr r3, [r3, #84] @ 0x54 8005bc0: 2b04 cmp r3, #4 8005bc2: d14e bne.n 8005c62 { /* Configure counters and size */ hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; 8005bc4: 68fb ldr r3, [r7, #12] 8005bc6: 681b ldr r3, [r3, #0] 8005bc8: 6c1b ldr r3, [r3, #64] @ 0x40 8005bca: 1c5a adds r2, r3, #1 8005bcc: 68fb ldr r3, [r7, #12] 8005bce: 649a str r2, [r3, #72] @ 0x48 hxspi->XferSize = hxspi->XferCount; 8005bd0: 68fb ldr r3, [r7, #12] 8005bd2: 6c9a ldr r2, [r3, #72] @ 0x48 8005bd4: 68fb ldr r3, [r7, #12] 8005bd6: 645a str r2, [r3, #68] @ 0x44 hxspi->pBuffPtr = (uint8_t *)pData; 8005bd8: 68fb ldr r3, [r7, #12] 8005bda: 68ba ldr r2, [r7, #8] 8005bdc: 641a str r2, [r3, #64] @ 0x40 /* Configure CR register with functional mode as indirect write */ MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); 8005bde: 68fb ldr r3, [r7, #12] 8005be0: 681b ldr r3, [r3, #0] 8005be2: 681a ldr r2, [r3, #0] 8005be4: 68fb ldr r3, [r7, #12] 8005be6: 681b ldr r3, [r3, #0] 8005be8: f022 5240 bic.w r2, r2, #805306368 @ 0x30000000 8005bec: 601a str r2, [r3, #0] do { /* Wait till fifo threshold flag is set to send data */ status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_FT, SET, tickstart, Timeout); 8005bee: 687b ldr r3, [r7, #4] 8005bf0: 9300 str r3, [sp, #0] 8005bf2: 69bb ldr r3, [r7, #24] 8005bf4: 2201 movs r2, #1 8005bf6: 2104 movs r1, #4 8005bf8: 68f8 ldr r0, [r7, #12] 8005bfa: f001 f804 bl 8006c06 8005bfe: 4603 mov r3, r0 8005c00: 77fb strb r3, [r7, #31] if (status != HAL_OK) 8005c02: 7ffb ldrb r3, [r7, #31] 8005c04: 2b00 cmp r3, #0 8005c06: d113 bne.n 8005c30 { break; } *((__IO uint8_t *)data_reg) = *hxspi->pBuffPtr; 8005c08: 68fb ldr r3, [r7, #12] 8005c0a: 6c1b ldr r3, [r3, #64] @ 0x40 8005c0c: 781a ldrb r2, [r3, #0] 8005c0e: 697b ldr r3, [r7, #20] 8005c10: 701a strb r2, [r3, #0] hxspi->pBuffPtr++; 8005c12: 68fb ldr r3, [r7, #12] 8005c14: 6c1b ldr r3, [r3, #64] @ 0x40 8005c16: 1c5a adds r2, r3, #1 8005c18: 68fb ldr r3, [r7, #12] 8005c1a: 641a str r2, [r3, #64] @ 0x40 hxspi->XferCount--; 8005c1c: 68fb ldr r3, [r7, #12] 8005c1e: 6c9b ldr r3, [r3, #72] @ 0x48 8005c20: 1e5a subs r2, r3, #1 8005c22: 68fb ldr r3, [r7, #12] 8005c24: 649a str r2, [r3, #72] @ 0x48 } while (hxspi->XferCount > 0U); 8005c26: 68fb ldr r3, [r7, #12] 8005c28: 6c9b ldr r3, [r3, #72] @ 0x48 8005c2a: 2b00 cmp r3, #0 8005c2c: d1df bne.n 8005bee 8005c2e: e000 b.n 8005c32 break; 8005c30: bf00 nop if (status == HAL_OK) 8005c32: 7ffb ldrb r3, [r7, #31] 8005c34: 2b00 cmp r3, #0 8005c36: d119 bne.n 8005c6c { /* Wait till transfer complete flag is set to go back in idle state */ status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, Timeout); 8005c38: 687b ldr r3, [r7, #4] 8005c3a: 9300 str r3, [sp, #0] 8005c3c: 69bb ldr r3, [r7, #24] 8005c3e: 2201 movs r2, #1 8005c40: 2102 movs r1, #2 8005c42: 68f8 ldr r0, [r7, #12] 8005c44: f000 ffdf bl 8006c06 8005c48: 4603 mov r3, r0 8005c4a: 77fb strb r3, [r7, #31] if (status == HAL_OK) 8005c4c: 7ffb ldrb r3, [r7, #31] 8005c4e: 2b00 cmp r3, #0 8005c50: d10c bne.n 8005c6c { /* Clear transfer complete flag */ HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); 8005c52: 68fb ldr r3, [r7, #12] 8005c54: 681b ldr r3, [r3, #0] 8005c56: 2202 movs r2, #2 8005c58: 625a str r2, [r3, #36] @ 0x24 hxspi->State = HAL_XSPI_STATE_READY; 8005c5a: 68fb ldr r3, [r7, #12] 8005c5c: 2202 movs r2, #2 8005c5e: 655a str r2, [r3, #84] @ 0x54 8005c60: e004 b.n 8005c6c } } } else { status = HAL_ERROR; 8005c62: 2301 movs r3, #1 8005c64: 77fb strb r3, [r7, #31] hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; 8005c66: 68fb ldr r3, [r7, #12] 8005c68: 2210 movs r2, #16 8005c6a: 659a str r2, [r3, #88] @ 0x58 } } return status; 8005c6c: 7ffb ldrb r3, [r7, #31] } 8005c6e: 4618 mov r0, r3 8005c70: 3720 adds r7, #32 8005c72: 46bd mov sp, r7 8005c74: bd80 pop {r7, pc} 08005c76 : * @param Timeout : Timeout duration * @note This function is used only in Indirect Read Mode * @retval HAL status */ HAL_StatusTypeDef HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *pData, uint32_t Timeout) { 8005c76: b580 push {r7, lr} 8005c78: b08c sub sp, #48 @ 0x30 8005c7a: af02 add r7, sp, #8 8005c7c: 60f8 str r0, [r7, #12] 8005c7e: 60b9 str r1, [r7, #8] 8005c80: 607a str r2, [r7, #4] HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); 8005c82: f7fb f835 bl 8000cf0 8005c86: 6238 str r0, [r7, #32] __IO uint32_t *data_reg = &hxspi->Instance->DR; 8005c88: 68fb ldr r3, [r7, #12] 8005c8a: 681b ldr r3, [r3, #0] 8005c8c: 3350 adds r3, #80 @ 0x50 8005c8e: 61fb str r3, [r7, #28] uint32_t addr_reg = hxspi->Instance->AR; 8005c90: 68fb ldr r3, [r7, #12] 8005c92: 681b ldr r3, [r3, #0] 8005c94: 6c9b ldr r3, [r3, #72] @ 0x48 8005c96: 61bb str r3, [r7, #24] uint32_t ir_reg = hxspi->Instance->IR; 8005c98: 68fb ldr r3, [r7, #12] 8005c9a: 681b ldr r3, [r3, #0] 8005c9c: f8d3 3110 ldr.w r3, [r3, #272] @ 0x110 8005ca0: 617b str r3, [r7, #20] /* Check the data pointer allocation */ if (pData == NULL) 8005ca2: 68bb ldr r3, [r7, #8] 8005ca4: 2b00 cmp r3, #0 8005ca6: d106 bne.n 8005cb6 { status = HAL_ERROR; 8005ca8: 2301 movs r3, #1 8005caa: f887 3027 strb.w r3, [r7, #39] @ 0x27 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; 8005cae: 68fb ldr r3, [r7, #12] 8005cb0: 2208 movs r2, #8 8005cb2: 659a str r2, [r3, #88] @ 0x58 8005cb4: e07c b.n 8005db0 } else { /* Check the state */ if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) 8005cb6: 68fb ldr r3, [r7, #12] 8005cb8: 6d5b ldr r3, [r3, #84] @ 0x54 8005cba: 2b04 cmp r3, #4 8005cbc: d172 bne.n 8005da4 { /* Configure counters and size */ hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; 8005cbe: 68fb ldr r3, [r7, #12] 8005cc0: 681b ldr r3, [r3, #0] 8005cc2: 6c1b ldr r3, [r3, #64] @ 0x40 8005cc4: 1c5a adds r2, r3, #1 8005cc6: 68fb ldr r3, [r7, #12] 8005cc8: 649a str r2, [r3, #72] @ 0x48 hxspi->XferSize = hxspi->XferCount; 8005cca: 68fb ldr r3, [r7, #12] 8005ccc: 6c9a ldr r2, [r3, #72] @ 0x48 8005cce: 68fb ldr r3, [r7, #12] 8005cd0: 645a str r2, [r3, #68] @ 0x44 hxspi->pBuffPtr = pData; 8005cd2: 68fb ldr r3, [r7, #12] 8005cd4: 68ba ldr r2, [r7, #8] 8005cd6: 641a str r2, [r3, #64] @ 0x40 /* Configure CR register with functional mode as indirect read */ MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_READ); 8005cd8: 68fb ldr r3, [r7, #12] 8005cda: 681b ldr r3, [r3, #0] 8005cdc: 681b ldr r3, [r3, #0] 8005cde: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000 8005ce2: 68fb ldr r3, [r7, #12] 8005ce4: 681b ldr r3, [r3, #0] 8005ce6: f042 5280 orr.w r2, r2, #268435456 @ 0x10000000 8005cea: 601a str r2, [r3, #0] /* Trig the transfer by re-writing address or instruction register */ if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) 8005cec: 68fb ldr r3, [r7, #12] 8005cee: 68db ldr r3, [r3, #12] 8005cf0: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 8005cf4: d104 bne.n 8005d00 { WRITE_REG(hxspi->Instance->AR, addr_reg); 8005cf6: 68fb ldr r3, [r7, #12] 8005cf8: 681b ldr r3, [r3, #0] 8005cfa: 69ba ldr r2, [r7, #24] 8005cfc: 649a str r2, [r3, #72] @ 0x48 8005cfe: e011 b.n 8005d24 } else { if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) 8005d00: 68fb ldr r3, [r7, #12] 8005d02: 681b ldr r3, [r3, #0] 8005d04: f8d3 3100 ldr.w r3, [r3, #256] @ 0x100 8005d08: f403 63e0 and.w r3, r3, #1792 @ 0x700 8005d0c: 2b00 cmp r3, #0 8005d0e: d004 beq.n 8005d1a { WRITE_REG(hxspi->Instance->AR, addr_reg); 8005d10: 68fb ldr r3, [r7, #12] 8005d12: 681b ldr r3, [r3, #0] 8005d14: 69ba ldr r2, [r7, #24] 8005d16: 649a str r2, [r3, #72] @ 0x48 8005d18: e004 b.n 8005d24 } else { WRITE_REG(hxspi->Instance->IR, ir_reg); 8005d1a: 68fb ldr r3, [r7, #12] 8005d1c: 681b ldr r3, [r3, #0] 8005d1e: 697a ldr r2, [r7, #20] 8005d20: f8c3 2110 str.w r2, [r3, #272] @ 0x110 } do { /* Wait till fifo threshold or transfer complete flags are set to read received data */ status = XSPI_WaitFlagStateUntilTimeout(hxspi, (HAL_XSPI_FLAG_FT | HAL_XSPI_FLAG_TC), SET, tickstart, Timeout); 8005d24: 687b ldr r3, [r7, #4] 8005d26: 9300 str r3, [sp, #0] 8005d28: 6a3b ldr r3, [r7, #32] 8005d2a: 2201 movs r2, #1 8005d2c: 2106 movs r1, #6 8005d2e: 68f8 ldr r0, [r7, #12] 8005d30: f000 ff69 bl 8006c06 8005d34: 4603 mov r3, r0 8005d36: f887 3027 strb.w r3, [r7, #39] @ 0x27 if (status != HAL_OK) 8005d3a: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 8005d3e: 2b00 cmp r3, #0 8005d40: d114 bne.n 8005d6c { break; } *hxspi->pBuffPtr = *((__IO uint8_t *)data_reg); 8005d42: 68fb ldr r3, [r7, #12] 8005d44: 6c1b ldr r3, [r3, #64] @ 0x40 8005d46: 69fa ldr r2, [r7, #28] 8005d48: 7812 ldrb r2, [r2, #0] 8005d4a: b2d2 uxtb r2, r2 8005d4c: 701a strb r2, [r3, #0] hxspi->pBuffPtr++; 8005d4e: 68fb ldr r3, [r7, #12] 8005d50: 6c1b ldr r3, [r3, #64] @ 0x40 8005d52: 1c5a adds r2, r3, #1 8005d54: 68fb ldr r3, [r7, #12] 8005d56: 641a str r2, [r3, #64] @ 0x40 hxspi->XferCount--; 8005d58: 68fb ldr r3, [r7, #12] 8005d5a: 6c9b ldr r3, [r3, #72] @ 0x48 8005d5c: 1e5a subs r2, r3, #1 8005d5e: 68fb ldr r3, [r7, #12] 8005d60: 649a str r2, [r3, #72] @ 0x48 } while (hxspi->XferCount > 0U); 8005d62: 68fb ldr r3, [r7, #12] 8005d64: 6c9b ldr r3, [r3, #72] @ 0x48 8005d66: 2b00 cmp r3, #0 8005d68: d1dc bne.n 8005d24 8005d6a: e000 b.n 8005d6e break; 8005d6c: bf00 nop if (status == HAL_OK) 8005d6e: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 8005d72: 2b00 cmp r3, #0 8005d74: d11c bne.n 8005db0 { /* Wait till transfer complete flag is set to go back in idle state */ status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, Timeout); 8005d76: 687b ldr r3, [r7, #4] 8005d78: 9300 str r3, [sp, #0] 8005d7a: 6a3b ldr r3, [r7, #32] 8005d7c: 2201 movs r2, #1 8005d7e: 2102 movs r1, #2 8005d80: 68f8 ldr r0, [r7, #12] 8005d82: f000 ff40 bl 8006c06 8005d86: 4603 mov r3, r0 8005d88: f887 3027 strb.w r3, [r7, #39] @ 0x27 if (status == HAL_OK) 8005d8c: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 8005d90: 2b00 cmp r3, #0 8005d92: d10d bne.n 8005db0 { /* Clear transfer complete flag */ HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); 8005d94: 68fb ldr r3, [r7, #12] 8005d96: 681b ldr r3, [r3, #0] 8005d98: 2202 movs r2, #2 8005d9a: 625a str r2, [r3, #36] @ 0x24 hxspi->State = HAL_XSPI_STATE_READY; 8005d9c: 68fb ldr r3, [r7, #12] 8005d9e: 2202 movs r2, #2 8005da0: 655a str r2, [r3, #84] @ 0x54 8005da2: e005 b.n 8005db0 } } } else { status = HAL_ERROR; 8005da4: 2301 movs r3, #1 8005da6: f887 3027 strb.w r3, [r7, #39] @ 0x27 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; 8005daa: 68fb ldr r3, [r7, #12] 8005dac: 2210 movs r2, #16 8005dae: 659a str r2, [r3, #88] @ 0x58 } } return status; 8005db0: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 } 8005db4: 4618 mov r0, r3 8005db6: 3728 adds r7, #40 @ 0x28 8005db8: 46bd mov sp, r7 8005dba: bd80 pop {r7, pc} 08005dbc : * @note If DMA peripheral access is configured as word, the number * of data and the fifo threshold should be aligned on word * @retval HAL status */ HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, const uint8_t *pData) { 8005dbc: b580 push {r7, lr} 8005dbe: b086 sub sp, #24 8005dc0: af00 add r7, sp, #0 8005dc2: 6078 str r0, [r7, #4] 8005dc4: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8005dc6: 2300 movs r3, #0 8005dc8: 75fb strb r3, [r7, #23] uint32_t data_size = hxspi->Instance->DLR + 1U; 8005dca: 687b ldr r3, [r7, #4] 8005dcc: 681b ldr r3, [r3, #0] 8005dce: 6c1b ldr r3, [r3, #64] @ 0x40 8005dd0: 3301 adds r3, #1 8005dd2: 60bb str r3, [r7, #8] DMA_QListTypeDef *p_queue = {NULL}; 8005dd4: 2300 movs r3, #0 8005dd6: 613b str r3, [r7, #16] uint32_t data_width = DMA_DEST_DATAWIDTH_BYTE; 8005dd8: 2300 movs r3, #0 8005dda: 60fb str r3, [r7, #12] /* Check the data pointer allocation */ if (pData == NULL) 8005ddc: 683b ldr r3, [r7, #0] 8005dde: 2b00 cmp r3, #0 8005de0: d105 bne.n 8005dee { status = HAL_ERROR; 8005de2: 2301 movs r3, #1 8005de4: 75fb strb r3, [r7, #23] hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; 8005de6: 687b ldr r3, [r7, #4] 8005de8: 2208 movs r2, #8 8005dea: 659a str r2, [r3, #88] @ 0x58 8005dec: e10d b.n 800600a } else { /* Check the state */ if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) 8005dee: 687b ldr r3, [r7, #4] 8005df0: 6d5b ldr r3, [r3, #84] @ 0x54 8005df2: 2b04 cmp r3, #4 8005df4: f040 8104 bne.w 8006000 { if ((hxspi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) 8005df8: 687b ldr r3, [r7, #4] 8005dfa: 6cdb ldr r3, [r3, #76] @ 0x4c 8005dfc: 6d1b ldr r3, [r3, #80] @ 0x50 8005dfe: f003 0380 and.w r3, r3, #128 @ 0x80 8005e02: 2b00 cmp r3, #0 8005e04: d017 beq.n 8005e36 { p_queue = hxspi->hdmatx->LinkedListQueue; 8005e06: 687b ldr r3, [r7, #4] 8005e08: 6cdb ldr r3, [r3, #76] @ 0x4c 8005e0a: 6f5b ldr r3, [r3, #116] @ 0x74 8005e0c: 613b str r3, [r7, #16] if ((p_queue != NULL) && (p_queue->Head != NULL)) 8005e0e: 693b ldr r3, [r7, #16] 8005e10: 2b00 cmp r3, #0 8005e12: d00a beq.n 8005e2a 8005e14: 693b ldr r3, [r7, #16] 8005e16: 681b ldr r3, [r3, #0] 8005e18: 2b00 cmp r3, #0 8005e1a: d006 beq.n 8005e2a { data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; 8005e1c: 693b ldr r3, [r7, #16] 8005e1e: 681b ldr r3, [r3, #0] 8005e20: 681b ldr r3, [r3, #0] 8005e22: f403 3340 and.w r3, r3, #196608 @ 0x30000 8005e26: 60fb str r3, [r7, #12] 8005e28: e009 b.n 8005e3e } else { /* Set Error Code function status */ hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; 8005e2a: 687b ldr r3, [r7, #4] 8005e2c: 2204 movs r2, #4 8005e2e: 659a str r2, [r3, #88] @ 0x58 /* Return function status */ status = HAL_ERROR; 8005e30: 2301 movs r3, #1 8005e32: 75fb strb r3, [r7, #23] 8005e34: e003 b.n 8005e3e } } else { data_width = hxspi->hdmatx->Init.DestDataWidth; 8005e36: 687b ldr r3, [r7, #4] 8005e38: 6cdb ldr r3, [r3, #76] @ 0x4c 8005e3a: 69db ldr r3, [r3, #28] 8005e3c: 60fb str r3, [r7, #12] } /* Configure counters and size */ if (data_width == DMA_DEST_DATAWIDTH_BYTE) 8005e3e: 68fb ldr r3, [r7, #12] 8005e40: 2b00 cmp r3, #0 8005e42: d103 bne.n 8005e4c { hxspi->XferCount = data_size; 8005e44: 687b ldr r3, [r7, #4] 8005e46: 68ba ldr r2, [r7, #8] 8005e48: 649a str r2, [r3, #72] @ 0x48 8005e4a: e030 b.n 8005eae } else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD) 8005e4c: 68fb ldr r3, [r7, #12] 8005e4e: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8005e52: d114 bne.n 8005e7e { if (((data_size % 2U) != 0U) || ((hxspi->Init.FifoThresholdByte % 2U) != 0U)) 8005e54: 68bb ldr r3, [r7, #8] 8005e56: f003 0301 and.w r3, r3, #1 8005e5a: 2b00 cmp r3, #0 8005e5c: d105 bne.n 8005e6a 8005e5e: 687b ldr r3, [r7, #4] 8005e60: 685b ldr r3, [r3, #4] 8005e62: f003 0301 and.w r3, r3, #1 8005e66: 2b00 cmp r3, #0 8005e68: d005 beq.n 8005e76 { /* The number of data or the fifo threshold is not aligned on halfword => no transfer possible with DMA peripheral access configured as halfword */ hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; 8005e6a: 687b ldr r3, [r7, #4] 8005e6c: 2208 movs r2, #8 8005e6e: 659a str r2, [r3, #88] @ 0x58 status = HAL_ERROR; 8005e70: 2301 movs r3, #1 8005e72: 75fb strb r3, [r7, #23] 8005e74: e01b b.n 8005eae } else { hxspi->XferCount = data_size; 8005e76: 687b ldr r3, [r7, #4] 8005e78: 68ba ldr r2, [r7, #8] 8005e7a: 649a str r2, [r3, #72] @ 0x48 8005e7c: e017 b.n 8005eae } } else if (data_width == DMA_DEST_DATAWIDTH_WORD) 8005e7e: 68fb ldr r3, [r7, #12] 8005e80: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8005e84: d113 bne.n 8005eae { if (((data_size % 4U) != 0U) || ((hxspi->Init.FifoThresholdByte % 4U) != 0U)) 8005e86: 68bb ldr r3, [r7, #8] 8005e88: f003 0303 and.w r3, r3, #3 8005e8c: 2b00 cmp r3, #0 8005e8e: d105 bne.n 8005e9c 8005e90: 687b ldr r3, [r7, #4] 8005e92: 685b ldr r3, [r3, #4] 8005e94: f003 0303 and.w r3, r3, #3 8005e98: 2b00 cmp r3, #0 8005e9a: d005 beq.n 8005ea8 { /* The number of data or the fifo threshold is not aligned on word => no transfer possible with DMA peripheral access configured as word */ hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; 8005e9c: 687b ldr r3, [r7, #4] 8005e9e: 2208 movs r2, #8 8005ea0: 659a str r2, [r3, #88] @ 0x58 status = HAL_ERROR; 8005ea2: 2301 movs r3, #1 8005ea4: 75fb strb r3, [r7, #23] 8005ea6: e002 b.n 8005eae } else { hxspi->XferCount = data_size; 8005ea8: 687b ldr r3, [r7, #4] 8005eaa: 68ba ldr r2, [r7, #8] 8005eac: 649a str r2, [r3, #72] @ 0x48 else { /* Nothing to do */ } if (status == HAL_OK) 8005eae: 7dfb ldrb r3, [r7, #23] 8005eb0: 2b00 cmp r3, #0 8005eb2: f040 80aa bne.w 800600a { hxspi->XferSize = hxspi->XferCount; 8005eb6: 687b ldr r3, [r7, #4] 8005eb8: 6c9a ldr r2, [r3, #72] @ 0x48 8005eba: 687b ldr r3, [r7, #4] 8005ebc: 645a str r2, [r3, #68] @ 0x44 hxspi->pBuffPtr = (uint8_t *)pData; 8005ebe: 687b ldr r3, [r7, #4] 8005ec0: 683a ldr r2, [r7, #0] 8005ec2: 641a str r2, [r3, #64] @ 0x40 /* Configure CR register with functional mode as indirect write */ MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); 8005ec4: 687b ldr r3, [r7, #4] 8005ec6: 681b ldr r3, [r3, #0] 8005ec8: 681a ldr r2, [r3, #0] 8005eca: 687b ldr r3, [r7, #4] 8005ecc: 681b ldr r3, [r3, #0] 8005ece: f022 5240 bic.w r2, r2, #805306368 @ 0x30000000 8005ed2: 601a str r2, [r3, #0] /* Clear flags related to interrupt */ HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC); 8005ed4: 687b ldr r3, [r7, #4] 8005ed6: 681b ldr r3, [r3, #0] 8005ed8: 2203 movs r2, #3 8005eda: 625a str r2, [r3, #36] @ 0x24 /* Update the state */ hxspi->State = HAL_XSPI_STATE_BUSY_TX; 8005edc: 687b ldr r3, [r7, #4] 8005ede: 2218 movs r2, #24 8005ee0: 655a str r2, [r3, #84] @ 0x54 /* Set the DMA transfer complete callback */ hxspi->hdmatx->XferCpltCallback = XSPI_DMACplt; 8005ee2: 687b ldr r3, [r7, #4] 8005ee4: 6cdb ldr r3, [r3, #76] @ 0x4c 8005ee6: 4a4b ldr r2, [pc, #300] @ (8006014 ) 8005ee8: 661a str r2, [r3, #96] @ 0x60 /* Set the DMA Half transfer complete callback */ hxspi->hdmatx->XferHalfCpltCallback = XSPI_DMAHalfCplt; 8005eea: 687b ldr r3, [r7, #4] 8005eec: 6cdb ldr r3, [r3, #76] @ 0x4c 8005eee: 4a4a ldr r2, [pc, #296] @ (8006018 ) 8005ef0: 665a str r2, [r3, #100] @ 0x64 /* Set the DMA error callback */ hxspi->hdmatx->XferErrorCallback = XSPI_DMAError; 8005ef2: 687b ldr r3, [r7, #4] 8005ef4: 6cdb ldr r3, [r3, #76] @ 0x4c 8005ef6: 4a49 ldr r2, [pc, #292] @ (800601c ) 8005ef8: 669a str r2, [r3, #104] @ 0x68 /* Clear the DMA abort callback */ hxspi->hdmatx->XferAbortCallback = NULL; 8005efa: 687b ldr r3, [r7, #4] 8005efc: 6cdb ldr r3, [r3, #76] @ 0x4c 8005efe: 2200 movs r2, #0 8005f00: 66da str r2, [r3, #108] @ 0x6c /* Enable the transmit DMA Channel */ if ((hxspi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) 8005f02: 687b ldr r3, [r7, #4] 8005f04: 6cdb ldr r3, [r3, #76] @ 0x4c 8005f06: 6d1b ldr r3, [r3, #80] @ 0x50 8005f08: f003 0380 and.w r3, r3, #128 @ 0x80 8005f0c: 2b00 cmp r3, #0 8005f0e: d037 beq.n 8005f80 { if (hxspi->hdmatx->LinkedListQueue != NULL) 8005f10: 687b ldr r3, [r7, #4] 8005f12: 6cdb ldr r3, [r3, #76] @ 0x4c 8005f14: 6f5b ldr r3, [r3, #116] @ 0x74 8005f16: 2b00 cmp r3, #0 8005f18: d029 beq.n 8005f6e { /* Enable the DMA channel */ MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET], \ 8005f1a: 693b ldr r3, [r7, #16] 8005f1c: 681b ldr r3, [r3, #0] 8005f1e: 681b ldr r3, [r3, #0] 8005f20: f023 1208 bic.w r2, r3, #524296 @ 0x80008 8005f24: 693b ldr r3, [r7, #16] 8005f26: 681b ldr r3, [r3, #0] 8005f28: f042 0208 orr.w r2, r2, #8 8005f2c: 601a str r2, [r3, #0] (DMA_CTR1_SINC | DMA_CTR1_DINC), (DMA_SINC_INCREMENTED | DMA_DINC_FIXED)); MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET], \ 8005f2e: 693b ldr r3, [r7, #16] 8005f30: 681b ldr r3, [r3, #0] 8005f32: 685a ldr r2, [r3, #4] 8005f34: 693b ldr r3, [r7, #16] 8005f36: 681b ldr r3, [r3, #0] 8005f38: f442 6280 orr.w r2, r2, #1024 @ 0x400 8005f3c: 605a str r2, [r3, #4] DMA_CTR2_DREQ, DMA_MEMORY_TO_PERIPH); /* Set DMA data size*/ p_queue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hxspi->XferSize; 8005f3e: 693b ldr r3, [r7, #16] 8005f40: 681b ldr r3, [r3, #0] 8005f42: 687a ldr r2, [r7, #4] 8005f44: 6c52 ldr r2, [r2, #68] @ 0x44 8005f46: 609a str r2, [r3, #8] /* Set DMA source address */ p_queue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData; 8005f48: 693b ldr r3, [r7, #16] 8005f4a: 681b ldr r3, [r3, #0] 8005f4c: 683a ldr r2, [r7, #0] 8005f4e: 60da str r2, [r3, #12] /* Set DMA destination address */ p_queue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hxspi->Instance->DR; 8005f50: 687b ldr r3, [r7, #4] 8005f52: 681b ldr r3, [r3, #0] 8005f54: f103 0250 add.w r2, r3, #80 @ 0x50 8005f58: 693b ldr r3, [r7, #16] 8005f5a: 681b ldr r3, [r3, #0] 8005f5c: 611a str r2, [r3, #16] status = HAL_DMAEx_List_Start_IT(hxspi->hdmatx); 8005f5e: 687b ldr r3, [r7, #4] 8005f60: 6cdb ldr r3, [r3, #76] @ 0x4c 8005f62: 4618 mov r0, r3 8005f64: f7fb f928 bl 80011b8 8005f68: 4603 mov r3, r0 8005f6a: 75fb strb r3, [r7, #23] 8005f6c: e02b b.n 8005fc6 } else { /* Set Error Code */ hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; 8005f6e: 687b ldr r3, [r7, #4] 8005f70: 2204 movs r2, #4 8005f72: 659a str r2, [r3, #88] @ 0x58 hxspi->State = HAL_XSPI_STATE_READY; 8005f74: 687b ldr r3, [r7, #4] 8005f76: 2202 movs r2, #2 8005f78: 655a str r2, [r3, #84] @ 0x54 /* Return function status */ status = HAL_ERROR; 8005f7a: 2301 movs r3, #1 8005f7c: 75fb strb r3, [r7, #23] 8005f7e: e022 b.n 8005fc6 } } else { if ((hxspi->hdmatx->Init.Direction == DMA_MEMORY_TO_PERIPH) && 8005f80: 687b ldr r3, [r7, #4] 8005f82: 6cdb ldr r3, [r3, #76] @ 0x4c 8005f84: 68db ldr r3, [r3, #12] 8005f86: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8005f8a: d117 bne.n 8005fbc (hxspi->hdmatx->Init.SrcInc == DMA_SINC_INCREMENTED) && (hxspi->hdmatx->Init.DestInc == DMA_DINC_FIXED)) 8005f8c: 687b ldr r3, [r7, #4] 8005f8e: 6cdb ldr r3, [r3, #76] @ 0x4c 8005f90: 691b ldr r3, [r3, #16] if ((hxspi->hdmatx->Init.Direction == DMA_MEMORY_TO_PERIPH) && 8005f92: 2b08 cmp r3, #8 8005f94: d112 bne.n 8005fbc (hxspi->hdmatx->Init.SrcInc == DMA_SINC_INCREMENTED) && (hxspi->hdmatx->Init.DestInc == DMA_DINC_FIXED)) 8005f96: 687b ldr r3, [r7, #4] 8005f98: 6cdb ldr r3, [r3, #76] @ 0x4c 8005f9a: 695b ldr r3, [r3, #20] 8005f9c: 2b00 cmp r3, #0 8005f9e: d10d bne.n 8005fbc { status = HAL_DMA_Start_IT(hxspi->hdmatx, (uint32_t)pData, (uint32_t)&hxspi->Instance->DR, hxspi->XferSize); 8005fa0: 687b ldr r3, [r7, #4] 8005fa2: 6cd8 ldr r0, [r3, #76] @ 0x4c 8005fa4: 6839 ldr r1, [r7, #0] 8005fa6: 687b ldr r3, [r7, #4] 8005fa8: 681b ldr r3, [r3, #0] 8005faa: 3350 adds r3, #80 @ 0x50 8005fac: 461a mov r2, r3 8005fae: 687b ldr r3, [r7, #4] 8005fb0: 6c5b ldr r3, [r3, #68] @ 0x44 8005fb2: f7fa ffd4 bl 8000f5e 8005fb6: 4603 mov r3, r0 8005fb8: 75fb strb r3, [r7, #23] 8005fba: e004 b.n 8005fc6 } else { /* no transmit possible with DMA peripheral, invalid configuration */ hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; 8005fbc: 687b ldr r3, [r7, #4] 8005fbe: 2208 movs r2, #8 8005fc0: 659a str r2, [r3, #88] @ 0x58 status = HAL_ERROR; 8005fc2: 2301 movs r3, #1 8005fc4: 75fb strb r3, [r7, #23] } } if (status == HAL_OK) 8005fc6: 7dfb ldrb r3, [r7, #23] 8005fc8: 2b00 cmp r3, #0 8005fca: d110 bne.n 8005fee { /* Enable the transfer error interrupt */ HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TE); 8005fcc: 687b ldr r3, [r7, #4] 8005fce: 681b ldr r3, [r3, #0] 8005fd0: 681a ldr r2, [r3, #0] 8005fd2: 687b ldr r3, [r7, #4] 8005fd4: 681b ldr r3, [r3, #0] 8005fd6: f442 3280 orr.w r2, r2, #65536 @ 0x10000 8005fda: 601a str r2, [r3, #0] /* Enable the DMA transfer by setting the DMAEN bit */ SET_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); 8005fdc: 687b ldr r3, [r7, #4] 8005fde: 681b ldr r3, [r3, #0] 8005fe0: 681a ldr r2, [r3, #0] 8005fe2: 687b ldr r3, [r7, #4] 8005fe4: 681b ldr r3, [r3, #0] 8005fe6: f042 0204 orr.w r2, r2, #4 8005fea: 601a str r2, [r3, #0] 8005fec: e00d b.n 800600a } else { status = HAL_ERROR; 8005fee: 2301 movs r3, #1 8005ff0: 75fb strb r3, [r7, #23] hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; 8005ff2: 687b ldr r3, [r7, #4] 8005ff4: 2204 movs r2, #4 8005ff6: 659a str r2, [r3, #88] @ 0x58 hxspi->State = HAL_XSPI_STATE_READY; 8005ff8: 687b ldr r3, [r7, #4] 8005ffa: 2202 movs r2, #2 8005ffc: 655a str r2, [r3, #84] @ 0x54 8005ffe: e004 b.n 800600a } } } else { status = HAL_ERROR; 8006000: 2301 movs r3, #1 8006002: 75fb strb r3, [r7, #23] hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; 8006004: 687b ldr r3, [r7, #4] 8006006: 2210 movs r2, #16 8006008: 659a str r2, [r3, #88] @ 0x58 } } return status; 800600a: 7dfb ldrb r3, [r7, #23] } 800600c: 4618 mov r0, r3 800600e: 3718 adds r7, #24 8006010: 46bd mov sp, r7 8006012: bd80 pop {r7, pc} 8006014: 08006ab5 .word 0x08006ab5 8006018: 08006af5 .word 0x08006af5 800601c: 08006b2f .word 0x08006b2f 08006020 : * @note If DMA peripheral access is configured as word, the number * of data and the fifo threshold should be aligned on word * @retval HAL status */ HAL_StatusTypeDef HAL_XSPI_Receive_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *pData) { 8006020: b580 push {r7, lr} 8006022: b088 sub sp, #32 8006024: af00 add r7, sp, #0 8006026: 6078 str r0, [r7, #4] 8006028: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 800602a: 2300 movs r3, #0 800602c: 77fb strb r3, [r7, #31] uint32_t data_size = hxspi->Instance->DLR + 1U; 800602e: 687b ldr r3, [r7, #4] 8006030: 681b ldr r3, [r3, #0] 8006032: 6c1b ldr r3, [r3, #64] @ 0x40 8006034: 3301 adds r3, #1 8006036: 613b str r3, [r7, #16] uint32_t addr_reg = hxspi->Instance->AR; 8006038: 687b ldr r3, [r7, #4] 800603a: 681b ldr r3, [r3, #0] 800603c: 6c9b ldr r3, [r3, #72] @ 0x48 800603e: 60fb str r3, [r7, #12] uint32_t ir_reg = hxspi->Instance->IR; 8006040: 687b ldr r3, [r7, #4] 8006042: 681b ldr r3, [r3, #0] 8006044: f8d3 3110 ldr.w r3, [r3, #272] @ 0x110 8006048: 60bb str r3, [r7, #8] DMA_QListTypeDef *p_queue = {NULL}; 800604a: 2300 movs r3, #0 800604c: 61bb str r3, [r7, #24] uint32_t data_width = DMA_DEST_DATAWIDTH_BYTE; 800604e: 2300 movs r3, #0 8006050: 617b str r3, [r7, #20] /* Check the data pointer allocation */ if (pData == NULL) 8006052: 683b ldr r3, [r7, #0] 8006054: 2b00 cmp r3, #0 8006056: d105 bne.n 8006064 { status = HAL_ERROR; 8006058: 2301 movs r3, #1 800605a: 77fb strb r3, [r7, #31] hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; 800605c: 687b ldr r3, [r7, #4] 800605e: 2208 movs r2, #8 8006060: 659a str r2, [r3, #88] @ 0x58 8006062: e12b b.n 80062bc } else { /* Check the state */ if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) 8006064: 687b ldr r3, [r7, #4] 8006066: 6d5b ldr r3, [r3, #84] @ 0x54 8006068: 2b04 cmp r3, #4 800606a: f040 8122 bne.w 80062b2 { if ((hxspi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) 800606e: 687b ldr r3, [r7, #4] 8006070: 6d1b ldr r3, [r3, #80] @ 0x50 8006072: 6d1b ldr r3, [r3, #80] @ 0x50 8006074: f003 0380 and.w r3, r3, #128 @ 0x80 8006078: 2b00 cmp r3, #0 800607a: d017 beq.n 80060ac { p_queue = hxspi->hdmarx->LinkedListQueue; 800607c: 687b ldr r3, [r7, #4] 800607e: 6d1b ldr r3, [r3, #80] @ 0x50 8006080: 6f5b ldr r3, [r3, #116] @ 0x74 8006082: 61bb str r3, [r7, #24] if ((p_queue != NULL) && (p_queue->Head != NULL)) 8006084: 69bb ldr r3, [r7, #24] 8006086: 2b00 cmp r3, #0 8006088: d00a beq.n 80060a0 800608a: 69bb ldr r3, [r7, #24] 800608c: 681b ldr r3, [r3, #0] 800608e: 2b00 cmp r3, #0 8006090: d006 beq.n 80060a0 { data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; 8006092: 69bb ldr r3, [r7, #24] 8006094: 681b ldr r3, [r3, #0] 8006096: 681b ldr r3, [r3, #0] 8006098: f403 3340 and.w r3, r3, #196608 @ 0x30000 800609c: 617b str r3, [r7, #20] 800609e: e009 b.n 80060b4 } else { /* Set Error Code */ hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; 80060a0: 687b ldr r3, [r7, #4] 80060a2: 2204 movs r2, #4 80060a4: 659a str r2, [r3, #88] @ 0x58 /* Return function status */ status = HAL_ERROR; 80060a6: 2301 movs r3, #1 80060a8: 77fb strb r3, [r7, #31] 80060aa: e003 b.n 80060b4 } } else { data_width = hxspi->hdmarx->Init.DestDataWidth; 80060ac: 687b ldr r3, [r7, #4] 80060ae: 6d1b ldr r3, [r3, #80] @ 0x50 80060b0: 69db ldr r3, [r3, #28] 80060b2: 617b str r3, [r7, #20] } /* Configure counters and size */ if (data_width == DMA_DEST_DATAWIDTH_BYTE) 80060b4: 697b ldr r3, [r7, #20] 80060b6: 2b00 cmp r3, #0 80060b8: d103 bne.n 80060c2 { hxspi->XferCount = data_size; 80060ba: 687b ldr r3, [r7, #4] 80060bc: 693a ldr r2, [r7, #16] 80060be: 649a str r2, [r3, #72] @ 0x48 80060c0: e030 b.n 8006124 } else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD) 80060c2: 697b ldr r3, [r7, #20] 80060c4: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80060c8: d114 bne.n 80060f4 { if (((data_size % 2U) != 0U) || ((hxspi->Init.FifoThresholdByte % 2U) != 0U)) 80060ca: 693b ldr r3, [r7, #16] 80060cc: f003 0301 and.w r3, r3, #1 80060d0: 2b00 cmp r3, #0 80060d2: d105 bne.n 80060e0 80060d4: 687b ldr r3, [r7, #4] 80060d6: 685b ldr r3, [r3, #4] 80060d8: f003 0301 and.w r3, r3, #1 80060dc: 2b00 cmp r3, #0 80060de: d005 beq.n 80060ec { /* The number of data or the fifo threshold is not aligned on halfword => no transfer possible with DMA peripheral access configured as halfword */ hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; 80060e0: 687b ldr r3, [r7, #4] 80060e2: 2208 movs r2, #8 80060e4: 659a str r2, [r3, #88] @ 0x58 status = HAL_ERROR; 80060e6: 2301 movs r3, #1 80060e8: 77fb strb r3, [r7, #31] 80060ea: e01b b.n 8006124 } else { hxspi->XferCount = data_size; 80060ec: 687b ldr r3, [r7, #4] 80060ee: 693a ldr r2, [r7, #16] 80060f0: 649a str r2, [r3, #72] @ 0x48 80060f2: e017 b.n 8006124 } } else if (data_width == DMA_DEST_DATAWIDTH_WORD) 80060f4: 697b ldr r3, [r7, #20] 80060f6: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 80060fa: d113 bne.n 8006124 { if (((data_size % 4U) != 0U) || ((hxspi->Init.FifoThresholdByte % 4U) != 0U)) 80060fc: 693b ldr r3, [r7, #16] 80060fe: f003 0303 and.w r3, r3, #3 8006102: 2b00 cmp r3, #0 8006104: d105 bne.n 8006112 8006106: 687b ldr r3, [r7, #4] 8006108: 685b ldr r3, [r3, #4] 800610a: f003 0303 and.w r3, r3, #3 800610e: 2b00 cmp r3, #0 8006110: d005 beq.n 800611e { /* The number of data or the fifo threshold is not aligned on word => no transfer possible with DMA peripheral access configured as word */ hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; 8006112: 687b ldr r3, [r7, #4] 8006114: 2208 movs r2, #8 8006116: 659a str r2, [r3, #88] @ 0x58 status = HAL_ERROR; 8006118: 2301 movs r3, #1 800611a: 77fb strb r3, [r7, #31] 800611c: e002 b.n 8006124 } else { hxspi->XferCount = data_size; 800611e: 687b ldr r3, [r7, #4] 8006120: 693a ldr r2, [r7, #16] 8006122: 649a str r2, [r3, #72] @ 0x48 else { /* Nothing to do */ } if (status == HAL_OK) 8006124: 7ffb ldrb r3, [r7, #31] 8006126: 2b00 cmp r3, #0 8006128: f040 80c8 bne.w 80062bc { hxspi->XferSize = hxspi->XferCount; 800612c: 687b ldr r3, [r7, #4] 800612e: 6c9a ldr r2, [r3, #72] @ 0x48 8006130: 687b ldr r3, [r7, #4] 8006132: 645a str r2, [r3, #68] @ 0x44 hxspi->pBuffPtr = pData; 8006134: 687b ldr r3, [r7, #4] 8006136: 683a ldr r2, [r7, #0] 8006138: 641a str r2, [r3, #64] @ 0x40 /* Configure CR register with functional mode as indirect read */ MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_READ); 800613a: 687b ldr r3, [r7, #4] 800613c: 681b ldr r3, [r3, #0] 800613e: 681b ldr r3, [r3, #0] 8006140: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000 8006144: 687b ldr r3, [r7, #4] 8006146: 681b ldr r3, [r3, #0] 8006148: f042 5280 orr.w r2, r2, #268435456 @ 0x10000000 800614c: 601a str r2, [r3, #0] /* Clear flags related to interrupt */ HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC); 800614e: 687b ldr r3, [r7, #4] 8006150: 681b ldr r3, [r3, #0] 8006152: 2203 movs r2, #3 8006154: 625a str r2, [r3, #36] @ 0x24 /* Update the state */ hxspi->State = HAL_XSPI_STATE_BUSY_RX; 8006156: 687b ldr r3, [r7, #4] 8006158: 2228 movs r2, #40 @ 0x28 800615a: 655a str r2, [r3, #84] @ 0x54 /* Set the DMA transfer complete callback */ hxspi->hdmarx->XferCpltCallback = XSPI_DMACplt; 800615c: 687b ldr r3, [r7, #4] 800615e: 6d1b ldr r3, [r3, #80] @ 0x50 8006160: 4a59 ldr r2, [pc, #356] @ (80062c8 ) 8006162: 661a str r2, [r3, #96] @ 0x60 /* Set the DMA Half transfer complete callback */ hxspi->hdmarx->XferHalfCpltCallback = XSPI_DMAHalfCplt; 8006164: 687b ldr r3, [r7, #4] 8006166: 6d1b ldr r3, [r3, #80] @ 0x50 8006168: 4a58 ldr r2, [pc, #352] @ (80062cc ) 800616a: 665a str r2, [r3, #100] @ 0x64 /* Set the DMA error callback */ hxspi->hdmarx->XferErrorCallback = XSPI_DMAError; 800616c: 687b ldr r3, [r7, #4] 800616e: 6d1b ldr r3, [r3, #80] @ 0x50 8006170: 4a57 ldr r2, [pc, #348] @ (80062d0 ) 8006172: 669a str r2, [r3, #104] @ 0x68 /* Clear the DMA abort callback */ hxspi->hdmarx->XferAbortCallback = NULL; 8006174: 687b ldr r3, [r7, #4] 8006176: 6d1b ldr r3, [r3, #80] @ 0x50 8006178: 2200 movs r2, #0 800617a: 66da str r2, [r3, #108] @ 0x6c /* Enable the receive DMA Channel */ if ((hxspi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) 800617c: 687b ldr r3, [r7, #4] 800617e: 6d1b ldr r3, [r3, #80] @ 0x50 8006180: 6d1b ldr r3, [r3, #80] @ 0x50 8006182: f003 0380 and.w r3, r3, #128 @ 0x80 8006186: 2b00 cmp r3, #0 8006188: d037 beq.n 80061fa { if (hxspi->hdmarx->LinkedListQueue != NULL) 800618a: 687b ldr r3, [r7, #4] 800618c: 6d1b ldr r3, [r3, #80] @ 0x50 800618e: 6f5b ldr r3, [r3, #116] @ 0x74 8006190: 2b00 cmp r3, #0 8006192: d029 beq.n 80061e8 { /* Enable the DMA channel */ MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET], \ 8006194: 69bb ldr r3, [r7, #24] 8006196: 681b ldr r3, [r3, #0] 8006198: 681b ldr r3, [r3, #0] 800619a: f023 1208 bic.w r2, r3, #524296 @ 0x80008 800619e: 69bb ldr r3, [r7, #24] 80061a0: 681b ldr r3, [r3, #0] 80061a2: f442 2200 orr.w r2, r2, #524288 @ 0x80000 80061a6: 601a str r2, [r3, #0] (DMA_CTR1_SINC | DMA_CTR1_DINC), (DMA_SINC_FIXED | DMA_DINC_INCREMENTED)); MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET], \ 80061a8: 69bb ldr r3, [r7, #24] 80061aa: 681b ldr r3, [r3, #0] 80061ac: 685a ldr r2, [r3, #4] 80061ae: 69bb ldr r3, [r7, #24] 80061b0: 681b ldr r3, [r3, #0] 80061b2: f422 6280 bic.w r2, r2, #1024 @ 0x400 80061b6: 605a str r2, [r3, #4] DMA_CTR2_DREQ, DMA_PERIPH_TO_MEMORY); /* Set DMA data size */ p_queue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hxspi->XferSize; 80061b8: 69bb ldr r3, [r7, #24] 80061ba: 681b ldr r3, [r3, #0] 80061bc: 687a ldr r2, [r7, #4] 80061be: 6c52 ldr r2, [r2, #68] @ 0x44 80061c0: 609a str r2, [r3, #8] /* Set DMA source address */ p_queue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hxspi->Instance->DR; 80061c2: 687b ldr r3, [r7, #4] 80061c4: 681b ldr r3, [r3, #0] 80061c6: f103 0250 add.w r2, r3, #80 @ 0x50 80061ca: 69bb ldr r3, [r7, #24] 80061cc: 681b ldr r3, [r3, #0] 80061ce: 60da str r2, [r3, #12] /* Set DMA destination address */ p_queue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; 80061d0: 69bb ldr r3, [r7, #24] 80061d2: 681b ldr r3, [r3, #0] 80061d4: 683a ldr r2, [r7, #0] 80061d6: 611a str r2, [r3, #16] status = HAL_DMAEx_List_Start_IT(hxspi->hdmarx); 80061d8: 687b ldr r3, [r7, #4] 80061da: 6d1b ldr r3, [r3, #80] @ 0x50 80061dc: 4618 mov r0, r3 80061de: f7fa ffeb bl 80011b8 80061e2: 4603 mov r3, r0 80061e4: 77fb strb r3, [r7, #31] 80061e6: e02b b.n 8006240 } else { /* Set Error Code */ hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; 80061e8: 687b ldr r3, [r7, #4] 80061ea: 2204 movs r2, #4 80061ec: 659a str r2, [r3, #88] @ 0x58 hxspi->State = HAL_XSPI_STATE_READY; 80061ee: 687b ldr r3, [r7, #4] 80061f0: 2202 movs r2, #2 80061f2: 655a str r2, [r3, #84] @ 0x54 /* Return function status */ status = HAL_ERROR; 80061f4: 2301 movs r3, #1 80061f6: 77fb strb r3, [r7, #31] 80061f8: e022 b.n 8006240 } } else { if ((hxspi->hdmarx->Init.Direction == DMA_PERIPH_TO_MEMORY) && (hxspi->hdmarx->Init.SrcInc == DMA_SINC_FIXED) 80061fa: 687b ldr r3, [r7, #4] 80061fc: 6d1b ldr r3, [r3, #80] @ 0x50 80061fe: 68db ldr r3, [r3, #12] 8006200: 2b00 cmp r3, #0 8006202: d118 bne.n 8006236 8006204: 687b ldr r3, [r7, #4] 8006206: 6d1b ldr r3, [r3, #80] @ 0x50 8006208: 691b ldr r3, [r3, #16] 800620a: 2b00 cmp r3, #0 800620c: d113 bne.n 8006236 && (hxspi->hdmarx->Init.DestInc == DMA_DINC_INCREMENTED)) 800620e: 687b ldr r3, [r7, #4] 8006210: 6d1b ldr r3, [r3, #80] @ 0x50 8006212: 695b ldr r3, [r3, #20] 8006214: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 8006218: d10d bne.n 8006236 { status = HAL_DMA_Start_IT(hxspi->hdmarx, (uint32_t)&hxspi->Instance->DR, (uint32_t)pData, hxspi->XferSize); 800621a: 687b ldr r3, [r7, #4] 800621c: 6d18 ldr r0, [r3, #80] @ 0x50 800621e: 687b ldr r3, [r7, #4] 8006220: 681b ldr r3, [r3, #0] 8006222: 3350 adds r3, #80 @ 0x50 8006224: 4619 mov r1, r3 8006226: 683a ldr r2, [r7, #0] 8006228: 687b ldr r3, [r7, #4] 800622a: 6c5b ldr r3, [r3, #68] @ 0x44 800622c: f7fa fe97 bl 8000f5e 8006230: 4603 mov r3, r0 8006232: 77fb strb r3, [r7, #31] 8006234: e004 b.n 8006240 } else { /* no receive possible with DMA peripheral, invalid configuration */ hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; 8006236: 687b ldr r3, [r7, #4] 8006238: 2208 movs r2, #8 800623a: 659a str r2, [r3, #88] @ 0x58 status = HAL_ERROR; 800623c: 2301 movs r3, #1 800623e: 77fb strb r3, [r7, #31] } } if (status == HAL_OK) 8006240: 7ffb ldrb r3, [r7, #31] 8006242: 2b00 cmp r3, #0 8006244: d12c bne.n 80062a0 { /* Enable the transfer error interrupt */ HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TE); 8006246: 687b ldr r3, [r7, #4] 8006248: 681b ldr r3, [r3, #0] 800624a: 681a ldr r2, [r3, #0] 800624c: 687b ldr r3, [r7, #4] 800624e: 681b ldr r3, [r3, #0] 8006250: f442 3280 orr.w r2, r2, #65536 @ 0x10000 8006254: 601a str r2, [r3, #0] /* Trig the transfer by re-writing address or instruction register */ if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) 8006256: 687b ldr r3, [r7, #4] 8006258: 68db ldr r3, [r3, #12] 800625a: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800625e: d104 bne.n 800626a { WRITE_REG(hxspi->Instance->AR, addr_reg); 8006260: 687b ldr r3, [r7, #4] 8006262: 681b ldr r3, [r3, #0] 8006264: 68fa ldr r2, [r7, #12] 8006266: 649a str r2, [r3, #72] @ 0x48 8006268: e011 b.n 800628e } else { if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) 800626a: 687b ldr r3, [r7, #4] 800626c: 681b ldr r3, [r3, #0] 800626e: f8d3 3100 ldr.w r3, [r3, #256] @ 0x100 8006272: f403 63e0 and.w r3, r3, #1792 @ 0x700 8006276: 2b00 cmp r3, #0 8006278: d004 beq.n 8006284 { WRITE_REG(hxspi->Instance->AR, addr_reg); 800627a: 687b ldr r3, [r7, #4] 800627c: 681b ldr r3, [r3, #0] 800627e: 68fa ldr r2, [r7, #12] 8006280: 649a str r2, [r3, #72] @ 0x48 8006282: e004 b.n 800628e } else { WRITE_REG(hxspi->Instance->IR, ir_reg); 8006284: 687b ldr r3, [r7, #4] 8006286: 681b ldr r3, [r3, #0] 8006288: 68ba ldr r2, [r7, #8] 800628a: f8c3 2110 str.w r2, [r3, #272] @ 0x110 } } /* Enable the DMA transfer by setting the DMAEN bit */ SET_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); 800628e: 687b ldr r3, [r7, #4] 8006290: 681b ldr r3, [r3, #0] 8006292: 681a ldr r2, [r3, #0] 8006294: 687b ldr r3, [r7, #4] 8006296: 681b ldr r3, [r3, #0] 8006298: f042 0204 orr.w r2, r2, #4 800629c: 601a str r2, [r3, #0] 800629e: e00d b.n 80062bc } else { status = HAL_ERROR; 80062a0: 2301 movs r3, #1 80062a2: 77fb strb r3, [r7, #31] hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; 80062a4: 687b ldr r3, [r7, #4] 80062a6: 2204 movs r2, #4 80062a8: 659a str r2, [r3, #88] @ 0x58 hxspi->State = HAL_XSPI_STATE_READY; 80062aa: 687b ldr r3, [r7, #4] 80062ac: 2202 movs r2, #2 80062ae: 655a str r2, [r3, #84] @ 0x54 80062b0: e004 b.n 80062bc } } } else { status = HAL_ERROR; 80062b2: 2301 movs r3, #1 80062b4: 77fb strb r3, [r7, #31] hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; 80062b6: 687b ldr r3, [r7, #4] 80062b8: 2210 movs r2, #16 80062ba: 659a str r2, [r3, #88] @ 0x58 } } return status; 80062bc: 7ffb ldrb r3, [r7, #31] } 80062be: 4618 mov r0, r3 80062c0: 3720 adds r7, #32 80062c2: 46bd mov sp, r7 80062c4: bd80 pop {r7, pc} 80062c6: bf00 nop 80062c8: 08006ab5 .word 0x08006ab5 80062cc: 08006af5 .word 0x08006af5 80062d0: 08006b2f .word 0x08006b2f 080062d4 : * @note This function is used only in Automatic Polling Mode * @retval HAL status */ HAL_StatusTypeDef HAL_XSPI_AutoPolling(XSPI_HandleTypeDef *hxspi, const XSPI_AutoPollingTypeDef *pCfg, uint32_t Timeout) { 80062d4: b580 push {r7, lr} 80062d6: b08a sub sp, #40 @ 0x28 80062d8: af02 add r7, sp, #8 80062da: 60f8 str r0, [r7, #12] 80062dc: 60b9 str r1, [r7, #8] 80062de: 607a str r2, [r7, #4] HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); 80062e0: f7fa fd06 bl 8000cf0 80062e4: 61b8 str r0, [r7, #24] uint32_t addr_reg = hxspi->Instance->AR; 80062e6: 68fb ldr r3, [r7, #12] 80062e8: 681b ldr r3, [r3, #0] 80062ea: 6c9b ldr r3, [r3, #72] @ 0x48 80062ec: 617b str r3, [r7, #20] uint32_t ir_reg = hxspi->Instance->IR; 80062ee: 68fb ldr r3, [r7, #12] 80062f0: 681b ldr r3, [r3, #0] 80062f2: f8d3 3110 ldr.w r3, [r3, #272] @ 0x110 80062f6: 613b str r3, [r7, #16] assert_param(IS_XSPI_AUTOMATIC_STOP(pCfg->AutomaticStop)); assert_param(IS_XSPI_INTERVAL(pCfg->IntervalTime)); assert_param(IS_XSPI_STATUS_BYTES_SIZE(dlr_reg + 1U)); /* Check the state */ if ((hxspi->State == HAL_XSPI_STATE_CMD_CFG) && (pCfg->AutomaticStop == HAL_XSPI_AUTOMATIC_STOP_ENABLE)) 80062f8: 68fb ldr r3, [r7, #12] 80062fa: 6d5b ldr r3, [r3, #84] @ 0x54 80062fc: 2b04 cmp r3, #4 80062fe: d167 bne.n 80063d0 8006300: 68bb ldr r3, [r7, #8] 8006302: 68db ldr r3, [r3, #12] 8006304: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8006308: d162 bne.n 80063d0 { /* Wait till busy flag is reset */ status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); 800630a: 687b ldr r3, [r7, #4] 800630c: 9300 str r3, [sp, #0] 800630e: 69bb ldr r3, [r7, #24] 8006310: 2200 movs r2, #0 8006312: 2120 movs r1, #32 8006314: 68f8 ldr r0, [r7, #12] 8006316: f000 fc76 bl 8006c06 800631a: 4603 mov r3, r0 800631c: 77fb strb r3, [r7, #31] if (status == HAL_OK) 800631e: 7ffb ldrb r3, [r7, #31] 8006320: 2b00 cmp r3, #0 8006322: d152 bne.n 80063ca { /* Configure registers */ WRITE_REG(hxspi->Instance->PSMAR, pCfg->MatchValue); 8006324: 68fb ldr r3, [r7, #12] 8006326: 681b ldr r3, [r3, #0] 8006328: 68ba ldr r2, [r7, #8] 800632a: 6812 ldr r2, [r2, #0] 800632c: f8c3 2088 str.w r2, [r3, #136] @ 0x88 WRITE_REG(hxspi->Instance->PSMKR, pCfg->MatchMask); 8006330: 68fb ldr r3, [r7, #12] 8006332: 681b ldr r3, [r3, #0] 8006334: 68ba ldr r2, [r7, #8] 8006336: 6852 ldr r2, [r2, #4] 8006338: f8c3 2080 str.w r2, [r3, #128] @ 0x80 WRITE_REG(hxspi->Instance->PIR, pCfg->IntervalTime); 800633c: 68fb ldr r3, [r7, #12] 800633e: 681b ldr r3, [r3, #0] 8006340: 68ba ldr r2, [r7, #8] 8006342: 6912 ldr r2, [r2, #16] 8006344: f8c3 2090 str.w r2, [r3, #144] @ 0x90 MODIFY_REG(hxspi->Instance->CR, (XSPI_CR_PMM | XSPI_CR_APMS | XSPI_CR_FMODE), 8006348: 68fb ldr r3, [r7, #12] 800634a: 681b ldr r3, [r3, #0] 800634c: 681b ldr r3, [r3, #0] 800634e: f023 5243 bic.w r2, r3, #817889280 @ 0x30c00000 8006352: 68bb ldr r3, [r7, #8] 8006354: 6899 ldr r1, [r3, #8] 8006356: 68bb ldr r3, [r7, #8] 8006358: 68db ldr r3, [r3, #12] 800635a: 430b orrs r3, r1 800635c: 431a orrs r2, r3 800635e: 68fb ldr r3, [r7, #12] 8006360: 681b ldr r3, [r3, #0] 8006362: f042 5200 orr.w r2, r2, #536870912 @ 0x20000000 8006366: 601a str r2, [r3, #0] (pCfg->MatchMode | pCfg->AutomaticStop | XSPI_FUNCTIONAL_MODE_AUTO_POLLING)); /* Trig the transfer by re-writing address or instruction register */ if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) 8006368: 68fb ldr r3, [r7, #12] 800636a: 68db ldr r3, [r3, #12] 800636c: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 8006370: d104 bne.n 800637c { WRITE_REG(hxspi->Instance->AR, addr_reg); 8006372: 68fb ldr r3, [r7, #12] 8006374: 681b ldr r3, [r3, #0] 8006376: 697a ldr r2, [r7, #20] 8006378: 649a str r2, [r3, #72] @ 0x48 800637a: e011 b.n 80063a0 } else { if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) 800637c: 68fb ldr r3, [r7, #12] 800637e: 681b ldr r3, [r3, #0] 8006380: f8d3 3100 ldr.w r3, [r3, #256] @ 0x100 8006384: f403 63e0 and.w r3, r3, #1792 @ 0x700 8006388: 2b00 cmp r3, #0 800638a: d004 beq.n 8006396 { WRITE_REG(hxspi->Instance->AR, addr_reg); 800638c: 68fb ldr r3, [r7, #12] 800638e: 681b ldr r3, [r3, #0] 8006390: 697a ldr r2, [r7, #20] 8006392: 649a str r2, [r3, #72] @ 0x48 8006394: e004 b.n 80063a0 } else { WRITE_REG(hxspi->Instance->IR, ir_reg); 8006396: 68fb ldr r3, [r7, #12] 8006398: 681b ldr r3, [r3, #0] 800639a: 693a ldr r2, [r7, #16] 800639c: f8c3 2110 str.w r2, [r3, #272] @ 0x110 } } /* Wait till status match flag is set to go back in idle state */ status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_SM, SET, tickstart, Timeout); 80063a0: 687b ldr r3, [r7, #4] 80063a2: 9300 str r3, [sp, #0] 80063a4: 69bb ldr r3, [r7, #24] 80063a6: 2201 movs r2, #1 80063a8: 2108 movs r1, #8 80063aa: 68f8 ldr r0, [r7, #12] 80063ac: f000 fc2b bl 8006c06 80063b0: 4603 mov r3, r0 80063b2: 77fb strb r3, [r7, #31] if (status == HAL_OK) 80063b4: 7ffb ldrb r3, [r7, #31] 80063b6: 2b00 cmp r3, #0 80063b8: d110 bne.n 80063dc { /* Clear status match flag */ HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_SM); 80063ba: 68fb ldr r3, [r7, #12] 80063bc: 681b ldr r3, [r3, #0] 80063be: 2208 movs r2, #8 80063c0: 625a str r2, [r3, #36] @ 0x24 hxspi->State = HAL_XSPI_STATE_READY; 80063c2: 68fb ldr r3, [r7, #12] 80063c4: 2202 movs r2, #2 80063c6: 655a str r2, [r3, #84] @ 0x54 if (status == HAL_OK) 80063c8: e008 b.n 80063dc } } else { status = HAL_BUSY; 80063ca: 2302 movs r3, #2 80063cc: 77fb strb r3, [r7, #31] if (status == HAL_OK) 80063ce: e005 b.n 80063dc } } else { status = HAL_ERROR; 80063d0: 2301 movs r3, #1 80063d2: 77fb strb r3, [r7, #31] hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; 80063d4: 68fb ldr r3, [r7, #12] 80063d6: 2210 movs r2, #16 80063d8: 659a str r2, [r3, #88] @ 0x58 80063da: e000 b.n 80063de if (status == HAL_OK) 80063dc: bf00 nop } return status; 80063de: 7ffb ldrb r3, [r7, #31] } 80063e0: 4618 mov r0, r3 80063e2: 3720 adds r7, #32 80063e4: 46bd mov sp, r7 80063e6: bd80 pop {r7, pc} 080063e8 : * @param pCfg : Pointer to structure that contains the memory mapped configuration information. * @note This function is used only in Memory mapped Mode * @retval HAL status */ HAL_StatusTypeDef HAL_XSPI_MemoryMapped(XSPI_HandleTypeDef *hxspi, const XSPI_MemoryMappedTypeDef *pCfg) { 80063e8: b580 push {r7, lr} 80063ea: b086 sub sp, #24 80063ec: af02 add r7, sp, #8 80063ee: 6078 str r0, [r7, #4] 80063f0: 6039 str r1, [r7, #0] HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); 80063f2: f7fa fc7d bl 8000cf0 80063f6: 60b8 str r0, [r7, #8] /* Check the parameters of the memory-mapped configuration structure */ assert_param(IS_XSPI_TIMEOUT_ACTIVATION(pCfg->TimeOutActivation)); /* Check the state */ if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) 80063f8: 687b ldr r3, [r7, #4] 80063fa: 6d5b ldr r3, [r3, #84] @ 0x54 80063fc: 2b04 cmp r3, #4 80063fe: d134 bne.n 800646a { /* Wait till busy flag is reset */ status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeout); 8006400: 687b ldr r3, [r7, #4] 8006402: 6ddb ldr r3, [r3, #92] @ 0x5c 8006404: 9300 str r3, [sp, #0] 8006406: 68bb ldr r3, [r7, #8] 8006408: 2200 movs r2, #0 800640a: 2120 movs r1, #32 800640c: 6878 ldr r0, [r7, #4] 800640e: f000 fbfa bl 8006c06 8006412: 4603 mov r3, r0 8006414: 73fb strb r3, [r7, #15] if (status == HAL_OK) 8006416: 7bfb ldrb r3, [r7, #15] 8006418: 2b00 cmp r3, #0 800641a: d12b bne.n 8006474 { hxspi->State = HAL_XSPI_STATE_BUSY_MEM_MAPPED; 800641c: 687b ldr r3, [r7, #4] 800641e: 2288 movs r2, #136 @ 0x88 8006420: 655a str r2, [r3, #84] @ 0x54 if (pCfg->TimeOutActivation == HAL_XSPI_TIMEOUT_COUNTER_ENABLE) 8006422: 683b ldr r3, [r7, #0] 8006424: 681b ldr r3, [r3, #0] 8006426: 2b08 cmp r3, #8 8006428: d111 bne.n 800644e { assert_param(IS_XSPI_TIMEOUT_PERIOD(pCfg->TimeoutPeriodClock)); /* Configure register */ WRITE_REG(hxspi->Instance->LPTR, pCfg->TimeoutPeriodClock); 800642a: 687b ldr r3, [r7, #4] 800642c: 681b ldr r3, [r3, #0] 800642e: 683a ldr r2, [r7, #0] 8006430: 6852 ldr r2, [r2, #4] 8006432: f8c3 2130 str.w r2, [r3, #304] @ 0x130 /* Clear flags related to interrupt */ HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TO); 8006436: 687b ldr r3, [r7, #4] 8006438: 681b ldr r3, [r3, #0] 800643a: 2210 movs r2, #16 800643c: 625a str r2, [r3, #36] @ 0x24 /* Enable the timeout interrupt */ HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TO); 800643e: 687b ldr r3, [r7, #4] 8006440: 681b ldr r3, [r3, #0] 8006442: 681a ldr r2, [r3, #0] 8006444: 687b ldr r3, [r7, #4] 8006446: 681b ldr r3, [r3, #0] 8006448: f442 1280 orr.w r2, r2, #1048576 @ 0x100000 800644c: 601a str r2, [r3, #0] } /* Configure CR register with functional mode as memory-mapped */ MODIFY_REG(hxspi->Instance->CR, (XSPI_CR_TCEN | XSPI_CR_FMODE), 800644e: 687b ldr r3, [r7, #4] 8006450: 681b ldr r3, [r3, #0] 8006452: 681a ldr r2, [r3, #0] 8006454: 4b0a ldr r3, [pc, #40] @ (8006480 ) 8006456: 4013 ands r3, r2 8006458: 683a ldr r2, [r7, #0] 800645a: 6812 ldr r2, [r2, #0] 800645c: 431a orrs r2, r3 800645e: 687b ldr r3, [r7, #4] 8006460: 681b ldr r3, [r3, #0] 8006462: f042 5240 orr.w r2, r2, #805306368 @ 0x30000000 8006466: 601a str r2, [r3, #0] 8006468: e004 b.n 8006474 (pCfg->TimeOutActivation | XSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)); } } else { status = HAL_ERROR; 800646a: 2301 movs r3, #1 800646c: 73fb strb r3, [r7, #15] hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; 800646e: 687b ldr r3, [r7, #4] 8006470: 2210 movs r2, #16 8006472: 659a str r2, [r3, #88] @ 0x58 } return status; 8006474: 7bfb ldrb r3, [r7, #15] } 8006476: 4618 mov r0, r3 8006478: 3710 adds r7, #16 800647a: 46bd mov sp, r7 800647c: bd80 pop {r7, pc} 800647e: bf00 nop 8006480: cffffff7 .word 0xcffffff7 08006484 : * @brief Transfer Error callback. * @param hxspi : XSPI handle * @retval None */ __weak void HAL_XSPI_ErrorCallback(XSPI_HandleTypeDef *hxspi) { 8006484: b480 push {r7} 8006486: b083 sub sp, #12 8006488: af00 add r7, sp, #0 800648a: 6078 str r0, [r7, #4] UNUSED(hxspi); /* NOTE : This function should not be modified, when the callback is needed, the HAL_XSPI_ErrorCallback could be implemented in the user file */ } 800648c: bf00 nop 800648e: 370c adds r7, #12 8006490: 46bd mov sp, r7 8006492: f85d 7b04 ldr.w r7, [sp], #4 8006496: 4770 bx lr 08006498 : * @brief Abort completed callback. * @param hxspi : XSPI handle * @retval None */ __weak void HAL_XSPI_AbortCpltCallback(XSPI_HandleTypeDef *hxspi) { 8006498: b480 push {r7} 800649a: b083 sub sp, #12 800649c: af00 add r7, sp, #0 800649e: 6078 str r0, [r7, #4] UNUSED(hxspi); /* NOTE: This function should not be modified, when the callback is needed, the HAL_XSPI_AbortCpltCallback could be implemented in the user file */ } 80064a0: bf00 nop 80064a2: 370c adds r7, #12 80064a4: 46bd mov sp, r7 80064a6: f85d 7b04 ldr.w r7, [sp], #4 80064aa: 4770 bx lr 080064ac : * @brief FIFO Threshold callback. * @param hxspi : XSPI handle * @retval None */ __weak void HAL_XSPI_FifoThresholdCallback(XSPI_HandleTypeDef *hxspi) { 80064ac: b480 push {r7} 80064ae: b083 sub sp, #12 80064b0: af00 add r7, sp, #0 80064b2: 6078 str r0, [r7, #4] UNUSED(hxspi); /* NOTE : This function should not be modified, when the callback is needed, the HAL_XSPI_FIFOThresholdCallback could be implemented in the user file */ } 80064b4: bf00 nop 80064b6: 370c adds r7, #12 80064b8: 46bd mov sp, r7 80064ba: f85d 7b04 ldr.w r7, [sp], #4 80064be: 4770 bx lr 080064c0 : * @brief Command completed callback. * @param hxspi : XSPI handle * @retval None */ __weak void HAL_XSPI_CmdCpltCallback(XSPI_HandleTypeDef *hxspi) { 80064c0: b480 push {r7} 80064c2: b083 sub sp, #12 80064c4: af00 add r7, sp, #0 80064c6: 6078 str r0, [r7, #4] UNUSED(hxspi); /* NOTE: This function should not be modified, when the callback is needed, the HAL_XSPI_CmdCpltCallback could be implemented in the user file */ } 80064c8: bf00 nop 80064ca: 370c adds r7, #12 80064cc: 46bd mov sp, r7 80064ce: f85d 7b04 ldr.w r7, [sp], #4 80064d2: 4770 bx lr 080064d4 : * @brief Rx Transfer completed callback. * @param hxspi : XSPI handle * @retval None */ __weak void HAL_XSPI_RxCpltCallback(XSPI_HandleTypeDef *hxspi) { 80064d4: b480 push {r7} 80064d6: b083 sub sp, #12 80064d8: af00 add r7, sp, #0 80064da: 6078 str r0, [r7, #4] UNUSED(hxspi); /* NOTE: This function should not be modified, when the callback is needed, the HAL_XSPI_RxCpltCallback could be implemented in the user file */ } 80064dc: bf00 nop 80064de: 370c adds r7, #12 80064e0: 46bd mov sp, r7 80064e2: f85d 7b04 ldr.w r7, [sp], #4 80064e6: 4770 bx lr 080064e8 : * @brief Tx Transfer completed callback. * @param hxspi : XSPI handle * @retval None */ __weak void HAL_XSPI_TxCpltCallback(XSPI_HandleTypeDef *hxspi) { 80064e8: b480 push {r7} 80064ea: b083 sub sp, #12 80064ec: af00 add r7, sp, #0 80064ee: 6078 str r0, [r7, #4] UNUSED(hxspi); /* NOTE: This function should not be modified, when the callback is needed, the HAL_XSPI_TxCpltCallback could be implemented in the user file */ } 80064f0: bf00 nop 80064f2: 370c adds r7, #12 80064f4: 46bd mov sp, r7 80064f6: f85d 7b04 ldr.w r7, [sp], #4 80064fa: 4770 bx lr 080064fc : * @brief Rx Half Transfer completed callback. * @param hxspi : XSPI handle * @retval None */ __weak void HAL_XSPI_RxHalfCpltCallback(XSPI_HandleTypeDef *hxspi) { 80064fc: b480 push {r7} 80064fe: b083 sub sp, #12 8006500: af00 add r7, sp, #0 8006502: 6078 str r0, [r7, #4] UNUSED(hxspi); /* NOTE: This function should not be modified, when the callback is needed, the HAL_XSPI_RxHalfCpltCallback could be implemented in the user file */ } 8006504: bf00 nop 8006506: 370c adds r7, #12 8006508: 46bd mov sp, r7 800650a: f85d 7b04 ldr.w r7, [sp], #4 800650e: 4770 bx lr 08006510 : * @brief Tx Half Transfer completed callback. * @param hxspi : XSPI handle * @retval None */ __weak void HAL_XSPI_TxHalfCpltCallback(XSPI_HandleTypeDef *hxspi) { 8006510: b480 push {r7} 8006512: b083 sub sp, #12 8006514: af00 add r7, sp, #0 8006516: 6078 str r0, [r7, #4] UNUSED(hxspi); /* NOTE: This function should not be modified, when the callback is needed, the HAL_XSPI_TxHalfCpltCallback could be implemented in the user file */ } 8006518: bf00 nop 800651a: 370c adds r7, #12 800651c: 46bd mov sp, r7 800651e: f85d 7b04 ldr.w r7, [sp], #4 8006522: 4770 bx lr 08006524 : * @brief Status Match callback. * @param hxspi : XSPI handle * @retval None */ __weak void HAL_XSPI_StatusMatchCallback(XSPI_HandleTypeDef *hxspi) { 8006524: b480 push {r7} 8006526: b083 sub sp, #12 8006528: af00 add r7, sp, #0 800652a: 6078 str r0, [r7, #4] UNUSED(hxspi); /* NOTE : This function should not be modified, when the callback is needed, the HAL_XSPI_StatusMatchCallback could be implemented in the user file */ } 800652c: bf00 nop 800652e: 370c adds r7, #12 8006530: 46bd mov sp, r7 8006532: f85d 7b04 ldr.w r7, [sp], #4 8006536: 4770 bx lr 08006538 : * @brief Timeout callback. * @param hxspi : XSPI handle * @retval None */ __weak void HAL_XSPI_TimeOutCallback(XSPI_HandleTypeDef *hxspi) { 8006538: b480 push {r7} 800653a: b083 sub sp, #12 800653c: af00 add r7, sp, #0 800653e: 6078 str r0, [r7, #4] UNUSED(hxspi); /* NOTE : This function should not be modified, when the callback is needed, the HAL_XSPI_TimeOutCallback could be implemented in the user file */ } 8006540: bf00 nop 8006542: 370c adds r7, #12 8006544: 46bd mov sp, r7 8006546: f85d 7b04 ldr.w r7, [sp], #4 800654a: 4770 bx lr 0800654c : * @param pCallback : pointer to the Callback function * @retval status */ HAL_StatusTypeDef HAL_XSPI_RegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef CallbackID, pXSPI_CallbackTypeDef pCallback) { 800654c: b480 push {r7} 800654e: b087 sub sp, #28 8006550: af00 add r7, sp, #0 8006552: 60f8 str r0, [r7, #12] 8006554: 460b mov r3, r1 8006556: 607a str r2, [r7, #4] 8006558: 72fb strb r3, [r7, #11] HAL_StatusTypeDef status = HAL_OK; 800655a: 2300 movs r3, #0 800655c: 75fb strb r3, [r7, #23] if (pCallback == NULL) 800655e: 687b ldr r3, [r7, #4] 8006560: 2b00 cmp r3, #0 8006562: d107 bne.n 8006574 { /* Update the error code */ hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; 8006564: 68fb ldr r3, [r7, #12] 8006566: 6d9b ldr r3, [r3, #88] @ 0x58 8006568: f043 0220 orr.w r2, r3, #32 800656c: 68fb ldr r3, [r7, #12] 800656e: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 8006570: 2301 movs r3, #1 8006572: e084 b.n 800667e } if (hxspi->State == HAL_XSPI_STATE_READY) 8006574: 68fb ldr r3, [r7, #12] 8006576: 6d5b ldr r3, [r3, #84] @ 0x54 8006578: 2b02 cmp r3, #2 800657a: d15a bne.n 8006632 { switch (CallbackID) 800657c: 7afb ldrb r3, [r7, #11] 800657e: 2b0b cmp r3, #11 8006580: d84e bhi.n 8006620 8006582: a201 add r2, pc, #4 @ (adr r2, 8006588 ) 8006584: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8006588: 080065b9 .word 0x080065b9 800658c: 080065c1 .word 0x080065c1 8006590: 080065c9 .word 0x080065c9 8006594: 080065d1 .word 0x080065d1 8006598: 080065d9 .word 0x080065d9 800659c: 080065e1 .word 0x080065e1 80065a0: 080065e9 .word 0x080065e9 80065a4: 080065f1 .word 0x080065f1 80065a8: 080065f9 .word 0x080065f9 80065ac: 08006603 .word 0x08006603 80065b0: 0800660d .word 0x0800660d 80065b4: 08006617 .word 0x08006617 { case HAL_XSPI_ERROR_CB_ID : hxspi->ErrorCallback = pCallback; 80065b8: 68fb ldr r3, [r7, #12] 80065ba: 687a ldr r2, [r7, #4] 80065bc: 661a str r2, [r3, #96] @ 0x60 break; 80065be: e05d b.n 800667c case HAL_XSPI_ABORT_CB_ID : hxspi->AbortCpltCallback = pCallback; 80065c0: 68fb ldr r3, [r7, #12] 80065c2: 687a ldr r2, [r7, #4] 80065c4: 665a str r2, [r3, #100] @ 0x64 break; 80065c6: e059 b.n 800667c case HAL_XSPI_FIFO_THRESHOLD_CB_ID : hxspi->FifoThresholdCallback = pCallback; 80065c8: 68fb ldr r3, [r7, #12] 80065ca: 687a ldr r2, [r7, #4] 80065cc: 669a str r2, [r3, #104] @ 0x68 break; 80065ce: e055 b.n 800667c case HAL_XSPI_CMD_CPLT_CB_ID : hxspi->CmdCpltCallback = pCallback; 80065d0: 68fb ldr r3, [r7, #12] 80065d2: 687a ldr r2, [r7, #4] 80065d4: 66da str r2, [r3, #108] @ 0x6c break; 80065d6: e051 b.n 800667c case HAL_XSPI_RX_CPLT_CB_ID : hxspi->RxCpltCallback = pCallback; 80065d8: 68fb ldr r3, [r7, #12] 80065da: 687a ldr r2, [r7, #4] 80065dc: 671a str r2, [r3, #112] @ 0x70 break; 80065de: e04d b.n 800667c case HAL_XSPI_TX_CPLT_CB_ID : hxspi->TxCpltCallback = pCallback; 80065e0: 68fb ldr r3, [r7, #12] 80065e2: 687a ldr r2, [r7, #4] 80065e4: 675a str r2, [r3, #116] @ 0x74 break; 80065e6: e049 b.n 800667c case HAL_XSPI_RX_HALF_CPLT_CB_ID : hxspi->RxHalfCpltCallback = pCallback; 80065e8: 68fb ldr r3, [r7, #12] 80065ea: 687a ldr r2, [r7, #4] 80065ec: 679a str r2, [r3, #120] @ 0x78 break; 80065ee: e045 b.n 800667c case HAL_XSPI_TX_HALF_CPLT_CB_ID : hxspi->TxHalfCpltCallback = pCallback; 80065f0: 68fb ldr r3, [r7, #12] 80065f2: 687a ldr r2, [r7, #4] 80065f4: 67da str r2, [r3, #124] @ 0x7c break; 80065f6: e041 b.n 800667c case HAL_XSPI_STATUS_MATCH_CB_ID : hxspi->StatusMatchCallback = pCallback; 80065f8: 68fb ldr r3, [r7, #12] 80065fa: 687a ldr r2, [r7, #4] 80065fc: f8c3 2080 str.w r2, [r3, #128] @ 0x80 break; 8006600: e03c b.n 800667c case HAL_XSPI_TIMEOUT_CB_ID : hxspi->TimeOutCallback = pCallback; 8006602: 68fb ldr r3, [r7, #12] 8006604: 687a ldr r2, [r7, #4] 8006606: f8c3 2084 str.w r2, [r3, #132] @ 0x84 break; 800660a: e037 b.n 800667c case HAL_XSPI_MSP_INIT_CB_ID : hxspi->MspInitCallback = pCallback; 800660c: 68fb ldr r3, [r7, #12] 800660e: 687a ldr r2, [r7, #4] 8006610: f8c3 2088 str.w r2, [r3, #136] @ 0x88 break; 8006614: e032 b.n 800667c case HAL_XSPI_MSP_DEINIT_CB_ID : hxspi->MspDeInitCallback = pCallback; 8006616: 68fb ldr r3, [r7, #12] 8006618: 687a ldr r2, [r7, #4] 800661a: f8c3 208c str.w r2, [r3, #140] @ 0x8c break; 800661e: e02d b.n 800667c default : /* Update the error code */ hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; 8006620: 68fb ldr r3, [r7, #12] 8006622: 6d9b ldr r3, [r3, #88] @ 0x58 8006624: f043 0220 orr.w r2, r3, #32 8006628: 68fb ldr r3, [r7, #12] 800662a: 659a str r2, [r3, #88] @ 0x58 /* update return status */ status = HAL_ERROR; 800662c: 2301 movs r3, #1 800662e: 75fb strb r3, [r7, #23] break; 8006630: e024 b.n 800667c } } else if (hxspi->State == HAL_XSPI_STATE_RESET) 8006632: 68fb ldr r3, [r7, #12] 8006634: 6d5b ldr r3, [r3, #84] @ 0x54 8006636: 2b00 cmp r3, #0 8006638: d118 bne.n 800666c { switch (CallbackID) 800663a: 7afb ldrb r3, [r7, #11] 800663c: 2b0a cmp r3, #10 800663e: d002 beq.n 8006646 8006640: 2b0b cmp r3, #11 8006642: d005 beq.n 8006650 8006644: e009 b.n 800665a { case HAL_XSPI_MSP_INIT_CB_ID : hxspi->MspInitCallback = pCallback; 8006646: 68fb ldr r3, [r7, #12] 8006648: 687a ldr r2, [r7, #4] 800664a: f8c3 2088 str.w r2, [r3, #136] @ 0x88 break; 800664e: e015 b.n 800667c case HAL_XSPI_MSP_DEINIT_CB_ID : hxspi->MspDeInitCallback = pCallback; 8006650: 68fb ldr r3, [r7, #12] 8006652: 687a ldr r2, [r7, #4] 8006654: f8c3 208c str.w r2, [r3, #140] @ 0x8c break; 8006658: e010 b.n 800667c default : /* Update the error code */ hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; 800665a: 68fb ldr r3, [r7, #12] 800665c: 6d9b ldr r3, [r3, #88] @ 0x58 800665e: f043 0220 orr.w r2, r3, #32 8006662: 68fb ldr r3, [r7, #12] 8006664: 659a str r2, [r3, #88] @ 0x58 /* update return status */ status = HAL_ERROR; 8006666: 2301 movs r3, #1 8006668: 75fb strb r3, [r7, #23] break; 800666a: e007 b.n 800667c } } else { /* Update the error code */ hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; 800666c: 68fb ldr r3, [r7, #12] 800666e: 6d9b ldr r3, [r3, #88] @ 0x58 8006670: f043 0220 orr.w r2, r3, #32 8006674: 68fb ldr r3, [r7, #12] 8006676: 659a str r2, [r3, #88] @ 0x58 /* update return status */ status = HAL_ERROR; 8006678: 2301 movs r3, #1 800667a: 75fb strb r3, [r7, #23] } return status; 800667c: 7dfb ldrb r3, [r7, #23] } 800667e: 4618 mov r0, r3 8006680: 371c adds r7, #28 8006682: 46bd mov sp, r7 8006684: f85d 7b04 ldr.w r7, [sp], #4 8006688: 4770 bx lr 800668a: bf00 nop 0800668c : * @brief Abort the current operation, return to the indirect mode. * @param hxspi : XSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi) { 800668c: b580 push {r7, lr} 800668e: b086 sub sp, #24 8006690: af02 add r7, sp, #8 8006692: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8006694: 2300 movs r3, #0 8006696: 73fb strb r3, [r7, #15] uint32_t tickstart = HAL_GetTick(); 8006698: f7fa fb2a bl 8000cf0 800669c: 60b8 str r0, [r7, #8] /* Check if the state is not in reset state */ if (hxspi->State != HAL_XSPI_STATE_RESET) 800669e: 687b ldr r3, [r7, #4] 80066a0: 6d5b ldr r3, [r3, #84] @ 0x54 80066a2: 2b00 cmp r3, #0 80066a4: d06f beq.n 8006786 { /* Check if the DMA is enabled */ if ((hxspi->Instance->CR & XSPI_CR_DMAEN) != 0U) 80066a6: 687b ldr r3, [r7, #4] 80066a8: 681b ldr r3, [r3, #0] 80066aa: 681b ldr r3, [r3, #0] 80066ac: f003 0304 and.w r3, r3, #4 80066b0: 2b00 cmp r3, #0 80066b2: d021 beq.n 80066f8 { /* Disable the DMA transfer on the XSPI side */ CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); 80066b4: 687b ldr r3, [r7, #4] 80066b6: 681b ldr r3, [r3, #0] 80066b8: 681a ldr r2, [r3, #0] 80066ba: 687b ldr r3, [r7, #4] 80066bc: 681b ldr r3, [r3, #0] 80066be: f022 0204 bic.w r2, r2, #4 80066c2: 601a str r2, [r3, #0] /* Disable the DMA transmit on the DMA side */ status = HAL_DMA_Abort(hxspi->hdmatx); 80066c4: 687b ldr r3, [r7, #4] 80066c6: 6cdb ldr r3, [r3, #76] @ 0x4c 80066c8: 4618 mov r0, r3 80066ca: f7fa fca8 bl 800101e 80066ce: 4603 mov r3, r0 80066d0: 73fb strb r3, [r7, #15] if (status != HAL_OK) 80066d2: 7bfb ldrb r3, [r7, #15] 80066d4: 2b00 cmp r3, #0 80066d6: d002 beq.n 80066de { hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; 80066d8: 687b ldr r3, [r7, #4] 80066da: 2204 movs r2, #4 80066dc: 659a str r2, [r3, #88] @ 0x58 } /* Disable the DMA receive on the DMA side */ status = HAL_DMA_Abort(hxspi->hdmarx); 80066de: 687b ldr r3, [r7, #4] 80066e0: 6d1b ldr r3, [r3, #80] @ 0x50 80066e2: 4618 mov r0, r3 80066e4: f7fa fc9b bl 800101e 80066e8: 4603 mov r3, r0 80066ea: 73fb strb r3, [r7, #15] if (status != HAL_OK) 80066ec: 7bfb ldrb r3, [r7, #15] 80066ee: 2b00 cmp r3, #0 80066f0: d002 beq.n 80066f8 { hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; 80066f2: 687b ldr r3, [r7, #4] 80066f4: 2204 movs r2, #4 80066f6: 659a str r2, [r3, #88] @ 0x58 } } if (HAL_XSPI_GET_FLAG(hxspi, HAL_XSPI_FLAG_BUSY) != RESET) 80066f8: 687b ldr r3, [r7, #4] 80066fa: 681b ldr r3, [r3, #0] 80066fc: 6a1b ldr r3, [r3, #32] 80066fe: f003 0320 and.w r3, r3, #32 8006702: 2b00 cmp r3, #0 8006704: d033 beq.n 800676e { /* Perform an abort of the XSPI */ SET_BIT(hxspi->Instance->CR, XSPI_CR_ABORT); 8006706: 687b ldr r3, [r7, #4] 8006708: 681b ldr r3, [r3, #0] 800670a: 681a ldr r2, [r3, #0] 800670c: 687b ldr r3, [r7, #4] 800670e: 681b ldr r3, [r3, #0] 8006710: f042 0202 orr.w r2, r2, #2 8006714: 601a str r2, [r3, #0] /* Wait until the transfer complete flag is set to go back in idle state */ status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, hxspi->Timeout); 8006716: 687b ldr r3, [r7, #4] 8006718: 6ddb ldr r3, [r3, #92] @ 0x5c 800671a: 9300 str r3, [sp, #0] 800671c: 68bb ldr r3, [r7, #8] 800671e: 2201 movs r2, #1 8006720: 2102 movs r1, #2 8006722: 6878 ldr r0, [r7, #4] 8006724: f000 fa6f bl 8006c06 8006728: 4603 mov r3, r0 800672a: 73fb strb r3, [r7, #15] if (status == HAL_OK) 800672c: 7bfb ldrb r3, [r7, #15] 800672e: 2b00 cmp r3, #0 8006730: d12e bne.n 8006790 { /* Clear transfer complete flag */ HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); 8006732: 687b ldr r3, [r7, #4] 8006734: 681b ldr r3, [r3, #0] 8006736: 2202 movs r2, #2 8006738: 625a str r2, [r3, #36] @ 0x24 /* Wait until the busy flag is reset to go back in idle state */ status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeout); 800673a: 687b ldr r3, [r7, #4] 800673c: 6ddb ldr r3, [r3, #92] @ 0x5c 800673e: 9300 str r3, [sp, #0] 8006740: 68bb ldr r3, [r7, #8] 8006742: 2200 movs r2, #0 8006744: 2120 movs r1, #32 8006746: 6878 ldr r0, [r7, #4] 8006748: f000 fa5d bl 8006c06 800674c: 4603 mov r3, r0 800674e: 73fb strb r3, [r7, #15] if (status == HAL_OK) 8006750: 7bfb ldrb r3, [r7, #15] 8006752: 2b00 cmp r3, #0 8006754: d11c bne.n 8006790 { /* Return to indirect mode */ CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE); 8006756: 687b ldr r3, [r7, #4] 8006758: 681b ldr r3, [r3, #0] 800675a: 681a ldr r2, [r3, #0] 800675c: 687b ldr r3, [r7, #4] 800675e: 681b ldr r3, [r3, #0] 8006760: f022 5240 bic.w r2, r2, #805306368 @ 0x30000000 8006764: 601a str r2, [r3, #0] hxspi->State = HAL_XSPI_STATE_READY; 8006766: 687b ldr r3, [r7, #4] 8006768: 2202 movs r2, #2 800676a: 655a str r2, [r3, #84] @ 0x54 800676c: e010 b.n 8006790 } } else { /* Return to indirect mode */ CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE); 800676e: 687b ldr r3, [r7, #4] 8006770: 681b ldr r3, [r3, #0] 8006772: 681a ldr r2, [r3, #0] 8006774: 687b ldr r3, [r7, #4] 8006776: 681b ldr r3, [r3, #0] 8006778: f022 5240 bic.w r2, r2, #805306368 @ 0x30000000 800677c: 601a str r2, [r3, #0] hxspi->State = HAL_XSPI_STATE_READY; 800677e: 687b ldr r3, [r7, #4] 8006780: 2202 movs r2, #2 8006782: 655a str r2, [r3, #84] @ 0x54 8006784: e004 b.n 8006790 } } else { status = HAL_ERROR; 8006786: 2301 movs r3, #1 8006788: 73fb strb r3, [r7, #15] hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; 800678a: 687b ldr r3, [r7, #4] 800678c: 2210 movs r2, #16 800678e: 659a str r2, [r3, #88] @ 0x58 } return status; 8006790: 7bfb ldrb r3, [r7, #15] } 8006792: 4618 mov r0, r3 8006794: 3710 adds r7, #16 8006796: 46bd mov sp, r7 8006798: bd80 pop {r7, pc} ... 0800679c : * @brief Abort the current operation, return to the indirect mode. (non-blocking function) * @param hxspi : XSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_XSPI_Abort_IT(XSPI_HandleTypeDef *hxspi) { 800679c: b580 push {r7, lr} 800679e: b084 sub sp, #16 80067a0: af00 add r7, sp, #0 80067a2: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80067a4: 2300 movs r3, #0 80067a6: 73fb strb r3, [r7, #15] /* Check if the state is not in reset state */ if (hxspi->State != HAL_XSPI_STATE_RESET) 80067a8: 687b ldr r3, [r7, #4] 80067aa: 6d5b ldr r3, [r3, #84] @ 0x54 80067ac: 2b00 cmp r3, #0 80067ae: d075 beq.n 800689c { /* Disable all interrupts */ HAL_XSPI_DISABLE_IT(hxspi, (HAL_XSPI_IT_TO | HAL_XSPI_IT_SM | HAL_XSPI_IT_FT | HAL_XSPI_IT_TC | HAL_XSPI_IT_TE)); 80067b0: 687b ldr r3, [r7, #4] 80067b2: 681b ldr r3, [r3, #0] 80067b4: 681a ldr r2, [r3, #0] 80067b6: 687b ldr r3, [r7, #4] 80067b8: 681b ldr r3, [r3, #0] 80067ba: f422 12f8 bic.w r2, r2, #2031616 @ 0x1f0000 80067be: 601a str r2, [r3, #0] hxspi->State = HAL_XSPI_STATE_ABORT; 80067c0: 687b ldr r3, [r7, #4] 80067c2: f44f 7280 mov.w r2, #256 @ 0x100 80067c6: 655a str r2, [r3, #84] @ 0x54 /* Check if the DMA is enabled */ if ((hxspi->Instance->CR & XSPI_CR_DMAEN) != 0U) 80067c8: 687b ldr r3, [r7, #4] 80067ca: 681b ldr r3, [r3, #0] 80067cc: 681b ldr r3, [r3, #0] 80067ce: f003 0304 and.w r3, r3, #4 80067d2: 2b00 cmp r3, #0 80067d4: d02e beq.n 8006834 { /* Disable the DMA transfer on the XSPI side */ CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); 80067d6: 687b ldr r3, [r7, #4] 80067d8: 681b ldr r3, [r3, #0] 80067da: 681a ldr r2, [r3, #0] 80067dc: 687b ldr r3, [r7, #4] 80067de: 681b ldr r3, [r3, #0] 80067e0: f022 0204 bic.w r2, r2, #4 80067e4: 601a str r2, [r3, #0] /* Disable the DMA transmit on the DMA side */ hxspi->hdmatx->XferAbortCallback = XSPI_DMAAbortCplt; 80067e6: 687b ldr r3, [r7, #4] 80067e8: 6cdb ldr r3, [r3, #76] @ 0x4c 80067ea: 4a31 ldr r2, [pc, #196] @ (80068b0 ) 80067ec: 66da str r2, [r3, #108] @ 0x6c if (HAL_DMA_Abort_IT(hxspi->hdmatx) != HAL_OK) 80067ee: 687b ldr r3, [r7, #4] 80067f0: 6cdb ldr r3, [r3, #76] @ 0x4c 80067f2: 4618 mov r0, r3 80067f4: f7fa fc8f bl 8001116 80067f8: 4603 mov r3, r0 80067fa: 2b00 cmp r3, #0 80067fc: d006 beq.n 800680c { hxspi->State = HAL_XSPI_STATE_READY; 80067fe: 687b ldr r3, [r7, #4] 8006800: 2202 movs r2, #2 8006802: 655a str r2, [r3, #84] @ 0x54 /* Abort callback */ #if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) hxspi->AbortCpltCallback(hxspi); 8006804: 687b ldr r3, [r7, #4] 8006806: 6e5b ldr r3, [r3, #100] @ 0x64 8006808: 6878 ldr r0, [r7, #4] 800680a: 4798 blx r3 HAL_XSPI_AbortCpltCallback(hxspi); #endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ } /* Disable the DMA receive on the DMA side */ hxspi->hdmarx->XferAbortCallback = XSPI_DMAAbortCplt; 800680c: 687b ldr r3, [r7, #4] 800680e: 6d1b ldr r3, [r3, #80] @ 0x50 8006810: 4a27 ldr r2, [pc, #156] @ (80068b0 ) 8006812: 66da str r2, [r3, #108] @ 0x6c if (HAL_DMA_Abort_IT(hxspi->hdmarx) != HAL_OK) 8006814: 687b ldr r3, [r7, #4] 8006816: 6d1b ldr r3, [r3, #80] @ 0x50 8006818: 4618 mov r0, r3 800681a: f7fa fc7c bl 8001116 800681e: 4603 mov r3, r0 8006820: 2b00 cmp r3, #0 8006822: d040 beq.n 80068a6 { hxspi->State = HAL_XSPI_STATE_READY; 8006824: 687b ldr r3, [r7, #4] 8006826: 2202 movs r2, #2 8006828: 655a str r2, [r3, #84] @ 0x54 /* Abort callback */ #if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) hxspi->AbortCpltCallback(hxspi); 800682a: 687b ldr r3, [r7, #4] 800682c: 6e5b ldr r3, [r3, #100] @ 0x64 800682e: 6878 ldr r0, [r7, #4] 8006830: 4798 blx r3 8006832: e038 b.n 80068a6 #endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ } } else { if (HAL_XSPI_GET_FLAG(hxspi, HAL_XSPI_FLAG_BUSY) != RESET) 8006834: 687b ldr r3, [r7, #4] 8006836: 681b ldr r3, [r3, #0] 8006838: 6a1b ldr r3, [r3, #32] 800683a: f003 0320 and.w r3, r3, #32 800683e: 2b00 cmp r3, #0 8006840: d01c beq.n 800687c { /* Clear transfer complete flag */ HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); 8006842: 687b ldr r3, [r7, #4] 8006844: 681b ldr r3, [r3, #0] 8006846: 2202 movs r2, #2 8006848: 625a str r2, [r3, #36] @ 0x24 /* Enable the transfer complete interrupts */ HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC); 800684a: 687b ldr r3, [r7, #4] 800684c: 681b ldr r3, [r3, #0] 800684e: 681a ldr r2, [r3, #0] 8006850: 687b ldr r3, [r7, #4] 8006852: 681b ldr r3, [r3, #0] 8006854: f442 3200 orr.w r2, r2, #131072 @ 0x20000 8006858: 601a str r2, [r3, #0] /* Perform an abort of the XSPI */ SET_BIT(hxspi->Instance->CR, XSPI_CR_ABORT); 800685a: 687b ldr r3, [r7, #4] 800685c: 681b ldr r3, [r3, #0] 800685e: 681a ldr r2, [r3, #0] 8006860: 687b ldr r3, [r7, #4] 8006862: 681b ldr r3, [r3, #0] 8006864: f042 0202 orr.w r2, r2, #2 8006868: 601a str r2, [r3, #0] /* Return to indirect mode */ CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE); 800686a: 687b ldr r3, [r7, #4] 800686c: 681b ldr r3, [r3, #0] 800686e: 681a ldr r2, [r3, #0] 8006870: 687b ldr r3, [r7, #4] 8006872: 681b ldr r3, [r3, #0] 8006874: f022 5240 bic.w r2, r2, #805306368 @ 0x30000000 8006878: 601a str r2, [r3, #0] 800687a: e014 b.n 80068a6 } else { /* Return to indirect mode */ CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE); 800687c: 687b ldr r3, [r7, #4] 800687e: 681b ldr r3, [r3, #0] 8006880: 681a ldr r2, [r3, #0] 8006882: 687b ldr r3, [r7, #4] 8006884: 681b ldr r3, [r3, #0] 8006886: f022 5240 bic.w r2, r2, #805306368 @ 0x30000000 800688a: 601a str r2, [r3, #0] hxspi->State = HAL_XSPI_STATE_READY; 800688c: 687b ldr r3, [r7, #4] 800688e: 2202 movs r2, #2 8006890: 655a str r2, [r3, #84] @ 0x54 /* Abort callback */ #if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) hxspi->AbortCpltCallback(hxspi); 8006892: 687b ldr r3, [r7, #4] 8006894: 6e5b ldr r3, [r3, #100] @ 0x64 8006896: 6878 ldr r0, [r7, #4] 8006898: 4798 blx r3 800689a: e004 b.n 80068a6 } } } else { status = HAL_ERROR; 800689c: 2301 movs r3, #1 800689e: 73fb strb r3, [r7, #15] hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; 80068a0: 687b ldr r3, [r7, #4] 80068a2: 2210 movs r2, #16 80068a4: 659a str r2, [r3, #88] @ 0x58 } return status; 80068a6: 7bfb ldrb r3, [r7, #15] } 80068a8: 4618 mov r0, r3 80068aa: 3710 adds r7, #16 80068ac: 46bd mov sp, r7 80068ae: bd80 pop {r7, pc} 80068b0: 08006b8b .word 0x08006b8b 080068b4 : * @param hxspi : XSPI handle. * @param Timeout : Timeout for the memory access. * @retval HAL state */ HAL_StatusTypeDef HAL_XSPI_SetTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Timeout) { 80068b4: b480 push {r7} 80068b6: b083 sub sp, #12 80068b8: af00 add r7, sp, #0 80068ba: 6078 str r0, [r7, #4] 80068bc: 6039 str r1, [r7, #0] hxspi->Timeout = Timeout; 80068be: 687b ldr r3, [r7, #4] 80068c0: 683a ldr r2, [r7, #0] 80068c2: 65da str r2, [r3, #92] @ 0x5c return HAL_OK; 80068c4: 2300 movs r3, #0 } 80068c6: 4618 mov r0, r3 80068c8: 370c adds r7, #12 80068ca: 46bd mov sp, r7 80068cc: f85d 7b04 ldr.w r7, [sp], #4 80068d0: 4770 bx lr ... 080068d4 : * @param pCfg : Pointer to Configuration of the IO Manager for the instance * @param Timeout : Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_XSPIM_Config(XSPI_HandleTypeDef *hxspi, const XSPIM_CfgTypeDef *pCfg, uint32_t Timeout) { 80068d4: b580 push {r7, lr} 80068d6: b08c sub sp, #48 @ 0x30 80068d8: af00 add r7, sp, #0 80068da: 60f8 str r0, [r7, #12] 80068dc: 60b9 str r1, [r7, #8] 80068de: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80068e0: 2300 movs r3, #0 80068e2: f887 302d strb.w r3, [r7, #45] @ 0x2d uint8_t index; uint8_t xspi_enabled = 0U; 80068e6: 2300 movs r3, #0 80068e8: f887 302e strb.w r3, [r7, #46] @ 0x2e XSPIM_CfgTypeDef IOM_cfg[XSPI_NB_INSTANCE] = {0}; 80068ec: f107 0314 add.w r3, r7, #20 80068f0: 2200 movs r2, #0 80068f2: 601a str r2, [r3, #0] 80068f4: 605a str r2, [r3, #4] 80068f6: 609a str r2, [r3, #8] 80068f8: 60da str r2, [r3, #12] 80068fa: 611a str r2, [r3, #16] 80068fc: 615a str r2, [r3, #20] assert_param(IS_XSPIM_NCS_OVR(pCfg->nCSOverride)); assert_param(IS_XSPIM_IO_PORT(pCfg->IOPort)); assert_param(IS_XSPIM_REQ2ACKTIME(pCfg->Req2AckTime)); /**************** Get current configuration of the instances ****************/ for (index = 0U; index < XSPI_NB_INSTANCE; index++) 80068fe: 2300 movs r3, #0 8006900: f887 302f strb.w r3, [r7, #47] @ 0x2f 8006904: e014 b.n 8006930 { XSPIM_GetConfig(index + 1U, &(IOM_cfg[index])); 8006906: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 800690a: 3301 adds r3, #1 800690c: b2d8 uxtb r0, r3 800690e: f897 202f ldrb.w r2, [r7, #47] @ 0x2f 8006912: f107 0114 add.w r1, r7, #20 8006916: 4613 mov r3, r2 8006918: 005b lsls r3, r3, #1 800691a: 4413 add r3, r2 800691c: 009b lsls r3, r3, #2 800691e: 440b add r3, r1 8006920: 4619 mov r1, r3 8006922: f000 fb31 bl 8006f88 for (index = 0U; index < XSPI_NB_INSTANCE; index++) 8006926: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 800692a: 3301 adds r3, #1 800692c: f887 302f strb.w r3, [r7, #47] @ 0x2f 8006930: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 8006934: 2b01 cmp r3, #1 8006936: d9e6 bls.n 8006906 } /********** Disable both XSPI to configure XSPI IO Manager **********/ if ((XSPI1->CR & XSPI_CR_EN) != 0U) 8006938: 4b5b ldr r3, [pc, #364] @ (8006aa8 ) 800693a: 681b ldr r3, [r3, #0] 800693c: f003 0301 and.w r3, r3, #1 8006940: 2b00 cmp r3, #0 8006942: d00b beq.n 800695c { CLEAR_BIT(XSPI1->CR, XSPI_CR_EN); 8006944: 4b58 ldr r3, [pc, #352] @ (8006aa8 ) 8006946: 681b ldr r3, [r3, #0] 8006948: 4a57 ldr r2, [pc, #348] @ (8006aa8 ) 800694a: f023 0301 bic.w r3, r3, #1 800694e: 6013 str r3, [r2, #0] xspi_enabled |= 0x1U; 8006950: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 8006954: f043 0301 orr.w r3, r3, #1 8006958: f887 302e strb.w r3, [r7, #46] @ 0x2e } if ((XSPI2->CR & XSPI_CR_EN) != 0U) 800695c: 4b53 ldr r3, [pc, #332] @ (8006aac ) 800695e: 681b ldr r3, [r3, #0] 8006960: f003 0301 and.w r3, r3, #1 8006964: 2b00 cmp r3, #0 8006966: d00b beq.n 8006980 { CLEAR_BIT(XSPI2->CR, XSPI_CR_EN); 8006968: 4b50 ldr r3, [pc, #320] @ (8006aac ) 800696a: 681b ldr r3, [r3, #0] 800696c: 4a4f ldr r2, [pc, #316] @ (8006aac ) 800696e: f023 0301 bic.w r3, r3, #1 8006972: 6013 str r3, [r2, #0] xspi_enabled |= 0x2U; 8006974: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 8006978: f043 0302 orr.w r3, r3, #2 800697c: f887 302e strb.w r3, [r7, #46] @ 0x2e } /***************** Deactivation of previous configuration *****************/ CLEAR_REG(XSPIM->CR); 8006980: 4b4b ldr r3, [pc, #300] @ (8006ab0 ) 8006982: 2200 movs r2, #0 8006984: 601a str r2, [r3, #0] /******************** Activation of new configuration *********************/ MODIFY_REG(XSPIM->CR, XSPIM_CR_REQ2ACK_TIME, ((pCfg->Req2AckTime - 1U) << XSPIM_CR_REQ2ACK_TIME_Pos)); 8006986: 4b4a ldr r3, [pc, #296] @ (8006ab0 ) 8006988: 681b ldr r3, [r3, #0] 800698a: f423 027f bic.w r2, r3, #16711680 @ 0xff0000 800698e: 68bb ldr r3, [r7, #8] 8006990: 689b ldr r3, [r3, #8] 8006992: 3b01 subs r3, #1 8006994: 041b lsls r3, r3, #16 8006996: 4946 ldr r1, [pc, #280] @ (8006ab0 ) 8006998: 4313 orrs r3, r2 800699a: 600b str r3, [r1, #0] if (hxspi->Instance == XSPI1) 800699c: 68fb ldr r3, [r7, #12] 800699e: 681b ldr r3, [r3, #0] 80069a0: 4a41 ldr r2, [pc, #260] @ (8006aa8 ) 80069a2: 4293 cmp r3, r2 80069a4: d110 bne.n 80069c8 { IOM_cfg[0].IOPort = pCfg->IOPort ; 80069a6: 68bb ldr r3, [r7, #8] 80069a8: 685b ldr r3, [r3, #4] 80069aa: 61bb str r3, [r7, #24] if (pCfg->nCSOverride != HAL_XSPI_CSSEL_OVR_DISABLED) 80069ac: 68bb ldr r3, [r7, #8] 80069ae: 681b ldr r3, [r3, #0] 80069b0: 2b00 cmp r3, #0 80069b2: d027 beq.n 8006a04 { MODIFY_REG(XSPIM->CR, (XSPIM_CR_CSSEL_OVR_O1 | XSPIM_CR_CSSEL_OVR_EN), (pCfg->nCSOverride)); 80069b4: 4b3e ldr r3, [pc, #248] @ (8006ab0 ) 80069b6: 681b ldr r3, [r3, #0] 80069b8: f023 0230 bic.w r2, r3, #48 @ 0x30 80069bc: 68bb ldr r3, [r7, #8] 80069be: 681b ldr r3, [r3, #0] 80069c0: 493b ldr r1, [pc, #236] @ (8006ab0 ) 80069c2: 4313 orrs r3, r2 80069c4: 600b str r3, [r1, #0] 80069c6: e01d b.n 8006a04 else { /* Nothing to do */ } } else if (hxspi->Instance == XSPI2) 80069c8: 68fb ldr r3, [r7, #12] 80069ca: 681b ldr r3, [r3, #0] 80069cc: 4a37 ldr r2, [pc, #220] @ (8006aac ) 80069ce: 4293 cmp r3, r2 80069d0: d110 bne.n 80069f4 { IOM_cfg[1].IOPort = pCfg->IOPort ; 80069d2: 68bb ldr r3, [r7, #8] 80069d4: 685b ldr r3, [r3, #4] 80069d6: 627b str r3, [r7, #36] @ 0x24 if (pCfg->nCSOverride != HAL_XSPI_CSSEL_OVR_DISABLED) 80069d8: 68bb ldr r3, [r7, #8] 80069da: 681b ldr r3, [r3, #0] 80069dc: 2b00 cmp r3, #0 80069de: d011 beq.n 8006a04 { MODIFY_REG(XSPIM->CR, (XSPIM_CR_CSSEL_OVR_O2 | XSPIM_CR_CSSEL_OVR_EN), (pCfg->nCSOverride)); 80069e0: 4b33 ldr r3, [pc, #204] @ (8006ab0 ) 80069e2: 681b ldr r3, [r3, #0] 80069e4: f023 0250 bic.w r2, r3, #80 @ 0x50 80069e8: 68bb ldr r3, [r7, #8] 80069ea: 681b ldr r3, [r3, #0] 80069ec: 4930 ldr r1, [pc, #192] @ (8006ab0 ) 80069ee: 4313 orrs r3, r2 80069f0: 600b str r3, [r1, #0] 80069f2: e007 b.n 8006a04 /* Nothing to do */ } } else { hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_PARAM; 80069f4: 68fb ldr r3, [r7, #12] 80069f6: 6d9b ldr r3, [r3, #88] @ 0x58 80069f8: f043 0208 orr.w r2, r3, #8 80069fc: 68fb ldr r3, [r7, #12] 80069fe: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 8006a00: 2301 movs r3, #1 8006a02: e04c b.n 8006a9e } for (index = 0U; index < (XSPI_NB_INSTANCE - 1U); index++) 8006a04: 2300 movs r3, #0 8006a06: f887 302f strb.w r3, [r7, #47] @ 0x2f 8006a0a: e02a b.n 8006a62 { if (IOM_cfg[index].IOPort == IOM_cfg[index + 1U].IOPort) 8006a0c: f897 202f ldrb.w r2, [r7, #47] @ 0x2f 8006a10: 4613 mov r3, r2 8006a12: 005b lsls r3, r3, #1 8006a14: 4413 add r3, r2 8006a16: 009b lsls r3, r3, #2 8006a18: 3330 adds r3, #48 @ 0x30 8006a1a: 443b add r3, r7 8006a1c: 3b18 subs r3, #24 8006a1e: 6819 ldr r1, [r3, #0] 8006a20: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 8006a24: 1c5a adds r2, r3, #1 8006a26: 4613 mov r3, r2 8006a28: 005b lsls r3, r3, #1 8006a2a: 4413 add r3, r2 8006a2c: 009b lsls r3, r3, #2 8006a2e: 3330 adds r3, #48 @ 0x30 8006a30: 443b add r3, r7 8006a32: 3b18 subs r3, #24 8006a34: 681b ldr r3, [r3, #0] 8006a36: 4299 cmp r1, r3 8006a38: d105 bne.n 8006a46 { /*Mux*/ SET_BIT(XSPIM->CR, XSPIM_CR_MUXEN); 8006a3a: 4b1d ldr r3, [pc, #116] @ (8006ab0 ) 8006a3c: 681b ldr r3, [r3, #0] 8006a3e: 4a1c ldr r2, [pc, #112] @ (8006ab0 ) 8006a40: f043 0301 orr.w r3, r3, #1 8006a44: 6013 str r3, [r2, #0] } else { /* Nothing to do */ } if (IOM_cfg[0].IOPort == HAL_XSPIM_IOPORT_2) 8006a46: 69bb ldr r3, [r7, #24] 8006a48: 2b01 cmp r3, #1 8006a4a: d105 bne.n 8006a58 { /*Mode*/ SET_BIT(XSPIM->CR, XSPIM_CR_MODE); 8006a4c: 4b18 ldr r3, [pc, #96] @ (8006ab0 ) 8006a4e: 681b ldr r3, [r3, #0] 8006a50: 4a17 ldr r2, [pc, #92] @ (8006ab0 ) 8006a52: f043 0302 orr.w r3, r3, #2 8006a56: 6013 str r3, [r2, #0] for (index = 0U; index < (XSPI_NB_INSTANCE - 1U); index++) 8006a58: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 8006a5c: 3301 adds r3, #1 8006a5e: f887 302f strb.w r3, [r7, #47] @ 0x2f 8006a62: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 8006a66: 2b00 cmp r3, #0 8006a68: d0d0 beq.n 8006a0c /* Nothing to do */ } } /******* Re-enable both XSPI after configure XSPI IO Manager ********/ if ((xspi_enabled & 0x1U) != 0U) 8006a6a: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 8006a6e: f003 0301 and.w r3, r3, #1 8006a72: 2b00 cmp r3, #0 8006a74: d005 beq.n 8006a82 { SET_BIT(XSPI1->CR, XSPI_CR_EN); 8006a76: 4b0c ldr r3, [pc, #48] @ (8006aa8 ) 8006a78: 681b ldr r3, [r3, #0] 8006a7a: 4a0b ldr r2, [pc, #44] @ (8006aa8 ) 8006a7c: f043 0301 orr.w r3, r3, #1 8006a80: 6013 str r3, [r2, #0] } if ((xspi_enabled & 0x2U) != 0U) 8006a82: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 8006a86: f003 0302 and.w r3, r3, #2 8006a8a: 2b00 cmp r3, #0 8006a8c: d005 beq.n 8006a9a { SET_BIT(XSPI2->CR, XSPI_CR_EN); 8006a8e: 4b07 ldr r3, [pc, #28] @ (8006aac ) 8006a90: 681b ldr r3, [r3, #0] 8006a92: 4a06 ldr r2, [pc, #24] @ (8006aac ) 8006a94: f043 0301 orr.w r3, r3, #1 8006a98: 6013 str r3, [r2, #0] } return status; 8006a9a: f897 302d ldrb.w r3, [r7, #45] @ 0x2d } 8006a9e: 4618 mov r0, r3 8006aa0: 3730 adds r7, #48 @ 0x30 8006aa2: 46bd mov sp, r7 8006aa4: bd80 pop {r7, pc} 8006aa6: bf00 nop 8006aa8: 52005000 .word 0x52005000 8006aac: 5200a000 .word 0x5200a000 8006ab0: 5200b400 .word 0x5200b400 08006ab4 : * @brief DMA XSPI process complete callback. * @param hdma : DMA handle * @retval None */ static void XSPI_DMACplt(DMA_HandleTypeDef *hdma) { 8006ab4: b480 push {r7} 8006ab6: b085 sub sp, #20 8006ab8: af00 add r7, sp, #0 8006aba: 6078 str r0, [r7, #4] XSPI_HandleTypeDef *hxspi = (XSPI_HandleTypeDef *)(hdma->Parent); 8006abc: 687b ldr r3, [r7, #4] 8006abe: 6ddb ldr r3, [r3, #92] @ 0x5c 8006ac0: 60fb str r3, [r7, #12] hxspi->XferCount = 0; 8006ac2: 68fb ldr r3, [r7, #12] 8006ac4: 2200 movs r2, #0 8006ac6: 649a str r2, [r3, #72] @ 0x48 /* Disable the DMA transfer on the XSPI side */ CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); 8006ac8: 68fb ldr r3, [r7, #12] 8006aca: 681b ldr r3, [r3, #0] 8006acc: 681a ldr r2, [r3, #0] 8006ace: 68fb ldr r3, [r7, #12] 8006ad0: 681b ldr r3, [r3, #0] 8006ad2: f022 0204 bic.w r2, r2, #4 8006ad6: 601a str r2, [r3, #0] /* Enable the XSPI transfer complete Interrupt */ HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC); 8006ad8: 68fb ldr r3, [r7, #12] 8006ada: 681b ldr r3, [r3, #0] 8006adc: 681a ldr r2, [r3, #0] 8006ade: 68fb ldr r3, [r7, #12] 8006ae0: 681b ldr r3, [r3, #0] 8006ae2: f442 3200 orr.w r2, r2, #131072 @ 0x20000 8006ae6: 601a str r2, [r3, #0] } 8006ae8: bf00 nop 8006aea: 3714 adds r7, #20 8006aec: 46bd mov sp, r7 8006aee: f85d 7b04 ldr.w r7, [sp], #4 8006af2: 4770 bx lr 08006af4 : * @brief DMA XSPI process half complete callback. * @param hdma : DMA handle * @retval None */ static void XSPI_DMAHalfCplt(DMA_HandleTypeDef *hdma) { 8006af4: b580 push {r7, lr} 8006af6: b084 sub sp, #16 8006af8: af00 add r7, sp, #0 8006afa: 6078 str r0, [r7, #4] XSPI_HandleTypeDef *hxspi = (XSPI_HandleTypeDef *)(hdma->Parent); 8006afc: 687b ldr r3, [r7, #4] 8006afe: 6ddb ldr r3, [r3, #92] @ 0x5c 8006b00: 60fb str r3, [r7, #12] hxspi->XferCount = (hxspi->XferCount >> 1); 8006b02: 68fb ldr r3, [r7, #12] 8006b04: 6c9b ldr r3, [r3, #72] @ 0x48 8006b06: 085a lsrs r2, r3, #1 8006b08: 68fb ldr r3, [r7, #12] 8006b0a: 649a str r2, [r3, #72] @ 0x48 if (hxspi->State == HAL_XSPI_STATE_BUSY_RX) 8006b0c: 68fb ldr r3, [r7, #12] 8006b0e: 6d5b ldr r3, [r3, #84] @ 0x54 8006b10: 2b28 cmp r3, #40 @ 0x28 8006b12: d104 bne.n 8006b1e { #if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) hxspi->RxHalfCpltCallback(hxspi); 8006b14: 68fb ldr r3, [r7, #12] 8006b16: 6f9b ldr r3, [r3, #120] @ 0x78 8006b18: 68f8 ldr r0, [r7, #12] 8006b1a: 4798 blx r3 hxspi->TxHalfCpltCallback(hxspi); #else HAL_XSPI_TxHalfCpltCallback(hxspi); #endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ } } 8006b1c: e003 b.n 8006b26 hxspi->TxHalfCpltCallback(hxspi); 8006b1e: 68fb ldr r3, [r7, #12] 8006b20: 6fdb ldr r3, [r3, #124] @ 0x7c 8006b22: 68f8 ldr r0, [r7, #12] 8006b24: 4798 blx r3 } 8006b26: bf00 nop 8006b28: 3710 adds r7, #16 8006b2a: 46bd mov sp, r7 8006b2c: bd80 pop {r7, pc} 08006b2e : * @brief DMA XSPI communication error callback. * @param hdma : DMA handle * @retval None */ static void XSPI_DMAError(DMA_HandleTypeDef *hdma) { 8006b2e: b580 push {r7, lr} 8006b30: b084 sub sp, #16 8006b32: af00 add r7, sp, #0 8006b34: 6078 str r0, [r7, #4] XSPI_HandleTypeDef *hxspi = (XSPI_HandleTypeDef *)(hdma->Parent); 8006b36: 687b ldr r3, [r7, #4] 8006b38: 6ddb ldr r3, [r3, #92] @ 0x5c 8006b3a: 60fb str r3, [r7, #12] hxspi->XferCount = 0; 8006b3c: 68fb ldr r3, [r7, #12] 8006b3e: 2200 movs r2, #0 8006b40: 649a str r2, [r3, #72] @ 0x48 hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; 8006b42: 68fb ldr r3, [r7, #12] 8006b44: 2204 movs r2, #4 8006b46: 659a str r2, [r3, #88] @ 0x58 /* Disable the DMA transfer on the XSPI side */ CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); 8006b48: 68fb ldr r3, [r7, #12] 8006b4a: 681b ldr r3, [r3, #0] 8006b4c: 681a ldr r2, [r3, #0] 8006b4e: 68fb ldr r3, [r7, #12] 8006b50: 681b ldr r3, [r3, #0] 8006b52: f022 0204 bic.w r2, r2, #4 8006b56: 601a str r2, [r3, #0] /* Abort the XSPI */ if (HAL_XSPI_Abort_IT(hxspi) != HAL_OK) 8006b58: 68f8 ldr r0, [r7, #12] 8006b5a: f7ff fe1f bl 800679c 8006b5e: 4603 mov r3, r0 8006b60: 2b00 cmp r3, #0 8006b62: d00e beq.n 8006b82 { /* Disable the interrupts */ HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE); 8006b64: 68fb ldr r3, [r7, #12] 8006b66: 681b ldr r3, [r3, #0] 8006b68: 681a ldr r2, [r3, #0] 8006b6a: 68fb ldr r3, [r7, #12] 8006b6c: 681b ldr r3, [r3, #0] 8006b6e: f422 22e0 bic.w r2, r2, #458752 @ 0x70000 8006b72: 601a str r2, [r3, #0] hxspi->State = HAL_XSPI_STATE_READY; 8006b74: 68fb ldr r3, [r7, #12] 8006b76: 2202 movs r2, #2 8006b78: 655a str r2, [r3, #84] @ 0x54 /* Error callback */ #if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) hxspi->ErrorCallback(hxspi); 8006b7a: 68fb ldr r3, [r7, #12] 8006b7c: 6e1b ldr r3, [r3, #96] @ 0x60 8006b7e: 68f8 ldr r0, [r7, #12] 8006b80: 4798 blx r3 #else HAL_XSPI_ErrorCallback(hxspi); #endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ } } 8006b82: bf00 nop 8006b84: 3710 adds r7, #16 8006b86: 46bd mov sp, r7 8006b88: bd80 pop {r7, pc} 08006b8a : * @brief DMA XSPI abort complete callback. * @param hdma : DMA handle * @retval None */ static void XSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) { 8006b8a: b580 push {r7, lr} 8006b8c: b084 sub sp, #16 8006b8e: af00 add r7, sp, #0 8006b90: 6078 str r0, [r7, #4] XSPI_HandleTypeDef *hxspi = (XSPI_HandleTypeDef *)(hdma->Parent); 8006b92: 687b ldr r3, [r7, #4] 8006b94: 6ddb ldr r3, [r3, #92] @ 0x5c 8006b96: 60fb str r3, [r7, #12] hxspi->XferCount = 0; 8006b98: 68fb ldr r3, [r7, #12] 8006b9a: 2200 movs r2, #0 8006b9c: 649a str r2, [r3, #72] @ 0x48 /* Check the state */ if (hxspi->State == HAL_XSPI_STATE_ABORT) 8006b9e: 68fb ldr r3, [r7, #12] 8006ba0: 6d5b ldr r3, [r3, #84] @ 0x54 8006ba2: f5b3 7f80 cmp.w r3, #256 @ 0x100 8006ba6: d123 bne.n 8006bf0 { /* DMA abort called by XSPI abort */ if (HAL_XSPI_GET_FLAG(hxspi, HAL_XSPI_FLAG_BUSY) != RESET) 8006ba8: 68fb ldr r3, [r7, #12] 8006baa: 681b ldr r3, [r3, #0] 8006bac: 6a1b ldr r3, [r3, #32] 8006bae: f003 0320 and.w r3, r3, #32 8006bb2: 2b00 cmp r3, #0 8006bb4: d014 beq.n 8006be0 { /* Clear transfer complete flag */ HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); 8006bb6: 68fb ldr r3, [r7, #12] 8006bb8: 681b ldr r3, [r3, #0] 8006bba: 2202 movs r2, #2 8006bbc: 625a str r2, [r3, #36] @ 0x24 /* Enable the transfer complete interrupts */ HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC); 8006bbe: 68fb ldr r3, [r7, #12] 8006bc0: 681b ldr r3, [r3, #0] 8006bc2: 681a ldr r2, [r3, #0] 8006bc4: 68fb ldr r3, [r7, #12] 8006bc6: 681b ldr r3, [r3, #0] 8006bc8: f442 3200 orr.w r2, r2, #131072 @ 0x20000 8006bcc: 601a str r2, [r3, #0] /* Perform an abort of the XSPI */ SET_BIT(hxspi->Instance->CR, XSPI_CR_ABORT); 8006bce: 68fb ldr r3, [r7, #12] 8006bd0: 681b ldr r3, [r3, #0] 8006bd2: 681a ldr r2, [r3, #0] 8006bd4: 68fb ldr r3, [r7, #12] 8006bd6: 681b ldr r3, [r3, #0] 8006bd8: f042 0202 orr.w r2, r2, #2 8006bdc: 601a str r2, [r3, #0] hxspi->ErrorCallback(hxspi); #else HAL_XSPI_ErrorCallback(hxspi); #endif /* defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ } } 8006bde: e00e b.n 8006bfe hxspi->State = HAL_XSPI_STATE_READY; 8006be0: 68fb ldr r3, [r7, #12] 8006be2: 2202 movs r2, #2 8006be4: 655a str r2, [r3, #84] @ 0x54 hxspi->AbortCpltCallback(hxspi); 8006be6: 68fb ldr r3, [r7, #12] 8006be8: 6e5b ldr r3, [r3, #100] @ 0x64 8006bea: 68f8 ldr r0, [r7, #12] 8006bec: 4798 blx r3 } 8006bee: e006 b.n 8006bfe hxspi->State = HAL_XSPI_STATE_READY; 8006bf0: 68fb ldr r3, [r7, #12] 8006bf2: 2202 movs r2, #2 8006bf4: 655a str r2, [r3, #84] @ 0x54 hxspi->ErrorCallback(hxspi); 8006bf6: 68fb ldr r3, [r7, #12] 8006bf8: 6e1b ldr r3, [r3, #96] @ 0x60 8006bfa: 68f8 ldr r0, [r7, #12] 8006bfc: 4798 blx r3 } 8006bfe: bf00 nop 8006c00: 3710 adds r7, #16 8006c02: 46bd mov sp, r7 8006c04: bd80 pop {r7, pc} 08006c06 : * @param Tickstart : Tick start value * @retval HAL status */ static HAL_StatusTypeDef XSPI_WaitFlagStateUntilTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout) { 8006c06: b580 push {r7, lr} 8006c08: b084 sub sp, #16 8006c0a: af00 add r7, sp, #0 8006c0c: 60f8 str r0, [r7, #12] 8006c0e: 60b9 str r1, [r7, #8] 8006c10: 603b str r3, [r7, #0] 8006c12: 4613 mov r3, r2 8006c14: 71fb strb r3, [r7, #7] /* Wait until flag is in expected state */ while ((HAL_XSPI_GET_FLAG(hxspi, Flag)) != State) 8006c16: e019 b.n 8006c4c { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8006c18: 69bb ldr r3, [r7, #24] 8006c1a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8006c1e: d015 beq.n 8006c4c { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 8006c20: f7fa f866 bl 8000cf0 8006c24: 4602 mov r2, r0 8006c26: 683b ldr r3, [r7, #0] 8006c28: 1ad3 subs r3, r2, r3 8006c2a: 69ba ldr r2, [r7, #24] 8006c2c: 429a cmp r2, r3 8006c2e: d302 bcc.n 8006c36 8006c30: 69bb ldr r3, [r7, #24] 8006c32: 2b00 cmp r3, #0 8006c34: d10a bne.n 8006c4c { hxspi->State = HAL_XSPI_STATE_READY; 8006c36: 68fb ldr r3, [r7, #12] 8006c38: 2202 movs r2, #2 8006c3a: 655a str r2, [r3, #84] @ 0x54 hxspi->ErrorCode |= HAL_XSPI_ERROR_TIMEOUT; 8006c3c: 68fb ldr r3, [r7, #12] 8006c3e: 6d9b ldr r3, [r3, #88] @ 0x58 8006c40: f043 0201 orr.w r2, r3, #1 8006c44: 68fb ldr r3, [r7, #12] 8006c46: 659a str r2, [r3, #88] @ 0x58 return HAL_TIMEOUT; 8006c48: 2303 movs r3, #3 8006c4a: e00e b.n 8006c6a while ((HAL_XSPI_GET_FLAG(hxspi, Flag)) != State) 8006c4c: 68fb ldr r3, [r7, #12] 8006c4e: 681b ldr r3, [r3, #0] 8006c50: 6a1a ldr r2, [r3, #32] 8006c52: 68bb ldr r3, [r7, #8] 8006c54: 4013 ands r3, r2 8006c56: 2b00 cmp r3, #0 8006c58: bf14 ite ne 8006c5a: 2301 movne r3, #1 8006c5c: 2300 moveq r3, #0 8006c5e: b2db uxtb r3, r3 8006c60: 461a mov r2, r3 8006c62: 79fb ldrb r3, [r7, #7] 8006c64: 429a cmp r2, r3 8006c66: d1d7 bne.n 8006c18 } } } return HAL_OK; 8006c68: 2300 movs r3, #0 } 8006c6a: 4618 mov r0, r3 8006c6c: 3710 adds r7, #16 8006c6e: 46bd mov sp, r7 8006c70: bd80 pop {r7, pc} ... 08006c74 : * @param hxspi : XSPI handle * @param pCmd : structure that contains the command configuration information * @retval HAL status */ static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, const XSPI_RegularCmdTypeDef *pCmd) { 8006c74: b480 push {r7} 8006c76: b089 sub sp, #36 @ 0x24 8006c78: af00 add r7, sp, #0 8006c7a: 6078 str r0, [r7, #4] 8006c7c: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8006c7e: 2300 movs r3, #0 8006c80: 77fb strb r3, [r7, #31] __IO uint32_t *tcr_reg; __IO uint32_t *ir_reg; __IO uint32_t *abr_reg; /* Re-initialize the value of the functional mode */ MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, 0U); 8006c82: 687b ldr r3, [r7, #4] 8006c84: 681b ldr r3, [r3, #0] 8006c86: 681a ldr r2, [r3, #0] 8006c88: 687b ldr r3, [r7, #4] 8006c8a: 681b ldr r3, [r3, #0] 8006c8c: f022 5240 bic.w r2, r2, #805306368 @ 0x30000000 8006c90: 601a str r2, [r3, #0] if (hxspi->Init.MemoryMode == HAL_XSPI_SINGLE_MEM) 8006c92: 687b ldr r3, [r7, #4] 8006c94: 689b ldr r3, [r3, #8] 8006c96: 2b00 cmp r3, #0 8006c98: d10a bne.n 8006cb0 { assert_param(IS_XSPI_IO_SELECT(pCmd->IOSelect)); MODIFY_REG(hxspi->Instance->CR, XSPI_CR_MSEL, pCmd->IOSelect); 8006c9a: 687b ldr r3, [r7, #4] 8006c9c: 681b ldr r3, [r3, #0] 8006c9e: 681b ldr r3, [r3, #0] 8006ca0: f023 4140 bic.w r1, r3, #3221225472 @ 0xc0000000 8006ca4: 683b ldr r3, [r7, #0] 8006ca6: 685a ldr r2, [r3, #4] 8006ca8: 687b ldr r3, [r7, #4] 8006caa: 681b ldr r3, [r3, #0] 8006cac: 430a orrs r2, r1 8006cae: 601a str r2, [r3, #0] } if (pCmd->OperationType == HAL_XSPI_OPTYPE_WRITE_CFG) 8006cb0: 683b ldr r3, [r7, #0] 8006cb2: 681b ldr r3, [r3, #0] 8006cb4: 2b02 cmp r3, #2 8006cb6: d114 bne.n 8006ce2 { ccr_reg = &(hxspi->Instance->WCCR); 8006cb8: 687b ldr r3, [r7, #4] 8006cba: 681b ldr r3, [r3, #0] 8006cbc: f503 73c0 add.w r3, r3, #384 @ 0x180 8006cc0: 61bb str r3, [r7, #24] tcr_reg = &(hxspi->Instance->WTCR); 8006cc2: 687b ldr r3, [r7, #4] 8006cc4: 681b ldr r3, [r3, #0] 8006cc6: f503 73c4 add.w r3, r3, #392 @ 0x188 8006cca: 617b str r3, [r7, #20] ir_reg = &(hxspi->Instance->WIR); 8006ccc: 687b ldr r3, [r7, #4] 8006cce: 681b ldr r3, [r3, #0] 8006cd0: f503 73c8 add.w r3, r3, #400 @ 0x190 8006cd4: 613b str r3, [r7, #16] abr_reg = &(hxspi->Instance->WABR); 8006cd6: 687b ldr r3, [r7, #4] 8006cd8: 681b ldr r3, [r3, #0] 8006cda: f503 73d0 add.w r3, r3, #416 @ 0x1a0 8006cde: 60fb str r3, [r7, #12] 8006ce0: e02c b.n 8006d3c } else if (pCmd->OperationType == HAL_XSPI_OPTYPE_WRAP_CFG) 8006ce2: 683b ldr r3, [r7, #0] 8006ce4: 681b ldr r3, [r3, #0] 8006ce6: 2b03 cmp r3, #3 8006ce8: d114 bne.n 8006d14 { ccr_reg = &(hxspi->Instance->WPCCR); 8006cea: 687b ldr r3, [r7, #4] 8006cec: 681b ldr r3, [r3, #0] 8006cee: f503 73a0 add.w r3, r3, #320 @ 0x140 8006cf2: 61bb str r3, [r7, #24] tcr_reg = &(hxspi->Instance->WPTCR); 8006cf4: 687b ldr r3, [r7, #4] 8006cf6: 681b ldr r3, [r3, #0] 8006cf8: f503 73a4 add.w r3, r3, #328 @ 0x148 8006cfc: 617b str r3, [r7, #20] ir_reg = &(hxspi->Instance->WPIR); 8006cfe: 687b ldr r3, [r7, #4] 8006d00: 681b ldr r3, [r3, #0] 8006d02: f503 73a8 add.w r3, r3, #336 @ 0x150 8006d06: 613b str r3, [r7, #16] abr_reg = &(hxspi->Instance->WPABR); 8006d08: 687b ldr r3, [r7, #4] 8006d0a: 681b ldr r3, [r3, #0] 8006d0c: f503 73b0 add.w r3, r3, #352 @ 0x160 8006d10: 60fb str r3, [r7, #12] 8006d12: e013 b.n 8006d3c } else { ccr_reg = &(hxspi->Instance->CCR); 8006d14: 687b ldr r3, [r7, #4] 8006d16: 681b ldr r3, [r3, #0] 8006d18: f503 7380 add.w r3, r3, #256 @ 0x100 8006d1c: 61bb str r3, [r7, #24] tcr_reg = &(hxspi->Instance->TCR); 8006d1e: 687b ldr r3, [r7, #4] 8006d20: 681b ldr r3, [r3, #0] 8006d22: f503 7384 add.w r3, r3, #264 @ 0x108 8006d26: 617b str r3, [r7, #20] ir_reg = &(hxspi->Instance->IR); 8006d28: 687b ldr r3, [r7, #4] 8006d2a: 681b ldr r3, [r3, #0] 8006d2c: f503 7388 add.w r3, r3, #272 @ 0x110 8006d30: 613b str r3, [r7, #16] abr_reg = &(hxspi->Instance->ABR); 8006d32: 687b ldr r3, [r7, #4] 8006d34: 681b ldr r3, [r3, #0] 8006d36: f503 7390 add.w r3, r3, #288 @ 0x120 8006d3a: 60fb str r3, [r7, #12] } /* Configure the CCR register with DQS mode */ *ccr_reg = pCmd->DQSMode; 8006d3c: 683b ldr r3, [r7, #0] 8006d3e: 6c9a ldr r2, [r3, #72] @ 0x48 8006d40: 69bb ldr r3, [r7, #24] 8006d42: 601a str r2, [r3, #0] if (pCmd->AlternateBytesMode != HAL_XSPI_ALT_BYTES_NONE) 8006d44: 683b ldr r3, [r7, #0] 8006d46: 6adb ldr r3, [r3, #44] @ 0x2c 8006d48: 2b00 cmp r3, #0 8006d4a: d012 beq.n 8006d72 { /* Configure the ABR register with alternate bytes value */ *abr_reg = pCmd->AlternateBytes; 8006d4c: 683b ldr r3, [r7, #0] 8006d4e: 6a9a ldr r2, [r3, #40] @ 0x28 8006d50: 68fb ldr r3, [r7, #12] 8006d52: 601a str r2, [r3, #0] /* Configure the CCR register with alternate bytes communication parameters */ MODIFY_REG((*ccr_reg), (XSPI_CCR_ABMODE | XSPI_CCR_ABDTR | XSPI_CCR_ABSIZE), 8006d54: 69bb ldr r3, [r7, #24] 8006d56: 681b ldr r3, [r3, #0] 8006d58: f423 127c bic.w r2, r3, #4128768 @ 0x3f0000 8006d5c: 683b ldr r3, [r7, #0] 8006d5e: 6ad9 ldr r1, [r3, #44] @ 0x2c 8006d60: 683b ldr r3, [r7, #0] 8006d62: 6b5b ldr r3, [r3, #52] @ 0x34 8006d64: 4319 orrs r1, r3 8006d66: 683b ldr r3, [r7, #0] 8006d68: 6b1b ldr r3, [r3, #48] @ 0x30 8006d6a: 430b orrs r3, r1 8006d6c: 431a orrs r2, r3 8006d6e: 69bb ldr r3, [r7, #24] 8006d70: 601a str r2, [r3, #0] (pCmd->AlternateBytesMode | pCmd->AlternateBytesDTRMode | pCmd->AlternateBytesWidth)); } /* Configure the TCR register with the number of dummy cycles */ MODIFY_REG((*tcr_reg), XSPI_TCR_DCYC, pCmd->DummyCycles); 8006d72: 697b ldr r3, [r7, #20] 8006d74: 681b ldr r3, [r3, #0] 8006d76: f023 021f bic.w r2, r3, #31 8006d7a: 683b ldr r3, [r7, #0] 8006d7c: 6c5b ldr r3, [r3, #68] @ 0x44 8006d7e: 431a orrs r2, r3 8006d80: 697b ldr r3, [r7, #20] 8006d82: 601a str r2, [r3, #0] if (pCmd->DataMode != HAL_XSPI_DATA_NONE) 8006d84: 683b ldr r3, [r7, #0] 8006d86: 6b9b ldr r3, [r3, #56] @ 0x38 8006d88: 2b00 cmp r3, #0 8006d8a: d009 beq.n 8006da0 { if (pCmd->OperationType == HAL_XSPI_OPTYPE_COMMON_CFG) 8006d8c: 683b ldr r3, [r7, #0] 8006d8e: 681b ldr r3, [r3, #0] 8006d90: 2b00 cmp r3, #0 8006d92: d105 bne.n 8006da0 { /* Configure the DLR register with the number of data */ hxspi->Instance->DLR = (pCmd->DataLength - 1U); 8006d94: 683b ldr r3, [r7, #0] 8006d96: 6bda ldr r2, [r3, #60] @ 0x3c 8006d98: 687b ldr r3, [r7, #4] 8006d9a: 681b ldr r3, [r3, #0] 8006d9c: 3a01 subs r2, #1 8006d9e: 641a str r2, [r3, #64] @ 0x40 } } /* Configure SSHIFT register to handle SDR/DTR data transfer */ if (pCmd->DataMode != HAL_XSPI_DATA_NONE) 8006da0: 683b ldr r3, [r7, #0] 8006da2: 6b9b ldr r3, [r3, #56] @ 0x38 8006da4: 2b00 cmp r3, #0 8006da6: d01e beq.n 8006de6 { if (pCmd->DataDTRMode == HAL_XSPI_DATA_DTR_ENABLE) 8006da8: 683b ldr r3, [r7, #0] 8006daa: 6c1b ldr r3, [r3, #64] @ 0x40 8006dac: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 8006db0: d10a bne.n 8006dc8 { /* Deactivate sample shifting when receiving data in DTR mode (DDTR=1) */ CLEAR_BIT(hxspi->Instance->TCR, XSPI_TCR_SSHIFT); 8006db2: 687b ldr r3, [r7, #4] 8006db4: 681b ldr r3, [r3, #0] 8006db6: f8d3 2108 ldr.w r2, [r3, #264] @ 0x108 8006dba: 687b ldr r3, [r7, #4] 8006dbc: 681b ldr r3, [r3, #0] 8006dbe: f022 4280 bic.w r2, r2, #1073741824 @ 0x40000000 8006dc2: f8c3 2108 str.w r2, [r3, #264] @ 0x108 8006dc6: e00e b.n 8006de6 } else if (hxspi->Init.SampleShifting == HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE) 8006dc8: 687b ldr r3, [r7, #4] 8006dca: 6a9b ldr r3, [r3, #40] @ 0x28 8006dcc: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8006dd0: d109 bne.n 8006de6 { /* Configure sample shifting */ SET_BIT(hxspi->Instance->TCR, XSPI_TCR_SSHIFT); 8006dd2: 687b ldr r3, [r7, #4] 8006dd4: 681b ldr r3, [r3, #0] 8006dd6: f8d3 2108 ldr.w r2, [r3, #264] @ 0x108 8006dda: 687b ldr r3, [r7, #4] 8006ddc: 681b ldr r3, [r3, #0] 8006dde: f042 4280 orr.w r2, r2, #1073741824 @ 0x40000000 8006de2: f8c3 2108 str.w r2, [r3, #264] @ 0x108 { /* Do nothing */ } } if (pCmd->InstructionMode != HAL_XSPI_INSTRUCTION_NONE) 8006de6: 683b ldr r3, [r7, #0] 8006de8: 68db ldr r3, [r3, #12] 8006dea: 2b00 cmp r3, #0 8006dec: d076 beq.n 8006edc { if (pCmd->AddressMode != HAL_XSPI_ADDRESS_NONE) 8006dee: 683b ldr r3, [r7, #0] 8006df0: 69db ldr r3, [r3, #28] 8006df2: 2b00 cmp r3, #0 8006df4: d044 beq.n 8006e80 { if (pCmd->DataMode != HAL_XSPI_DATA_NONE) 8006df6: 683b ldr r3, [r7, #0] 8006df8: 6b9b ldr r3, [r3, #56] @ 0x38 8006dfa: 2b00 cmp r3, #0 8006dfc: d01e beq.n 8006e3c { /* ---- Command with instruction, address and data ---- */ /* Configure the CCR register with all communication parameters */ MODIFY_REG((*ccr_reg), (XSPI_CCR_IMODE | XSPI_CCR_IDTR | XSPI_CCR_ISIZE | 8006dfe: 69bb ldr r3, [r7, #24] 8006e00: 681a ldr r2, [r3, #0] 8006e02: 4b5d ldr r3, [pc, #372] @ (8006f78 ) 8006e04: 4013 ands r3, r2 8006e06: 683a ldr r2, [r7, #0] 8006e08: 68d1 ldr r1, [r2, #12] 8006e0a: 683a ldr r2, [r7, #0] 8006e0c: 6952 ldr r2, [r2, #20] 8006e0e: 4311 orrs r1, r2 8006e10: 683a ldr r2, [r7, #0] 8006e12: 6912 ldr r2, [r2, #16] 8006e14: 4311 orrs r1, r2 8006e16: 683a ldr r2, [r7, #0] 8006e18: 69d2 ldr r2, [r2, #28] 8006e1a: 4311 orrs r1, r2 8006e1c: 683a ldr r2, [r7, #0] 8006e1e: 6a52 ldr r2, [r2, #36] @ 0x24 8006e20: 4311 orrs r1, r2 8006e22: 683a ldr r2, [r7, #0] 8006e24: 6a12 ldr r2, [r2, #32] 8006e26: 4311 orrs r1, r2 8006e28: 683a ldr r2, [r7, #0] 8006e2a: 6b92 ldr r2, [r2, #56] @ 0x38 8006e2c: 4311 orrs r1, r2 8006e2e: 683a ldr r2, [r7, #0] 8006e30: 6c12 ldr r2, [r2, #64] @ 0x40 8006e32: 430a orrs r2, r1 8006e34: 431a orrs r2, r3 8006e36: 69bb ldr r3, [r7, #24] 8006e38: 601a str r2, [r3, #0] 8006e3a: e017 b.n 8006e6c else { /* ---- Command with instruction and address ---- */ /* Configure the CCR register with all communication parameters */ MODIFY_REG((*ccr_reg), (XSPI_CCR_IMODE | XSPI_CCR_IDTR | XSPI_CCR_ISIZE | 8006e3c: 69bb ldr r3, [r7, #24] 8006e3e: 681a ldr r2, [r3, #0] 8006e40: 4b4e ldr r3, [pc, #312] @ (8006f7c ) 8006e42: 4013 ands r3, r2 8006e44: 683a ldr r2, [r7, #0] 8006e46: 68d1 ldr r1, [r2, #12] 8006e48: 683a ldr r2, [r7, #0] 8006e4a: 6952 ldr r2, [r2, #20] 8006e4c: 4311 orrs r1, r2 8006e4e: 683a ldr r2, [r7, #0] 8006e50: 6912 ldr r2, [r2, #16] 8006e52: 4311 orrs r1, r2 8006e54: 683a ldr r2, [r7, #0] 8006e56: 69d2 ldr r2, [r2, #28] 8006e58: 4311 orrs r1, r2 8006e5a: 683a ldr r2, [r7, #0] 8006e5c: 6a52 ldr r2, [r2, #36] @ 0x24 8006e5e: 4311 orrs r1, r2 8006e60: 683a ldr r2, [r7, #0] 8006e62: 6a12 ldr r2, [r2, #32] 8006e64: 430a orrs r2, r1 8006e66: 431a orrs r2, r3 8006e68: 69bb ldr r3, [r7, #24] 8006e6a: 601a str r2, [r3, #0] XSPI_CCR_ADMODE | XSPI_CCR_ADDTR | XSPI_CCR_ADSIZE), (pCmd->InstructionMode | pCmd->InstructionDTRMode | pCmd->InstructionWidth | pCmd->AddressMode | pCmd->AddressDTRMode | pCmd->AddressWidth)); } /* Configure the IR register with the instruction value */ *ir_reg = pCmd->Instruction; 8006e6c: 683b ldr r3, [r7, #0] 8006e6e: 689a ldr r2, [r3, #8] 8006e70: 693b ldr r3, [r7, #16] 8006e72: 601a str r2, [r3, #0] /* Configure the AR register with the address value */ hxspi->Instance->AR = pCmd->Address; 8006e74: 687b ldr r3, [r7, #4] 8006e76: 681b ldr r3, [r3, #0] 8006e78: 683a ldr r2, [r7, #0] 8006e7a: 6992 ldr r2, [r2, #24] 8006e7c: 649a str r2, [r3, #72] @ 0x48 8006e7e: e065 b.n 8006f4c assert_param(IS_XSPI_PROG_ADDR(hxspi->Instance->AR, pCmd->Address)); } } else { if (pCmd->DataMode != HAL_XSPI_DATA_NONE) 8006e80: 683b ldr r3, [r7, #0] 8006e82: 6b9b ldr r3, [r3, #56] @ 0x38 8006e84: 2b00 cmp r3, #0 8006e86: d015 beq.n 8006eb4 { /* ---- Command with instruction and data ---- */ /* Configure the CCR register with all communication parameters */ MODIFY_REG((*ccr_reg), (XSPI_CCR_IMODE | XSPI_CCR_IDTR | XSPI_CCR_ISIZE | 8006e88: 69bb ldr r3, [r7, #24] 8006e8a: 681a ldr r2, [r3, #0] 8006e8c: 4b3c ldr r3, [pc, #240] @ (8006f80 ) 8006e8e: 4013 ands r3, r2 8006e90: 683a ldr r2, [r7, #0] 8006e92: 68d1 ldr r1, [r2, #12] 8006e94: 683a ldr r2, [r7, #0] 8006e96: 6952 ldr r2, [r2, #20] 8006e98: 4311 orrs r1, r2 8006e9a: 683a ldr r2, [r7, #0] 8006e9c: 6912 ldr r2, [r2, #16] 8006e9e: 4311 orrs r1, r2 8006ea0: 683a ldr r2, [r7, #0] 8006ea2: 6b92 ldr r2, [r2, #56] @ 0x38 8006ea4: 4311 orrs r1, r2 8006ea6: 683a ldr r2, [r7, #0] 8006ea8: 6c12 ldr r2, [r2, #64] @ 0x40 8006eaa: 430a orrs r2, r1 8006eac: 431a orrs r2, r3 8006eae: 69bb ldr r3, [r7, #24] 8006eb0: 601a str r2, [r3, #0] 8006eb2: e00e b.n 8006ed2 else { /* ---- Command with only instruction ---- */ /* Configure the CCR register with all communication parameters */ MODIFY_REG((*ccr_reg), (XSPI_CCR_IMODE | XSPI_CCR_IDTR | XSPI_CCR_ISIZE), 8006eb4: 69bb ldr r3, [r7, #24] 8006eb6: 681b ldr r3, [r3, #0] 8006eb8: f023 023f bic.w r2, r3, #63 @ 0x3f 8006ebc: 683b ldr r3, [r7, #0] 8006ebe: 68d9 ldr r1, [r3, #12] 8006ec0: 683b ldr r3, [r7, #0] 8006ec2: 695b ldr r3, [r3, #20] 8006ec4: 4319 orrs r1, r3 8006ec6: 683b ldr r3, [r7, #0] 8006ec8: 691b ldr r3, [r3, #16] 8006eca: 430b orrs r3, r1 8006ecc: 431a orrs r2, r3 8006ece: 69bb ldr r3, [r7, #24] 8006ed0: 601a str r2, [r3, #0] (pCmd->InstructionMode | pCmd->InstructionDTRMode | pCmd->InstructionWidth)); } /* Configure the IR register with the instruction value */ *ir_reg = pCmd->Instruction; 8006ed2: 683b ldr r3, [r7, #0] 8006ed4: 689a ldr r2, [r3, #8] 8006ed6: 693b ldr r3, [r7, #16] 8006ed8: 601a str r2, [r3, #0] 8006eda: e037 b.n 8006f4c } } else { if (pCmd->AddressMode != HAL_XSPI_ADDRESS_NONE) 8006edc: 683b ldr r3, [r7, #0] 8006ede: 69db ldr r3, [r3, #28] 8006ee0: 2b00 cmp r3, #0 8006ee2: d02e beq.n 8006f42 { if (pCmd->DataMode != HAL_XSPI_DATA_NONE) 8006ee4: 683b ldr r3, [r7, #0] 8006ee6: 6b9b ldr r3, [r3, #56] @ 0x38 8006ee8: 2b00 cmp r3, #0 8006eea: d015 beq.n 8006f18 { /* ---- Command with address and data ---- */ /* Configure the CCR register with all communication parameters */ MODIFY_REG((*ccr_reg), (XSPI_CCR_ADMODE | XSPI_CCR_ADDTR | XSPI_CCR_ADSIZE | 8006eec: 69bb ldr r3, [r7, #24] 8006eee: 681a ldr r2, [r3, #0] 8006ef0: 4b24 ldr r3, [pc, #144] @ (8006f84 ) 8006ef2: 4013 ands r3, r2 8006ef4: 683a ldr r2, [r7, #0] 8006ef6: 69d1 ldr r1, [r2, #28] 8006ef8: 683a ldr r2, [r7, #0] 8006efa: 6a52 ldr r2, [r2, #36] @ 0x24 8006efc: 4311 orrs r1, r2 8006efe: 683a ldr r2, [r7, #0] 8006f00: 6a12 ldr r2, [r2, #32] 8006f02: 4311 orrs r1, r2 8006f04: 683a ldr r2, [r7, #0] 8006f06: 6b92 ldr r2, [r2, #56] @ 0x38 8006f08: 4311 orrs r1, r2 8006f0a: 683a ldr r2, [r7, #0] 8006f0c: 6c12 ldr r2, [r2, #64] @ 0x40 8006f0e: 430a orrs r2, r1 8006f10: 431a orrs r2, r3 8006f12: 69bb ldr r3, [r7, #24] 8006f14: 601a str r2, [r3, #0] 8006f16: e00e b.n 8006f36 else { /* ---- Command with only address ---- */ /* Configure the CCR register with all communication parameters */ MODIFY_REG((*ccr_reg), (XSPI_CCR_ADMODE | XSPI_CCR_ADDTR | XSPI_CCR_ADSIZE), 8006f18: 69bb ldr r3, [r7, #24] 8006f1a: 681b ldr r3, [r3, #0] 8006f1c: f423 527c bic.w r2, r3, #16128 @ 0x3f00 8006f20: 683b ldr r3, [r7, #0] 8006f22: 69d9 ldr r1, [r3, #28] 8006f24: 683b ldr r3, [r7, #0] 8006f26: 6a5b ldr r3, [r3, #36] @ 0x24 8006f28: 4319 orrs r1, r3 8006f2a: 683b ldr r3, [r7, #0] 8006f2c: 6a1b ldr r3, [r3, #32] 8006f2e: 430b orrs r3, r1 8006f30: 431a orrs r2, r3 8006f32: 69bb ldr r3, [r7, #24] 8006f34: 601a str r2, [r3, #0] (pCmd->AddressMode | pCmd->AddressDTRMode | pCmd->AddressWidth)); } /* Configure the AR register with the instruction value */ hxspi->Instance->AR = pCmd->Address; 8006f36: 687b ldr r3, [r7, #4] 8006f38: 681b ldr r3, [r3, #0] 8006f3a: 683a ldr r2, [r7, #0] 8006f3c: 6992 ldr r2, [r2, #24] 8006f3e: 649a str r2, [r3, #72] @ 0x48 8006f40: e004 b.n 8006f4c } } else { /* ---- Invalid command configuration (no instruction, no address) ---- */ status = HAL_ERROR; 8006f42: 2301 movs r3, #1 8006f44: 77fb strb r3, [r7, #31] hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; 8006f46: 687b ldr r3, [r7, #4] 8006f48: 2208 movs r2, #8 8006f4a: 659a str r2, [r3, #88] @ 0x58 } } if (pCmd->DataMode != HAL_XSPI_DATA_NONE) 8006f4c: 683b ldr r3, [r7, #0] 8006f4e: 6b9b ldr r3, [r3, #56] @ 0x38 8006f50: 2b00 cmp r3, #0 8006f52: d009 beq.n 8006f68 { if (pCmd->OperationType == HAL_XSPI_OPTYPE_COMMON_CFG) 8006f54: 683b ldr r3, [r7, #0] 8006f56: 681b ldr r3, [r3, #0] 8006f58: 2b00 cmp r3, #0 8006f5a: d105 bne.n 8006f68 { /* Configure the DLR register with the number of data */ hxspi->Instance->DLR = (pCmd->DataLength - 1U); 8006f5c: 683b ldr r3, [r7, #0] 8006f5e: 6bda ldr r2, [r3, #60] @ 0x3c 8006f60: 687b ldr r3, [r7, #4] 8006f62: 681b ldr r3, [r3, #0] 8006f64: 3a01 subs r2, #1 8006f66: 641a str r2, [r3, #64] @ 0x40 /* Verify if programmed data fit with requirement of Reference Manual 28.5 chapter */ assert_param(IS_XSPI_PROG_DATA(hxspi->Instance->DLR, (pCmd->DataLength - 1U))); } } return status; 8006f68: 7ffb ldrb r3, [r7, #31] } 8006f6a: 4618 mov r0, r3 8006f6c: 3724 adds r7, #36 @ 0x24 8006f6e: 46bd mov sp, r7 8006f70: f85d 7b04 ldr.w r7, [sp], #4 8006f74: 4770 bx lr 8006f76: bf00 nop 8006f78: f0ffc0c0 .word 0xf0ffc0c0 8006f7c: ffffc0c0 .word 0xffffc0c0 8006f80: f0ffffc0 .word 0xf0ffffc0 8006f84: f0ffc0ff .word 0xf0ffc0ff 08006f88 : * @param instance_nb : number of the instance * @param pCfg : configuration of the IO Manager for the instance * @retval HAL status */ static void XSPIM_GetConfig(uint8_t instance_nb, XSPIM_CfgTypeDef *pCfg) { 8006f88: b480 push {r7} 8006f8a: b085 sub sp, #20 8006f8c: af00 add r7, sp, #0 8006f8e: 4603 mov r3, r0 8006f90: 6039 str r1, [r7, #0] 8006f92: 71fb strb r3, [r7, #7] uint32_t mux; uint32_t mode; if (instance_nb == 1U) 8006f94: 79fb ldrb r3, [r7, #7] 8006f96: 2b01 cmp r3, #1 8006f98: d124 bne.n 8006fe4 { if ((XSPIM->CR & XSPIM_CR_MODE) == 0U) 8006f9a: 4b2c ldr r3, [pc, #176] @ (800704c ) 8006f9c: 681b ldr r3, [r3, #0] 8006f9e: f003 0302 and.w r3, r3, #2 8006fa2: 2b00 cmp r3, #0 8006fa4: d103 bne.n 8006fae { pCfg->IOPort = HAL_XSPIM_IOPORT_1; 8006fa6: 683b ldr r3, [r7, #0] 8006fa8: 2200 movs r2, #0 8006faa: 605a str r2, [r3, #4] 8006fac: e002 b.n 8006fb4 } else { pCfg->IOPort = HAL_XSPIM_IOPORT_2; 8006fae: 683b ldr r3, [r7, #0] 8006fb0: 2201 movs r2, #1 8006fb2: 605a str r2, [r3, #4] } if ((XSPIM->CR & XSPIM_CR_CSSEL_OVR_EN) != XSPIM_CR_CSSEL_OVR_EN) 8006fb4: 4b25 ldr r3, [pc, #148] @ (800704c ) 8006fb6: 681b ldr r3, [r3, #0] 8006fb8: f003 0310 and.w r3, r3, #16 8006fbc: 2b10 cmp r3, #16 8006fbe: d003 beq.n 8006fc8 { pCfg->nCSOverride = HAL_XSPI_CSSEL_OVR_DISABLED; 8006fc0: 683b ldr r3, [r7, #0] 8006fc2: 2200 movs r2, #0 8006fc4: 601a str r2, [r3, #0] else { pCfg->nCSOverride = HAL_XSPI_CSSEL_OVR_NCS1; } } } 8006fc6: e03a b.n 800703e else if ((XSPIM->CR & XSPIM_CR_CSSEL_OVR_O1) == XSPIM_CR_CSSEL_OVR_O1) 8006fc8: 4b20 ldr r3, [pc, #128] @ (800704c ) 8006fca: 681b ldr r3, [r3, #0] 8006fcc: f003 0320 and.w r3, r3, #32 8006fd0: 2b20 cmp r3, #32 8006fd2: d103 bne.n 8006fdc pCfg->nCSOverride = HAL_XSPI_CSSEL_OVR_NCS2; 8006fd4: 683b ldr r3, [r7, #0] 8006fd6: 2270 movs r2, #112 @ 0x70 8006fd8: 601a str r2, [r3, #0] } 8006fda: e030 b.n 800703e pCfg->nCSOverride = HAL_XSPI_CSSEL_OVR_NCS1; 8006fdc: 683b ldr r3, [r7, #0] 8006fde: 2210 movs r2, #16 8006fe0: 601a str r2, [r3, #0] } 8006fe2: e02c b.n 800703e mux = (XSPIM->CR & XSPIM_CR_MUXEN); 8006fe4: 4b19 ldr r3, [pc, #100] @ (800704c ) 8006fe6: 681b ldr r3, [r3, #0] 8006fe8: f003 0301 and.w r3, r3, #1 8006fec: 60fb str r3, [r7, #12] mode = ((XSPIM->CR & XSPIM_CR_MODE) >> XSPIM_CR_MODE_Pos); 8006fee: 4b17 ldr r3, [pc, #92] @ (800704c ) 8006ff0: 681b ldr r3, [r3, #0] 8006ff2: 085b lsrs r3, r3, #1 8006ff4: f003 0301 and.w r3, r3, #1 8006ff8: 60bb str r3, [r7, #8] if (mux != mode) 8006ffa: 68fa ldr r2, [r7, #12] 8006ffc: 68bb ldr r3, [r7, #8] 8006ffe: 429a cmp r2, r3 8007000: d003 beq.n 800700a pCfg->IOPort = HAL_XSPIM_IOPORT_1; 8007002: 683b ldr r3, [r7, #0] 8007004: 2200 movs r2, #0 8007006: 605a str r2, [r3, #4] 8007008: e002 b.n 8007010 pCfg->IOPort = HAL_XSPIM_IOPORT_2; 800700a: 683b ldr r3, [r7, #0] 800700c: 2201 movs r2, #1 800700e: 605a str r2, [r3, #4] if ((XSPIM->CR & XSPIM_CR_CSSEL_OVR_EN) != XSPIM_CR_CSSEL_OVR_EN) 8007010: 4b0e ldr r3, [pc, #56] @ (800704c ) 8007012: 681b ldr r3, [r3, #0] 8007014: f003 0310 and.w r3, r3, #16 8007018: 2b10 cmp r3, #16 800701a: d003 beq.n 8007024 pCfg->nCSOverride = HAL_XSPI_CSSEL_OVR_DISABLED; 800701c: 683b ldr r3, [r7, #0] 800701e: 2200 movs r2, #0 8007020: 601a str r2, [r3, #0] } 8007022: e00c b.n 800703e else if ((XSPIM->CR & XSPIM_CR_CSSEL_OVR_O2) == XSPIM_CR_CSSEL_OVR_O2) 8007024: 4b09 ldr r3, [pc, #36] @ (800704c ) 8007026: 681b ldr r3, [r3, #0] 8007028: f003 0340 and.w r3, r3, #64 @ 0x40 800702c: 2b40 cmp r3, #64 @ 0x40 800702e: d103 bne.n 8007038 pCfg->nCSOverride = HAL_XSPI_CSSEL_OVR_NCS2; 8007030: 683b ldr r3, [r7, #0] 8007032: 2270 movs r2, #112 @ 0x70 8007034: 601a str r2, [r3, #0] } 8007036: e002 b.n 800703e pCfg->nCSOverride = HAL_XSPI_CSSEL_OVR_NCS1; 8007038: 683b ldr r3, [r7, #0] 800703a: 2210 movs r2, #16 800703c: 601a str r2, [r3, #0] } 800703e: bf00 nop 8007040: 3714 adds r7, #20 8007042: 46bd mov sp, r7 8007044: f85d 7b04 ldr.w r7, [sp], #4 8007048: 4770 bx lr 800704a: bf00 nop 800704c: 5200b400 .word 0x5200b400 08007050 : /** * @brief Boots the application by mapping the memory and jumping to the application. * @retval BOOTStatus_TypeDef Status of the operation. */ BOOTStatus_TypeDef BOOT_Application(void) { 8007050: b580 push {r7, lr} 8007052: b082 sub sp, #8 8007054: af00 add r7, sp, #0 BOOTStatus_TypeDef retr; /* Mount the memory */ retr = MapMemory(); 8007056: f000 f80e bl 8007076 800705a: 4603 mov r3, r0 800705c: 71fb strb r3, [r7, #7] if (BOOT_OK == retr) 800705e: 79fb ldrb r3, [r7, #7] 8007060: 2b00 cmp r3, #0 8007062: d103 bne.n 800706c { /* Jump on the application */ retr = JumpToApplication(); 8007064: f000 f836 bl 80070d4 8007068: 4603 mov r3, r0 800706a: 71fb strb r3, [r7, #7] } return retr; 800706c: 79fb ldrb r3, [r7, #7] } 800706e: 4618 mov r0, r3 8007070: 3708 adds r7, #8 8007072: 46bd mov sp, r7 8007074: bd80 pop {r7, pc} 08007076 : /** * @brief Maps the external memory. * @retval BOOTStatus_TypeDef Status of the operation. */ BOOTStatus_TypeDef MapMemory(void) { 8007076: b580 push {r7, lr} 8007078: b082 sub sp, #8 800707a: af00 add r7, sp, #0 BOOTStatus_TypeDef retr = BOOT_OK; 800707c: 2300 movs r3, #0 800707e: 71fb strb r3, [r7, #7] /* Map all the memory */ for (uint8_t index = 0; index < (sizeof(extmem_list_config) / sizeof(EXTMEM_DefinitionTypeDef)); index++) 8007080: 2300 movs r3, #0 8007082: 71bb strb r3, [r7, #6] 8007084: e01d b.n 80070c2 { switch (EXTMEM_MemoryMappedMode(index, EXTMEM_ENABLE)) 8007086: 79bb ldrb r3, [r7, #6] 8007088: 2100 movs r1, #0 800708a: 4618 mov r0, r3 800708c: f000 f96c bl 8007368 8007090: 4603 mov r3, r0 8007092: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8007096: d002 beq.n 800709e 8007098: 2b00 cmp r3, #0 800709a: d00e beq.n 80070ba 800709c: e00a b.n 80070b4 { case EXTMEM_ERROR_NOTSUPPORTED : if (EXTMEM_MEMORY_BOOTXIP == index) 800709e: 79bb ldrb r3, [r7, #6] 80070a0: 2b00 cmp r3, #0 80070a2: d102 bne.n 80070aa { retr = BOOT_ERROR_INCOMPATIBLEMEMORY; 80070a4: 2304 movs r3, #4 80070a6: 71fb strb r3, [r7, #7] { /* We consider the memory will be not used any more */ EXTMEM_DeInit(index); } case EXTMEM_OK: break; 80070a8: e007 b.n 80070ba EXTMEM_DeInit(index); 80070aa: 79bb ldrb r3, [r7, #6] 80070ac: 4618 mov r0, r3 80070ae: f000 f921 bl 80072f4 break; 80070b2: e002 b.n 80070ba default : retr = BOOT_ERROR_MAPPEDMODEFAIL; 80070b4: 2303 movs r3, #3 80070b6: 71fb strb r3, [r7, #7] break; 80070b8: e000 b.n 80070bc break; 80070ba: bf00 nop for (uint8_t index = 0; index < (sizeof(extmem_list_config) / sizeof(EXTMEM_DefinitionTypeDef)); index++) 80070bc: 79bb ldrb r3, [r7, #6] 80070be: 3301 adds r3, #1 80070c0: 71bb strb r3, [r7, #6] 80070c2: 79bb ldrb r3, [r7, #6] 80070c4: 2b01 cmp r3, #1 80070c6: d9de bls.n 8007086 } } return retr; 80070c8: 79fb ldrb r3, [r7, #7] } 80070ca: 4618 mov r0, r3 80070cc: 3708 adds r7, #8 80070ce: 46bd mov sp, r7 80070d0: bd80 pop {r7, pc} ... 080070d4 : /** * @brief Jumps to the application using its vector table. * @retval BOOTStatus_TypeDef Status of the operation. */ BOOTStatus_TypeDef JumpToApplication(void) { 80070d4: b590 push {r4, r7, lr} 80070d6: b091 sub sp, #68 @ 0x44 80070d8: af00 add r7, sp, #0 80070da: f107 0340 add.w r3, r7, #64 @ 0x40 80070de: 3b40 subs r3, #64 @ 0x40 80070e0: 331f adds r3, #31 80070e2: 095b lsrs r3, r3, #5 80070e4: 015c lsls r4, r3, #5 uint32_t primask_bit; typedef void (*pFunction)(void); static pFunction JumpToApp; uint32_t Application_vector; if (EXTMEM_OK != EXTMEM_GetMapAddress(EXTMEM_MEMORY_BOOTXIP, &Application_vector)) 80070e6: f107 032c add.w r3, r7, #44 @ 0x2c 80070ea: 4619 mov r1, r3 80070ec: 2000 movs r0, #0 80070ee: f000 f9ad bl 800744c 80070f2: 4603 mov r3, r0 80070f4: 2b00 cmp r3, #0 80070f6: d001 beq.n 80070fc { return BOOT_ERROR_INCOMPATIBLEMEMORY; 80070f8: 2304 movs r3, #4 80070fa: e08b b.n 8007214 } /* Suspend SysTick */ HAL_SuspendTick(); 80070fc: f7f9 fe28 bl 8000d50 #if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) /* if I-Cache is enabled, disable I-Cache-----------------------------------*/ if (SCB->CCR & SCB_CCR_IC_Msk) 8007100: 4b46 ldr r3, [pc, #280] @ (800721c ) 8007102: 695b ldr r3, [r3, #20] 8007104: f403 3300 and.w r3, r3, #131072 @ 0x20000 8007108: 2b00 cmp r3, #0 800710a: d016 beq.n 800713a __ASM volatile ("dsb 0xF":::"memory"); 800710c: f3bf 8f4f dsb sy } 8007110: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8007112: f3bf 8f6f isb sy } 8007116: bf00 nop SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ 8007118: 4b40 ldr r3, [pc, #256] @ (800721c ) 800711a: 695b ldr r3, [r3, #20] 800711c: 4a3f ldr r2, [pc, #252] @ (800721c ) 800711e: f423 3300 bic.w r3, r3, #131072 @ 0x20000 8007122: 6153 str r3, [r2, #20] SCB->ICIALLU = 0UL; /* invalidate I-Cache */ 8007124: 4b3d ldr r3, [pc, #244] @ (800721c ) 8007126: 2200 movs r2, #0 8007128: f8c3 2250 str.w r2, [r3, #592] @ 0x250 __ASM volatile ("dsb 0xF":::"memory"); 800712c: f3bf 8f4f dsb sy } 8007130: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8007132: f3bf 8f6f isb sy } 8007136: bf00 nop } 8007138: bf00 nop } #endif /* __ICACHE_PRESENT */ #if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) /* if D-Cache is enabled, disable D-Cache-----------------------------------*/ if (SCB->CCR & SCB_CCR_DC_Msk) 800713a: 4b38 ldr r3, [pc, #224] @ (800721c ) 800713c: 695b ldr r3, [r3, #20] 800713e: f403 3380 and.w r3, r3, #65536 @ 0x10000 8007142: 2b00 cmp r3, #0 8007144: d043 beq.n 80071ce #if ((defined(__GNUC__) || defined(__clang__)) && !defined(__OPTIMIZE__)) __ALIGNED(__SCB_DCACHE_LINE_SIZE) #endif ; SCB->CSSELR = 0U; /* select Level 1 data cache */ 8007146: 4b35 ldr r3, [pc, #212] @ (800721c ) 8007148: 2200 movs r2, #0 800714a: f8c3 2084 str.w r2, [r3, #132] @ 0x84 __ASM volatile ("dsb 0xF":::"memory"); 800714e: f3bf 8f4f dsb sy } 8007152: bf00 nop __DSB(); SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ 8007154: 4b31 ldr r3, [pc, #196] @ (800721c ) 8007156: 695b ldr r3, [r3, #20] 8007158: 4a30 ldr r2, [pc, #192] @ (800721c ) 800715a: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800715e: 6153 str r3, [r2, #20] __ASM volatile ("dsb 0xF":::"memory"); 8007160: f3bf 8f4f dsb sy } 8007164: bf00 nop /* As we can't align the stack to the cache line size, invalidate each of the variables */ SCB->DCCIMVAC = (uint32_t)&locals.sets; SCB->DCCIMVAC = (uint32_t)&locals.ways; SCB->DCCIMVAC = (uint32_t)&locals.ccsidr; #else SCB->DCCIMVAC = (uint32_t)&locals; 8007166: 4b2d ldr r3, [pc, #180] @ (800721c ) 8007168: 4622 mov r2, r4 800716a: f8c3 2270 str.w r2, [r3, #624] @ 0x270 __ASM volatile ("dsb 0xF":::"memory"); 800716e: f3bf 8f4f dsb sy } 8007172: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8007174: f3bf 8f6f isb sy } 8007178: bf00 nop #endif __DSB(); __ISB(); #endif locals.ccsidr = SCB->CCSIDR; 800717a: 4b28 ldr r3, [pc, #160] @ (800721c ) 800717c: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8007180: 6023 str r3, [r4, #0] /* clean & invalidate D-Cache */ locals.sets = (uint32_t)(CCSIDR_SETS(locals.ccsidr)); 8007182: 6823 ldr r3, [r4, #0] 8007184: 0b5b lsrs r3, r3, #13 8007186: f3c3 030e ubfx r3, r3, #0, #15 800718a: 6063 str r3, [r4, #4] do { locals.ways = (uint32_t)(CCSIDR_WAYS(locals.ccsidr)); 800718c: 6823 ldr r3, [r4, #0] 800718e: 08db lsrs r3, r3, #3 8007190: f3c3 0309 ubfx r3, r3, #0, #10 8007194: 60a3 str r3, [r4, #8] do { SCB->DCCISW = (((locals.sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | 8007196: 6863 ldr r3, [r4, #4] 8007198: 015a lsls r2, r3, #5 800719a: f643 73e0 movw r3, #16352 @ 0x3fe0 800719e: 4013 ands r3, r2 ((locals.ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); 80071a0: 68a2 ldr r2, [r4, #8] 80071a2: 0792 lsls r2, r2, #30 SCB->DCCISW = (((locals.sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | 80071a4: 491d ldr r1, [pc, #116] @ (800721c ) 80071a6: 4313 orrs r3, r2 80071a8: f8c1 3274 str.w r3, [r1, #628] @ 0x274 #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (locals.ways-- != 0U); 80071ac: 68a3 ldr r3, [r4, #8] 80071ae: 1e5a subs r2, r3, #1 80071b0: 60a2 str r2, [r4, #8] 80071b2: 2b00 cmp r3, #0 80071b4: d1ef bne.n 8007196 } while(locals.sets-- != 0U); 80071b6: 6863 ldr r3, [r4, #4] 80071b8: 1e5a subs r2, r3, #1 80071ba: 6062 str r2, [r4, #4] 80071bc: 2b00 cmp r3, #0 80071be: d1e5 bne.n 800718c __ASM volatile ("dsb 0xF":::"memory"); 80071c0: f3bf 8f4f dsb sy } 80071c4: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 80071c6: f3bf 8f6f isb sy } 80071ca: bf00 nop __DSB(); __ISB(); #endif } 80071cc: bf00 nop */ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile ("MRS %0, primask" : "=r" (result) ); 80071ce: f3ef 8310 mrs r3, PRIMASK 80071d2: 633b str r3, [r7, #48] @ 0x30 return(result); 80071d4: 6b3b ldr r3, [r7, #48] @ 0x30 SCB_DisableDCache(); } #endif /* __DCACHE_PRESENT */ /* Initialize user application's Stack Pointer & Jump to user application */ primask_bit = __get_PRIMASK(); 80071d6: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("cpsid i" : : : "memory"); 80071d8: b672 cpsid i } 80071da: bf00 nop __disable_irq(); /* Apply offsets for image location and vector table offset */ Application_vector += EXTMEM_XIP_IMAGE_OFFSET + EXTMEM_HEADER_OFFSET; 80071dc: 6afb ldr r3, [r7, #44] @ 0x2c 80071de: 62fb str r3, [r7, #44] @ 0x2c SCB->VTOR = (uint32_t)Application_vector; 80071e0: 4a0e ldr r2, [pc, #56] @ (800721c ) 80071e2: 6afb ldr r3, [r7, #44] @ 0x2c 80071e4: 6093 str r3, [r2, #8] JumpToApp = (pFunction)(*(__IO uint32_t *)(Application_vector + 4u)); 80071e6: 6afb ldr r3, [r7, #44] @ 0x2c 80071e8: 3304 adds r3, #4 80071ea: 681b ldr r3, [r3, #0] 80071ec: 461a mov r2, r3 80071ee: 4b0c ldr r3, [pc, #48] @ (8007220 ) 80071f0: 601a str r2, [r3, #0] #elif (defined(__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) /* on ARM v8m, set MSPLIM before setting MSP to avoid unwanted stack overflow faults */ __set_MSPLIM(0x00000000); #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8_1M_MAIN__ or __ARM_ARCH_8M_BASE__ */ __set_MSP(*(__IO uint32_t *) Application_vector); 80071f2: 6afb ldr r3, [r7, #44] @ 0x2c 80071f4: 681b ldr r3, [r3, #0] 80071f6: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); 80071f8: 6b7b ldr r3, [r7, #52] @ 0x34 80071fa: f383 8808 msr MSP, r3 } 80071fe: bf00 nop 8007200: 6bfb ldr r3, [r7, #60] @ 0x3c 8007202: 63bb str r3, [r7, #56] @ 0x38 \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8007204: 6bbb ldr r3, [r7, #56] @ 0x38 8007206: f383 8810 msr PRIMASK, r3 } 800720a: bf00 nop /* Re-enable the interrupts */ __set_PRIMASK(primask_bit); JumpToApp(); 800720c: 4b04 ldr r3, [pc, #16] @ (8007220 ) 800720e: 681b ldr r3, [r3, #0] 8007210: 4798 blx r3 return BOOT_OK; 8007212: 2300 movs r3, #0 } 8007214: 4618 mov r0, r3 8007216: 3744 adds r7, #68 @ 0x44 8007218: 46bd mov sp, r7 800721a: bd90 pop {r4, r7, pc} 800721c: e000ed00 .word 0xe000ed00 8007220: 24000168 .word 0x24000168 08007224 : * @param MemId Memory identifier. * @param ClockInput Clock input value for the memory. * @retval EXTMEM_StatusTypeDef Status of the operation. */ EXTMEM_StatusTypeDef EXTMEM_Init(uint32_t MemId, uint32_t ClockInput) { 8007224: b580 push {r7, lr} 8007226: b084 sub sp, #16 8007228: af00 add r7, sp, #0 800722a: 6078 str r0, [r7, #4] 800722c: 6039 str r1, [r7, #0] EXTMEM_StatusTypeDef retr = EXTMEM_ERROR_INVALID_ID; 800722e: 23fb movs r3, #251 @ 0xfb 8007230: 73fb strb r3, [r7, #15] EXTMEM_FUNC_CALL(); /* Check the memory ID */ if (MemId < (sizeof(extmem_list_config) / sizeof(EXTMEM_DefinitionTypeDef))) 8007232: 687b ldr r3, [r7, #4] 8007234: 2b01 cmp r3, #1 8007236: d855 bhi.n 80072e4 { retr = EXTMEM_OK; 8007238: 2300 movs r3, #0 800723a: 73fb strb r3, [r7, #15] /* Check type of EXTMEM driver used to access memory */ switch (extmem_list_config[MemId].MemType) 800723c: 4a2c ldr r2, [pc, #176] @ (80072f0 ) 800723e: 687b ldr r3, [r7, #4] 8007240: 21ac movs r1, #172 @ 0xac 8007242: fb01 f303 mul.w r3, r1, r3 8007246: 4413 add r3, r2 8007248: 781b ldrb r3, [r3, #0] 800724a: 2b00 cmp r3, #0 800724c: d002 beq.n 8007254 800724e: 2b02 cmp r3, #2 8007250: d021 beq.n 8007296 8007252: e041 b.n 80072d8 { #if EXTMEM_DRIVER_NOR_SFDP == 1 case EXTMEM_NOR_SFDP: { /* Initialize the memory using NOR SFDP driver */ if (EXTMEM_DRIVER_NOR_SFDP_OK != EXTMEM_DRIVER_NOR_SFDP_Init(extmem_list_config[MemId].Handle, 8007254: 4a26 ldr r2, [pc, #152] @ (80072f0 ) 8007256: 687b ldr r3, [r7, #4] 8007258: 21ac movs r1, #172 @ 0xac 800725a: fb01 f303 mul.w r3, r1, r3 800725e: 4413 add r3, r2 8007260: 3304 adds r3, #4 8007262: 6818 ldr r0, [r3, #0] 8007264: 4a22 ldr r2, [pc, #136] @ (80072f0 ) 8007266: 687b ldr r3, [r7, #4] 8007268: 21ac movs r1, #172 @ 0xac 800726a: fb01 f303 mul.w r3, r1, r3 800726e: 4413 add r3, r2 8007270: 3308 adds r3, #8 8007272: 7819 ldrb r1, [r3, #0] 8007274: 687b ldr r3, [r7, #4] 8007276: 22ac movs r2, #172 @ 0xac 8007278: fb02 f303 mul.w r3, r2, r3 800727c: 3308 adds r3, #8 800727e: 4a1c ldr r2, [pc, #112] @ (80072f0 ) 8007280: 4413 add r3, r2 8007282: 3304 adds r3, #4 8007284: 683a ldr r2, [r7, #0] 8007286: f002 fe0b bl 8009ea0 800728a: 4603 mov r3, r0 800728c: 2b00 cmp r3, #0 800728e: d026 beq.n 80072de extmem_list_config[MemId].ConfigType, ClockInput, &extmem_list_config[MemId].NorSfdpObject)) { retr = EXTMEM_ERROR_DRIVER; 8007290: 23fd movs r3, #253 @ 0xfd 8007292: 73fb strb r3, [r7, #15] } break; 8007294: e023 b.n 80072de #endif /* EXTMEM_DRIVER_SDCARD == 1 */ #if EXTMEM_DRIVER_PSRAM == 1 case EXTMEM_PSRAM : { /* Initialize the memory using PSRAM driver */ if (EXTMEM_DRIVER_PSRAM_OK != EXTMEM_DRIVER_PSRAM_Init(extmem_list_config[MemId].Handle, 8007296: 4a16 ldr r2, [pc, #88] @ (80072f0 ) 8007298: 687b ldr r3, [r7, #4] 800729a: 21ac movs r1, #172 @ 0xac 800729c: fb01 f303 mul.w r3, r1, r3 80072a0: 4413 add r3, r2 80072a2: 3304 adds r3, #4 80072a4: 6818 ldr r0, [r3, #0] 80072a6: 4a12 ldr r2, [pc, #72] @ (80072f0 ) 80072a8: 687b ldr r3, [r7, #4] 80072aa: 21ac movs r1, #172 @ 0xac 80072ac: fb01 f303 mul.w r3, r1, r3 80072b0: 4413 add r3, r2 80072b2: 3308 adds r3, #8 80072b4: 7819 ldrb r1, [r3, #0] 80072b6: 687b ldr r3, [r7, #4] 80072b8: 22ac movs r2, #172 @ 0xac 80072ba: fb02 f303 mul.w r3, r2, r3 80072be: 3308 adds r3, #8 80072c0: 4a0b ldr r2, [pc, #44] @ (80072f0 ) 80072c2: 4413 add r3, r2 80072c4: 3304 adds r3, #4 80072c6: 683a ldr r2, [r7, #0] 80072c8: f000 f90e bl 80074e8 80072cc: 4603 mov r3, r0 80072ce: 2b00 cmp r3, #0 80072d0: d007 beq.n 80072e2 extmem_list_config[MemId].ConfigType, ClockInput, &extmem_list_config[MemId].PsramObject)) { retr = EXTMEM_ERROR_DRIVER; 80072d2: 23fd movs r3, #253 @ 0xfd 80072d4: 73fb strb r3, [r7, #15] } break; 80072d6: e004 b.n 80072e2 #endif /* EXTMEM_DRIVER_USER == 1 */ /* Unknown type of EXTMEM driver */ default: { EXTMEM_DEBUG("\terror : unknown memory type\n"); retr = EXTMEM_ERROR_UNKNOWNMEMORY; 80072d8: 23fe movs r3, #254 @ 0xfe 80072da: 73fb strb r3, [r7, #15] break; 80072dc: e002 b.n 80072e4 break; 80072de: bf00 nop 80072e0: e000 b.n 80072e4 break; 80072e2: bf00 nop } } } return retr; 80072e4: f997 300f ldrsb.w r3, [r7, #15] } 80072e8: 4618 mov r0, r3 80072ea: 3710 adds r7, #16 80072ec: 46bd mov sp, r7 80072ee: bd80 pop {r7, pc} 80072f0: 2400016c .word 0x2400016c 080072f4 : * @brief Deinitializes the external memory. * @param MemId Memory identifier. * @retval EXTMEM_StatusTypeDef Status of the operation. */ EXTMEM_StatusTypeDef EXTMEM_DeInit(uint32_t MemId) { 80072f4: b580 push {r7, lr} 80072f6: b084 sub sp, #16 80072f8: af00 add r7, sp, #0 80072fa: 6078 str r0, [r7, #4] EXTMEM_StatusTypeDef retr = EXTMEM_ERROR_INVALID_ID; 80072fc: 23fb movs r3, #251 @ 0xfb 80072fe: 73fb strb r3, [r7, #15] EXTMEM_FUNC_CALL(); /* Check the memory ID */ if (MemId < (sizeof(extmem_list_config) / sizeof(EXTMEM_DefinitionTypeDef))) 8007300: 687b ldr r3, [r7, #4] 8007302: 2b01 cmp r3, #1 8007304: d828 bhi.n 8007358 { retr = EXTMEM_OK; 8007306: 2300 movs r3, #0 8007308: 73fb strb r3, [r7, #15] /* Check type of EXTMEM driver used to access memory */ switch (extmem_list_config[MemId].MemType) 800730a: 4a16 ldr r2, [pc, #88] @ (8007364 ) 800730c: 687b ldr r3, [r7, #4] 800730e: 21ac movs r1, #172 @ 0xac 8007310: fb01 f303 mul.w r3, r1, r3 8007314: 4413 add r3, r2 8007316: 781b ldrb r3, [r3, #0] 8007318: 2b00 cmp r3, #0 800731a: d002 beq.n 8007322 800731c: 2b02 cmp r3, #2 800731e: d00c beq.n 800733a 8007320: e017 b.n 8007352 #if EXTMEM_DRIVER_NOR_SFDP == 1 case EXTMEM_NOR_SFDP: { /* Uninitialize the memory using NOR SFDP driver */ /* Return is always OK no need to test the returned value */ (void)EXTMEM_DRIVER_NOR_SFDP_DeInit(&extmem_list_config[MemId].NorSfdpObject); 8007322: 687b ldr r3, [r7, #4] 8007324: 22ac movs r2, #172 @ 0xac 8007326: fb02 f303 mul.w r3, r2, r3 800732a: 3308 adds r3, #8 800732c: 4a0d ldr r2, [pc, #52] @ (8007364 ) 800732e: 4413 add r3, r2 8007330: 3304 adds r3, #4 8007332: 4618 mov r0, r3 8007334: f002 fe68 bl 800a008 break; 8007338: e00e b.n 8007358 #if EXTMEM_DRIVER_PSRAM == 1 case EXTMEM_PSRAM : { /* Uninitialize the memory using PSRAM driver */ /* Return is always OK no need to test the returned value */ (void)EXTMEM_DRIVER_PSRAM_DeInit(&extmem_list_config[MemId].PsramObject); 800733a: 687b ldr r3, [r7, #4] 800733c: 22ac movs r2, #172 @ 0xac 800733e: fb02 f303 mul.w r3, r2, r3 8007342: 3308 adds r3, #8 8007344: 4a07 ldr r2, [pc, #28] @ (8007364 ) 8007346: 4413 add r3, r2 8007348: 3304 adds r3, #4 800734a: 4618 mov r0, r3 800734c: f000 f93e bl 80075cc break; 8007350: e002 b.n 8007358 #endif /* EXTMEM_DRIVER_USER == 1 */ /* Unknown type of EXTMEM driver */ default: { EXTMEM_DEBUG("\terror : unknown memory type\n"); retr = EXTMEM_ERROR_UNKNOWNMEMORY; 8007352: 23fe movs r3, #254 @ 0xfe 8007354: 73fb strb r3, [r7, #15] break; 8007356: bf00 nop } } } return retr; 8007358: f997 300f ldrsb.w r3, [r7, #15] } 800735c: 4618 mov r0, r3 800735e: 3710 adds r7, #16 8007360: 46bd mov sp, r7 8007362: bd80 pop {r7, pc} 8007364: 2400016c .word 0x2400016c 08007368 : * @param MemId Memory identifier. * @param State Enable or disable state (@ref EXTMEM_StateTypeDef). * @retval EXTMEM_StatusTypeDef Status of the operation. */ EXTMEM_StatusTypeDef EXTMEM_MemoryMappedMode(uint32_t MemId, EXTMEM_StateTypeDef State) { 8007368: b580 push {r7, lr} 800736a: b084 sub sp, #16 800736c: af00 add r7, sp, #0 800736e: 6078 str r0, [r7, #4] 8007370: 460b mov r3, r1 8007372: 70fb strb r3, [r7, #3] EXTMEM_StatusTypeDef retr = EXTMEM_ERROR_INVALID_ID; 8007374: 23fb movs r3, #251 @ 0xfb 8007376: 73fb strb r3, [r7, #15] EXTMEM_FUNC_CALL(); /* Check the memory ID */ if (MemId < (sizeof(extmem_list_config) / sizeof(EXTMEM_DefinitionTypeDef))) 8007378: 687b ldr r3, [r7, #4] 800737a: 2b01 cmp r3, #1 800737c: d85d bhi.n 800743a { retr = EXTMEM_OK; 800737e: 2300 movs r3, #0 8007380: 73fb strb r3, [r7, #15] /* Check type of EXTMEM driver used to access memory */ switch (extmem_list_config[MemId].MemType) 8007382: 4a31 ldr r2, [pc, #196] @ (8007448 ) 8007384: 687b ldr r3, [r7, #4] 8007386: 21ac movs r1, #172 @ 0xac 8007388: fb01 f303 mul.w r3, r1, r3 800738c: 4413 add r3, r2 800738e: 781b ldrb r3, [r3, #0] 8007390: 2b00 cmp r3, #0 8007392: d002 beq.n 800739a 8007394: 2b02 cmp r3, #2 8007396: d025 beq.n 80073e4 8007398: e049 b.n 800742e { #if EXTMEM_DRIVER_NOR_SFDP == 1 case EXTMEM_NOR_SFDP: { /* Perform the memory Map operation using the NOR SFDP driver */ if (EXTMEM_ENABLE == State) 800739a: 78fb ldrb r3, [r7, #3] 800739c: 2b00 cmp r3, #0 800739e: d110 bne.n 80073c2 { /* Start the memory mapped mode */ if (EXTMEM_DRIVER_NOR_SFDP_OK != EXTMEM_DRIVER_NOR_SFDP_Enable_MemoryMappedMode(&extmem_list_config[MemId].NorSfdpObject)) 80073a0: 687b ldr r3, [r7, #4] 80073a2: 22ac movs r2, #172 @ 0xac 80073a4: fb02 f303 mul.w r3, r2, r3 80073a8: 3308 adds r3, #8 80073aa: 4a27 ldr r2, [pc, #156] @ (8007448 ) 80073ac: 4413 add r3, r2 80073ae: 3304 adds r3, #4 80073b0: 4618 mov r0, r3 80073b2: f002 fe38 bl 800a026 80073b6: 4603 mov r3, r0 if (EXTMEM_DRIVER_NOR_SFDP_OK != 80073b8: 2b00 cmp r3, #0 80073ba: d03b beq.n 8007434 { return EXTMEM_ERROR_DRIVER; 80073bc: f06f 0302 mvn.w r3, #2 80073c0: e03d b.n 800743e } else { /* Stop the memory mapped mode */ if (EXTMEM_DRIVER_NOR_SFDP_OK != EXTMEM_DRIVER_NOR_SFDP_Disable_MemoryMappedMode(&extmem_list_config[MemId].NorSfdpObject)) 80073c2: 687b ldr r3, [r7, #4] 80073c4: 22ac movs r2, #172 @ 0xac 80073c6: fb02 f303 mul.w r3, r2, r3 80073ca: 3308 adds r3, #8 80073cc: 4a1e ldr r2, [pc, #120] @ (8007448 ) 80073ce: 4413 add r3, r2 80073d0: 3304 adds r3, #4 80073d2: 4618 mov r0, r3 80073d4: f002 fe48 bl 800a068 80073d8: 4603 mov r3, r0 if (EXTMEM_DRIVER_NOR_SFDP_OK != 80073da: 2b00 cmp r3, #0 80073dc: d02a beq.n 8007434 { return EXTMEM_ERROR_DRIVER; 80073de: f06f 0302 mvn.w r3, #2 80073e2: e02c b.n 800743e #endif /* EXTMEM_DRIVER_NOR_SFDP == 1 */ #if EXTMEM_DRIVER_PSRAM == 1 case EXTMEM_PSRAM : { /* Perform the memory Map operation using the PSRAM driver */ if (EXTMEM_ENABLE == State) 80073e4: 78fb ldrb r3, [r7, #3] 80073e6: 2b00 cmp r3, #0 80073e8: d110 bne.n 800740c { /* Start the memory mapped mode */ if (EXTMEM_DRIVER_PSRAM_OK != EXTMEM_DRIVER_PSRAM_Enable_MemoryMappedMode(&extmem_list_config[MemId].PsramObject)) 80073ea: 687b ldr r3, [r7, #4] 80073ec: 22ac movs r2, #172 @ 0xac 80073ee: fb02 f303 mul.w r3, r2, r3 80073f2: 3308 adds r3, #8 80073f4: 4a14 ldr r2, [pc, #80] @ (8007448 ) 80073f6: 4413 add r3, r2 80073f8: 3304 adds r3, #4 80073fa: 4618 mov r0, r3 80073fc: f000 f8f3 bl 80075e6 8007400: 4603 mov r3, r0 if (EXTMEM_DRIVER_PSRAM_OK != 8007402: 2b00 cmp r3, #0 8007404: d018 beq.n 8007438 { return EXTMEM_ERROR_DRIVER; 8007406: f06f 0302 mvn.w r3, #2 800740a: e018 b.n 800743e } else { /* Stop the memory mapped mode */ if (EXTMEM_DRIVER_PSRAM_OK != EXTMEM_DRIVER_PSRAM_Disable_MemoryMappedMode(&extmem_list_config[MemId].PsramObject)) 800740c: 687b ldr r3, [r7, #4] 800740e: 22ac movs r2, #172 @ 0xac 8007410: fb02 f303 mul.w r3, r2, r3 8007414: 3308 adds r3, #8 8007416: 4a0c ldr r2, [pc, #48] @ (8007448 ) 8007418: 4413 add r3, r2 800741a: 3304 adds r3, #4 800741c: 4618 mov r0, r3 800741e: f000 f913 bl 8007648 8007422: 4603 mov r3, r0 if (EXTMEM_DRIVER_PSRAM_OK != 8007424: 2b00 cmp r3, #0 8007426: d007 beq.n 8007438 { return EXTMEM_ERROR_DRIVER; 8007428: f06f 0302 mvn.w r3, #2 800742c: e007 b.n 800743e #endif /* EXTMEM_DRIVER_SDCARD == 1 */ /* Unknown type of EXTMEM driver */ default: { EXTMEM_DEBUG("\terror : unknown memory type\n"); retr = EXTMEM_ERROR_UNKNOWNMEMORY; 800742e: 23fe movs r3, #254 @ 0xfe 8007430: 73fb strb r3, [r7, #15] break; 8007432: e002 b.n 800743a break; 8007434: bf00 nop 8007436: e000 b.n 800743a break; 8007438: bf00 nop } } } return retr; 800743a: f997 300f ldrsb.w r3, [r7, #15] } 800743e: 4618 mov r0, r3 8007440: 3710 adds r7, #16 8007442: 46bd mov sp, r7 8007444: bd80 pop {r7, pc} 8007446: bf00 nop 8007448: 2400016c .word 0x2400016c 0800744c : * @param MemId Memory identifier. * @param BaseAddress Pointer to variable to receive the base address. * @retval EXTMEM_StatusTypeDef Status of the operation. */ EXTMEM_StatusTypeDef EXTMEM_GetMapAddress(uint32_t MemId, uint32_t *BaseAddress) { 800744c: b480 push {r7} 800744e: b085 sub sp, #20 8007450: af00 add r7, sp, #0 8007452: 6078 str r0, [r7, #4] 8007454: 6039 str r1, [r7, #0] EXTMEM_StatusTypeDef retr = EXTMEM_ERROR_INVALID_ID; 8007456: 23fb movs r3, #251 @ 0xfb 8007458: 73fb strb r3, [r7, #15] EXTMEM_FUNC_CALL(); /* Check the memory ID */ if (MemId < (sizeof(extmem_list_config) / sizeof(EXTMEM_DefinitionTypeDef))) 800745a: 687b ldr r3, [r7, #4] 800745c: 2b01 cmp r3, #1 800745e: d834 bhi.n 80074ca { retr = EXTMEM_OK; 8007460: 2300 movs r3, #0 8007462: 73fb strb r3, [r7, #15] /* Check type of EXTMEM driver used to access memory */ switch (extmem_list_config[MemId].MemType) 8007464: 4a1d ldr r2, [pc, #116] @ (80074dc ) 8007466: 687b ldr r3, [r7, #4] 8007468: 21ac movs r1, #172 @ 0xac 800746a: fb01 f303 mul.w r3, r1, r3 800746e: 4413 add r3, r2 8007470: 781b ldrb r3, [r3, #0] 8007472: 2b00 cmp r3, #0 8007474: d001 beq.n 800747a 8007476: 2b02 cmp r3, #2 8007478: d124 bne.n 80074c4 case EXTMEM_PSRAM: case EXTMEM_NOR_SFDP: { /* Define Map address based on Instance used for memory access */ #if defined(XSPI1) if (((XSPI_HandleTypeDef *)extmem_list_config[MemId].Handle)->Instance == XSPI1) 800747a: 4a18 ldr r2, [pc, #96] @ (80074dc ) 800747c: 687b ldr r3, [r7, #4] 800747e: 21ac movs r1, #172 @ 0xac 8007480: fb01 f303 mul.w r3, r1, r3 8007484: 4413 add r3, r2 8007486: 3304 adds r3, #4 8007488: 681b ldr r3, [r3, #0] 800748a: 681b ldr r3, [r3, #0] 800748c: 4a14 ldr r2, [pc, #80] @ (80074e0 ) 800748e: 4293 cmp r3, r2 8007490: d104 bne.n 800749c { *BaseAddress = XSPI1_BASE; 8007492: 683b ldr r3, [r7, #0] 8007494: f04f 4210 mov.w r2, #2415919104 @ 0x90000000 8007498: 601a str r2, [r3, #0] else { retr = EXTMEM_ERROR_DRIVER; } break; 800749a: e016 b.n 80074ca else if (((XSPI_HandleTypeDef *)extmem_list_config[MemId].Handle)->Instance == XSPI2) 800749c: 4a0f ldr r2, [pc, #60] @ (80074dc ) 800749e: 687b ldr r3, [r7, #4] 80074a0: 21ac movs r1, #172 @ 0xac 80074a2: fb01 f303 mul.w r3, r1, r3 80074a6: 4413 add r3, r2 80074a8: 3304 adds r3, #4 80074aa: 681b ldr r3, [r3, #0] 80074ac: 681b ldr r3, [r3, #0] 80074ae: 4a0d ldr r2, [pc, #52] @ (80074e4 ) 80074b0: 4293 cmp r3, r2 80074b2: d104 bne.n 80074be *BaseAddress = XSPI2_BASE; 80074b4: 683b ldr r3, [r7, #0] 80074b6: f04f 42e0 mov.w r2, #1879048192 @ 0x70000000 80074ba: 601a str r2, [r3, #0] break; 80074bc: e005 b.n 80074ca retr = EXTMEM_ERROR_DRIVER; 80074be: 23fd movs r3, #253 @ 0xfd 80074c0: 73fb strb r3, [r7, #15] break; 80074c2: e002 b.n 80074ca #endif /* EXTMEM_DRIVER_USER == 1 */ /* Unknown type of EXTMEM driver */ default : { EXTMEM_DEBUG("\terror : unknown memory type\n"); retr = EXTMEM_ERROR_UNKNOWNMEMORY; 80074c4: 23fe movs r3, #254 @ 0xfe 80074c6: 73fb strb r3, [r7, #15] break; 80074c8: bf00 nop } } } return retr; 80074ca: f997 300f ldrsb.w r3, [r7, #15] } 80074ce: 4618 mov r0, r3 80074d0: 3714 adds r7, #20 80074d2: 46bd mov sp, r7 80074d4: f85d 7b04 ldr.w r7, [sp], #4 80074d8: 4770 bx lr 80074da: bf00 nop 80074dc: 2400016c .word 0x2400016c 80074e0: 52005000 .word 0x52005000 80074e4: 5200a000 .word 0x5200a000 080074e8 : * @retval @ref EXTMEM_DRIVER_PSRAM_StatusTypeDef */ EXTMEM_DRIVER_PSRAM_StatusTypeDef EXTMEM_DRIVER_PSRAM_Init(void *Peripheral, EXTMEM_LinkConfig_TypeDef Config, uint32_t ClockInput, EXTMEM_DRIVER_PSRAM_ObjectTypeDef *PsramObject) { 80074e8: b580 push {r7, lr} 80074ea: b088 sub sp, #32 80074ec: af00 add r7, sp, #0 80074ee: 60f8 str r0, [r7, #12] 80074f0: 607a str r2, [r7, #4] 80074f2: 603b str r3, [r7, #0] 80074f4: 460b mov r3, r1 80074f6: 72fb strb r3, [r7, #11] EXTMEM_DRIVER_PSRAM_StatusTypeDef retr = EXTMEM_DRIVER_PSRAM_OK; 80074f8: 2300 movs r3, #0 80074fa: 77fb strb r3, [r7, #31] /* Initialize the instance */ DEBUG_STR("initialize the instance") /* Initialize XSPI low layer */ (void)SAL_XSPI_Init(&PsramObject->psram_private.SALObject, Peripheral); 80074fc: 683b ldr r3, [r7, #0] 80074fe: 68f9 ldr r1, [r7, #12] 8007500: 4618 mov r0, r3 8007502: f000 f965 bl 80077d0 /* Abort any ongoing XSPI action */ (void)SAL_XSPI_DisableMapMode(&PsramObject->psram_private.SALObject); 8007506: 683b ldr r3, [r7, #0] 8007508: 4618 mov r0, r3 800750a: f000 fec9 bl 80082a0 /* Set the frequency prescaler */ DEBUG_STR("set memory speed according freqIn and freqMax supported by the memory") if (HAL_OK != SAL_XSPI_SetClock(&PsramObject->psram_private.SALObject, ClockInput, PsramObject->psram_public.FreqMax, 800750e: 6838 ldr r0, [r7, #0] 8007510: 683b ldr r3, [r7, #0] 8007512: 6d9a ldr r2, [r3, #88] @ 0x58 8007514: f107 0318 add.w r3, r7, #24 8007518: 6879 ldr r1, [r7, #4] 800751a: f000 f919 bl 8007750 800751e: 4603 mov r3, r0 8007520: 2b00 cmp r3, #0 8007522: d002 beq.n 800752a &ClockOut)) { retr = EXTMEM_DRIVER_PSRAM_ERROR; 8007524: 2380 movs r3, #128 @ 0x80 8007526: 77fb strb r3, [r7, #31] goto error; 8007528: e04a b.n 80075c0 } /* Set the memory size */ DEBUG_STR("set memory size according") (void)SAL_XSPI_MemoryConfig(&PsramObject->psram_private.SALObject, PARAM_FLASHSIZE, 800752a: 6838 ldr r0, [r7, #0] &PsramObject->psram_public.MemorySize); 800752c: 683b ldr r3, [r7, #0] 800752e: 3354 adds r3, #84 @ 0x54 (void)SAL_XSPI_MemoryConfig(&PsramObject->psram_private.SALObject, PARAM_FLASHSIZE, 8007530: 461a mov r2, r3 8007532: 2104 movs r1, #4 8007534: f000 f998 bl 8007868 /* Set the memory size */ DEBUG_STR("set xspi link config") linkvalue = PHY_LINK_RAM8; 8007538: 230a movs r3, #10 800753a: 75fb strb r3, [r7, #23] (void)SAL_XSPI_MemoryConfig(&PsramObject->psram_private.SALObject, PARAM_PHY_LINK, &linkvalue); 800753c: 683b ldr r3, [r7, #0] 800753e: f107 0217 add.w r2, r7, #23 8007542: 2100 movs r1, #0 8007544: 4618 mov r0, r3 8007546: f000 f98f bl 8007868 /* Set the configuration to perform register operation */ (void)SAL_XSPI_MemoryConfig(&PsramObject->psram_private.SALObject, PARAM_DUMMY_CYCLES, 800754a: 6838 ldr r0, [r7, #0] &PsramObject->psram_public.REG_DummyCycle); 800754c: 683b ldr r3, [r7, #0] 800754e: 3369 adds r3, #105 @ 0x69 (void)SAL_XSPI_MemoryConfig(&PsramObject->psram_private.SALObject, PARAM_DUMMY_CYCLES, 8007550: 461a mov r2, r3 8007552: 2101 movs r1, #1 8007554: f000 f988 bl 8007868 /* Execute the command sequence */ for (uint8_t command_index = 0u; command_index < PsramObject->psram_public.NumberOfConfig; command_index++) 8007558: 2300 movs r3, #0 800755a: 77bb strb r3, [r7, #30] 800755c: e00d b.n 800757a { retr = PSRAM_ExecuteCommand(PsramObject, command_index); 800755e: 7fbb ldrb r3, [r7, #30] 8007560: 4619 mov r1, r3 8007562: 6838 ldr r0, [r7, #0] 8007564: f000 f885 bl 8007672 8007568: 4603 mov r3, r0 800756a: 77fb strb r3, [r7, #31] if (retr != EXTMEM_DRIVER_PSRAM_OK) 800756c: f997 301f ldrsb.w r3, [r7, #31] 8007570: 2b00 cmp r3, #0 8007572: d124 bne.n 80075be for (uint8_t command_index = 0u; command_index < PsramObject->psram_public.NumberOfConfig; command_index++) 8007574: 7fbb ldrb r3, [r7, #30] 8007576: 3301 adds r3, #1 8007578: 77bb strb r3, [r7, #30] 800757a: 683b ldr r3, [r7, #0] 800757c: f893 305c ldrb.w r3, [r3, #92] @ 0x5c 8007580: 7fba ldrb r2, [r7, #30] 8007582: 429a cmp r2, r3 8007584: d3eb bcc.n 800755e { goto error; } } switch (Config) 8007586: 7afb ldrb r3, [r7, #11] 8007588: 2b03 cmp r3, #3 800758a: d00b beq.n 80075a4 800758c: 2b04 cmp r3, #4 800758e: d113 bne.n 80075b8 { case EXTMEM_LINK_CONFIG_16LINES: linkvalue = PHY_LINK_RAM16; 8007590: 230b movs r3, #11 8007592: 75fb strb r3, [r7, #23] (void)SAL_XSPI_MemoryConfig(&PsramObject->psram_private.SALObject, PARAM_PHY_LINK, &linkvalue); 8007594: 683b ldr r3, [r7, #0] 8007596: f107 0217 add.w r2, r7, #23 800759a: 2100 movs r1, #0 800759c: 4618 mov r0, r3 800759e: f000 f963 bl 8007868 break; 80075a2: e00d b.n 80075c0 case EXTMEM_LINK_CONFIG_8LINES: linkvalue = PHY_LINK_RAM8; 80075a4: 230a movs r3, #10 80075a6: 75fb strb r3, [r7, #23] (void)SAL_XSPI_MemoryConfig(&PsramObject->psram_private.SALObject, PARAM_PHY_LINK, &linkvalue); 80075a8: 683b ldr r3, [r7, #0] 80075aa: f107 0217 add.w r2, r7, #23 80075ae: 2100 movs r1, #0 80075b0: 4618 mov r0, r3 80075b2: f000 f959 bl 8007868 break; 80075b6: e003 b.n 80075c0 default: retr = EXTMEM_DRIVER_PSRAM_ERROR; 80075b8: 2380 movs r3, #128 @ 0x80 80075ba: 77fb strb r3, [r7, #31] goto error; 80075bc: e000 b.n 80075c0 goto error; 80075be: bf00 nop break; } error: return retr; 80075c0: f997 301f ldrsb.w r3, [r7, #31] } 80075c4: 4618 mov r0, r3 80075c6: 3720 adds r7, #32 80075c8: 46bd mov sp, r7 80075ca: bd80 pop {r7, pc} 080075cc : * @brief Deinitializes the PSRAM driver. * @param PsramObject Pointer to the PSRAM driver object. * @retval @ref EXTMEM_DRIVER_PSRAM_StatusTypeDef */ EXTMEM_DRIVER_PSRAM_StatusTypeDef EXTMEM_DRIVER_PSRAM_DeInit(EXTMEM_DRIVER_PSRAM_ObjectTypeDef *PsramObject) { 80075cc: b580 push {r7, lr} 80075ce: b082 sub sp, #8 80075d0: af00 add r7, sp, #0 80075d2: 6078 str r0, [r7, #4] /* Abort any ongoing XSPI action */ (void)SAL_XSPI_DisableMapMode(&PsramObject->psram_private.SALObject); 80075d4: 687b ldr r3, [r7, #4] 80075d6: 4618 mov r0, r3 80075d8: f000 fe62 bl 80082a0 return EXTMEM_DRIVER_PSRAM_OK; 80075dc: 2300 movs r3, #0 } 80075de: 4618 mov r0, r3 80075e0: 3708 adds r7, #8 80075e2: 46bd mov sp, r7 80075e4: bd80 pop {r7, pc} 080075e6 : * @param PsramObject Pointer to the PSRAM driver object. * @retval @ref EXTMEM_DRIVER_PSRAM_StatusTypeDef */ EXTMEM_DRIVER_PSRAM_StatusTypeDef EXTMEM_DRIVER_PSRAM_Enable_MemoryMappedMode(EXTMEM_DRIVER_PSRAM_ObjectTypeDef *PsramObject) { 80075e6: b590 push {r4, r7, lr} 80075e8: b087 sub sp, #28 80075ea: af02 add r7, sp, #8 80075ec: 6078 str r0, [r7, #4] EXTMEM_DRIVER_PSRAM_StatusTypeDef retr = EXTMEM_DRIVER_PSRAM_OK; 80075ee: 2300 movs r3, #0 80075f0: 73fb strb r3, [r7, #15] /* Configure the read wrap mode */ if (HAL_OK != SAL_XSPI_ConfigureWrappMode(&PsramObject->psram_private.SALObject, 80075f2: 6878 ldr r0, [r7, #4] 80075f4: 687b ldr r3, [r7, #4] 80075f6: f893 106d ldrb.w r1, [r3, #109] @ 0x6d 80075fa: 687b ldr r3, [r7, #4] 80075fc: f893 306b ldrb.w r3, [r3, #107] @ 0x6b 8007600: 461a mov r2, r3 8007602: f000 fd9a bl 800813a 8007606: 4603 mov r3, r0 8007608: 2b00 cmp r3, #0 800760a: d001 beq.n 8007610 PsramObject->psram_public.WrapRead_command, PsramObject->psram_public.Write_DummyCycle)) { retr = EXTMEM_DRIVER_PSRAM_ERROR_MAP_ENABLE; 800760c: 23fb movs r3, #251 @ 0xfb 800760e: 73fb strb r3, [r7, #15] } /* Enable memory mapped mode */ if (HAL_OK != SAL_XSPI_EnableMapMode(&PsramObject->psram_private.SALObject, 8007610: 6878 ldr r0, [r7, #4] 8007612: 687b ldr r3, [r7, #4] 8007614: f893 106c ldrb.w r1, [r3, #108] @ 0x6c 8007618: 687b ldr r3, [r7, #4] 800761a: f893 206e ldrb.w r2, [r3, #110] @ 0x6e 800761e: 687b ldr r3, [r7, #4] 8007620: f893 406a ldrb.w r4, [r3, #106] @ 0x6a 8007624: 687b ldr r3, [r7, #4] 8007626: f893 306b ldrb.w r3, [r3, #107] @ 0x6b 800762a: 9300 str r3, [sp, #0] 800762c: 4623 mov r3, r4 800762e: f000 fdc0 bl 80081b2 8007632: 4603 mov r3, r0 8007634: 2b00 cmp r3, #0 8007636: d001 beq.n 800763c PsramObject->psram_public.Read_command, PsramObject->psram_public.Read_DummyCycle, PsramObject->psram_public.Write_command, PsramObject->psram_public.Write_DummyCycle)) { retr = EXTMEM_DRIVER_PSRAM_ERROR_MAP_ENABLE; 8007638: 23fb movs r3, #251 @ 0xfb 800763a: 73fb strb r3, [r7, #15] } return retr; 800763c: f997 300f ldrsb.w r3, [r7, #15] } 8007640: 4618 mov r0, r3 8007642: 3714 adds r7, #20 8007644: 46bd mov sp, r7 8007646: bd90 pop {r4, r7, pc} 08007648 : * @param PsramObject Pointer to the PSRAM driver object. * @retval @ref EXTMEM_DRIVER_PSRAM_StatusTypeDef */ EXTMEM_DRIVER_PSRAM_StatusTypeDef EXTMEM_DRIVER_PSRAM_Disable_MemoryMappedMode(EXTMEM_DRIVER_PSRAM_ObjectTypeDef *PsramObject) { 8007648: b580 push {r7, lr} 800764a: b084 sub sp, #16 800764c: af00 add r7, sp, #0 800764e: 6078 str r0, [r7, #4] EXTMEM_DRIVER_PSRAM_StatusTypeDef retr = EXTMEM_DRIVER_PSRAM_OK; 8007650: 2300 movs r3, #0 8007652: 73fb strb r3, [r7, #15] /* Disable memory mapped mode */ if (HAL_OK != SAL_XSPI_DisableMapMode(&PsramObject->psram_private.SALObject)) 8007654: 687b ldr r3, [r7, #4] 8007656: 4618 mov r0, r3 8007658: f000 fe22 bl 80082a0 800765c: 4603 mov r3, r0 800765e: 2b00 cmp r3, #0 8007660: d001 beq.n 8007666 { retr = EXTMEM_DRIVER_PSRAM_ERROR_MAP_DISABLE; 8007662: 23fa movs r3, #250 @ 0xfa 8007664: 73fb strb r3, [r7, #15] } return retr; 8007666: f997 300f ldrsb.w r3, [r7, #15] } 800766a: 4618 mov r0, r3 800766c: 3710 adds r7, #16 800766e: 46bd mov sp, r7 8007670: bd80 pop {r7, pc} 08007672 : * @param PsramObject Pointer to the PSRAM driver object. * @param Index Index of the command to execute. * @retval @ref EXTMEM_DRIVER_PSRAM_StatusTypeDef */ EXTMEM_DRIVER_PSRAM_StatusTypeDef PSRAM_ExecuteCommand(EXTMEM_DRIVER_PSRAM_ObjectTypeDef *PsramObject, uint8_t Index) { 8007672: b590 push {r4, r7, lr} 8007674: b087 sub sp, #28 8007676: af02 add r7, sp, #8 8007678: 6078 str r0, [r7, #4] 800767a: 460b mov r3, r1 800767c: 70fb strb r3, [r7, #3] EXTMEM_DRIVER_PSRAM_StatusTypeDef retr = EXTMEM_DRIVER_PSRAM_OK; 800767e: 2300 movs r3, #0 8007680: 73fb strb r3, [r7, #15] uint8_t regval[2]; if (PsramObject->psram_public.ReadREGSize > 2u) 8007682: 687b ldr r3, [r7, #4] 8007684: f893 3068 ldrb.w r3, [r3, #104] @ 0x68 8007688: 2b02 cmp r3, #2 800768a: d902 bls.n 8007692 { retr = EXTMEM_DRIVER_PSRAM_ERROR_REGSIZE; 800768c: 23f9 movs r3, #249 @ 0xf9 800768e: 73fb strb r3, [r7, #15] goto error; 8007690: e058 b.n 8007744 } if (HAL_OK != SAL_XSPI_Read(&PsramObject->psram_private.SALObject, 8007692: 6878 ldr r0, [r7, #4] 8007694: 687b ldr r3, [r7, #4] 8007696: f893 4066 ldrb.w r4, [r3, #102] @ 0x66 PsramObject->psram_public.ReadREG, PsramObject->psram_public.config[Index].REGAddress, 800769a: 78fa ldrb r2, [r7, #3] 800769c: 6879 ldr r1, [r7, #4] 800769e: 4613 mov r3, r2 80076a0: 005b lsls r3, r3, #1 80076a2: 4413 add r3, r2 80076a4: 440b add r3, r1 80076a6: 335f adds r3, #95 @ 0x5f 80076a8: 781b ldrb r3, [r3, #0] if (HAL_OK != SAL_XSPI_Read(&PsramObject->psram_private.SALObject, 80076aa: 4619 mov r1, r3 regval, PsramObject->psram_public.ReadREGSize)) 80076ac: 687b ldr r3, [r7, #4] 80076ae: f893 3068 ldrb.w r3, [r3, #104] @ 0x68 if (HAL_OK != SAL_XSPI_Read(&PsramObject->psram_private.SALObject, 80076b2: 461a mov r2, r3 80076b4: f107 030c add.w r3, r7, #12 80076b8: 9200 str r2, [sp, #0] 80076ba: 460a mov r2, r1 80076bc: 4621 mov r1, r4 80076be: f000 fb05 bl 8007ccc 80076c2: 4603 mov r3, r0 80076c4: 2b00 cmp r3, #0 80076c6: d002 beq.n 80076ce { retr = EXTMEM_DRIVER_PSRAM_ERROR_READREG; 80076c8: 23ff movs r3, #255 @ 0xff 80076ca: 73fb strb r3, [r7, #15] goto error; 80076cc: e03a b.n 8007744 } MODIFY_REG(regval[0], 80076ce: 7b3b ldrb r3, [r7, #12] 80076d0: b259 sxtb r1, r3 80076d2: 78fa ldrb r2, [r7, #3] 80076d4: 6878 ldr r0, [r7, #4] 80076d6: 4613 mov r3, r2 80076d8: 005b lsls r3, r3, #1 80076da: 4413 add r3, r2 80076dc: 4403 add r3, r0 80076de: 335d adds r3, #93 @ 0x5d 80076e0: 781b ldrb r3, [r3, #0] 80076e2: b25b sxtb r3, r3 80076e4: 43db mvns r3, r3 80076e6: b25b sxtb r3, r3 80076e8: 400b ands r3, r1 80076ea: b259 sxtb r1, r3 80076ec: 78fa ldrb r2, [r7, #3] 80076ee: 6878 ldr r0, [r7, #4] 80076f0: 4613 mov r3, r2 80076f2: 005b lsls r3, r3, #1 80076f4: 4413 add r3, r2 80076f6: 4403 add r3, r0 80076f8: 335e adds r3, #94 @ 0x5e 80076fa: 781b ldrb r3, [r3, #0] 80076fc: b25b sxtb r3, r3 80076fe: 430b orrs r3, r1 8007700: b25b sxtb r3, r3 8007702: b2db uxtb r3, r3 8007704: 733b strb r3, [r7, #12] PsramObject->psram_public.config[Index].WriteMask, PsramObject->psram_public.config[Index].WriteValue); if (HAL_OK != SAL_XSPI_Write(&PsramObject->psram_private.SALObject, 8007706: 6878 ldr r0, [r7, #4] 8007708: 687b ldr r3, [r7, #4] 800770a: f893 4067 ldrb.w r4, [r3, #103] @ 0x67 PsramObject->psram_public.WriteREG, PsramObject->psram_public.config[Index].REGAddress, 800770e: 78fa ldrb r2, [r7, #3] 8007710: 6879 ldr r1, [r7, #4] 8007712: 4613 mov r3, r2 8007714: 005b lsls r3, r3, #1 8007716: 4413 add r3, r2 8007718: 440b add r3, r1 800771a: 335f adds r3, #95 @ 0x5f 800771c: 781b ldrb r3, [r3, #0] if (HAL_OK != SAL_XSPI_Write(&PsramObject->psram_private.SALObject, 800771e: 4619 mov r1, r3 regval, PsramObject->psram_public.ReadREGSize)) 8007720: 687b ldr r3, [r7, #4] 8007722: f893 3068 ldrb.w r3, [r3, #104] @ 0x68 if (HAL_OK != SAL_XSPI_Write(&PsramObject->psram_private.SALObject, 8007726: 461a mov r2, r3 8007728: f107 030c add.w r3, r7, #12 800772c: 9200 str r2, [sp, #0] 800772e: 460a mov r2, r1 8007730: 4621 mov r1, r4 8007732: f000 fb33 bl 8007d9c 8007736: 4603 mov r3, r0 8007738: 2b00 cmp r3, #0 800773a: d002 beq.n 8007742 { retr = EXTMEM_DRIVER_PSRAM_ERROR_WRITEREG; 800773c: 23fe movs r3, #254 @ 0xfe 800773e: 73fb strb r3, [r7, #15] goto error; 8007740: e000 b.n 8007744 } error: 8007742: bf00 nop return retr; 8007744: f997 300f ldrsb.w r3, [r7, #15] } 8007748: 4618 mov r0, r3 800774a: 3714 adds r7, #20 800774c: 46bd mov sp, r7 800774e: bd90 pop {r4, r7, pc} 08007750 : * @param ClockReal Pointer on the value of the real clock used * @return @ref HAL_StatusTypeDef **/ HAL_StatusTypeDef SAL_XSPI_SetClock(SAL_XSPI_ObjectTypeDef *SalXspi, uint32_t ClockIn, uint32_t ClockRequested, uint32_t *ClockReal) { 8007750: b480 push {r7} 8007752: b087 sub sp, #28 8007754: af00 add r7, sp, #0 8007756: 60f8 str r0, [r7, #12] 8007758: 60b9 str r1, [r7, #8] 800775a: 607a str r2, [r7, #4] 800775c: 603b str r3, [r7, #0] HAL_StatusTypeDef retr = HAL_OK; 800775e: 2300 movs r3, #0 8007760: 75fb strb r3, [r7, #23] uint32_t divider; if (ClockRequested == 0u) 8007762: 687b ldr r3, [r7, #4] 8007764: 2b00 cmp r3, #0 8007766: d102 bne.n 800776e { retr = HAL_ERROR; 8007768: 2301 movs r3, #1 800776a: 75fb strb r3, [r7, #23] 800776c: e028 b.n 80077c0 } else { divider = (ClockIn / ClockRequested); 800776e: 68ba ldr r2, [r7, #8] 8007770: 687b ldr r3, [r7, #4] 8007772: fbb2 f3f3 udiv r3, r2, r3 8007776: 613b str r3, [r7, #16] if (divider >= 1u) 8007778: 693b ldr r3, [r7, #16] 800777a: 2b00 cmp r3, #0 800777c: d00d beq.n 800779a { *ClockReal = ClockIn / divider; 800777e: 68ba ldr r2, [r7, #8] 8007780: 693b ldr r3, [r7, #16] 8007782: fbb2 f2f3 udiv r2, r2, r3 8007786: 683b ldr r3, [r7, #0] 8007788: 601a str r2, [r3, #0] if (*ClockReal <= ClockRequested) 800778a: 683b ldr r3, [r7, #0] 800778c: 681b ldr r3, [r3, #0] 800778e: 687a ldr r2, [r7, #4] 8007790: 429a cmp r2, r3 8007792: d302 bcc.n 800779a { divider--; 8007794: 693b ldr r3, [r7, #16] 8007796: 3b01 subs r3, #1 8007798: 613b str r3, [r7, #16] } } /* Real clock calculation */ *ClockReal = ClockIn / (divider + 1u); 800779a: 693b ldr r3, [r7, #16] 800779c: 3301 adds r3, #1 800779e: 68ba ldr r2, [r7, #8] 80077a0: fbb2 f2f3 udiv r2, r2, r3 80077a4: 683b ldr r3, [r7, #0] 80077a6: 601a str r2, [r3, #0] DEBUG_PARAM_END(); DEBUG_PARAM_BEGIN(); DEBUG_PARAM_DATA("::CLKFREQ::"); DEBUG_PARAM_INTD(*ClockReal); DEBUG_PARAM_END(); MODIFY_REG(SalXspi->hxspi->Instance->DCR2, XSPI_DCR2_PRESCALER, (uint32_t)divider << XSPI_DCR2_PRESCALER_Pos); 80077a8: 68fb ldr r3, [r7, #12] 80077aa: 681b ldr r3, [r3, #0] 80077ac: 681b ldr r3, [r3, #0] 80077ae: 68db ldr r3, [r3, #12] 80077b0: f023 01ff bic.w r1, r3, #255 @ 0xff 80077b4: 68fb ldr r3, [r7, #12] 80077b6: 681b ldr r3, [r3, #0] 80077b8: 681b ldr r3, [r3, #0] 80077ba: 693a ldr r2, [r7, #16] 80077bc: 430a orrs r2, r1 80077be: 60da str r2, [r3, #12] } return retr; 80077c0: 7dfb ldrb r3, [r7, #23] } 80077c2: 4618 mov r0, r3 80077c4: 371c adds r7, #28 80077c6: 46bd mov sp, r7 80077c8: f85d 7b04 ldr.w r7, [sp], #4 80077cc: 4770 bx lr ... 080077d0 : * @param SalXspi SAL XSPI handle * @param HALHandle HAl XSPI handle used for memory access * @return @ref HAL_StatusTypeDef **/ HAL_StatusTypeDef SAL_XSPI_Init(SAL_XSPI_ObjectTypeDef *SalXspi, void *HALHandle) { 80077d0: b580 push {r7, lr} 80077d2: b096 sub sp, #88 @ 0x58 80077d4: af00 add r7, sp, #0 80077d6: 6078 str r0, [r7, #4] 80077d8: 6039 str r1, [r7, #0] XSPI_RegularCmdTypeDef s_commandbase = 80077da: f107 030c add.w r3, r7, #12 80077de: 224c movs r2, #76 @ 0x4c 80077e0: 2100 movs r1, #0 80077e2: 4618 mov r0, r3 80077e4: f002 fc56 bl 800a094 80077e8: 235a movs r3, #90 @ 0x5a 80077ea: 617b str r3, [r7, #20] 80077ec: 2301 movs r3, #1 80077ee: 61bb str r3, [r7, #24] 80077f0: f44f 7380 mov.w r3, #256 @ 0x100 80077f4: 62bb str r3, [r7, #40] @ 0x28 80077f6: f44f 5300 mov.w r3, #8192 @ 0x2000 80077fa: 62fb str r3, [r7, #44] @ 0x2c 80077fc: f04f 7380 mov.w r3, #16777216 @ 0x1000000 8007800: 647b str r3, [r7, #68] @ 0x44 8007802: 2308 movs r3, #8 8007804: 653b str r3, [r7, #80] @ 0x50 #if defined(XSPI_CCR_SIOO) .SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD, #endif /* XSPI_CCR_SIOO */ }; SalXspi->hxspi = (XSPI_HandleTypeDef *)HALHandle; 8007806: 687b ldr r3, [r7, #4] 8007808: 683a ldr r2, [r7, #0] 800780a: 601a str r2, [r3, #0] SalXspi->Commandbase = s_commandbase; 800780c: 687b ldr r3, [r7, #4] 800780e: 3304 adds r3, #4 8007810: f107 010c add.w r1, r7, #12 8007814: 224c movs r2, #76 @ 0x4c 8007816: 4618 mov r0, r3 8007818: f002 fc68 bl 800a0ec SalXspi->CommandExtension = 0; 800781c: 687b ldr r3, [r7, #4] 800781e: 2200 movs r2, #0 8007820: f883 2050 strb.w r2, [r3, #80] @ 0x50 SalXspi->PhyLink = PHY_LINK_1S1S1S; 8007824: 687b ldr r3, [r7, #4] 8007826: 2200 movs r2, #0 8007828: f883 2052 strb.w r2, [r3, #82] @ 0x52 #if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) /* Set completion call back */ HAL_XSPI_RegisterCallback(SalXspi->hxspi, HAL_XSPI_RX_CPLT_CB_ID, SAL_XSPI_CompleteCallback); 800782c: 687b ldr r3, [r7, #4] 800782e: 681b ldr r3, [r3, #0] 8007830: 4a0b ldr r2, [pc, #44] @ (8007860 ) 8007832: 2104 movs r1, #4 8007834: 4618 mov r0, r3 8007836: f7fe fe89 bl 800654c HAL_XSPI_RegisterCallback(SalXspi->hxspi, HAL_XSPI_TX_CPLT_CB_ID, SAL_XSPI_CompleteCallback); 800783a: 687b ldr r3, [r7, #4] 800783c: 681b ldr r3, [r3, #0] 800783e: 4a08 ldr r2, [pc, #32] @ (8007860 ) 8007840: 2105 movs r1, #5 8007842: 4618 mov r0, r3 8007844: f7fe fe82 bl 800654c /* Set the error callback */ HAL_XSPI_RegisterCallback(SalXspi->hxspi, HAL_XSPI_ERROR_CB_ID, SAL_XSPI_ErrorCallback); 8007848: 687b ldr r3, [r7, #4] 800784a: 681b ldr r3, [r3, #0] 800784c: 4a05 ldr r2, [pc, #20] @ (8007864 ) 800784e: 2100 movs r1, #0 8007850: 4618 mov r0, r3 8007852: f7fe fe7b bl 800654c #endif /* USE_HAL_XSPI_REGISTER_CALLBACKS */ return HAL_OK; 8007856: 2300 movs r3, #0 } 8007858: 4618 mov r0, r3 800785a: 3758 adds r7, #88 @ 0x58 800785c: 46bd mov sp, r7 800785e: bd80 pop {r7, pc} 8007860: 08008499 .word 0x08008499 8007864: 08008479 .word 0x08008479 08007868 : * @param ParamVal Pointer on the parameter value * @return @ref HAL_StatusTypeDef **/ HAL_StatusTypeDef SAL_XSPI_MemoryConfig(SAL_XSPI_ObjectTypeDef *SalXspi, SAL_XSPI_MemParamTypeTypeDef ParametersType, void *ParamVal) { 8007868: b580 push {r7, lr} 800786a: b098 sub sp, #96 @ 0x60 800786c: af00 add r7, sp, #0 800786e: 60f8 str r0, [r7, #12] 8007870: 460b mov r3, r1 8007872: 607a str r2, [r7, #4] 8007874: 72fb strb r3, [r7, #11] HAL_StatusTypeDef retr = HAL_OK; 8007876: 2300 movs r3, #0 8007878: f887 305f strb.w r3, [r7, #95] @ 0x5f XSPI_RegularCmdTypeDef s_commandbase = SalXspi->Commandbase; 800787c: 68fb ldr r3, [r7, #12] 800787e: f107 0010 add.w r0, r7, #16 8007882: 3304 adds r3, #4 8007884: 224c movs r2, #76 @ 0x4c 8007886: 4619 mov r1, r3 8007888: f002 fc30 bl 800a0ec switch (ParametersType) 800788c: 7afb ldrb r3, [r7, #11] 800788e: 2b04 cmp r3, #4 8007890: f200 812a bhi.w 8007ae8 8007894: a201 add r2, pc, #4 @ (adr r2, 800789c ) 8007896: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800789a: bf00 nop 800789c: 080078b1 .word 0x080078b1 80078a0: 08007ad9 .word 0x08007ad9 80078a4: 08007aab .word 0x08007aab 80078a8: 08007ae9 .word 0x08007ae9 80078ac: 08007ab3 .word 0x08007ab3 { case PARAM_PHY_LINK: { SalXspi->PhyLink = *((SAL_XSPI_PhysicalLinkTypeDef *)ParamVal); 80078b0: 687b ldr r3, [r7, #4] 80078b2: 781a ldrb r2, [r3, #0] 80078b4: 68fb ldr r3, [r7, #12] 80078b6: f883 2052 strb.w r2, [r3, #82] @ 0x52 DEBUG_PARAM_BEGIN(); DEBUG_PARAM_DATA("::PARAM_PHY_LINK::"); DEBUG_PARAM_DATA(STR_PHY_LINK(SalXspi->PhyLink)); switch (SalXspi->PhyLink) 80078ba: 68fb ldr r3, [r7, #12] 80078bc: f893 3052 ldrb.w r3, [r3, #82] @ 0x52 80078c0: 2b0b cmp r3, #11 80078c2: f200 80ed bhi.w 8007aa0 80078c6: a201 add r2, pc, #4 @ (adr r2, 80078cc ) 80078c8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80078cc: 080078fd .word 0x080078fd 80078d0: 080078fd .word 0x080078fd 80078d4: 080078fd .word 0x080078fd 80078d8: 080078fd .word 0x080078fd 80078dc: 0800792d .word 0x0800792d 80078e0: 0800792d .word 0x0800792d 80078e4: 0800795d .word 0x0800795d 80078e8: 08007991 .word 0x08007991 80078ec: 080079c1 .word 0x080079c1 80078f0: 080079f7 .word 0x080079f7 80078f4: 08007a2d .word 0x08007a2d 80078f8: 08007a67 .word 0x08007a67 case PHY_LINK_1S1D1D: case PHY_LINK_1S2S2S: case PHY_LINK_1S1S2S: case PHY_LINK_1S1S1S: { s_commandbase.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE; 80078fc: 2301 movs r3, #1 80078fe: 61fb str r3, [r7, #28] s_commandbase.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS; 8007900: 2300 movs r3, #0 8007902: 623b str r3, [r7, #32] s_commandbase.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE; 8007904: 2300 movs r3, #0 8007906: 627b str r3, [r7, #36] @ 0x24 s_commandbase.AddressMode = HAL_XSPI_ADDRESS_1_LINE; 8007908: f44f 7380 mov.w r3, #256 @ 0x100 800790c: 62fb str r3, [r7, #44] @ 0x2c s_commandbase.AddressWidth = HAL_XSPI_ADDRESS_24_BITS; 800790e: f44f 5300 mov.w r3, #8192 @ 0x2000 8007912: 633b str r3, [r7, #48] @ 0x30 s_commandbase.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_DISABLE; 8007914: 2300 movs r3, #0 8007916: 637b str r3, [r7, #52] @ 0x34 s_commandbase.DataMode = HAL_XSPI_DATA_1_LINE; 8007918: f04f 7380 mov.w r3, #16777216 @ 0x1000000 800791c: 64bb str r3, [r7, #72] @ 0x48 s_commandbase.DataDTRMode = HAL_XSPI_DATA_DTR_DISABLE; 800791e: 2300 movs r3, #0 8007920: 653b str r3, [r7, #80] @ 0x50 s_commandbase.DummyCycles = 8; 8007922: 2308 movs r3, #8 8007924: 657b str r3, [r7, #84] @ 0x54 s_commandbase.DQSMode = HAL_XSPI_DQS_DISABLE; 8007926: 2300 movs r3, #0 8007928: 65bb str r3, [r7, #88] @ 0x58 break; 800792a: e0bd b.n 8007aa8 } case PHY_LINK_4S4D4D: case PHY_LINK_4S4S4S: { s_commandbase.InstructionMode = HAL_XSPI_INSTRUCTION_4_LINES; 800792c: 2303 movs r3, #3 800792e: 61fb str r3, [r7, #28] s_commandbase.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS; 8007930: 2300 movs r3, #0 8007932: 623b str r3, [r7, #32] s_commandbase.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE; 8007934: 2300 movs r3, #0 8007936: 627b str r3, [r7, #36] @ 0x24 s_commandbase.AddressMode = HAL_XSPI_ADDRESS_4_LINES; 8007938: f44f 7340 mov.w r3, #768 @ 0x300 800793c: 62fb str r3, [r7, #44] @ 0x2c s_commandbase.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_DISABLE; 800793e: 2300 movs r3, #0 8007940: 637b str r3, [r7, #52] @ 0x34 s_commandbase.AddressWidth = HAL_XSPI_ADDRESS_24_BITS; 8007942: f44f 5300 mov.w r3, #8192 @ 0x2000 8007946: 633b str r3, [r7, #48] @ 0x30 s_commandbase.DataMode = HAL_XSPI_DATA_4_LINES; 8007948: f04f 7340 mov.w r3, #50331648 @ 0x3000000 800794c: 64bb str r3, [r7, #72] @ 0x48 s_commandbase.DataDTRMode = HAL_XSPI_DATA_DTR_DISABLE; 800794e: 2300 movs r3, #0 8007950: 653b str r3, [r7, #80] @ 0x50 s_commandbase.DummyCycles = 6; 8007952: 2306 movs r3, #6 8007954: 657b str r3, [r7, #84] @ 0x54 s_commandbase.DQSMode = HAL_XSPI_DQS_DISABLE; 8007956: 2300 movs r3, #0 8007958: 65bb str r3, [r7, #88] @ 0x58 break; 800795a: e0a5 b.n 8007aa8 } case PHY_LINK_4D4D4D: { s_commandbase.InstructionMode = HAL_XSPI_INSTRUCTION_4_LINES; 800795c: 2303 movs r3, #3 800795e: 61fb str r3, [r7, #28] s_commandbase.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS; 8007960: 2300 movs r3, #0 8007962: 623b str r3, [r7, #32] s_commandbase.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_ENABLE; 8007964: 2308 movs r3, #8 8007966: 627b str r3, [r7, #36] @ 0x24 s_commandbase.AddressMode = HAL_XSPI_ADDRESS_4_LINES; 8007968: f44f 7340 mov.w r3, #768 @ 0x300 800796c: 62fb str r3, [r7, #44] @ 0x2c s_commandbase.AddressWidth = HAL_XSPI_ADDRESS_24_BITS; 800796e: f44f 5300 mov.w r3, #8192 @ 0x2000 8007972: 633b str r3, [r7, #48] @ 0x30 s_commandbase.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_ENABLE; 8007974: f44f 6300 mov.w r3, #2048 @ 0x800 8007978: 637b str r3, [r7, #52] @ 0x34 s_commandbase.DataMode = HAL_XSPI_DATA_4_LINES; 800797a: f04f 7340 mov.w r3, #50331648 @ 0x3000000 800797e: 64bb str r3, [r7, #72] @ 0x48 s_commandbase.DataDTRMode = HAL_XSPI_DATA_DTR_ENABLE; 8007980: f04f 6300 mov.w r3, #134217728 @ 0x8000000 8007984: 653b str r3, [r7, #80] @ 0x50 s_commandbase.DummyCycles = 6; 8007986: 2306 movs r3, #6 8007988: 657b str r3, [r7, #84] @ 0x54 s_commandbase.DQSMode = HAL_XSPI_DQS_DISABLE; 800798a: 2300 movs r3, #0 800798c: 65bb str r3, [r7, #88] @ 0x58 break; 800798e: e08b b.n 8007aa8 } case PHY_LINK_1S8S8S: { s_commandbase.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE; 8007990: 2301 movs r3, #1 8007992: 61fb str r3, [r7, #28] s_commandbase.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS; 8007994: 2300 movs r3, #0 8007996: 623b str r3, [r7, #32] s_commandbase.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE; 8007998: 2300 movs r3, #0 800799a: 627b str r3, [r7, #36] @ 0x24 s_commandbase.AddressMode = HAL_XSPI_ADDRESS_8_LINES; 800799c: f44f 6380 mov.w r3, #1024 @ 0x400 80079a0: 62fb str r3, [r7, #44] @ 0x2c s_commandbase.AddressWidth = HAL_XSPI_ADDRESS_32_BITS; 80079a2: f44f 5340 mov.w r3, #12288 @ 0x3000 80079a6: 633b str r3, [r7, #48] @ 0x30 s_commandbase.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_DISABLE; 80079a8: 2300 movs r3, #0 80079aa: 637b str r3, [r7, #52] @ 0x34 s_commandbase.DataMode = HAL_XSPI_DATA_8_LINES; 80079ac: f04f 6380 mov.w r3, #67108864 @ 0x4000000 80079b0: 64bb str r3, [r7, #72] @ 0x48 s_commandbase.DataDTRMode = HAL_XSPI_DATA_DTR_DISABLE; 80079b2: 2300 movs r3, #0 80079b4: 653b str r3, [r7, #80] @ 0x50 s_commandbase.DummyCycles = 8; 80079b6: 2308 movs r3, #8 80079b8: 657b str r3, [r7, #84] @ 0x54 s_commandbase.DQSMode = HAL_XSPI_DQS_DISABLE; 80079ba: 2300 movs r3, #0 80079bc: 65bb str r3, [r7, #88] @ 0x58 break; 80079be: e073 b.n 8007aa8 } case PHY_LINK_8S8D8D: { s_commandbase.InstructionMode = HAL_XSPI_INSTRUCTION_8_LINES; 80079c0: 2304 movs r3, #4 80079c2: 61fb str r3, [r7, #28] s_commandbase.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS; 80079c4: 2300 movs r3, #0 80079c6: 623b str r3, [r7, #32] s_commandbase.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE; 80079c8: 2300 movs r3, #0 80079ca: 627b str r3, [r7, #36] @ 0x24 s_commandbase.AddressMode = HAL_XSPI_ADDRESS_8_LINES; 80079cc: f44f 6380 mov.w r3, #1024 @ 0x400 80079d0: 62fb str r3, [r7, #44] @ 0x2c s_commandbase.AddressWidth = HAL_XSPI_ADDRESS_32_BITS; 80079d2: f44f 5340 mov.w r3, #12288 @ 0x3000 80079d6: 633b str r3, [r7, #48] @ 0x30 s_commandbase.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_ENABLE; 80079d8: f44f 6300 mov.w r3, #2048 @ 0x800 80079dc: 637b str r3, [r7, #52] @ 0x34 s_commandbase.DataMode = HAL_XSPI_DATA_8_LINES; 80079de: f04f 6380 mov.w r3, #67108864 @ 0x4000000 80079e2: 64bb str r3, [r7, #72] @ 0x48 s_commandbase.DataDTRMode = HAL_XSPI_DATA_DTR_ENABLE; 80079e4: f04f 6300 mov.w r3, #134217728 @ 0x8000000 80079e8: 653b str r3, [r7, #80] @ 0x50 s_commandbase.DummyCycles = 8; 80079ea: 2308 movs r3, #8 80079ec: 657b str r3, [r7, #84] @ 0x54 s_commandbase.DQSMode = HAL_XSPI_DQS_ENABLE; 80079ee: f04f 5300 mov.w r3, #536870912 @ 0x20000000 80079f2: 65bb str r3, [r7, #88] @ 0x58 break; 80079f4: e058 b.n 8007aa8 } case PHY_LINK_8D8D8D: { s_commandbase.InstructionMode = HAL_XSPI_INSTRUCTION_8_LINES; 80079f6: 2304 movs r3, #4 80079f8: 61fb str r3, [r7, #28] s_commandbase.InstructionWidth = HAL_XSPI_INSTRUCTION_16_BITS; 80079fa: 2310 movs r3, #16 80079fc: 623b str r3, [r7, #32] s_commandbase.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_ENABLE; 80079fe: 2308 movs r3, #8 8007a00: 627b str r3, [r7, #36] @ 0x24 s_commandbase.AddressMode = HAL_XSPI_ADDRESS_8_LINES; 8007a02: f44f 6380 mov.w r3, #1024 @ 0x400 8007a06: 62fb str r3, [r7, #44] @ 0x2c s_commandbase.AddressWidth = HAL_XSPI_ADDRESS_32_BITS; 8007a08: f44f 5340 mov.w r3, #12288 @ 0x3000 8007a0c: 633b str r3, [r7, #48] @ 0x30 s_commandbase.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_ENABLE; 8007a0e: f44f 6300 mov.w r3, #2048 @ 0x800 8007a12: 637b str r3, [r7, #52] @ 0x34 s_commandbase.DataMode = HAL_XSPI_DATA_8_LINES; 8007a14: f04f 6380 mov.w r3, #67108864 @ 0x4000000 8007a18: 64bb str r3, [r7, #72] @ 0x48 s_commandbase.DataDTRMode = HAL_XSPI_DATA_DTR_ENABLE; 8007a1a: f04f 6300 mov.w r3, #134217728 @ 0x8000000 8007a1e: 653b str r3, [r7, #80] @ 0x50 s_commandbase.DummyCycles = 20; 8007a20: 2314 movs r3, #20 8007a22: 657b str r3, [r7, #84] @ 0x54 s_commandbase.DQSMode = HAL_XSPI_DQS_ENABLE; 8007a24: f04f 5300 mov.w r3, #536870912 @ 0x20000000 8007a28: 65bb str r3, [r7, #88] @ 0x58 break; 8007a2a: e03d b.n 8007aa8 } case PHY_LINK_RAM8: { s_commandbase.InstructionMode = HAL_XSPI_INSTRUCTION_8_LINES; 8007a2c: 2304 movs r3, #4 8007a2e: 61fb str r3, [r7, #28] s_commandbase.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS; 8007a30: 2300 movs r3, #0 8007a32: 623b str r3, [r7, #32] s_commandbase.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE; 8007a34: 2300 movs r3, #0 8007a36: 627b str r3, [r7, #36] @ 0x24 s_commandbase.AddressMode = HAL_XSPI_ADDRESS_8_LINES; 8007a38: f44f 6380 mov.w r3, #1024 @ 0x400 8007a3c: 62fb str r3, [r7, #44] @ 0x2c s_commandbase.AddressWidth = HAL_XSPI_ADDRESS_32_BITS; 8007a3e: f44f 5340 mov.w r3, #12288 @ 0x3000 8007a42: 633b str r3, [r7, #48] @ 0x30 s_commandbase.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_ENABLE; 8007a44: f44f 6300 mov.w r3, #2048 @ 0x800 8007a48: 637b str r3, [r7, #52] @ 0x34 s_commandbase.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE; 8007a4a: 2300 movs r3, #0 8007a4c: 63fb str r3, [r7, #60] @ 0x3c s_commandbase.DataMode = HAL_XSPI_DATA_8_LINES; 8007a4e: f04f 6380 mov.w r3, #67108864 @ 0x4000000 8007a52: 64bb str r3, [r7, #72] @ 0x48 s_commandbase.DataDTRMode = HAL_XSPI_DATA_DTR_ENABLE; 8007a54: f04f 6300 mov.w r3, #134217728 @ 0x8000000 8007a58: 653b str r3, [r7, #80] @ 0x50 s_commandbase.DummyCycles = 10; 8007a5a: 230a movs r3, #10 8007a5c: 657b str r3, [r7, #84] @ 0x54 s_commandbase.DQSMode = HAL_XSPI_DQS_ENABLE; 8007a5e: f04f 5300 mov.w r3, #536870912 @ 0x20000000 8007a62: 65bb str r3, [r7, #88] @ 0x58 break; 8007a64: e020 b.n 8007aa8 } #if defined(HAL_XSPI_DATA_16_LINES) case PHY_LINK_RAM16 : { s_commandbase.InstructionMode = HAL_XSPI_INSTRUCTION_8_LINES; 8007a66: 2304 movs r3, #4 8007a68: 61fb str r3, [r7, #28] s_commandbase.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS; 8007a6a: 2300 movs r3, #0 8007a6c: 623b str r3, [r7, #32] s_commandbase.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE; 8007a6e: 2300 movs r3, #0 8007a70: 627b str r3, [r7, #36] @ 0x24 s_commandbase.AddressMode = HAL_XSPI_ADDRESS_8_LINES; 8007a72: f44f 6380 mov.w r3, #1024 @ 0x400 8007a76: 62fb str r3, [r7, #44] @ 0x2c s_commandbase.AddressWidth = HAL_XSPI_ADDRESS_32_BITS; 8007a78: f44f 5340 mov.w r3, #12288 @ 0x3000 8007a7c: 633b str r3, [r7, #48] @ 0x30 s_commandbase.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_ENABLE; 8007a7e: f44f 6300 mov.w r3, #2048 @ 0x800 8007a82: 637b str r3, [r7, #52] @ 0x34 s_commandbase.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE; 8007a84: 2300 movs r3, #0 8007a86: 63fb str r3, [r7, #60] @ 0x3c s_commandbase.DataMode = HAL_XSPI_DATA_16_LINES; 8007a88: f04f 63a0 mov.w r3, #83886080 @ 0x5000000 8007a8c: 64bb str r3, [r7, #72] @ 0x48 s_commandbase.DataDTRMode = HAL_XSPI_DATA_DTR_ENABLE; 8007a8e: f04f 6300 mov.w r3, #134217728 @ 0x8000000 8007a92: 653b str r3, [r7, #80] @ 0x50 s_commandbase.DummyCycles = 10; 8007a94: 230a movs r3, #10 8007a96: 657b str r3, [r7, #84] @ 0x54 s_commandbase.DQSMode = HAL_XSPI_DQS_ENABLE; 8007a98: f04f 5300 mov.w r3, #536870912 @ 0x20000000 8007a9c: 65bb str r3, [r7, #88] @ 0x58 break; 8007a9e: e003 b.n 8007aa8 } #endif /* HAL_XSPI_DATA_16_LINES */ default: retr = HAL_ERROR; 8007aa0: 2301 movs r3, #1 8007aa2: f887 305f strb.w r3, [r7, #95] @ 0x5f break; 8007aa6: bf00 nop } DEBUG_PARAM_END(); break; 8007aa8: e022 b.n 8007af0 case PARAM_ADDRESS_4BYTES: { DEBUG_PARAM_BEGIN(); DEBUG_PARAM_DATA("::PARAM_ADDRESS_4BYTES"); DEBUG_PARAM_END(); s_commandbase.AddressWidth = HAL_XSPI_ADDRESS_32_BITS; 8007aaa: f44f 5340 mov.w r3, #12288 @ 0x3000 8007aae: 633b str r3, [r7, #48] @ 0x30 break; 8007ab0: e01e b.n 8007af0 } case PARAM_FLASHSIZE: { uint8_t valParam = *((uint8_t *)ParamVal); 8007ab2: 687b ldr r3, [r7, #4] 8007ab4: 781b ldrb r3, [r3, #0] 8007ab6: f887 305e strb.w r3, [r7, #94] @ 0x5e DEBUG_PARAM_BEGIN(); DEBUG_PARAM_DATA("::PARAM_FLASHSIZE::"); DEBUG_PARAM_INT(valParam); DEBUG_PARAM_END(); MODIFY_REG(SalXspi->hxspi->Instance->DCR1, XSPI_DCR1_DEVSIZE, ((uint32_t)valParam) << XSPI_DCR1_DEVSIZE_Pos); 8007aba: 68fb ldr r3, [r7, #12] 8007abc: 681b ldr r3, [r3, #0] 8007abe: 681b ldr r3, [r3, #0] 8007ac0: 689b ldr r3, [r3, #8] 8007ac2: f423 11f8 bic.w r1, r3, #2031616 @ 0x1f0000 8007ac6: f897 305e ldrb.w r3, [r7, #94] @ 0x5e 8007aca: 041a lsls r2, r3, #16 8007acc: 68fb ldr r3, [r7, #12] 8007ace: 681b ldr r3, [r3, #0] 8007ad0: 681b ldr r3, [r3, #0] 8007ad2: 430a orrs r2, r1 8007ad4: 609a str r2, [r3, #8] break; 8007ad6: e00b b.n 8007af0 } case PARAM_DUMMY_CYCLES: { uint8_t valParam = *((uint8_t *)ParamVal); 8007ad8: 687b ldr r3, [r7, #4] 8007ada: 781b ldrb r3, [r3, #0] 8007adc: f887 305d strb.w r3, [r7, #93] @ 0x5d DEBUG_PARAM_BEGIN(); DEBUG_PARAM_DATA("::PARAM_DUMMY_CYCLES::"); DEBUG_PARAM_INT(valParam); DEBUG_PARAM_END(); s_commandbase.DummyCycles = valParam; 8007ae0: f897 305d ldrb.w r3, [r7, #93] @ 0x5d 8007ae4: 657b str r3, [r7, #84] @ 0x54 break; 8007ae6: e003 b.n 8007af0 } default: DEBUG_PARAM_BEGIN(); DEBUG_PARAM_DATA("::SAL_XSPI_MemoryConfig::ERROR"); DEBUG_PARAM_END(); retr = HAL_ERROR; 8007ae8: 2301 movs r3, #1 8007aea: f887 305f strb.w r3, [r7, #95] @ 0x5f break; 8007aee: bf00 nop } SalXspi->Commandbase = s_commandbase; 8007af0: 68fb ldr r3, [r7, #12] 8007af2: 3304 adds r3, #4 8007af4: f107 0110 add.w r1, r7, #16 8007af8: 224c movs r2, #76 @ 0x4c 8007afa: 4618 mov r0, r3 8007afc: f002 faf6 bl 800a0ec return retr; 8007b00: f897 305f ldrb.w r3, [r7, #95] @ 0x5f } 8007b04: 4618 mov r0, r3 8007b06: 3760 adds r7, #96 @ 0x60 8007b08: 46bd mov sp, r7 8007b0a: bd80 pop {r7, pc} 08007b0c : * @param Data Data pointer * @param DataSize Size of the data to read * @return @ref HAL_StatusTypeDef **/ HAL_StatusTypeDef SAL_XSPI_GetSFDP(SAL_XSPI_ObjectTypeDef *SalXspi, uint32_t Address, uint8_t *Data, uint32_t DataSize) { 8007b0c: b580 push {r7, lr} 8007b0e: b098 sub sp, #96 @ 0x60 8007b10: af00 add r7, sp, #0 8007b12: 60f8 str r0, [r7, #12] 8007b14: 60b9 str r1, [r7, #8] 8007b16: 607a str r2, [r7, #4] 8007b18: 603b str r3, [r7, #0] HAL_StatusTypeDef retr; XSPI_RegularCmdTypeDef s_command = SalXspi->Commandbase; 8007b1a: 68fb ldr r3, [r7, #12] 8007b1c: f107 0010 add.w r0, r7, #16 8007b20: 3304 adds r3, #4 8007b22: 224c movs r2, #76 @ 0x4c 8007b24: 4619 mov r1, r3 8007b26: f002 fae1 bl 800a0ec /* Initialize the read ID command */ s_command.Instruction = XSPI_FormatCommand(SalXspi->CommandExtension, s_command.InstructionWidth, 8007b2a: 68fb ldr r3, [r7, #12] 8007b2c: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 8007b30: 6a39 ldr r1, [r7, #32] 8007b32: 225a movs r2, #90 @ 0x5a 8007b34: 4618 mov r0, r3 8007b36: f000 fc0a bl 800834e 8007b3a: 4603 mov r3, r0 8007b3c: 61bb str r3, [r7, #24] EXTMEM_READ_SFDP_COMMAND); s_command.Address = Address; 8007b3e: 68bb ldr r3, [r7, #8] 8007b40: 62bb str r3, [r7, #40] @ 0x28 s_command.DataLength = DataSize; 8007b42: 683b ldr r3, [r7, #0] 8007b44: 64fb str r3, [r7, #76] @ 0x4c s_command.DummyCycles = SalXspi->SFDPDummyCycle; 8007b46: 68fb ldr r3, [r7, #12] 8007b48: f893 3051 ldrb.w r3, [r3, #81] @ 0x51 8007b4c: 657b str r3, [r7, #84] @ 0x54 if ((s_command.AddressMode == HAL_XSPI_ADDRESS_1_LINE) || (s_command.AddressMode == HAL_XSPI_ADDRESS_4_LINES)) 8007b4e: 6afb ldr r3, [r7, #44] @ 0x2c 8007b50: f5b3 7f80 cmp.w r3, #256 @ 0x100 8007b54: d003 beq.n 8007b5e 8007b56: 6afb ldr r3, [r7, #44] @ 0x2c 8007b58: f5b3 7f40 cmp.w r3, #768 @ 0x300 8007b5c: d102 bne.n 8007b64 { s_command.AddressWidth = HAL_XSPI_ADDRESS_24_BITS; 8007b5e: f44f 5300 mov.w r3, #8192 @ 0x2000 8007b62: 633b str r3, [r7, #48] @ 0x30 } if (s_command.DataDTRMode == HAL_XSPI_DATA_DTR_ENABLE) 8007b64: 6d3b ldr r3, [r7, #80] @ 0x50 8007b66: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 8007b6a: d103 bne.n 8007b74 { s_command.DQSMode = HAL_XSPI_DQS_ENABLE; 8007b6c: f04f 5300 mov.w r3, #536870912 @ 0x20000000 8007b70: 65bb str r3, [r7, #88] @ 0x58 8007b72: e001 b.n 8007b78 } else { s_command.DQSMode = HAL_XSPI_DQS_DISABLE; 8007b74: 2300 movs r3, #0 8007b76: 65bb str r3, [r7, #88] @ 0x58 } /* Configure the command */ retr = HAL_XSPI_Command(SalXspi->hxspi, &s_command, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); 8007b78: 68fb ldr r3, [r7, #12] 8007b7a: 681b ldr r3, [r3, #0] 8007b7c: f107 0110 add.w r1, r7, #16 8007b80: 2264 movs r2, #100 @ 0x64 8007b82: 4618 mov r0, r3 8007b84: f7fd ff74 bl 8005a70 8007b88: 4603 mov r3, r0 8007b8a: f887 305f strb.w r3, [r7, #95] @ 0x5f if (retr != HAL_OK) 8007b8e: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8007b92: 2b00 cmp r3, #0 8007b94: d10a bne.n 8007bac { goto error; } /* Reception of the data */ retr = HAL_XSPI_Receive(SalXspi->hxspi, Data, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); 8007b96: 68fb ldr r3, [r7, #12] 8007b98: 681b ldr r3, [r3, #0] 8007b9a: 2264 movs r2, #100 @ 0x64 8007b9c: 6879 ldr r1, [r7, #4] 8007b9e: 4618 mov r0, r3 8007ba0: f7fe f869 bl 8005c76 8007ba4: 4603 mov r3, r0 8007ba6: f887 305f strb.w r3, [r7, #95] @ 0x5f 8007baa: e000 b.n 8007bae goto error; 8007bac: bf00 nop error: if (retr != HAL_OK) 8007bae: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8007bb2: 2b00 cmp r3, #0 8007bb4: d004 beq.n 8007bc0 { /* Abort any ongoing transaction for the next action */ (void)HAL_XSPI_Abort(SalXspi->hxspi); 8007bb6: 68fb ldr r3, [r7, #12] 8007bb8: 681b ldr r3, [r3, #0] 8007bba: 4618 mov r0, r3 8007bbc: f7fe fd66 bl 800668c } return retr; 8007bc0: f897 305f ldrb.w r3, [r7, #95] @ 0x5f } 8007bc4: 4618 mov r0, r3 8007bc6: 3760 adds r7, #96 @ 0x60 8007bc8: 46bd mov sp, r7 8007bca: bd80 pop {r7, pc} 08007bcc : * @param Data Data pointer where read ID should be stored * @param DataSize Number of data to read * @return @ref HAL_StatusTypeDef **/ HAL_StatusTypeDef SAL_XSPI_GetId(SAL_XSPI_ObjectTypeDef *SalXspi, uint8_t *Data, uint32_t DataSize) { 8007bcc: b580 push {r7, lr} 8007bce: b098 sub sp, #96 @ 0x60 8007bd0: af00 add r7, sp, #0 8007bd2: 60f8 str r0, [r7, #12] 8007bd4: 60b9 str r1, [r7, #8] 8007bd6: 607a str r2, [r7, #4] HAL_StatusTypeDef retr; XSPI_RegularCmdTypeDef s_command = SalXspi->Commandbase; 8007bd8: 68fb ldr r3, [r7, #12] 8007bda: f107 0010 add.w r0, r7, #16 8007bde: 3304 adds r3, #4 8007be0: 224c movs r2, #76 @ 0x4c 8007be2: 4619 mov r1, r3 8007be4: f002 fa82 bl 800a0ec /* Initialize the Read ID command */ s_command.Instruction = XSPI_FormatCommand(SalXspi->CommandExtension, s_command.InstructionWidth, 8007be8: 68fb ldr r3, [r7, #12] 8007bea: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 8007bee: 6a39 ldr r1, [r7, #32] 8007bf0: 229f movs r2, #159 @ 0x9f 8007bf2: 4618 mov r0, r3 8007bf4: f000 fbab bl 800834e 8007bf8: 4603 mov r3, r0 8007bfa: 61bb str r3, [r7, #24] EXTMEM_READ_JEDEC_ID_SPI_COMMAND); s_command.DataLength = DataSize; 8007bfc: 687b ldr r3, [r7, #4] 8007bfe: 64fb str r3, [r7, #76] @ 0x4c if (s_command.InstructionMode == HAL_XSPI_INSTRUCTION_1_LINE) 8007c00: 69fb ldr r3, [r7, #28] 8007c02: 2b01 cmp r3, #1 8007c04: d107 bne.n 8007c16 { s_command.AddressMode = HAL_XSPI_ADDRESS_NONE; 8007c06: 2300 movs r3, #0 8007c08: 62fb str r3, [r7, #44] @ 0x2c s_command.DummyCycles = 0; 8007c0a: 2300 movs r3, #0 8007c0c: 657b str r3, [r7, #84] @ 0x54 /* This behavior is linked with micron memory to read ID in 1S8S8S */ s_command.DataMode = HAL_XSPI_DATA_1_LINE; 8007c0e: f04f 7380 mov.w r3, #16777216 @ 0x1000000 8007c12: 64bb str r3, [r7, #72] @ 0x48 8007c14: e030 b.n 8007c78 } else if (s_command.InstructionMode == HAL_XSPI_INSTRUCTION_4_LINES) 8007c16: 69fb ldr r3, [r7, #28] 8007c18: 2b03 cmp r3, #3 8007c1a: d107 bne.n 8007c2c { s_command.AddressMode = HAL_XSPI_ADDRESS_NONE; 8007c1c: 2300 movs r3, #0 8007c1e: 62fb str r3, [r7, #44] @ 0x2c s_command.DummyCycles = 0; 8007c20: 2300 movs r3, #0 8007c22: 657b str r3, [r7, #84] @ 0x54 /* This behavior is linked with ISSI memory to read ID in 4S4S4S */ s_command.DataMode = HAL_XSPI_DATA_4_LINES; 8007c24: f04f 7340 mov.w r3, #50331648 @ 0x3000000 8007c28: 64bb str r3, [r7, #72] @ 0x48 8007c2a: e025 b.n 8007c78 } else if (s_command.InstructionMode == HAL_XSPI_INSTRUCTION_8_LINES) 8007c2c: 69fb ldr r3, [r7, #28] 8007c2e: 2b04 cmp r3, #4 8007c30: d11e bne.n 8007c70 { s_command.Address = 0; 8007c32: 2300 movs r3, #0 8007c34: 62bb str r3, [r7, #40] @ 0x28 /* Specific case for Macronix memories : RDID is not Data DTR */ if ((Data[0] == 0xC2) && (s_command.DataDTRMode == HAL_XSPI_DATA_DTR_ENABLE)) 8007c36: 68bb ldr r3, [r7, #8] 8007c38: 781b ldrb r3, [r3, #0] 8007c3a: 2bc2 cmp r3, #194 @ 0xc2 8007c3c: d108 bne.n 8007c50 8007c3e: 6d3b ldr r3, [r7, #80] @ 0x50 8007c40: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 8007c44: d104 bne.n 8007c50 { s_command.DummyCycles = 4; 8007c46: 2304 movs r3, #4 8007c48: 657b str r3, [r7, #84] @ 0x54 s_command.DataDTRMode = HAL_XSPI_DATA_DTR_DISABLE; 8007c4a: 2300 movs r3, #0 8007c4c: 653b str r3, [r7, #80] @ 0x50 8007c4e: e013 b.n 8007c78 } /* Specific case for GigaDevice memories : RDID has no address even in Octal mode */ else if ((Data[0] == 0xC8) && (s_command.DataDTRMode == HAL_XSPI_DATA_DTR_ENABLE)) 8007c50: 68bb ldr r3, [r7, #8] 8007c52: 781b ldrb r3, [r3, #0] 8007c54: 2bc8 cmp r3, #200 @ 0xc8 8007c56: d108 bne.n 8007c6a 8007c58: 6d3b ldr r3, [r7, #80] @ 0x50 8007c5a: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 8007c5e: d104 bne.n 8007c6a { s_command.DummyCycles = 8; 8007c60: 2308 movs r3, #8 8007c62: 657b str r3, [r7, #84] @ 0x54 s_command.AddressMode = HAL_XSPI_ADDRESS_NONE; 8007c64: 2300 movs r3, #0 8007c66: 62fb str r3, [r7, #44] @ 0x2c 8007c68: e006 b.n 8007c78 } else { s_command.DummyCycles = 8; 8007c6a: 2308 movs r3, #8 8007c6c: 657b str r3, [r7, #84] @ 0x54 8007c6e: e003 b.n 8007c78 } /* Required behavior to be confirmed on the other memories */ } else { s_command.Address = 0; 8007c70: 2300 movs r3, #0 8007c72: 62bb str r3, [r7, #40] @ 0x28 s_command.DummyCycles = 8; 8007c74: 2308 movs r3, #8 8007c76: 657b str r3, [r7, #84] @ 0x54 } /* Configure the command */ retr = HAL_XSPI_Command(SalXspi->hxspi, &s_command, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); 8007c78: 68fb ldr r3, [r7, #12] 8007c7a: 681b ldr r3, [r3, #0] 8007c7c: f107 0110 add.w r1, r7, #16 8007c80: 2264 movs r2, #100 @ 0x64 8007c82: 4618 mov r0, r3 8007c84: f7fd fef4 bl 8005a70 8007c88: 4603 mov r3, r0 8007c8a: f887 305f strb.w r3, [r7, #95] @ 0x5f if (retr != HAL_OK) 8007c8e: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8007c92: 2b00 cmp r3, #0 8007c94: d10a bne.n 8007cac { goto error; } /* Reception of the data */ retr = HAL_XSPI_Receive(SalXspi->hxspi, Data, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); 8007c96: 68fb ldr r3, [r7, #12] 8007c98: 681b ldr r3, [r3, #0] 8007c9a: 2264 movs r2, #100 @ 0x64 8007c9c: 68b9 ldr r1, [r7, #8] 8007c9e: 4618 mov r0, r3 8007ca0: f7fd ffe9 bl 8005c76 8007ca4: 4603 mov r3, r0 8007ca6: f887 305f strb.w r3, [r7, #95] @ 0x5f 8007caa: e000 b.n 8007cae goto error; 8007cac: bf00 nop error: if (retr != HAL_OK) 8007cae: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8007cb2: 2b00 cmp r3, #0 8007cb4: d004 beq.n 8007cc0 { /* Abort any ongoing transaction for the next action */ (void)HAL_XSPI_Abort(SalXspi->hxspi); 8007cb6: 68fb ldr r3, [r7, #12] 8007cb8: 681b ldr r3, [r3, #0] 8007cba: 4618 mov r0, r3 8007cbc: f7fe fce6 bl 800668c } return retr; 8007cc0: f897 305f ldrb.w r3, [r7, #95] @ 0x5f } 8007cc4: 4618 mov r0, r3 8007cc6: 3760 adds r7, #96 @ 0x60 8007cc8: 46bd mov sp, r7 8007cca: bd80 pop {r7, pc} 08007ccc : * @param DataSize Size of the data to read * @return @ref HAL_StatusTypeDef **/ HAL_StatusTypeDef SAL_XSPI_Read(SAL_XSPI_ObjectTypeDef *SalXspi, uint8_t Command, uint32_t Address, uint8_t *Data, uint32_t DataSize) { 8007ccc: b580 push {r7, lr} 8007cce: b098 sub sp, #96 @ 0x60 8007cd0: af00 add r7, sp, #0 8007cd2: 60f8 str r0, [r7, #12] 8007cd4: 607a str r2, [r7, #4] 8007cd6: 603b str r3, [r7, #0] 8007cd8: 460b mov r3, r1 8007cda: 72fb strb r3, [r7, #11] HAL_StatusTypeDef retr; XSPI_RegularCmdTypeDef s_command = SalXspi->Commandbase; 8007cdc: 68fb ldr r3, [r7, #12] 8007cde: f107 0010 add.w r0, r7, #16 8007ce2: 3304 adds r3, #4 8007ce4: 224c movs r2, #76 @ 0x4c 8007ce6: 4619 mov r1, r3 8007ce8: f002 fa00 bl 800a0ec /* Initialize the read ID command */ s_command.Instruction = XSPI_FormatCommand(SalXspi->CommandExtension, s_command.InstructionWidth, Command); 8007cec: 68fb ldr r3, [r7, #12] 8007cee: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 8007cf2: 6a39 ldr r1, [r7, #32] 8007cf4: 7afa ldrb r2, [r7, #11] 8007cf6: 4618 mov r0, r3 8007cf8: f000 fb29 bl 800834e 8007cfc: 4603 mov r3, r0 8007cfe: 61bb str r3, [r7, #24] s_command.Address = Address; 8007d00: 687b ldr r3, [r7, #4] 8007d02: 62bb str r3, [r7, #40] @ 0x28 s_command.DataLength = DataSize; 8007d04: 6ebb ldr r3, [r7, #104] @ 0x68 8007d06: 64fb str r3, [r7, #76] @ 0x4c /* DTR management for single/dual/quad */ switch (SalXspi->PhyLink) 8007d08: 68fb ldr r3, [r7, #12] 8007d0a: f893 3052 ldrb.w r3, [r3, #82] @ 0x52 8007d0e: 2b05 cmp r3, #5 8007d10: d006 beq.n 8007d20 8007d12: 2b05 cmp r3, #5 8007d14: dc1a bgt.n 8007d4c 8007d16: 2b01 cmp r3, #1 8007d18: d014 beq.n 8007d44 8007d1a: 2b02 cmp r3, #2 8007d1c: d00b beq.n 8007d36 s_command.DataMode = HAL_XSPI_DATA_2_LINES; break; default : /* Keep default parameters */ break; 8007d1e: e015 b.n 8007d4c s_command.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_ENABLE; 8007d20: f44f 6300 mov.w r3, #2048 @ 0x800 8007d24: 637b str r3, [r7, #52] @ 0x34 s_command.DataDTRMode = HAL_XSPI_DATA_DTR_ENABLE; 8007d26: f04f 6300 mov.w r3, #134217728 @ 0x8000000 8007d2a: 653b str r3, [r7, #80] @ 0x50 s_command.DummyCycles = SalXspi->DTRDummyCycle; 8007d2c: 68fb ldr r3, [r7, #12] 8007d2e: f893 3053 ldrb.w r3, [r3, #83] @ 0x53 8007d32: 657b str r3, [r7, #84] @ 0x54 break; 8007d34: e00b b.n 8007d4e s_command.AddressMode = HAL_XSPI_ADDRESS_2_LINES; 8007d36: f44f 7300 mov.w r3, #512 @ 0x200 8007d3a: 62fb str r3, [r7, #44] @ 0x2c s_command.DataMode = HAL_XSPI_DATA_2_LINES; 8007d3c: f04f 7300 mov.w r3, #33554432 @ 0x2000000 8007d40: 64bb str r3, [r7, #72] @ 0x48 break; 8007d42: e004 b.n 8007d4e s_command.DataMode = HAL_XSPI_DATA_2_LINES; 8007d44: f04f 7300 mov.w r3, #33554432 @ 0x2000000 8007d48: 64bb str r3, [r7, #72] @ 0x48 break; 8007d4a: e000 b.n 8007d4e break; 8007d4c: bf00 nop } /* Configure the command */ retr = HAL_XSPI_Command(SalXspi->hxspi, &s_command, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); 8007d4e: 68fb ldr r3, [r7, #12] 8007d50: 681b ldr r3, [r3, #0] 8007d52: f107 0110 add.w r1, r7, #16 8007d56: 2264 movs r2, #100 @ 0x64 8007d58: 4618 mov r0, r3 8007d5a: f7fd fe89 bl 8005a70 8007d5e: 4603 mov r3, r0 8007d60: f887 305f strb.w r3, [r7, #95] @ 0x5f if (retr != HAL_OK) 8007d64: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8007d68: 2b00 cmp r3, #0 8007d6a: d107 bne.n 8007d7c { goto error; } /* Read data */ retr = XSPI_Receive(SalXspi, Data); 8007d6c: 6839 ldr r1, [r7, #0] 8007d6e: 68f8 ldr r0, [r7, #12] 8007d70: f000 fb4c bl 800840c 8007d74: 4603 mov r3, r0 8007d76: f887 305f strb.w r3, [r7, #95] @ 0x5f 8007d7a: e000 b.n 8007d7e goto error; 8007d7c: bf00 nop error: if (retr != HAL_OK) 8007d7e: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8007d82: 2b00 cmp r3, #0 8007d84: d004 beq.n 8007d90 { /* Abort any ongoing transaction for the next action */ (void)HAL_XSPI_Abort(SalXspi->hxspi); 8007d86: 68fb ldr r3, [r7, #12] 8007d88: 681b ldr r3, [r3, #0] 8007d8a: 4618 mov r0, r3 8007d8c: f7fe fc7e bl 800668c } return retr; 8007d90: f897 305f ldrb.w r3, [r7, #95] @ 0x5f } 8007d94: 4618 mov r0, r3 8007d96: 3760 adds r7, #96 @ 0x60 8007d98: 46bd mov sp, r7 8007d9a: bd80 pop {r7, pc} 08007d9c : * @param DataSize Size of the data to write * @return @ref HAL_StatusTypeDef **/ HAL_StatusTypeDef SAL_XSPI_Write(SAL_XSPI_ObjectTypeDef *SalXspi, uint8_t Command, uint32_t Address, const uint8_t *Data, uint32_t DataSize) { 8007d9c: b580 push {r7, lr} 8007d9e: b098 sub sp, #96 @ 0x60 8007da0: af00 add r7, sp, #0 8007da2: 60f8 str r0, [r7, #12] 8007da4: 607a str r2, [r7, #4] 8007da6: 603b str r3, [r7, #0] 8007da8: 460b mov r3, r1 8007daa: 72fb strb r3, [r7, #11] HAL_StatusTypeDef retr; XSPI_RegularCmdTypeDef s_command = SalXspi->Commandbase; 8007dac: 68fb ldr r3, [r7, #12] 8007dae: f107 0010 add.w r0, r7, #16 8007db2: 3304 adds r3, #4 8007db4: 224c movs r2, #76 @ 0x4c 8007db6: 4619 mov r1, r3 8007db8: f002 f998 bl 800a0ec /* Initialize the read ID command */ s_command.Instruction = XSPI_FormatCommand(SalXspi->CommandExtension, s_command.InstructionWidth, Command); 8007dbc: 68fb ldr r3, [r7, #12] 8007dbe: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 8007dc2: 6a39 ldr r1, [r7, #32] 8007dc4: 7afa ldrb r2, [r7, #11] 8007dc6: 4618 mov r0, r3 8007dc8: f000 fac1 bl 800834e 8007dcc: 4603 mov r3, r0 8007dce: 61bb str r3, [r7, #24] s_command.Address = Address; 8007dd0: 687b ldr r3, [r7, #4] 8007dd2: 62bb str r3, [r7, #40] @ 0x28 s_command.DataLength = DataSize; 8007dd4: 6ebb ldr r3, [r7, #104] @ 0x68 8007dd6: 64fb str r3, [r7, #76] @ 0x4c s_command.DummyCycles = 0u; 8007dd8: 2300 movs r3, #0 8007dda: 657b str r3, [r7, #84] @ 0x54 s_command.DQSMode = HAL_XSPI_DQS_DISABLE; 8007ddc: 2300 movs r3, #0 8007dde: 65bb str r3, [r7, #88] @ 0x58 /* Configure the command */ retr = HAL_XSPI_Command(SalXspi->hxspi, &s_command, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); 8007de0: 68fb ldr r3, [r7, #12] 8007de2: 681b ldr r3, [r3, #0] 8007de4: f107 0110 add.w r1, r7, #16 8007de8: 2264 movs r2, #100 @ 0x64 8007dea: 4618 mov r0, r3 8007dec: f7fd fe40 bl 8005a70 8007df0: 4603 mov r3, r0 8007df2: f887 305f strb.w r3, [r7, #95] @ 0x5f if (HAL_OK != retr) 8007df6: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8007dfa: 2b00 cmp r3, #0 8007dfc: d107 bne.n 8007e0e { goto error; } /* Transmit data */ retr = XSPI_Transmit(SalXspi, Data); 8007dfe: 6839 ldr r1, [r7, #0] 8007e00: 68f8 ldr r0, [r7, #12] 8007e02: f000 facd bl 80083a0 8007e06: 4603 mov r3, r0 8007e08: f887 305f strb.w r3, [r7, #95] @ 0x5f 8007e0c: e000 b.n 8007e10 goto error; 8007e0e: bf00 nop error: if (retr != HAL_OK) 8007e10: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8007e14: 2b00 cmp r3, #0 8007e16: d004 beq.n 8007e22 { /* Abort any ongoing transaction for the next action */ (void)HAL_XSPI_Abort(SalXspi->hxspi); 8007e18: 68fb ldr r3, [r7, #12] 8007e1a: 681b ldr r3, [r3, #0] 8007e1c: 4618 mov r0, r3 8007e1e: f7fe fc35 bl 800668c } return retr; 8007e22: f897 305f ldrb.w r3, [r7, #95] @ 0x5f } 8007e26: 4618 mov r0, r3 8007e28: 3760 adds r7, #96 @ 0x60 8007e2a: 46bd mov sp, r7 8007e2c: bd80 pop {r7, pc} 08007e2e : * @param DataSize Size of the data to write * @return @ref HAL_StatusTypeDef **/ HAL_StatusTypeDef SAL_XSPI_CommandSendData(SAL_XSPI_ObjectTypeDef *SalXspi, uint8_t Command, uint8_t *Data, uint16_t DataSize) { 8007e2e: b580 push {r7, lr} 8007e30: b098 sub sp, #96 @ 0x60 8007e32: af00 add r7, sp, #0 8007e34: 60f8 str r0, [r7, #12] 8007e36: 607a str r2, [r7, #4] 8007e38: 461a mov r2, r3 8007e3a: 460b mov r3, r1 8007e3c: 72fb strb r3, [r7, #11] 8007e3e: 4613 mov r3, r2 8007e40: 813b strh r3, [r7, #8] XSPI_RegularCmdTypeDef s_command = SalXspi->Commandbase; 8007e42: 68fb ldr r3, [r7, #12] 8007e44: f107 0010 add.w r0, r7, #16 8007e48: 3304 adds r3, #4 8007e4a: 224c movs r2, #76 @ 0x4c 8007e4c: 4619 mov r1, r3 8007e4e: f002 f94d bl 800a0ec HAL_StatusTypeDef retr; /* Initialize the writing of status register */ s_command.Instruction = XSPI_FormatCommand(SalXspi->CommandExtension, s_command.InstructionWidth, Command); 8007e52: 68fb ldr r3, [r7, #12] 8007e54: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 8007e58: 6a39 ldr r1, [r7, #32] 8007e5a: 7afa ldrb r2, [r7, #11] 8007e5c: 4618 mov r0, r3 8007e5e: f000 fa76 bl 800834e 8007e62: 4603 mov r3, r0 8007e64: 61bb str r3, [r7, #24] s_command.AddressMode = HAL_XSPI_ADDRESS_NONE; 8007e66: 2300 movs r3, #0 8007e68: 62fb str r3, [r7, #44] @ 0x2c s_command.DummyCycles = 0U; 8007e6a: 2300 movs r3, #0 8007e6c: 657b str r3, [r7, #84] @ 0x54 s_command.DataLength = DataSize; 8007e6e: 893b ldrh r3, [r7, #8] 8007e70: 64fb str r3, [r7, #76] @ 0x4c s_command.DQSMode = HAL_XSPI_DQS_DISABLE; 8007e72: 2300 movs r3, #0 8007e74: 65bb str r3, [r7, #88] @ 0x58 if (DataSize == 0u) 8007e76: 893b ldrh r3, [r7, #8] 8007e78: 2b00 cmp r3, #0 8007e7a: d101 bne.n 8007e80 { s_command.DataMode = HAL_XSPI_DATA_NONE; 8007e7c: 2300 movs r3, #0 8007e7e: 64bb str r3, [r7, #72] @ 0x48 } /* Send the command */ retr = HAL_XSPI_Command(SalXspi->hxspi, &s_command, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); 8007e80: 68fb ldr r3, [r7, #12] 8007e82: 681b ldr r3, [r3, #0] 8007e84: f107 0110 add.w r1, r7, #16 8007e88: 2264 movs r2, #100 @ 0x64 8007e8a: 4618 mov r0, r3 8007e8c: f7fd fdf0 bl 8005a70 8007e90: 4603 mov r3, r0 8007e92: f887 305f strb.w r3, [r7, #95] @ 0x5f if ((retr == HAL_OK) && (DataSize != 0u)) 8007e96: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8007e9a: 2b00 cmp r3, #0 8007e9c: d10c bne.n 8007eb8 8007e9e: 893b ldrh r3, [r7, #8] 8007ea0: 2b00 cmp r3, #0 8007ea2: d009 beq.n 8007eb8 { retr = HAL_XSPI_Transmit(SalXspi->hxspi, Data, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); 8007ea4: 68fb ldr r3, [r7, #12] 8007ea6: 681b ldr r3, [r3, #0] 8007ea8: 2264 movs r2, #100 @ 0x64 8007eaa: 6879 ldr r1, [r7, #4] 8007eac: 4618 mov r0, r3 8007eae: f7fd fe6f bl 8005b90 8007eb2: 4603 mov r3, r0 8007eb4: f887 305f strb.w r3, [r7, #95] @ 0x5f } if (retr != HAL_OK) 8007eb8: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8007ebc: 2b00 cmp r3, #0 8007ebe: d004 beq.n 8007eca { /* Abort any ongoing transaction for the next action */ (void)HAL_XSPI_Abort(SalXspi->hxspi); 8007ec0: 68fb ldr r3, [r7, #12] 8007ec2: 681b ldr r3, [r3, #0] 8007ec4: 4618 mov r0, r3 8007ec6: f7fe fbe1 bl 800668c } return retr; 8007eca: f897 305f ldrb.w r3, [r7, #95] @ 0x5f } 8007ece: 4618 mov r0, r3 8007ed0: 3760 adds r7, #96 @ 0x60 8007ed2: 46bd mov sp, r7 8007ed4: bd80 pop {r7, pc} 08007ed6 : * @param DataSize Size of the data to receive * @return @ref HAL_StatusTypeDef **/ HAL_StatusTypeDef SAL_XSPI_SendReadCommand(SAL_XSPI_ObjectTypeDef *SalXspi, uint8_t Command, uint8_t *Data, uint16_t DataSize) { 8007ed6: b580 push {r7, lr} 8007ed8: b098 sub sp, #96 @ 0x60 8007eda: af00 add r7, sp, #0 8007edc: 60f8 str r0, [r7, #12] 8007ede: 607a str r2, [r7, #4] 8007ee0: 461a mov r2, r3 8007ee2: 460b mov r3, r1 8007ee4: 72fb strb r3, [r7, #11] 8007ee6: 4613 mov r3, r2 8007ee8: 813b strh r3, [r7, #8] XSPI_RegularCmdTypeDef s_command = SalXspi->Commandbase; 8007eea: 68fb ldr r3, [r7, #12] 8007eec: f107 0010 add.w r0, r7, #16 8007ef0: 3304 adds r3, #4 8007ef2: 224c movs r2, #76 @ 0x4c 8007ef4: 4619 mov r1, r3 8007ef6: f002 f8f9 bl 800a0ec HAL_StatusTypeDef retr; /* Initialize the reading of status register */ s_command.Instruction = XSPI_FormatCommand(SalXspi->CommandExtension, s_command.InstructionWidth, Command); 8007efa: 68fb ldr r3, [r7, #12] 8007efc: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 8007f00: 6a39 ldr r1, [r7, #32] 8007f02: 7afa ldrb r2, [r7, #11] 8007f04: 4618 mov r0, r3 8007f06: f000 fa22 bl 800834e 8007f0a: 4603 mov r3, r0 8007f0c: 61bb str r3, [r7, #24] s_command.AddressMode = HAL_XSPI_ADDRESS_NONE; 8007f0e: 2300 movs r3, #0 8007f10: 62fb str r3, [r7, #44] @ 0x2c s_command.DummyCycles = 0u; 8007f12: 2300 movs r3, #0 8007f14: 657b str r3, [r7, #84] @ 0x54 s_command.DataLength = DataSize; 8007f16: 893b ldrh r3, [r7, #8] 8007f18: 64fb str r3, [r7, #76] @ 0x4c s_command.DQSMode = HAL_XSPI_DQS_DISABLE; 8007f1a: 2300 movs r3, #0 8007f1c: 65bb str r3, [r7, #88] @ 0x58 if (DataSize == 0u) 8007f1e: 893b ldrh r3, [r7, #8] 8007f20: 2b00 cmp r3, #0 8007f22: d101 bne.n 8007f28 { s_command.DataMode = HAL_XSPI_DATA_NONE; 8007f24: 2300 movs r3, #0 8007f26: 64bb str r3, [r7, #72] @ 0x48 } /* Send the command */ retr = HAL_XSPI_Command(SalXspi->hxspi, &s_command, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); 8007f28: 68fb ldr r3, [r7, #12] 8007f2a: 681b ldr r3, [r3, #0] 8007f2c: f107 0110 add.w r1, r7, #16 8007f30: 2264 movs r2, #100 @ 0x64 8007f32: 4618 mov r0, r3 8007f34: f7fd fd9c bl 8005a70 8007f38: 4603 mov r3, r0 8007f3a: f887 305f strb.w r3, [r7, #95] @ 0x5f if ((retr == HAL_OK) && (DataSize != 0u)) 8007f3e: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8007f42: 2b00 cmp r3, #0 8007f44: d10c bne.n 8007f60 8007f46: 893b ldrh r3, [r7, #8] 8007f48: 2b00 cmp r3, #0 8007f4a: d009 beq.n 8007f60 { /* Receive data */ retr = HAL_XSPI_Receive(SalXspi->hxspi, Data, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); 8007f4c: 68fb ldr r3, [r7, #12] 8007f4e: 681b ldr r3, [r3, #0] 8007f50: 2264 movs r2, #100 @ 0x64 8007f52: 6879 ldr r1, [r7, #4] 8007f54: 4618 mov r0, r3 8007f56: f7fd fe8e bl 8005c76 8007f5a: 4603 mov r3, r0 8007f5c: f887 305f strb.w r3, [r7, #95] @ 0x5f } if (retr != HAL_OK) 8007f60: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8007f64: 2b00 cmp r3, #0 8007f66: d004 beq.n 8007f72 { /* Abort any ongoing transaction for the next action */ (void)HAL_XSPI_Abort(SalXspi->hxspi); 8007f68: 68fb ldr r3, [r7, #12] 8007f6a: 681b ldr r3, [r3, #0] 8007f6c: 4618 mov r0, r3 8007f6e: f7fe fb8d bl 800668c } return retr; 8007f72: f897 305f ldrb.w r3, [r7, #95] @ 0x5f } 8007f76: 4618 mov r0, r3 8007f78: 3760 adds r7, #96 @ 0x60 8007f7a: 46bd mov sp, r7 8007f7c: bd80 pop {r7, pc} 08007f7e : * @return @ref HAL_StatusTypeDef **/ HAL_StatusTypeDef SAL_XSPI_CommandSendReadAddress(SAL_XSPI_ObjectTypeDef *SalXspi, uint8_t Command, uint32_t Address, uint8_t *Data, uint16_t DataSize, uint8_t ManuId) { 8007f7e: b580 push {r7, lr} 8007f80: b098 sub sp, #96 @ 0x60 8007f82: af00 add r7, sp, #0 8007f84: 60f8 str r0, [r7, #12] 8007f86: 607a str r2, [r7, #4] 8007f88: 603b str r3, [r7, #0] 8007f8a: 460b mov r3, r1 8007f8c: 72fb strb r3, [r7, #11] XSPI_RegularCmdTypeDef s_command = SalXspi->Commandbase; 8007f8e: 68fb ldr r3, [r7, #12] 8007f90: f107 0010 add.w r0, r7, #16 8007f94: 3304 adds r3, #4 8007f96: 224c movs r2, #76 @ 0x4c 8007f98: 4619 mov r1, r3 8007f9a: f002 f8a7 bl 800a0ec HAL_StatusTypeDef retr; /* Initialize the reading of status register */ s_command.Instruction = XSPI_FormatCommand(SalXspi->CommandExtension, s_command.InstructionWidth, Command); 8007f9e: 68fb ldr r3, [r7, #12] 8007fa0: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 8007fa4: 6a39 ldr r1, [r7, #32] 8007fa6: 7afa ldrb r2, [r7, #11] 8007fa8: 4618 mov r0, r3 8007faa: f000 f9d0 bl 800834e 8007fae: 4603 mov r3, r0 8007fb0: 61bb str r3, [r7, #24] s_command.Address = Address; 8007fb2: 687b ldr r3, [r7, #4] 8007fb4: 62bb str r3, [r7, #40] @ 0x28 s_command.DummyCycles = SalXspi->SFDPDummyCycle; 8007fb6: 68fb ldr r3, [r7, #12] 8007fb8: f893 3051 ldrb.w r3, [r3, #81] @ 0x51 8007fbc: 657b str r3, [r7, #84] @ 0x54 s_command.DataLength = DataSize; 8007fbe: f8b7 3068 ldrh.w r3, [r7, #104] @ 0x68 8007fc2: 64fb str r3, [r7, #76] @ 0x4c /* Specific case for Macronix memories : RDID and RDCR are not Data DTR */ if ((ManuId == EXTMEM_MANUFACTURER_MACRONIX) && (s_command.DataDTRMode == HAL_XSPI_DATA_DTR_ENABLE)) 8007fc4: f897 306c ldrb.w r3, [r7, #108] @ 0x6c 8007fc8: 2bc2 cmp r3, #194 @ 0xc2 8007fca: d106 bne.n 8007fda 8007fcc: 6d3b ldr r3, [r7, #80] @ 0x50 8007fce: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 8007fd2: d102 bne.n 8007fda { s_command.DataDTRMode = HAL_XSPI_DATA_DTR_DISABLE; 8007fd4: 2300 movs r3, #0 8007fd6: 653b str r3, [r7, #80] @ 0x50 8007fd8: e00e b.n 8007ff8 } /* Specific case for GigaDevice memories : Read Configuration Register are not Data DTR */ else if ((ManuId == 0xC8) && (s_command.DataDTRMode == HAL_XSPI_DATA_DTR_ENABLE)) 8007fda: f897 306c ldrb.w r3, [r7, #108] @ 0x6c 8007fde: 2bc8 cmp r3, #200 @ 0xc8 8007fe0: d108 bne.n 8007ff4 8007fe2: 6d3b ldr r3, [r7, #80] @ 0x50 8007fe4: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 8007fe8: d104 bne.n 8007ff4 { s_command.DataDTRMode = HAL_XSPI_DATA_DTR_DISABLE; 8007fea: 2300 movs r3, #0 8007fec: 653b str r3, [r7, #80] @ 0x50 s_command.DQSMode = HAL_XSPI_DQS_DISABLE; 8007fee: 2300 movs r3, #0 8007ff0: 65bb str r3, [r7, #88] @ 0x58 8007ff2: e001 b.n 8007ff8 } else { s_command.DQSMode = HAL_XSPI_DQS_DISABLE; 8007ff4: 2300 movs r3, #0 8007ff6: 65bb str r3, [r7, #88] @ 0x58 } /* Send the command */ retr = HAL_XSPI_Command(SalXspi->hxspi, &s_command, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); 8007ff8: 68fb ldr r3, [r7, #12] 8007ffa: 681b ldr r3, [r3, #0] 8007ffc: f107 0110 add.w r1, r7, #16 8008000: 2264 movs r2, #100 @ 0x64 8008002: 4618 mov r0, r3 8008004: f7fd fd34 bl 8005a70 8008008: 4603 mov r3, r0 800800a: f887 305f strb.w r3, [r7, #95] @ 0x5f if (retr == HAL_OK) 800800e: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8008012: 2b00 cmp r3, #0 8008014: d109 bne.n 800802a { /* Retrieve data */ retr = HAL_XSPI_Receive(SalXspi->hxspi, Data, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); 8008016: 68fb ldr r3, [r7, #12] 8008018: 681b ldr r3, [r3, #0] 800801a: 2264 movs r2, #100 @ 0x64 800801c: 6839 ldr r1, [r7, #0] 800801e: 4618 mov r0, r3 8008020: f7fd fe29 bl 8005c76 8008024: 4603 mov r3, r0 8008026: f887 305f strb.w r3, [r7, #95] @ 0x5f } if (retr != HAL_OK) 800802a: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 800802e: 2b00 cmp r3, #0 8008030: d004 beq.n 800803c { /* Abort any ongoing transaction for the next action */ (void)HAL_XSPI_Abort(SalXspi->hxspi); 8008032: 68fb ldr r3, [r7, #12] 8008034: 681b ldr r3, [r3, #0] 8008036: 4618 mov r0, r3 8008038: f7fe fb28 bl 800668c } return retr; 800803c: f897 305f ldrb.w r3, [r7, #95] @ 0x5f } 8008040: 4618 mov r0, r3 8008042: 3760 adds r7, #96 @ 0x60 8008044: 46bd mov sp, r7 8008046: bd80 pop {r7, pc} 08008048 : * @return @ref HAL_StatusTypeDef **/ HAL_StatusTypeDef SAL_XSPI_CheckStatusRegister(SAL_XSPI_ObjectTypeDef *SalXspi, uint8_t Command, uint32_t Address, uint8_t MatchValue, uint8_t MatchMask, uint8_t ManuId, uint32_t Timeout) { 8008048: b580 push {r7, lr} 800804a: b09e sub sp, #120 @ 0x78 800804c: af00 add r7, sp, #0 800804e: 60f8 str r0, [r7, #12] 8008050: 607a str r2, [r7, #4] 8008052: 461a mov r2, r3 8008054: 460b mov r3, r1 8008056: 72fb strb r3, [r7, #11] 8008058: 4613 mov r3, r2 800805a: 72bb strb r3, [r7, #10] XSPI_RegularCmdTypeDef s_command = SalXspi->Commandbase; 800805c: 68fb ldr r3, [r7, #12] 800805e: f107 0028 add.w r0, r7, #40 @ 0x28 8008062: 3304 adds r3, #4 8008064: 224c movs r2, #76 @ 0x4c 8008066: 4619 mov r1, r3 8008068: f002 f840 bl 800a0ec XSPI_AutoPollingTypeDef s_config = 800806c: 7abb ldrb r3, [r7, #10] 800806e: 617b str r3, [r7, #20] 8008070: f897 3080 ldrb.w r3, [r7, #128] @ 0x80 8008074: 61bb str r3, [r7, #24] 8008076: 2300 movs r3, #0 8008078: 61fb str r3, [r7, #28] 800807a: f44f 0380 mov.w r3, #4194304 @ 0x400000 800807e: 623b str r3, [r7, #32] 8008080: 2310 movs r3, #16 8008082: 627b str r3, [r7, #36] @ 0x24 .IntervalTime = 0x10 }; HAL_StatusTypeDef retr; /* Initialize the reading of status register */ s_command.Instruction = XSPI_FormatCommand(SalXspi->CommandExtension, s_command.InstructionWidth, Command); 8008084: 68fb ldr r3, [r7, #12] 8008086: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 800808a: 6bb9 ldr r1, [r7, #56] @ 0x38 800808c: 7afa ldrb r2, [r7, #11] 800808e: 4618 mov r0, r3 8008090: f000 f95d bl 800834e 8008094: 4603 mov r3, r0 8008096: 633b str r3, [r7, #48] @ 0x30 s_command.DataLength = 1u; 8008098: 2301 movs r3, #1 800809a: 667b str r3, [r7, #100] @ 0x64 s_command.DQSMode = HAL_XSPI_DQS_DISABLE; 800809c: 2300 movs r3, #0 800809e: 673b str r3, [r7, #112] @ 0x70 if (s_command.InstructionMode == HAL_XSPI_INSTRUCTION_1_LINE) 80080a0: 6b7b ldr r3, [r7, #52] @ 0x34 80080a2: 2b01 cmp r3, #1 80080a4: d106 bne.n 80080b4 { /* Specific behavior for Cypress to force 1 line on status read */ s_command.DataMode = HAL_XSPI_DATA_1_LINE; 80080a6: f04f 7380 mov.w r3, #16777216 @ 0x1000000 80080aa: 663b str r3, [r7, #96] @ 0x60 s_command.AddressMode = HAL_XSPI_DATA_NONE; 80080ac: 2300 movs r3, #0 80080ae: 647b str r3, [r7, #68] @ 0x44 s_command.DummyCycles = 0u; 80080b0: 2300 movs r3, #0 80080b2: 66fb str r3, [r7, #108] @ 0x6c } /* Address is used only in 8 LINES format */ if (s_command.DataMode == HAL_XSPI_DATA_8_LINES) 80080b4: 6e3b ldr r3, [r7, #96] @ 0x60 80080b6: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 80080ba: d114 bne.n 80080e6 { /* Specific case for Macronix memories : RDID and RDCR are not Data DTR */ if ((ManuId == EXTMEM_MANUFACTURER_MACRONIX) && (s_command.DataDTRMode == HAL_XSPI_DATA_DTR_ENABLE)) 80080bc: f897 3084 ldrb.w r3, [r7, #132] @ 0x84 80080c0: 2bc2 cmp r3, #194 @ 0xc2 80080c2: d108 bne.n 80080d6 80080c4: 6ebb ldr r3, [r7, #104] @ 0x68 80080c6: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 80080ca: d104 bne.n 80080d6 { s_command.DQSMode = HAL_XSPI_DQS_ENABLE; 80080cc: f04f 5300 mov.w r3, #536870912 @ 0x20000000 80080d0: 673b str r3, [r7, #112] @ 0x70 s_command.DataDTRMode = HAL_XSPI_DATA_DTR_DISABLE; 80080d2: 2300 movs r3, #0 80080d4: 66bb str r3, [r7, #104] @ 0x68 } s_command.AddressMode = HAL_XSPI_ADDRESS_8_LINES; 80080d6: f44f 6380 mov.w r3, #1024 @ 0x400 80080da: 647b str r3, [r7, #68] @ 0x44 s_command.AddressWidth = HAL_XSPI_ADDRESS_32_BITS; 80080dc: f44f 5340 mov.w r3, #12288 @ 0x3000 80080e0: 64bb str r3, [r7, #72] @ 0x48 s_command.Address = Address; 80080e2: 687b ldr r3, [r7, #4] 80080e4: 643b str r3, [r7, #64] @ 0x40 } /* Send the command */ retr = HAL_XSPI_Command(SalXspi->hxspi, &s_command, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); 80080e6: 68fb ldr r3, [r7, #12] 80080e8: 681b ldr r3, [r3, #0] 80080ea: f107 0128 add.w r1, r7, #40 @ 0x28 80080ee: 2264 movs r2, #100 @ 0x64 80080f0: 4618 mov r0, r3 80080f2: f7fd fcbd bl 8005a70 80080f6: 4603 mov r3, r0 80080f8: f887 3077 strb.w r3, [r7, #119] @ 0x77 if (retr == HAL_OK) 80080fc: f897 3077 ldrb.w r3, [r7, #119] @ 0x77 8008100: 2b00 cmp r3, #0 8008102: d10b bne.n 800811c { retr = HAL_XSPI_AutoPolling(SalXspi->hxspi, &s_config, Timeout); 8008104: 68fb ldr r3, [r7, #12] 8008106: 681b ldr r3, [r3, #0] 8008108: f107 0114 add.w r1, r7, #20 800810c: f8d7 2088 ldr.w r2, [r7, #136] @ 0x88 8008110: 4618 mov r0, r3 8008112: f7fe f8df bl 80062d4 8008116: 4603 mov r3, r0 8008118: f887 3077 strb.w r3, [r7, #119] @ 0x77 DEBUG_AUTOPOLLING(SalXspi->hxspi->Instance->DR, s_config.MatchValue, s_config.MatchMask) } if (retr != HAL_OK) 800811c: f897 3077 ldrb.w r3, [r7, #119] @ 0x77 8008120: 2b00 cmp r3, #0 8008122: d004 beq.n 800812e { /* Abort any ongoing transaction for the next action */ (void)HAL_XSPI_Abort(SalXspi->hxspi); 8008124: 68fb ldr r3, [r7, #12] 8008126: 681b ldr r3, [r3, #0] 8008128: 4618 mov r0, r3 800812a: f7fe faaf bl 800668c } return retr; 800812e: f897 3077 ldrb.w r3, [r7, #119] @ 0x77 } 8008132: 4618 mov r0, r3 8008134: 3778 adds r7, #120 @ 0x78 8008136: 46bd mov sp, r7 8008138: bd80 pop {r7, pc} 0800813a : * @param WrapCommand Wrap command to execute in case of write operation * @param WrapDummy Number of dummy cycle for the read operation * @return @ref HAL_StatusTypeDef **/ HAL_StatusTypeDef SAL_XSPI_ConfigureWrappMode(SAL_XSPI_ObjectTypeDef *SalXspi, uint8_t WrapCommand, uint8_t WrapDummy) { 800813a: b580 push {r7, lr} 800813c: b096 sub sp, #88 @ 0x58 800813e: af00 add r7, sp, #0 8008140: 6078 str r0, [r7, #4] 8008142: 460b mov r3, r1 8008144: 70fb strb r3, [r7, #3] 8008146: 4613 mov r3, r2 8008148: 70bb strb r3, [r7, #2] HAL_StatusTypeDef retr; XSPI_RegularCmdTypeDef s_command = SalXspi->Commandbase; 800814a: 687b ldr r3, [r7, #4] 800814c: f107 0008 add.w r0, r7, #8 8008150: 3304 adds r3, #4 8008152: 224c movs r2, #76 @ 0x4c 8008154: 4619 mov r1, r3 8008156: f001 ffc9 bl 800a0ec /* Initialize the read ID command */ s_command.OperationType = HAL_XSPI_OPTYPE_WRAP_CFG; 800815a: 2303 movs r3, #3 800815c: 60bb str r3, [r7, #8] s_command.Instruction = XSPI_FormatCommand(SalXspi->CommandExtension, s_command.InstructionWidth, WrapCommand); 800815e: 687b ldr r3, [r7, #4] 8008160: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 8008164: 69b9 ldr r1, [r7, #24] 8008166: 78fa ldrb r2, [r7, #3] 8008168: 4618 mov r0, r3 800816a: f000 f8f0 bl 800834e 800816e: 4603 mov r3, r0 8008170: 613b str r3, [r7, #16] s_command.DummyCycles = WrapDummy; 8008172: 78bb ldrb r3, [r7, #2] 8008174: 64fb str r3, [r7, #76] @ 0x4c /* Configure the read command */ retr = HAL_XSPI_Command(SalXspi->hxspi, &s_command, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); 8008176: 687b ldr r3, [r7, #4] 8008178: 681b ldr r3, [r3, #0] 800817a: f107 0108 add.w r1, r7, #8 800817e: 2264 movs r2, #100 @ 0x64 8008180: 4618 mov r0, r3 8008182: f7fd fc75 bl 8005a70 8008186: 4603 mov r3, r0 8008188: f887 3057 strb.w r3, [r7, #87] @ 0x57 if (retr != HAL_OK) 800818c: f897 3057 ldrb.w r3, [r7, #87] @ 0x57 8008190: 2b00 cmp r3, #0 { goto error; } error: 8008192: bf00 nop if (retr != HAL_OK) 8008194: f897 3057 ldrb.w r3, [r7, #87] @ 0x57 8008198: 2b00 cmp r3, #0 800819a: d004 beq.n 80081a6 { /* Abort any ongoing transaction for the next action */ (void)HAL_XSPI_Abort(SalXspi->hxspi); 800819c: 687b ldr r3, [r7, #4] 800819e: 681b ldr r3, [r3, #0] 80081a0: 4618 mov r0, r3 80081a2: f7fe fa73 bl 800668c } return retr; 80081a6: f897 3057 ldrb.w r3, [r7, #87] @ 0x57 } 80081aa: 4618 mov r0, r3 80081ac: 3758 adds r7, #88 @ 0x58 80081ae: 46bd mov sp, r7 80081b0: bd80 pop {r7, pc} 080081b2 : * @param DummyWrite number of dummy cycle for the read operation * @return @ref HAL_StatusTypeDef **/ HAL_StatusTypeDef SAL_XSPI_EnableMapMode(SAL_XSPI_ObjectTypeDef *SalXspi, uint8_t CommandRead, uint8_t DummyRead, uint8_t CommandWrite, uint8_t DummyWrite) { 80081b2: b580 push {r7, lr} 80081b4: b098 sub sp, #96 @ 0x60 80081b6: af00 add r7, sp, #0 80081b8: 6078 str r0, [r7, #4] 80081ba: 4608 mov r0, r1 80081bc: 4611 mov r1, r2 80081be: 461a mov r2, r3 80081c0: 4603 mov r3, r0 80081c2: 70fb strb r3, [r7, #3] 80081c4: 460b mov r3, r1 80081c6: 70bb strb r3, [r7, #2] 80081c8: 4613 mov r3, r2 80081ca: 707b strb r3, [r7, #1] HAL_StatusTypeDef retr; XSPI_RegularCmdTypeDef s_command = SalXspi->Commandbase; 80081cc: 687b ldr r3, [r7, #4] 80081ce: f107 0010 add.w r0, r7, #16 80081d2: 3304 adds r3, #4 80081d4: 224c movs r2, #76 @ 0x4c 80081d6: 4619 mov r1, r3 80081d8: f001 ff88 bl 800a0ec XSPI_MemoryMappedTypeDef sMemMappedCfg = {0}; 80081dc: f107 0308 add.w r3, r7, #8 80081e0: 2200 movs r2, #0 80081e2: 601a str r2, [r3, #0] 80081e4: 605a str r2, [r3, #4] /* Initialize the read ID command */ s_command.OperationType = HAL_XSPI_OPTYPE_READ_CFG; 80081e6: 2301 movs r3, #1 80081e8: 613b str r3, [r7, #16] s_command.Instruction = XSPI_FormatCommand(SalXspi->CommandExtension, s_command.InstructionWidth, CommandRead); 80081ea: 687b ldr r3, [r7, #4] 80081ec: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 80081f0: 6a39 ldr r1, [r7, #32] 80081f2: 78fa ldrb r2, [r7, #3] 80081f4: 4618 mov r0, r3 80081f6: f000 f8aa bl 800834e 80081fa: 4603 mov r3, r0 80081fc: 61bb str r3, [r7, #24] s_command.DummyCycles = DummyRead; 80081fe: 78bb ldrb r3, [r7, #2] 8008200: 657b str r3, [r7, #84] @ 0x54 /* Configure the read command */ retr = HAL_XSPI_Command(SalXspi->hxspi, &s_command, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); 8008202: 687b ldr r3, [r7, #4] 8008204: 681b ldr r3, [r3, #0] 8008206: f107 0110 add.w r1, r7, #16 800820a: 2264 movs r2, #100 @ 0x64 800820c: 4618 mov r0, r3 800820e: f7fd fc2f bl 8005a70 8008212: 4603 mov r3, r0 8008214: f887 305f strb.w r3, [r7, #95] @ 0x5f if (retr != HAL_OK) 8008218: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 800821c: 2b00 cmp r3, #0 800821e: d12d bne.n 800827c { goto error; } /* Initialize the read ID command */ s_command.OperationType = HAL_XSPI_OPTYPE_WRITE_CFG; 8008220: 2302 movs r3, #2 8008222: 613b str r3, [r7, #16] s_command.Instruction = XSPI_FormatCommand(SalXspi->CommandExtension, s_command.InstructionWidth, CommandWrite); 8008224: 687b ldr r3, [r7, #4] 8008226: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 800822a: 6a39 ldr r1, [r7, #32] 800822c: 787a ldrb r2, [r7, #1] 800822e: 4618 mov r0, r3 8008230: f000 f88d bl 800834e 8008234: 4603 mov r3, r0 8008236: 61bb str r3, [r7, #24] s_command.DummyCycles = DummyWrite; 8008238: f897 3068 ldrb.w r3, [r7, #104] @ 0x68 800823c: 657b str r3, [r7, #84] @ 0x54 /* Configure the read command */ retr = HAL_XSPI_Command(SalXspi->hxspi, &s_command, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); 800823e: 687b ldr r3, [r7, #4] 8008240: 681b ldr r3, [r3, #0] 8008242: f107 0110 add.w r1, r7, #16 8008246: 2264 movs r2, #100 @ 0x64 8008248: 4618 mov r0, r3 800824a: f7fd fc11 bl 8005a70 800824e: 4603 mov r3, r0 8008250: f887 305f strb.w r3, [r7, #95] @ 0x5f if (retr != HAL_OK) 8008254: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8008258: 2b00 cmp r3, #0 800825a: d111 bne.n 8008280 { goto error; } /* Activation of memory-mapped mode */ sMemMappedCfg.TimeOutActivation = HAL_XSPI_TIMEOUT_COUNTER_DISABLE; 800825c: 2300 movs r3, #0 800825e: 60bb str r3, [r7, #8] sMemMappedCfg.TimeoutPeriodClock = 0x50; 8008260: 2350 movs r3, #80 @ 0x50 8008262: 60fb str r3, [r7, #12] retr = HAL_XSPI_MemoryMapped(SalXspi->hxspi, &sMemMappedCfg); 8008264: 687b ldr r3, [r7, #4] 8008266: 681b ldr r3, [r3, #0] 8008268: f107 0208 add.w r2, r7, #8 800826c: 4611 mov r1, r2 800826e: 4618 mov r0, r3 8008270: f7fe f8ba bl 80063e8 8008274: 4603 mov r3, r0 8008276: f887 305f strb.w r3, [r7, #95] @ 0x5f 800827a: e002 b.n 8008282 goto error; 800827c: bf00 nop 800827e: e000 b.n 8008282 goto error; 8008280: bf00 nop error: if (retr != HAL_OK) 8008282: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8008286: 2b00 cmp r3, #0 8008288: d004 beq.n 8008294 { /* Abort any ongoing transaction for the next action */ (void)HAL_XSPI_Abort(SalXspi->hxspi); 800828a: 687b ldr r3, [r7, #4] 800828c: 681b ldr r3, [r3, #0] 800828e: 4618 mov r0, r3 8008290: f7fe f9fc bl 800668c } return retr; 8008294: f897 305f ldrb.w r3, [r7, #95] @ 0x5f } 8008298: 4618 mov r0, r3 800829a: 3760 adds r7, #96 @ 0x60 800829c: 46bd mov sp, r7 800829e: bd80 pop {r7, pc} 080082a0 : * @brief This function disables the memory mapped mode * @param SalXspi SAL XSPI handle * @return @ref HAL_StatusTypeDef **/ HAL_StatusTypeDef SAL_XSPI_DisableMapMode(SAL_XSPI_ObjectTypeDef *SalXspi) { 80082a0: b580 push {r7, lr} 80082a2: b082 sub sp, #8 80082a4: af00 add r7, sp, #0 80082a6: 6078 str r0, [r7, #4] __ASM volatile ("dsb 0xF":::"memory"); 80082a8: f3bf 8f4f dsb sy } 80082ac: bf00 nop __DSB(); return HAL_XSPI_Abort(SalXspi->hxspi); 80082ae: 687b ldr r3, [r7, #4] 80082b0: 681b ldr r3, [r3, #0] 80082b2: 4618 mov r0, r3 80082b4: f7fe f9ea bl 800668c 80082b8: 4603 mov r3, r0 } 80082ba: 4618 mov r0, r3 80082bc: 3708 adds r7, #8 80082be: 46bd mov sp, r7 80082c0: bd80 pop {r7, pc} 080082c2 : * @param SalXspi SAL XSPI handle * @param DataOrder Selected data order * @return @ref HAL_StatusTypeDef **/ HAL_StatusTypeDef SAL_XSPI_UpdateMemoryType(SAL_XSPI_ObjectTypeDef *SalXspi, SAL_XSPI_DataOrderTypeDef DataOrder) { 80082c2: b480 push {r7} 80082c4: b085 sub sp, #20 80082c6: af00 add r7, sp, #0 80082c8: 6078 str r0, [r7, #4] 80082ca: 460b mov r3, r1 80082cc: 70fb strb r3, [r7, #3] HAL_StatusTypeDef retr = HAL_OK; 80082ce: 2300 movs r3, #0 80082d0: 73fb strb r3, [r7, #15] /* Read the memory type value */ uint32_t memorytype = READ_REG(SalXspi->hxspi->Instance->DCR1) & XSPI_DCR1_MTYP; 80082d2: 687b ldr r3, [r7, #4] 80082d4: 681b ldr r3, [r3, #0] 80082d6: 681b ldr r3, [r3, #0] 80082d8: 689b ldr r3, [r3, #8] 80082da: f003 63e0 and.w r3, r3, #117440512 @ 0x7000000 80082de: 60bb str r3, [r7, #8] switch (DataOrder) 80082e0: 78fb ldrb r3, [r7, #3] 80082e2: 2b00 cmp r3, #0 80082e4: d11e bne.n 8008324 { case SAL_XSPI_ORDERINVERTED : if (memorytype == HAL_XSPI_MEMTYPE_MICRON) 80082e6: 68bb ldr r3, [r7, #8] 80082e8: 2b00 cmp r3, #0 80082ea: d103 bne.n 80082f4 { memorytype = HAL_XSPI_MEMTYPE_MACRONIX; 80082ec: f04f 7380 mov.w r3, #16777216 @ 0x1000000 80082f0: 60bb str r3, [r7, #8] 80082f2: e008 b.n 8008306 } else if (memorytype == HAL_XSPI_MEMTYPE_MACRONIX) 80082f4: 68bb ldr r3, [r7, #8] 80082f6: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 80082fa: d102 bne.n 8008302 { memorytype = HAL_XSPI_MEMTYPE_MICRON; 80082fc: 2300 movs r3, #0 80082fe: 60bb str r3, [r7, #8] 8008300: e001 b.n 8008306 } else { retr = HAL_ERROR; 8008302: 2301 movs r3, #1 8008304: 73fb strb r3, [r7, #15] } MODIFY_REG(SalXspi->hxspi->Instance->DCR1, XSPI_DCR1_MTYP, memorytype); 8008306: 687b ldr r3, [r7, #4] 8008308: 681b ldr r3, [r3, #0] 800830a: 681b ldr r3, [r3, #0] 800830c: 689b ldr r3, [r3, #8] 800830e: f023 61e0 bic.w r1, r3, #117440512 @ 0x7000000 8008312: 687b ldr r3, [r7, #4] 8008314: 681b ldr r3, [r3, #0] 8008316: 681b ldr r3, [r3, #0] 8008318: 68ba ldr r2, [r7, #8] 800831a: 430a orrs r2, r1 800831c: 609a str r2, [r3, #8] break; 800831e: bf00 nop DEBUG_PARAM_BEGIN(); DEBUG_PARAM_DATA("::SAL_XSPI_UpdateMemoryType::"); DEBUG_PARAM_INT(memorytype); DEBUG_PARAM_END(); return retr; 8008320: 7bfb ldrb r3, [r7, #15] 8008322: e000 b.n 8008326 return HAL_ERROR; 8008324: 2301 movs r3, #1 } 8008326: 4618 mov r0, r3 8008328: 3714 adds r7, #20 800832a: 46bd mov sp, r7 800832c: f85d 7b04 ldr.w r7, [sp], #4 8008330: 4770 bx lr 08008332 : HAL_StatusTypeDef SAL_XSPI_Abort(SAL_XSPI_ObjectTypeDef *SalXspi) { 8008332: b580 push {r7, lr} 8008334: b082 sub sp, #8 8008336: af00 add r7, sp, #0 8008338: 6078 str r0, [r7, #4] return HAL_XSPI_Abort(SalXspi->hxspi); 800833a: 687b ldr r3, [r7, #4] 800833c: 681b ldr r3, [r3, #0] 800833e: 4618 mov r0, r3 8008340: f7fe f9a4 bl 800668c 8008344: 4603 mov r3, r0 } 8008346: 4618 mov r0, r3 8008348: 3708 adds r7, #8 800834a: 46bd mov sp, r7 800834c: bd80 pop {r7, pc} 0800834e : * @param InstructionWidth Instruction width * @param Command Command * @return Formatted command */ uint16_t XSPI_FormatCommand(uint8_t CommandExtension, uint32_t InstructionWidth, uint8_t Command) { 800834e: b480 push {r7} 8008350: b085 sub sp, #20 8008352: af00 add r7, sp, #0 8008354: 4603 mov r3, r0 8008356: 6039 str r1, [r7, #0] 8008358: 71fb strb r3, [r7, #7] 800835a: 4613 mov r3, r2 800835c: 71bb strb r3, [r7, #6] uint16_t retr; if (InstructionWidth == HAL_XSPI_INSTRUCTION_16_BITS) 800835e: 683b ldr r3, [r7, #0] 8008360: 2b10 cmp r3, #16 8008362: d114 bne.n 800838e /* 0b00 Command Extension is the same as the Command. (Command / Command Extension has the same value for the whole clock period. */ /* 0b01 Command Extension is the inverse of the Command. Command Extension acts as a confirmation of the Command */ /* 0b11 Command and Command Extension forms a 16 bit command word :: Not yet handled */ retr = ((uint16_t)Command << 8u); 8008364: 79bb ldrb r3, [r7, #6] 8008366: b29b uxth r3, r3 8008368: 021b lsls r3, r3, #8 800836a: 81fb strh r3, [r7, #14] if (CommandExtension == 1u) 800836c: 79fb ldrb r3, [r7, #7] 800836e: 2b01 cmp r3, #1 8008370: d107 bne.n 8008382 { retr |= (uint8_t)(~Command & 0xFFu); 8008372: 79bb ldrb r3, [r7, #6] 8008374: 43db mvns r3, r3 8008376: b2db uxtb r3, r3 8008378: 461a mov r2, r3 800837a: 89fb ldrh r3, [r7, #14] 800837c: 4313 orrs r3, r2 800837e: 81fb strh r3, [r7, #14] 8008380: e007 b.n 8008392 } else { retr |= (uint8_t)(Command & 0xFFu); 8008382: 79bb ldrb r3, [r7, #6] 8008384: b29a uxth r2, r3 8008386: 89fb ldrh r3, [r7, #14] 8008388: 4313 orrs r3, r2 800838a: 81fb strh r3, [r7, #14] 800838c: e001 b.n 8008392 } } else { retr = Command; 800838e: 79bb ldrb r3, [r7, #6] 8008390: 81fb strh r3, [r7, #14] } return retr; 8008392: 89fb ldrh r3, [r7, #14] } 8008394: 4618 mov r0, r3 8008396: 3714 adds r7, #20 8008398: 46bd mov sp, r7 800839a: f85d 7b04 ldr.w r7, [sp], #4 800839e: 4770 bx lr 080083a0 : * @param SalXspi SAL XSPI Handle * @param Data Data pointer * @return Status of the command execution */ HAL_StatusTypeDef XSPI_Transmit(SAL_XSPI_ObjectTypeDef *SalXspi, const uint8_t *Data) { 80083a0: b580 push {r7, lr} 80083a2: b084 sub sp, #16 80083a4: af00 add r7, sp, #0 80083a6: 6078 str r0, [r7, #4] 80083a8: 6039 str r1, [r7, #0] HAL_StatusTypeDef retr; #if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) if (SalXspi->hxspi->hdmatx == NULL) 80083aa: 687b ldr r3, [r7, #4] 80083ac: 681b ldr r3, [r3, #0] 80083ae: 6cdb ldr r3, [r3, #76] @ 0x4c 80083b0: 2b00 cmp r3, #0 80083b2: d109 bne.n 80083c8 #endif /* USE_HAL_XSPI_REGISTER_CALLBACKS */ { /* Transmit data */ retr = HAL_XSPI_Transmit(SalXspi->hxspi, Data, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); 80083b4: 687b ldr r3, [r7, #4] 80083b6: 681b ldr r3, [r3, #0] 80083b8: 2264 movs r2, #100 @ 0x64 80083ba: 6839 ldr r1, [r7, #0] 80083bc: 4618 mov r0, r3 80083be: f7fd fbe7 bl 8005b90 80083c2: 4603 mov r3, r0 80083c4: 73fb strb r3, [r7, #15] 80083c6: e01a b.n 80083fe } #if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) else { /* Set completion call back */ salXSPI_status = SALXSPI_TRANSFER_NONE; 80083c8: 4b0f ldr r3, [pc, #60] @ (8008408 ) 80083ca: 2200 movs r2, #0 80083cc: 701a strb r2, [r3, #0] /* Reception of the data */ retr = HAL_XSPI_Transmit_DMA(SalXspi->hxspi, (uint8_t *)Data); 80083ce: 687b ldr r3, [r7, #4] 80083d0: 681b ldr r3, [r3, #0] 80083d2: 6839 ldr r1, [r7, #0] 80083d4: 4618 mov r0, r3 80083d6: f7fd fcf1 bl 8005dbc 80083da: 4603 mov r3, r0 80083dc: 73fb strb r3, [r7, #15] if (retr == HAL_OK) 80083de: 7bfb ldrb r3, [r7, #15] 80083e0: 2b00 cmp r3, #0 80083e2: d10c bne.n 80083fe { /* Wait data reception completion */ while (salXSPI_status == SALXSPI_TRANSFER_NONE); 80083e4: bf00 nop 80083e6: 4b08 ldr r3, [pc, #32] @ (8008408 ) 80083e8: 781b ldrb r3, [r3, #0] 80083ea: b2db uxtb r3, r3 80083ec: 2b00 cmp r3, #0 80083ee: d0fa beq.n 80083e6 if (salXSPI_status == SALXSPI_TRANSFER_ERROR) 80083f0: 4b05 ldr r3, [pc, #20] @ (8008408 ) 80083f2: 781b ldrb r3, [r3, #0] 80083f4: b2db uxtb r3, r3 80083f6: 2b02 cmp r3, #2 80083f8: d101 bne.n 80083fe { retr = HAL_ERROR; 80083fa: 2301 movs r3, #1 80083fc: 73fb strb r3, [r7, #15] } } } #endif /* USE_HAL_XSPI_REGISTER_CALLBACKS */ return retr; 80083fe: 7bfb ldrb r3, [r7, #15] } 8008400: 4618 mov r0, r3 8008402: 3710 adds r7, #16 8008404: 46bd mov sp, r7 8008406: bd80 pop {r7, pc} 8008408: 240002c4 .word 0x240002c4 0800840c : * @param SalXspi SAL XSPI Handle * @param Data Data pointer * @return Status of the command execution */ HAL_StatusTypeDef XSPI_Receive(SAL_XSPI_ObjectTypeDef *SalXspi, uint8_t *Data) { 800840c: b580 push {r7, lr} 800840e: b084 sub sp, #16 8008410: af00 add r7, sp, #0 8008412: 6078 str r0, [r7, #4] 8008414: 6039 str r1, [r7, #0] HAL_StatusTypeDef retr; #if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) if (SalXspi->hxspi->hdmarx == NULL) 8008416: 687b ldr r3, [r7, #4] 8008418: 681b ldr r3, [r3, #0] 800841a: 6d1b ldr r3, [r3, #80] @ 0x50 800841c: 2b00 cmp r3, #0 800841e: d109 bne.n 8008434 #endif /* USE_HAL_XSPI_REGISTER_CALLBACKS */ { /* Reception of the data */ retr = HAL_XSPI_Receive(SalXspi->hxspi, Data, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); 8008420: 687b ldr r3, [r7, #4] 8008422: 681b ldr r3, [r3, #0] 8008424: 2264 movs r2, #100 @ 0x64 8008426: 6839 ldr r1, [r7, #0] 8008428: 4618 mov r0, r3 800842a: f7fd fc24 bl 8005c76 800842e: 4603 mov r3, r0 8008430: 73fb strb r3, [r7, #15] 8008432: e01a b.n 800846a } #if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) else { /* Set completion call back */ salXSPI_status = SALXSPI_TRANSFER_NONE; 8008434: 4b0f ldr r3, [pc, #60] @ (8008474 ) 8008436: 2200 movs r2, #0 8008438: 701a strb r2, [r3, #0] /* Reception of the data */ retr = HAL_XSPI_Receive_DMA(SalXspi->hxspi, Data); 800843a: 687b ldr r3, [r7, #4] 800843c: 681b ldr r3, [r3, #0] 800843e: 6839 ldr r1, [r7, #0] 8008440: 4618 mov r0, r3 8008442: f7fd fded bl 8006020 8008446: 4603 mov r3, r0 8008448: 73fb strb r3, [r7, #15] if (retr == HAL_OK) 800844a: 7bfb ldrb r3, [r7, #15] 800844c: 2b00 cmp r3, #0 800844e: d10c bne.n 800846a { /* Wait data completion */ while (salXSPI_status == SALXSPI_TRANSFER_NONE); 8008450: bf00 nop 8008452: 4b08 ldr r3, [pc, #32] @ (8008474 ) 8008454: 781b ldrb r3, [r3, #0] 8008456: b2db uxtb r3, r3 8008458: 2b00 cmp r3, #0 800845a: d0fa beq.n 8008452 if (salXSPI_status == SALXSPI_TRANSFER_ERROR) 800845c: 4b05 ldr r3, [pc, #20] @ (8008474 ) 800845e: 781b ldrb r3, [r3, #0] 8008460: b2db uxtb r3, r3 8008462: 2b02 cmp r3, #2 8008464: d101 bne.n 800846a { retr = HAL_ERROR; 8008466: 2301 movs r3, #1 8008468: 73fb strb r3, [r7, #15] } } } #endif /* USE_HAL_XSPI_REGISTER_CALLBACKS */ return retr; 800846a: 7bfb ldrb r3, [r7, #15] } 800846c: 4618 mov r0, r3 800846e: 3710 adds r7, #16 8008470: 46bd mov sp, r7 8008472: bd80 pop {r7, pc} 8008474: 240002c4 .word 0x240002c4 08008478 : * * @param hxspi Handle on the XSPI peripheral * @return none */ void SAL_XSPI_ErrorCallback(struct __XSPI_HandleTypeDef *hxspi) { 8008478: b480 push {r7} 800847a: b083 sub sp, #12 800847c: af00 add r7, sp, #0 800847e: 6078 str r0, [r7, #4] salXSPI_status = SALXSPI_TRANSFER_ERROR; 8008480: 4b04 ldr r3, [pc, #16] @ (8008494 ) 8008482: 2202 movs r2, #2 8008484: 701a strb r2, [r3, #0] } 8008486: bf00 nop 8008488: 370c adds r7, #12 800848a: 46bd mov sp, r7 800848c: f85d 7b04 ldr.w r7, [sp], #4 8008490: 4770 bx lr 8008492: bf00 nop 8008494: 240002c4 .word 0x240002c4 08008498 : * * @param hxspi Handle on the XSPI peripheral * @return none */ void SAL_XSPI_CompleteCallback(struct __XSPI_HandleTypeDef *hxspi) { 8008498: b480 push {r7} 800849a: b083 sub sp, #12 800849c: af00 add r7, sp, #0 800849e: 6078 str r0, [r7, #4] salXSPI_status = SALXSPI_TRANSFER_OK; 80084a0: 4b04 ldr r3, [pc, #16] @ (80084b4 ) 80084a2: 2201 movs r2, #1 80084a4: 701a strb r2, [r3, #0] } 80084a6: bf00 nop 80084a8: 370c adds r7, #12 80084aa: 46bd mov sp, r7 80084ac: f85d 7b04 ldr.w r7, [sp], #4 80084b0: 4770 bx lr 80084b2: bf00 nop 80084b4: 240002c4 .word 0x240002c4 080084b8 : * @param Object Pointer to the NOR SFDP memory instance object descriptor. * @param sfdp_header Pointer to the SFDP header structure to be filled. * @retval SFDP_StatusTypeDef Status of the operation: EXTMEM_SFDP_OK if successful, error code otherwise. */ SFDP_StatusTypeDef SFDP_ReadHeader(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object, SFDP_HeaderTypeDef *sfdp_header) { 80084b8: b580 push {r7, lr} 80084ba: b084 sub sp, #16 80084bc: af00 add r7, sp, #0 80084be: 6078 str r0, [r7, #4] 80084c0: 6039 str r1, [r7, #0] SFDP_StatusTypeDef retr; uint8_t retry_counter = 0; 80084c2: 2300 movs r3, #0 80084c4: 73bb strb r3, [r7, #14] SFDP_DEBUG_STR(__func__); do { /* Reset the signature value */ sfdp_header->Signature = 0; 80084c6: 683b ldr r3, [r7, #0] 80084c8: 2200 movs r2, #0 80084ca: 601a str r2, [r3, #0] /* send the SFDP command to read the header */ if (HAL_OK != SAL_XSPI_GetSFDP(&Object->sfdp_private.SALObject, 0, (uint8_t *)sfdp_header, SFDP_HEADER_SIZE)) 80084cc: 687b ldr r3, [r7, #4] 80084ce: f103 0008 add.w r0, r3, #8 80084d2: 2308 movs r3, #8 80084d4: 683a ldr r2, [r7, #0] 80084d6: 2100 movs r1, #0 80084d8: f7ff fb18 bl 8007b0c 80084dc: 4603 mov r3, r0 80084de: 2b00 cmp r3, #0 80084e0: d002 beq.n 80084e8 { retr = EXTMEM_SFDP_ERROR_SFDPREAD; 80084e2: 2303 movs r3, #3 80084e4: 73fb strb r3, [r7, #15] goto error; 80084e6: e01f b.n 8008528 } /* view the header signature value */ SFDP_DEBUG_INT("SFDP signature::", sfdp_header->Signature); switch (CheckSFDP_Signature(Object, sfdp_header->Signature)) 80084e8: 683b ldr r3, [r7, #0] 80084ea: 681b ldr r3, [r3, #0] 80084ec: 4619 mov r1, r3 80084ee: 6878 ldr r0, [r7, #4] 80084f0: f001 fcac bl 8009e4c 80084f4: 4603 mov r3, r0 80084f6: 2b00 cmp r3, #0 80084f8: d002 beq.n 8008500 80084fa: 2b05 cmp r3, #5 80084fc: d005 beq.n 800850a 80084fe: e00a b.n 8008516 { case EXTMEM_SFDP_OK: SFDP_DEBUG_INT("param_number=", sfdp_header->param_number); SFDP_DEBUG_INT("AccessProtocol=", sfdp_header->AccessProtocol); retr = EXTMEM_SFDP_OK; 8008500: 2300 movs r3, #0 8008502: 73fb strb r3, [r7, #15] retry_counter = 2u; 8008504: 2302 movs r3, #2 8008506: 73bb strb r3, [r7, #14] break; 8008508: e00a b.n 8008520 case EXTMEM_SFDP_ERROR_SIGNATUREMTYPE: retr = EXTMEM_SFDP_ERROR_SIGNATURE; 800850a: 2304 movs r3, #4 800850c: 73fb strb r3, [r7, #15] retry_counter++; 800850e: 7bbb ldrb r3, [r7, #14] 8008510: 3301 adds r3, #1 8008512: 73bb strb r3, [r7, #14] break; 8008514: e004 b.n 8008520 /* case EXTMEM_SFDP_ERROR_SIGNATURE :*/ default : retr = EXTMEM_SFDP_ERROR_SIGNATURE; 8008516: 2304 movs r3, #4 8008518: 73fb strb r3, [r7, #15] retry_counter = 2u; 800851a: 2302 movs r3, #2 800851c: 73bb strb r3, [r7, #14] break; 800851e: bf00 nop } } while (retry_counter < 2u); 8008520: 7bbb ldrb r3, [r7, #14] 8008522: 2b01 cmp r3, #1 8008524: d9cf bls.n 80084c6 error: 8008526: bf00 nop return retr; 8008528: 7bfb ldrb r3, [r7, #15] } 800852a: 4618 mov r0, r3 800852c: 3710 adds r7, #16 800852e: 46bd mov sp, r7 8008530: bd80 pop {r7, pc} ... 08008534 : * @param Object Pointer to the NOR SFDP memory instance object descriptor. * @param sfdp_header Pointer to the SFDP header structure to be filled. * @retval SFDP_StatusTypeDef Status of the operation: EXTMEM_SFDP_OK if successful, error code otherwise. */ SFDP_StatusTypeDef SFDP_GetHeader(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object, SFDP_HeaderTypeDef *sfdp_header) { 8008534: b590 push {r4, r7, lr} 8008536: b089 sub sp, #36 @ 0x24 8008538: af00 add r7, sp, #0 800853a: 6078 str r0, [r7, #4] 800853c: 6039 str r1, [r7, #0] SFDP_StatusTypeDef retr = EXTMEM_SFDP_ERROR_SIGNATURE; 800853e: 2304 movs r3, #4 8008540: 77fb strb r3, [r7, #31] SFDP_DEBUG_STR(__func__); const TableConfig_t table_config[] = 8008542: 4b2a ldr r3, [pc, #168] @ (80085ec ) 8008544: f107 040c add.w r4, r7, #12 8008548: cb0f ldmia r3, {r0, r1, r2, r3} 800854a: e884 000f stmia.w r4, {r0, r1, r2, r3} {PHY_LINK_8D8D8D, 10u}, {PHY_LINK_8D8D8D, 16u} }; /* Loop to find the link configuration of the memory */ for (uint8_t index = 0u; 800854e: 2300 movs r3, #0 8008550: 77bb strb r3, [r7, #30] 8008552: e040 b.n 80085d6 { /* Set the command mode */ SFDP_DEBUG_STR("try a command configuration"); /* Configure the link */ Object->sfdp_private.DriverInfo.SpiPhyLink = table_config[index].PhyLink; 8008554: 7fbb ldrb r3, [r7, #30] 8008556: 005b lsls r3, r3, #1 8008558: 3320 adds r3, #32 800855a: 443b add r3, r7 800855c: f813 2c14 ldrb.w r2, [r3, #-20] 8008560: 687b ldr r3, [r7, #4] 8008562: f883 2064 strb.w r2, [r3, #100] @ 0x64 (void)SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_PHY_LINK, 8008566: 687b ldr r3, [r7, #4] 8008568: f103 0008 add.w r0, r3, #8 &Object->sfdp_private.DriverInfo.SpiPhyLink); 800856c: 687b ldr r3, [r7, #4] 800856e: 3364 adds r3, #100 @ 0x64 (void)SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_PHY_LINK, 8008570: 461a mov r2, r3 8008572: 2100 movs r1, #0 8008574: f7ff f978 bl 8007868 SAL_XSPI_SET_SFDPDUMMYCYLE(Object->sfdp_private.SALObject, table_config[index].DummyCycle); 8008578: 7fbb ldrb r3, [r7, #30] 800857a: 005b lsls r3, r3, #1 800857c: 3320 adds r3, #32 800857e: 443b add r3, r7 8008580: f813 2c13 ldrb.w r2, [r3, #-19] 8008584: 687b ldr r3, [r7, #4] 8008586: f883 2059 strb.w r2, [r3, #89] @ 0x59 /* Loop on the instruction extension */ for (uint8_t IExt = 0u; 800858a: 2300 movs r3, #0 800858c: 777b strb r3, [r7, #29] 800858e: e017 b.n 80085c0 (IExt < 2u) && (retr == EXTMEM_SFDP_ERROR_SIGNATURE); IExt++) { SAL_XSPI_SET_COMMANDEXTENSION(Object->sfdp_private.SALObject, IExt); 8008590: 687b ldr r3, [r7, #4] 8008592: 7f7a ldrb r2, [r7, #29] 8008594: f883 2058 strb.w r2, [r3, #88] @ 0x58 /* Read the sfdp header */ if (EXTMEM_SFDP_OK == SFDP_ReadHeader(Object, sfdp_header)) 8008598: 6839 ldr r1, [r7, #0] 800859a: 6878 ldr r0, [r7, #4] 800859c: f7ff ff8c bl 80084b8 80085a0: 4603 mov r3, r0 80085a2: 2b00 cmp r3, #0 80085a4: d101 bne.n 80085aa { retr = EXTMEM_SFDP_OK; 80085a6: 2300 movs r3, #0 80085a8: 77fb strb r3, [r7, #31] } if (table_config[index].PhyLink < PHY_LINK_4S4S4S) 80085aa: 7fbb ldrb r3, [r7, #30] 80085ac: 005b lsls r3, r3, #1 80085ae: 3320 adds r3, #32 80085b0: 443b add r3, r7 80085b2: f813 3c14 ldrb.w r3, [r3, #-20] 80085b6: 2b03 cmp r3, #3 80085b8: d909 bls.n 80085ce (IExt < 2u) && (retr == EXTMEM_SFDP_ERROR_SIGNATURE); IExt++) 80085ba: 7f7b ldrb r3, [r7, #29] 80085bc: 3301 adds r3, #1 80085be: 777b strb r3, [r7, #29] 80085c0: 7f7b ldrb r3, [r7, #29] 80085c2: 2b01 cmp r3, #1 80085c4: d804 bhi.n 80085d0 80085c6: 7ffb ldrb r3, [r7, #31] 80085c8: 2b04 cmp r3, #4 80085ca: d0e1 beq.n 8008590 80085cc: e000 b.n 80085d0 { /* Config 1 is invalid so exit the loop */ break; 80085ce: bf00 nop ; index++) 80085d0: 7fbb ldrb r3, [r7, #30] 80085d2: 3301 adds r3, #1 80085d4: 77bb strb r3, [r7, #30] (index < (sizeof(table_config) / sizeof(TableConfig_t))) && 80085d6: 7fbb ldrb r3, [r7, #30] 80085d8: 2b07 cmp r3, #7 80085da: d802 bhi.n 80085e2 80085dc: 7ffb ldrb r3, [r7, #31] 80085de: 2b04 cmp r3, #4 80085e0: d0b8 beq.n 8008554 } } } return retr; 80085e2: 7ffb ldrb r3, [r7, #31] } 80085e4: 4618 mov r0, r3 80085e6: 3724 adds r7, #36 @ 0x24 80085e8: 46bd mov sp, r7 80085ea: bd90 pop {r4, r7, pc} 80085ec: 0800a128 .word 0x0800a128 080085f0 : * @brief Collects all SFDP parameter table information and builds driver data. * @param Object Pointer to the NOR SFDP memory instance object descriptor. * @retval SFDP_StatusTypeDef Status of the operation: EXTMEM_SFDP_OK if successful, error code otherwise. */ SFDP_StatusTypeDef SFDP_CollectData(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object) { 80085f0: b580 push {r7, lr} 80085f2: b088 sub sp, #32 80085f4: af00 add r7, sp, #0 80085f6: 6078 str r0, [r7, #4] SFDP_StatusTypeDef retr = EXTMEM_SFDP_OK; 80085f8: 2300 movs r3, #0 80085fa: 77fb strb r3, [r7, #31] uint32_t sfdp_address = SFDP_HEADER_SIZE; 80085fc: 2308 movs r3, #8 80085fe: 61bb str r3, [r7, #24] SFDP_DEBUG_STR(__func__); /* Reset the table mask */ Object->sfdp_private.Sfdp_table_mask = 0; 8008600: 687b ldr r3, [r7, #4] 8008602: 2200 movs r2, #0 8008604: f8c3 2094 str.w r2, [r3, #148] @ 0x94 /* Reset the param info */ (void)memset(sfdp_param_info, 0x0, sizeof(sfdp_param_info)); 8008608: 2278 movs r2, #120 @ 0x78 800860a: 2100 movs r1, #0 800860c: 485f ldr r0, [pc, #380] @ (800878c ) 800860e: f001 fd41 bl 800a094 /* Get the table param info */ for (uint8_t index = 0u; index < (Object->sfdp_private.Sfdp_param_number + 1u); index++) 8008612: 2300 movs r3, #0 8008614: 75fb strb r3, [r7, #23] 8008616: e027 b.n 8008668 { CHECK_FUNCTION_CALL(sfdp_get_paraminfo(Object, sfdp_address, &sfdp_param_info[index])) 8008618: 7dfa ldrb r2, [r7, #23] 800861a: 4613 mov r3, r2 800861c: 005b lsls r3, r3, #1 800861e: 4413 add r3, r2 8008620: 009b lsls r3, r3, #2 8008622: 4a5a ldr r2, [pc, #360] @ (800878c ) 8008624: 4413 add r3, r2 8008626: 461a mov r2, r3 8008628: 69b9 ldr r1, [r7, #24] 800862a: 6878 ldr r0, [r7, #4] 800862c: f001 f84e bl 80096cc 8008630: 4603 mov r3, r0 8008632: 77fb strb r3, [r7, #31] 8008634: 7ffb ldrb r3, [r7, #31] 8008636: 2b00 cmp r3, #0 8008638: f040 80a2 bne.w 8008780 Object->sfdp_private.Sfdp_table_mask |= (uint32_t)sfdp_param_info[index].type; 800863c: 687b ldr r3, [r7, #4] 800863e: f8d3 1094 ldr.w r1, [r3, #148] @ 0x94 8008642: 7dfa ldrb r2, [r7, #23] 8008644: 4851 ldr r0, [pc, #324] @ (800878c ) 8008646: 4613 mov r3, r2 8008648: 005b lsls r3, r3, #1 800864a: 4413 add r3, r2 800864c: 009b lsls r3, r3, #2 800864e: 4403 add r3, r0 8008650: 681b ldr r3, [r3, #0] 8008652: ea41 0203 orr.w r2, r1, r3 8008656: 687b ldr r3, [r7, #4] 8008658: f8c3 2094 str.w r2, [r3, #148] @ 0x94 sfdp_address += SFDP_PARAM_HEADER_SIZE; 800865c: 69bb ldr r3, [r7, #24] 800865e: 3308 adds r3, #8 8008660: 61bb str r3, [r7, #24] for (uint8_t index = 0u; index < (Object->sfdp_private.Sfdp_param_number + 1u); index++) 8008662: 7dfb ldrb r3, [r7, #23] 8008664: 3301 adds r3, #1 8008666: 75fb strb r3, [r7, #23] 8008668: 7dfa ldrb r2, [r7, #23] 800866a: 687b ldr r3, [r7, #4] 800866c: f893 309c ldrb.w r3, [r3, #156] @ 0x9c 8008670: 3301 adds r3, #1 8008672: 429a cmp r2, r3 8008674: d3d0 bcc.n 8008618 } /* Read each table param to extract the information to build the driver */ for (uint8_t index = 0u; sfdp_param_info[index].type != SFDP_PARAMID_UNKNOWN; index++) 8008676: 2300 movs r3, #0 8008678: 75bb strb r3, [r7, #22] 800867a: e075 b.n 8008768 { uint8_t *ptr = NULL; 800867c: 2300 movs r3, #0 800867e: 613b str r3, [r7, #16] uint32_t size = sfdp_param_info[index].size; 8008680: 7dba ldrb r2, [r7, #22] 8008682: 4942 ldr r1, [pc, #264] @ (800878c ) 8008684: 4613 mov r3, r2 8008686: 005b lsls r3, r3, #1 8008688: 4413 add r3, r2 800868a: 009b lsls r3, r3, #2 800868c: 440b add r3, r1 800868e: 3308 adds r3, #8 8008690: 781b ldrb r3, [r3, #0] 8008692: 60fb str r3, [r7, #12] switch (sfdp_param_info[index].type) 8008694: 7dba ldrb r2, [r7, #22] 8008696: 493d ldr r1, [pc, #244] @ (800878c ) 8008698: 4613 mov r3, r2 800869a: 005b lsls r3, r3, #1 800869c: 4413 add r3, r2 800869e: 009b lsls r3, r3, #2 80086a0: 440b add r3, r1 80086a2: 681b ldr r3, [r3, #0] 80086a4: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80086a8: d029 beq.n 80086fe 80086aa: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80086ae: d829 bhi.n 8008704 80086b0: f5b3 7f00 cmp.w r3, #512 @ 0x200 80086b4: d01d beq.n 80086f2 80086b6: f5b3 7f00 cmp.w r3, #512 @ 0x200 80086ba: d823 bhi.n 8008704 80086bc: 2b80 cmp r3, #128 @ 0x80 80086be: d01b beq.n 80086f8 80086c0: 2b80 cmp r3, #128 @ 0x80 80086c2: d81f bhi.n 8008704 80086c4: 2b08 cmp r3, #8 80086c6: d002 beq.n 80086ce 80086c8: 2b40 cmp r3, #64 @ 0x40 80086ca: d00f beq.n 80086ec case SFDP_PARAMID_OCTAL_DDR: ptr = JEDEC_OctalDdr.data_BYTE; break; default : SFDP_DEBUG_STR("the table is not yet handled by the SW"); break; 80086cc: e01a b.n 8008704 JEDEC_Basic.size = sfdp_param_info[index].size; 80086ce: 7dba ldrb r2, [r7, #22] 80086d0: 492e ldr r1, [pc, #184] @ (800878c ) 80086d2: 4613 mov r3, r2 80086d4: 005b lsls r3, r3, #1 80086d6: 4413 add r3, r2 80086d8: 009b lsls r3, r3, #2 80086da: 440b add r3, r1 80086dc: 3308 adds r3, #8 80086de: 781b ldrb r3, [r3, #0] 80086e0: 461a mov r2, r3 80086e2: 4b2b ldr r3, [pc, #172] @ (8008790 ) 80086e4: 601a str r2, [r3, #0] ptr = JEDEC_Basic.Params.data_BYTE; 80086e6: 4b2b ldr r3, [pc, #172] @ (8008794 ) 80086e8: 613b str r3, [r7, #16] break; 80086ea: e00c b.n 8008706 ptr = JEDEC_Address4Bytes.data_BYTE; 80086ec: 4b2a ldr r3, [pc, #168] @ (8008798 ) 80086ee: 613b str r3, [r7, #16] break; 80086f0: e009 b.n 8008706 ptr = JEDEC_SCCR_Map.data_b; 80086f2: 4b2a ldr r3, [pc, #168] @ (800879c ) 80086f4: 613b str r3, [r7, #16] break; 80086f6: e006 b.n 8008706 ptr = JEDEC_XSPI10.data_BYTE; 80086f8: 4b29 ldr r3, [pc, #164] @ (80087a0 ) 80086fa: 613b str r3, [r7, #16] break; 80086fc: e003 b.n 8008706 ptr = JEDEC_OctalDdr.data_BYTE; 80086fe: 4b29 ldr r3, [pc, #164] @ (80087a4 ) 8008700: 613b str r3, [r7, #16] break; 8008702: e000 b.n 8008706 break; 8008704: bf00 nop } if (ptr != NULL) 8008706: 693b ldr r3, [r7, #16] 8008708: 2b00 cmp r3, #0 800870a: d016 beq.n 800873a { if (HAL_OK != SAL_XSPI_GetSFDP(&Object->sfdp_private.SALObject, 800870c: 687b ldr r3, [r7, #4] 800870e: f103 0008 add.w r0, r3, #8 8008712: 7dba ldrb r2, [r7, #22] 8008714: 491d ldr r1, [pc, #116] @ (800878c ) 8008716: 4613 mov r3, r2 8008718: 005b lsls r3, r3, #1 800871a: 4413 add r3, r2 800871c: 009b lsls r3, r3, #2 800871e: 440b add r3, r1 8008720: 3304 adds r3, #4 8008722: 6819 ldr r1, [r3, #0] sfdp_param_info[index].address, ptr, size * 4u)) 8008724: 68fb ldr r3, [r7, #12] 8008726: 009b lsls r3, r3, #2 if (HAL_OK != SAL_XSPI_GetSFDP(&Object->sfdp_private.SALObject, 8008728: 693a ldr r2, [r7, #16] 800872a: f7ff f9ef bl 8007b0c 800872e: 4603 mov r3, r0 8008730: 2b00 cmp r3, #0 8008732: d002 beq.n 800873a { retr = EXTMEM_SFDP_ERROR_DRIVER; 8008734: 230c movs r3, #12 8008736: 77fb strb r3, [r7, #31] goto error; 8008738: e022 b.n 8008780 } } if (SFDP_PARAMID_BASIC_SPIPROTOCOL == sfdp_param_info[index].type) 800873a: 7dba ldrb r2, [r7, #22] 800873c: 4913 ldr r1, [pc, #76] @ (800878c ) 800873e: 4613 mov r3, r2 8008740: 005b lsls r3, r3, #1 8008742: 4413 add r3, r2 8008744: 009b lsls r3, r3, #2 8008746: 440b add r3, r1 8008748: 681b ldr r3, [r3, #0] 800874a: 2b08 cmp r3, #8 800874c: d109 bne.n 8008762 { /* Save data about the reset procedure */ Object->sfdp_private.Reset_info = JEDEC_Basic.Params.Param_DWORD.D16.SoftResetRescueSequence_Support; 800874e: 4b10 ldr r3, [pc, #64] @ (8008790 ) 8008750: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8008754: f3c3 0305 ubfx r3, r3, #0, #6 8008758: b2db uxtb r3, r3 800875a: 461a mov r2, r3 800875c: 687b ldr r3, [r7, #4] 800875e: f8c3 2098 str.w r2, [r3, #152] @ 0x98 for (uint8_t index = 0u; sfdp_param_info[index].type != SFDP_PARAMID_UNKNOWN; index++) 8008762: 7dbb ldrb r3, [r7, #22] 8008764: 3301 adds r3, #1 8008766: 75bb strb r3, [r7, #22] 8008768: 7dba ldrb r2, [r7, #22] 800876a: 4908 ldr r1, [pc, #32] @ (800878c ) 800876c: 4613 mov r3, r2 800876e: 005b lsls r3, r3, #1 8008770: 4413 add r3, r2 8008772: 009b lsls r3, r3, #2 8008774: 440b add r3, r1 8008776: 681b ldr r3, [r3, #0] 8008778: 2b00 cmp r3, #0 800877a: f47f af7f bne.w 800867c } } error: 800877e: bf00 nop return retr; 8008780: 7ffb ldrb r3, [r7, #31] } 8008782: 4618 mov r0, r3 8008784: 3720 adds r7, #32 8008786: 46bd mov sp, r7 8008788: bd80 pop {r7, pc} 800878a: bf00 nop 800878c: 240002c8 .word 0x240002c8 8008790: 24000340 .word 0x24000340 8008794: 24000344 .word 0x24000344 8008798: 240003a0 .word 0x240003a0 800879c: 240003c0 .word 0x240003c0 80087a0: 240003a8 .word 0x240003a8 80087a4: 24000430 .word 0x24000430 080087a8 : * @brief Resets the NOR memory device using the SFDP-defined reset procedure. * @param Object Pointer to the NOR SFDP memory instance object descriptor. * @retval SFDP_StatusTypeDef Status of the operation: EXTMEM_SFDP_OK if successful, error code otherwise. */ SFDP_StatusTypeDef SFDP_MemoryReset(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object) { 80087a8: b580 push {r7, lr} 80087aa: b086 sub sp, #24 80087ac: af00 add r7, sp, #0 80087ae: 6078 str r0, [r7, #4] RESET_METHOD reset_method; SFDP_StatusTypeDef retr = EXTMEM_SFDP_ERROR_NO_PARAMTABLE_BASIC; 80087b0: 2307 movs r3, #7 80087b2: 75bb strb r3, [r7, #22] uint32_t sfdp_address = SFDP_HEADER_SIZE; 80087b4: 2308 movs r3, #8 80087b6: 613b str r3, [r7, #16] uint8_t find = 0u; 80087b8: 2300 movs r3, #0 80087ba: 73fb strb r3, [r7, #15] SFDP_DEBUG_STR(__func__); /* Get the table param info */ for (uint8_t index = 0u; index < (Object->sfdp_private.Sfdp_param_number + 1u); index++) 80087bc: 2300 movs r3, #0 80087be: 73bb strb r3, [r7, #14] 80087c0: e02e b.n 8008820 { retr = sfdp_get_paraminfo(Object, sfdp_address, &sfdp_param_info[0]); 80087c2: 4a64 ldr r2, [pc, #400] @ (8008954 ) 80087c4: 6939 ldr r1, [r7, #16] 80087c6: 6878 ldr r0, [r7, #4] 80087c8: f000 ff80 bl 80096cc 80087cc: 4603 mov r3, r0 80087ce: 75bb strb r3, [r7, #22] if (EXTMEM_SFDP_OK == retr) 80087d0: 7dbb ldrb r3, [r7, #22] 80087d2: 2b00 cmp r3, #0 80087d4: d118 bne.n 8008808 { /* Check if the table is basic table */ if (SFDP_PARAMID_BASIC_SPIPROTOCOL == sfdp_param_info[0].type) 80087d6: 4b5f ldr r3, [pc, #380] @ (8008954 ) 80087d8: 681b ldr r3, [r3, #0] 80087da: 2b08 cmp r3, #8 80087dc: d114 bne.n 8008808 { /* Read the JEDEC basic param */ if (HAL_OK != SAL_XSPI_GetSFDP(&Object->sfdp_private.SALObject, 80087de: 687b ldr r3, [r7, #4] 80087e0: f103 0008 add.w r0, r3, #8 80087e4: 4b5b ldr r3, [pc, #364] @ (8008954 ) 80087e6: 6859 ldr r1, [r3, #4] sfdp_param_info[0].address, JEDEC_Basic.Params.data_BYTE, ((uint32_t)sfdp_param_info[0].size) * 4u)) 80087e8: 4b5a ldr r3, [pc, #360] @ (8008954 ) 80087ea: 7a1b ldrb r3, [r3, #8] 80087ec: 009b lsls r3, r3, #2 if (HAL_OK != SAL_XSPI_GetSFDP(&Object->sfdp_private.SALObject, 80087ee: 4a5a ldr r2, [pc, #360] @ (8008958 ) 80087f0: f7ff f98c bl 8007b0c 80087f4: 4603 mov r3, r0 80087f6: 2b00 cmp r3, #0 80087f8: d002 beq.n 8008800 { retr = EXTMEM_SFDP_ERROR_DRIVER; 80087fa: 230c movs r3, #12 80087fc: 75bb strb r3, [r7, #22] 80087fe: e003 b.n 8008808 } else { retr = EXTMEM_SFDP_OK; 8008800: 2300 movs r3, #0 8008802: 75bb strb r3, [r7, #22] find = 1u; 8008804: 2301 movs r3, #1 8008806: 73fb strb r3, [r7, #15] } } } if ((EXTMEM_SFDP_OK != retr) || (1u == find)) 8008808: 7dbb ldrb r3, [r7, #22] 800880a: 2b00 cmp r3, #0 800880c: d10f bne.n 800882e 800880e: 7bfb ldrb r3, [r7, #15] 8008810: 2b01 cmp r3, #1 8008812: d00c beq.n 800882e { /* Stop reading, if there is an error or if the table has been found */ break; } /* Look for the next table */ sfdp_address += SFDP_PARAM_HEADER_SIZE; 8008814: 693b ldr r3, [r7, #16] 8008816: 3308 adds r3, #8 8008818: 613b str r3, [r7, #16] for (uint8_t index = 0u; index < (Object->sfdp_private.Sfdp_param_number + 1u); index++) 800881a: 7bbb ldrb r3, [r7, #14] 800881c: 3301 adds r3, #1 800881e: 73bb strb r3, [r7, #14] 8008820: 7bba ldrb r2, [r7, #14] 8008822: 687b ldr r3, [r7, #4] 8008824: f893 309c ldrb.w r3, [r3, #156] @ 0x9c 8008828: 3301 adds r3, #1 800882a: 429a cmp r2, r3 800882c: d3c9 bcc.n 80087c2 } /* If an error has been returned or if the table has not been found */ if ((EXTMEM_SFDP_OK != retr) || (0u == find)) 800882e: 7dbb ldrb r3, [r7, #22] 8008830: 2b00 cmp r3, #0 8008832: d102 bne.n 800883a 8008834: 7bfb ldrb r3, [r7, #15] 8008836: 2b00 cmp r3, #0 8008838: d102 bne.n 8008840 { retr = EXTMEM_SFDP_ERROR_DRIVER; 800883a: 230c movs r3, #12 800883c: 75bb strb r3, [r7, #22] goto error; 800883e: e083 b.n 8008948 } /* Determine how to proceed memory reset */ if (0x0u == JEDEC_Basic.Params.Param_DWORD.D16.SoftResetRescueSequence_Support) 8008840: 4b46 ldr r3, [pc, #280] @ (800895c ) 8008842: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8008846: f003 033f and.w r3, r3, #63 @ 0x3f 800884a: b2db uxtb r3, r3 800884c: 2b00 cmp r3, #0 800884e: d102 bne.n 8008856 { /* 00_0000b: no software reset instruction is supported */ reset_method = RESET_NONE; 8008850: 2300 movs r3, #0 8008852: 75fb strb r3, [r7, #23] 8008854: e053 b.n 80088fe } else if (0x1u == (0x1u & JEDEC_Basic.Params.Param_DWORD.D16.SoftResetRescueSequence_Support)) 8008856: 4b41 ldr r3, [pc, #260] @ (800895c ) 8008858: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800885c: f3c3 0305 ubfx r3, r3, #0, #6 8008860: b2db uxtb r3, r3 8008862: f003 0301 and.w r3, r3, #1 8008866: b2db uxtb r3, r3 8008868: 2b00 cmp r3, #0 800886a: d002 beq.n 8008872 { /* xx_xxx1b: drive Fh on all 4 data wires for 8 clocks */ reset_method = RESET_FH_4DATA_8CLOCK; 800886c: 2301 movs r3, #1 800886e: 75fb strb r3, [r7, #23] 8008870: e045 b.n 80088fe } else if (0x2u == (0x2u & JEDEC_Basic.Params.Param_DWORD.D16.SoftResetRescueSequence_Support)) 8008872: 4b3a ldr r3, [pc, #232] @ (800895c ) 8008874: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8008878: f3c3 0305 ubfx r3, r3, #0, #6 800887c: b2db uxtb r3, r3 800887e: f003 0302 and.w r3, r3, #2 8008882: b2db uxtb r3, r3 8008884: 2b00 cmp r3, #0 8008886: d002 beq.n 800888e { /* xx_xx1xb: drive Fh on all 4 data wires for 10 clocks if device is operating in 4-byte address mode */ reset_method = RESET_FH_4DATA_10CLOCK; 8008888: 2302 movs r3, #2 800888a: 75fb strb r3, [r7, #23] 800888c: e037 b.n 80088fe } else if (0x4u == (0x4u & JEDEC_Basic.Params.Param_DWORD.D16.SoftResetRescueSequence_Support)) 800888e: 4b33 ldr r3, [pc, #204] @ (800895c ) 8008890: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8008894: f3c3 0305 ubfx r3, r3, #0, #6 8008898: b2db uxtb r3, r3 800889a: f003 0304 and.w r3, r3, #4 800889e: b2db uxtb r3, r3 80088a0: 2b00 cmp r3, #0 80088a2: d002 beq.n 80088aa { /* xx_x1xxb: drive Fh on all 4 data wires for 16 clocks */ reset_method = RESET_FH_4DATA_16CLOCK; 80088a4: 2303 movs r3, #3 80088a6: 75fb strb r3, [r7, #23] 80088a8: e029 b.n 80088fe } else if (0x8u == (0x8u & JEDEC_Basic.Params.Param_DWORD.D16.SoftResetRescueSequence_Support)) 80088aa: 4b2c ldr r3, [pc, #176] @ (800895c ) 80088ac: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80088b0: f3c3 0305 ubfx r3, r3, #0, #6 80088b4: b2db uxtb r3, r3 80088b6: f003 0308 and.w r3, r3, #8 80088ba: b2db uxtb r3, r3 80088bc: 2b00 cmp r3, #0 80088be: d002 beq.n 80088c6 { /* xx_1xxxb: issue instruction F0h */ reset_method = RESET_INSTRUCTION_F0; 80088c0: 2304 movs r3, #4 80088c2: 75fb strb r3, [r7, #23] 80088c4: e01b b.n 80088fe } else if (0x10u == (0x10u & JEDEC_Basic.Params.Param_DWORD.D16.SoftResetRescueSequence_Support)) 80088c6: 4b25 ldr r3, [pc, #148] @ (800895c ) 80088c8: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80088cc: f3c3 0305 ubfx r3, r3, #0, #6 80088d0: b2db uxtb r3, r3 80088d2: f003 0310 and.w r3, r3, #16 80088d6: b2db uxtb r3, r3 80088d8: 2b00 cmp r3, #0 80088da: d002 beq.n 80088e2 { /* x1_xxxxb: issue reset enable instruction 66h, then issue reset instruction 99h. The reset enable, reset sequence may be issued on 1, 2, or 4 wires depending on the device operating mode. */ reset_method = RESET_INSTRUCTION_66_99; 80088dc: 2305 movs r3, #5 80088de: 75fb strb r3, [r7, #23] 80088e0: e00d b.n 80088fe } else if (0x20u == (0x20u & JEDEC_Basic.Params.Param_DWORD.D16.SoftResetRescueSequence_Support)) 80088e2: 4b1e ldr r3, [pc, #120] @ (800895c ) 80088e4: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80088e8: f3c3 0305 ubfx r3, r3, #0, #6 80088ec: b2db uxtb r3, r3 80088ee: 2b1f cmp r3, #31 80088f0: d902 bls.n 80088f8 xx_xx1x_xxxxb: Hardware reset xx_x1xx_xxxxb: Software reset (see bits 13:8 in this DWORD) xx_1xxx_xxxxb: Power cycle x1_xxxx_xxxxb: Reserved */ retr = EXTMEM_SFDP_ERROR_NOTYETHANDLED; 80088f2: 230f movs r3, #15 80088f4: 75bb strb r3, [r7, #22] goto error; 80088f6: e027 b.n 8008948 } else { /* No coherence, should be managed as error */ retr = EXTMEM_SFDP_ERROR_DRIVER; 80088f8: 230c movs r3, #12 80088fa: 75bb strb r3, [r7, #22] goto error; 80088fc: e024 b.n 8008948 } switch (reset_method) 80088fe: 7dfb ldrb r3, [r7, #23] 8008900: 2b05 cmp r3, #5 8008902: d009 beq.n 8008918 8008904: 2b05 cmp r3, #5 8008906: dc1b bgt.n 8008940 8008908: 2b00 cmp r3, #0 800890a: d01c beq.n 8008946 800890c: 2b00 cmp r3, #0 800890e: db17 blt.n 8008940 8008910: 3b01 subs r3, #1 8008912: 2b03 cmp r3, #3 8008914: d814 bhi.n 8008940 8008916: e010 b.n 800893a case RESET_NONE: break; case RESET_INSTRUCTION_66_99: /* Perform the reset in 1, 2 and 4 lines */ SFDP_DEBUG_STR("::reset 0x66 0x99"); (void)SAL_XSPI_CommandSendData(&Object->sfdp_private.SALObject, 0x66, NULL, 0); 8008918: 687b ldr r3, [r7, #4] 800891a: f103 0008 add.w r0, r3, #8 800891e: 2300 movs r3, #0 8008920: 2200 movs r2, #0 8008922: 2166 movs r1, #102 @ 0x66 8008924: f7ff fa83 bl 8007e2e (void)SAL_XSPI_CommandSendData(&Object->sfdp_private.SALObject, 0x99, NULL, 0); 8008928: 687b ldr r3, [r7, #4] 800892a: f103 0008 add.w r0, r3, #8 800892e: 2300 movs r3, #0 8008930: 2200 movs r2, #0 8008932: 2199 movs r1, #153 @ 0x99 8008934: f7ff fa7b bl 8007e2e break; 8008938: e006 b.n 8008948 case RESET_INSTRUCTION_F0: case RESET_FH_4DATA_8CLOCK: case RESET_FH_4DATA_10CLOCK: case RESET_FH_4DATA_16CLOCK: retr = EXTMEM_SFDP_ERROR_NOTYETHANDLED; 800893a: 230f movs r3, #15 800893c: 75bb strb r3, [r7, #22] break; 800893e: e003 b.n 8008948 /* case RESET_ERROR:*/ default : retr = EXTMEM_SFDP_ERROR_PARAM; 8008940: 2301 movs r3, #1 8008942: 75bb strb r3, [r7, #22] break; 8008944: e000 b.n 8008948 break; 8008946: bf00 nop } error : return retr; 8008948: 7dbb ldrb r3, [r7, #22] } 800894a: 4618 mov r0, r3 800894c: 3718 adds r7, #24 800894e: 46bd mov sp, r7 8008950: bd80 pop {r7, pc} 8008952: bf00 nop 8008954: 240002c8 .word 0x240002c8 8008958: 24000344 .word 0x24000344 800895c: 24000340 .word 0x24000340 08008960 : * @param Object Pointer to the NOR SFDP memory instance object descriptor. * @param FreqUpdated Pointer to a variable set to 1 if the frequency is updated, 0 otherwise. * @retval SFDP_StatusTypeDef Status of the operation: EXTMEM_SFDP_OK if successful, error code otherwise. */ SFDP_StatusTypeDef SFDP_BuildGenericDriver(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object, uint8_t *FreqUpdated) { 8008960: b5f0 push {r4, r5, r6, r7, lr} 8008962: b08f sub sp, #60 @ 0x3c 8008964: af04 add r7, sp, #16 8008966: 6078 str r0, [r7, #4] 8008968: 6039 str r1, [r7, #0] SFDP_StatusTypeDef retr = EXTMEM_SFDP_OK; 800896a: 2300 movs r3, #0 800896c: f887 3027 strb.w r3, [r7, #39] @ 0x27 static const uint16_t block_erase_unit[] = { 16u, 256u, 4000u, 64000u}; static const uint32_t chip_erase_unit[] = { 16u, 256u, 4000u, 64000u}; SFDP_DEBUG_STR(__func__); uint8_t flag4byteAddress = 0u; 8008970: 2300 movs r3, #0 8008972: f887 3026 strb.w r3, [r7, #38] @ 0x26 uint32_t dummyCycles; uint32_t dummyCyclesValue; uint8_t FlashSize; if ((Object->sfdp_private.Sfdp_table_mask & (uint32_t)SFDP_PARAMID_BASIC_SPIPROTOCOL) != 8008976: 687b ldr r3, [r7, #4] 8008978: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800897c: f003 0308 and.w r3, r3, #8 8008980: 2b00 cmp r3, #0 8008982: d104 bne.n 800898e (uint32_t)SFDP_PARAMID_BASIC_SPIPROTOCOL) { /* This table is mandatory to build the driver data */ retr = EXTMEM_SFDP_ERROR_NO_PARAMTABLE_BASIC; 8008984: 2307 movs r3, #7 8008986: f887 3027 strb.w r3, [r7, #39] @ 0x27 goto error; 800898a: f000 be26 b.w 80095da /* --------------------------------------------------- * Flash sizing * --------------------------------------------------- */ /* Calculation of the flash density in puissance of 2 */ if ((JEDEC_Basic.Params.Param_DWORD.D2.FlashSize & 0x80000000u) == 0x0u) 800898e: 4bba ldr r3, [pc, #744] @ (8008c78 ) 8008990: 689b ldr r3, [r3, #8] 8008992: 2b00 cmp r3, #0 8008994: db13 blt.n 80089be { #if ( __CORTEX_M == 0) #error "the assembly instruction is not available" #else Object->sfdp_private.FlashSize = 31u - (uint8_t)__CLZ((JEDEC_Basic.Params.Param_DWORD.D2.FlashSize + 1u)); 8008996: 4bb8 ldr r3, [pc, #736] @ (8008c78 ) 8008998: 689b ldr r3, [r3, #8] 800899a: 3301 adds r3, #1 800899c: 61bb str r3, [r7, #24] if (value == 0U) 800899e: 69bb ldr r3, [r7, #24] 80089a0: 2b00 cmp r3, #0 80089a2: d101 bne.n 80089a8 return 32U; 80089a4: 2320 movs r3, #32 80089a6: e003 b.n 80089b0 return __builtin_clz(value); 80089a8: 69bb ldr r3, [r7, #24] 80089aa: fab3 f383 clz r3, r3 80089ae: b2db uxtb r3, r3 80089b0: f1c3 031f rsb r3, r3, #31 80089b4: b2da uxtb r2, r3 80089b6: 687b ldr r3, [r7, #4] 80089b8: f883 205e strb.w r2, [r3, #94] @ 0x5e 80089bc: e005 b.n 80089ca #endif /* __CORTEX_M */ } else { Object->sfdp_private.FlashSize = (uint8_t)(JEDEC_Basic.Params.Param_DWORD.D2.FlashSize & 0x7FFFFFFFu); 80089be: 4bae ldr r3, [pc, #696] @ (8008c78 ) 80089c0: 689b ldr r3, [r3, #8] 80089c2: b2da uxtb r2, r3 80089c4: 687b ldr r3, [r7, #4] 80089c6: f883 205e strb.w r2, [r3, #94] @ 0x5e } /* Conversion bit to byte */ Object->sfdp_private.FlashSize = Object->sfdp_private.FlashSize - 3u; /* divide by eight the value */ 80089ca: 687b ldr r3, [r7, #4] 80089cc: f893 305e ldrb.w r3, [r3, #94] @ 0x5e 80089d0: 3b03 subs r3, #3 80089d2: b2da uxtb r2, r3 80089d4: 687b ldr r3, [r7, #4] 80089d6: f883 205e strb.w r2, [r3, #94] @ 0x5e SFDP_DEBUG_INT("-> flash size: 2^", Object->sfdp_private.FlashSize); FlashSize = Object->sfdp_private.FlashSize - 1u; 80089da: 687b ldr r3, [r7, #4] 80089dc: f893 305e ldrb.w r3, [r3, #94] @ 0x5e 80089e0: 3b01 subs r3, #1 80089e2: b2db uxtb r3, r3 80089e4: 74fb strb r3, [r7, #19] (void) SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_FLASHSIZE, &FlashSize); 80089e6: 687b ldr r3, [r7, #4] 80089e8: 3308 adds r3, #8 80089ea: f107 0213 add.w r2, r7, #19 80089ee: 2104 movs r1, #4 80089f0: 4618 mov r0, r3 80089f2: f7fe ff39 bl 8007868 /* get the page size info */ Object->sfdp_private.PageSize = ((uint32_t)1u << JEDEC_Basic.Params.Param_DWORD.D11.PageSize); 80089f6: 4ba0 ldr r3, [pc, #640] @ (8008c78 ) 80089f8: f893 302c ldrb.w r3, [r3, #44] @ 0x2c 80089fc: f3c3 1303 ubfx r3, r3, #4, #4 8008a00: b2db uxtb r3, r3 8008a02: 461a mov r2, r3 8008a04: 2301 movs r3, #1 8008a06: fa03 f202 lsl.w r2, r3, r2 8008a0a: 687b ldr r3, [r7, #4] 8008a0c: 661a str r2, [r3, #96] @ 0x60 /* --------------------------------------------------- * Set default command * --------------------------------------------------- */ Object->sfdp_private.DriverInfo.PageProgramInstruction = SFDP_DRIVER_PAGE_PROGRAM_COMMAND; 8008a0e: 687b ldr r3, [r7, #4] 8008a10: 2202 movs r2, #2 8008a12: f883 2075 strb.w r2, [r3, #117] @ 0x75 /* --------------------------------------------------- * Erase management * --------------------------------------------------- */ /* Manage erase data */ Object->sfdp_private.DriverInfo.EraseType1Size = (uint8_t)JEDEC_Basic.Params.Param_DWORD.D8.EraseType1_Size; 8008a16: 4b98 ldr r3, [pc, #608] @ (8008c78 ) 8008a18: f893 2020 ldrb.w r2, [r3, #32] 8008a1c: 687b ldr r3, [r7, #4] 8008a1e: f883 2077 strb.w r2, [r3, #119] @ 0x77 Object->sfdp_private.DriverInfo.EraseType1Command = (uint8_t)JEDEC_Basic.Params.Param_DWORD.D8.EraseType1_Instruction; 8008a22: 4b95 ldr r3, [pc, #596] @ (8008c78 ) 8008a24: f893 2021 ldrb.w r2, [r3, #33] @ 0x21 8008a28: 687b ldr r3, [r7, #4] 8008a2a: f883 2078 strb.w r2, [r3, #120] @ 0x78 Object->sfdp_private.DriverInfo.EraseType2Size = (uint8_t)JEDEC_Basic.Params.Param_DWORD.D8.EraseType2_Size; 8008a2e: 4b92 ldr r3, [pc, #584] @ (8008c78 ) 8008a30: f893 2022 ldrb.w r2, [r3, #34] @ 0x22 8008a34: 687b ldr r3, [r7, #4] 8008a36: f883 2079 strb.w r2, [r3, #121] @ 0x79 Object->sfdp_private.DriverInfo.EraseType2Command = (uint8_t)JEDEC_Basic.Params.Param_DWORD.D8.EraseType2_Instruction; 8008a3a: 4b8f ldr r3, [pc, #572] @ (8008c78 ) 8008a3c: f893 2023 ldrb.w r2, [r3, #35] @ 0x23 8008a40: 687b ldr r3, [r7, #4] 8008a42: f883 207a strb.w r2, [r3, #122] @ 0x7a Object->sfdp_private.DriverInfo.EraseType3Size = (uint8_t)JEDEC_Basic.Params.Param_DWORD.D9.EraseType3_Size; 8008a46: 4b8c ldr r3, [pc, #560] @ (8008c78 ) 8008a48: f893 2024 ldrb.w r2, [r3, #36] @ 0x24 8008a4c: 687b ldr r3, [r7, #4] 8008a4e: f883 207b strb.w r2, [r3, #123] @ 0x7b Object->sfdp_private.DriverInfo.EraseType3Command = (uint8_t)JEDEC_Basic.Params.Param_DWORD.D9.EraseType3_Instruction; 8008a52: 4b89 ldr r3, [pc, #548] @ (8008c78 ) 8008a54: f893 2025 ldrb.w r2, [r3, #37] @ 0x25 8008a58: 687b ldr r3, [r7, #4] 8008a5a: f883 207c strb.w r2, [r3, #124] @ 0x7c Object->sfdp_private.DriverInfo.EraseType4Size = (uint8_t)JEDEC_Basic.Params.Param_DWORD.D9.EraseType4_Size; 8008a5e: 4b86 ldr r3, [pc, #536] @ (8008c78 ) 8008a60: f893 2026 ldrb.w r2, [r3, #38] @ 0x26 8008a64: 687b ldr r3, [r7, #4] 8008a66: f883 207d strb.w r2, [r3, #125] @ 0x7d Object->sfdp_private.DriverInfo.EraseType4Command = (uint8_t)JEDEC_Basic.Params.Param_DWORD.D9.EraseType4_Instruction; 8008a6a: 4b83 ldr r3, [pc, #524] @ (8008c78 ) 8008a6c: f893 2027 ldrb.w r2, [r3, #39] @ 0x27 8008a70: 687b ldr r3, [r7, #4] 8008a72: f883 207e strb.w r2, [r3, #126] @ 0x7e if (Object->sfdp_private.DriverInfo.EraseType1Size != 0x0u) 8008a76: 687b ldr r3, [r7, #4] 8008a78: f893 3077 ldrb.w r3, [r3, #119] @ 0x77 8008a7c: 2b00 cmp r3, #0 8008a7e: d01d beq.n 8008abc { Object->sfdp_private.DriverInfo.EraseType1Timing = (uint32_t)JEDEC_Basic.Params.Param_DWORD.D10.MutliplierEraseTime * 8008a80: 4b7d ldr r3, [pc, #500] @ (8008c78 ) 8008a82: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8008a86: f3c3 0303 ubfx r3, r3, #0, #4 8008a8a: b2db uxtb r3, r3 8008a8c: 461a mov r2, r3 (JEDEC_Basic.Params.Param_DWORD.D10.EraseType1_TypicalTime_count + 1u) * 8008a8e: 4b7a ldr r3, [pc, #488] @ (8008c78 ) 8008a90: 8d1b ldrh r3, [r3, #40] @ 0x28 8008a92: f3c3 1304 ubfx r3, r3, #4, #5 8008a96: b2db uxtb r3, r3 8008a98: 3301 adds r3, #1 (uint32_t)JEDEC_Basic.Params.Param_DWORD.D10.MutliplierEraseTime * 8008a9a: fb02 f303 mul.w r3, r2, r3 block_erase_unit[JEDEC_Basic.Params.Param_DWORD.D10.EraseType1_TypicalTime_units]; 8008a9e: 4a76 ldr r2, [pc, #472] @ (8008c78 ) 8008aa0: f892 2029 ldrb.w r2, [r2, #41] @ 0x29 8008aa4: f3c2 0241 ubfx r2, r2, #1, #2 8008aa8: b2d2 uxtb r2, r2 8008aaa: 4611 mov r1, r2 8008aac: 4a73 ldr r2, [pc, #460] @ (8008c7c ) 8008aae: f832 2011 ldrh.w r2, [r2, r1, lsl #1] (JEDEC_Basic.Params.Param_DWORD.D10.EraseType1_TypicalTime_count + 1u) * 8008ab2: fb03 f202 mul.w r2, r3, r2 Object->sfdp_private.DriverInfo.EraseType1Timing = 8008ab6: 687b ldr r3, [r7, #4] 8008ab8: f8c3 2080 str.w r2, [r3, #128] @ 0x80 } if (Object->sfdp_private.DriverInfo.EraseType2Size != 0x0u) 8008abc: 687b ldr r3, [r7, #4] 8008abe: f893 3079 ldrb.w r3, [r3, #121] @ 0x79 8008ac2: 2b00 cmp r3, #0 8008ac4: d01e beq.n 8008b04 { Object->sfdp_private.DriverInfo.EraseType2Timing = (uint32_t)JEDEC_Basic.Params.Param_DWORD.D10.MutliplierEraseTime * 8008ac6: 4b6c ldr r3, [pc, #432] @ (8008c78 ) 8008ac8: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8008acc: f3c3 0303 ubfx r3, r3, #0, #4 8008ad0: b2db uxtb r3, r3 8008ad2: 461a mov r2, r3 (JEDEC_Basic.Params.Param_DWORD.D10.EraseType2_TypicalTime_count + 1u) * 8008ad4: 4b68 ldr r3, [pc, #416] @ (8008c78 ) 8008ad6: f893 3029 ldrb.w r3, [r3, #41] @ 0x29 8008ada: f3c3 03c4 ubfx r3, r3, #3, #5 8008ade: b2db uxtb r3, r3 8008ae0: 3301 adds r3, #1 (uint32_t)JEDEC_Basic.Params.Param_DWORD.D10.MutliplierEraseTime * 8008ae2: fb02 f303 mul.w r3, r2, r3 block_erase_unit[JEDEC_Basic.Params.Param_DWORD.D10.EraseType2_TypicalTime_units]; 8008ae6: 4a64 ldr r2, [pc, #400] @ (8008c78 ) 8008ae8: f892 202a ldrb.w r2, [r2, #42] @ 0x2a 8008aec: f3c2 0201 ubfx r2, r2, #0, #2 8008af0: b2d2 uxtb r2, r2 8008af2: 4611 mov r1, r2 8008af4: 4a61 ldr r2, [pc, #388] @ (8008c7c ) 8008af6: f832 2011 ldrh.w r2, [r2, r1, lsl #1] (JEDEC_Basic.Params.Param_DWORD.D10.EraseType2_TypicalTime_count + 1u) * 8008afa: fb03 f202 mul.w r2, r3, r2 Object->sfdp_private.DriverInfo.EraseType2Timing = 8008afe: 687b ldr r3, [r7, #4] 8008b00: f8c3 2084 str.w r2, [r3, #132] @ 0x84 } if (Object->sfdp_private.DriverInfo.EraseType3Size != 0x0u) 8008b04: 687b ldr r3, [r7, #4] 8008b06: f893 307b ldrb.w r3, [r3, #123] @ 0x7b 8008b0a: 2b00 cmp r3, #0 8008b0c: d01d beq.n 8008b4a { Object->sfdp_private.DriverInfo.EraseType3Timing = (uint32_t)JEDEC_Basic.Params.Param_DWORD.D10.MutliplierEraseTime * 8008b0e: 4b5a ldr r3, [pc, #360] @ (8008c78 ) 8008b10: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8008b14: f3c3 0303 ubfx r3, r3, #0, #4 8008b18: b2db uxtb r3, r3 8008b1a: 461a mov r2, r3 (JEDEC_Basic.Params.Param_DWORD.D10.EraseType3_TypicalTime_count + 1u) * 8008b1c: 4b56 ldr r3, [pc, #344] @ (8008c78 ) 8008b1e: f893 302a ldrb.w r3, [r3, #42] @ 0x2a 8008b22: f3c3 0384 ubfx r3, r3, #2, #5 8008b26: b2db uxtb r3, r3 8008b28: 3301 adds r3, #1 (uint32_t)JEDEC_Basic.Params.Param_DWORD.D10.MutliplierEraseTime * 8008b2a: fb02 f303 mul.w r3, r2, r3 block_erase_unit[JEDEC_Basic.Params.Param_DWORD.D10.EraseType3_TypicalTime_units]; 8008b2e: 4a52 ldr r2, [pc, #328] @ (8008c78 ) 8008b30: 8d52 ldrh r2, [r2, #42] @ 0x2a 8008b32: f3c2 12c1 ubfx r2, r2, #7, #2 8008b36: b2d2 uxtb r2, r2 8008b38: 4611 mov r1, r2 8008b3a: 4a50 ldr r2, [pc, #320] @ (8008c7c ) 8008b3c: f832 2011 ldrh.w r2, [r2, r1, lsl #1] (JEDEC_Basic.Params.Param_DWORD.D10.EraseType3_TypicalTime_count + 1u) * 8008b40: fb03 f202 mul.w r2, r3, r2 Object->sfdp_private.DriverInfo.EraseType3Timing = 8008b44: 687b ldr r3, [r7, #4] 8008b46: f8c3 2088 str.w r2, [r3, #136] @ 0x88 } if (Object->sfdp_private.DriverInfo.EraseType4Size != 0x0u) 8008b4a: 687b ldr r3, [r7, #4] 8008b4c: f893 307d ldrb.w r3, [r3, #125] @ 0x7d 8008b50: 2b00 cmp r3, #0 8008b52: d01e beq.n 8008b92 { Object->sfdp_private.DriverInfo.EraseType4Timing = (uint32_t)JEDEC_Basic.Params.Param_DWORD.D10.MutliplierEraseTime * 8008b54: 4b48 ldr r3, [pc, #288] @ (8008c78 ) 8008b56: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8008b5a: f3c3 0303 ubfx r3, r3, #0, #4 8008b5e: b2db uxtb r3, r3 8008b60: 461a mov r2, r3 (JEDEC_Basic.Params.Param_DWORD.D10.EraseType4_TypicalTime_count + 1u) * 8008b62: 4b45 ldr r3, [pc, #276] @ (8008c78 ) 8008b64: f893 302b ldrb.w r3, [r3, #43] @ 0x2b 8008b68: f3c3 0344 ubfx r3, r3, #1, #5 8008b6c: b2db uxtb r3, r3 8008b6e: 3301 adds r3, #1 (uint32_t)JEDEC_Basic.Params.Param_DWORD.D10.MutliplierEraseTime * 8008b70: fb02 f303 mul.w r3, r2, r3 block_erase_unit[JEDEC_Basic.Params.Param_DWORD.D10.EraseType4_TypicalTime_units]; 8008b74: 4a40 ldr r2, [pc, #256] @ (8008c78 ) 8008b76: f892 202b ldrb.w r2, [r2, #43] @ 0x2b 8008b7a: f3c2 1281 ubfx r2, r2, #6, #2 8008b7e: b2d2 uxtb r2, r2 8008b80: 4611 mov r1, r2 8008b82: 4a3e ldr r2, [pc, #248] @ (8008c7c ) 8008b84: f832 2011 ldrh.w r2, [r2, r1, lsl #1] (JEDEC_Basic.Params.Param_DWORD.D10.EraseType4_TypicalTime_count + 1u) * 8008b88: fb03 f202 mul.w r2, r3, r2 Object->sfdp_private.DriverInfo.EraseType4Timing = 8008b8c: 687b ldr r3, [r7, #4] 8008b8e: f8c3 208c str.w r2, [r3, #140] @ 0x8c } Object->sfdp_private.DriverInfo.EraseChipTiming = JEDEC_Basic.Params.Param_DWORD.D10.MutliplierEraseTime * 8008b92: 4b39 ldr r3, [pc, #228] @ (8008c78 ) 8008b94: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8008b98: f3c3 0303 ubfx r3, r3, #0, #4 8008b9c: b2db uxtb r3, r3 8008b9e: 461a mov r2, r3 (JEDEC_Basic.Params.Param_DWORD.D11.ChipErase_TypicalTime_count + 1u) * 8008ba0: 4b35 ldr r3, [pc, #212] @ (8008c78 ) 8008ba2: f893 302f ldrb.w r3, [r3, #47] @ 0x2f 8008ba6: f3c3 0304 ubfx r3, r3, #0, #5 8008baa: b2db uxtb r3, r3 8008bac: 3301 adds r3, #1 JEDEC_Basic.Params.Param_DWORD.D10.MutliplierEraseTime * 8008bae: fb02 f303 mul.w r3, r2, r3 chip_erase_unit[JEDEC_Basic.Params.Param_DWORD.D11.ChipErase_TypicalTime_units]; 8008bb2: 4a31 ldr r2, [pc, #196] @ (8008c78 ) 8008bb4: f892 202f ldrb.w r2, [r2, #47] @ 0x2f 8008bb8: f3c2 1241 ubfx r2, r2, #5, #2 8008bbc: b2d2 uxtb r2, r2 8008bbe: 4611 mov r1, r2 8008bc0: 4a2f ldr r2, [pc, #188] @ (8008c80 ) 8008bc2: f852 2021 ldr.w r2, [r2, r1, lsl #2] (JEDEC_Basic.Params.Param_DWORD.D11.ChipErase_TypicalTime_count + 1u) * 8008bc6: fb03 f202 mul.w r2, r3, r2 Object->sfdp_private.DriverInfo.EraseChipTiming = 8008bca: 687b ldr r3, [r7, #4] 8008bcc: f8c3 2090 str.w r2, [r3, #144] @ 0x90 * WIP/WEL : write in progress/ write enable management * ------------------------------------------------------ */ /* This bit definition is maintained for legacy compatibility only. New system implementations should refer to 6.4.19 for a full definition of volatile and non-volatile behavior. */ Object->sfdp_private.DriverInfo.ReadWELCommand = SFDP_DRIVER_READ_STATUS_REGISTER_COMMAND; 8008bd0: 687b ldr r3, [r7, #4] 8008bd2: 2205 movs r2, #5 8008bd4: f883 2071 strb.w r2, [r3, #113] @ 0x71 Object->sfdp_private.DriverInfo.ReadWIPCommand = SFDP_DRIVER_READ_STATUS_REGISTER_COMMAND; 8008bd8: 687b ldr r3, [r7, #4] 8008bda: 2205 movs r2, #5 8008bdc: f883 206c strb.w r2, [r3, #108] @ 0x6c if (JEDEC_Basic.Params.Param_DWORD.D1.WriteEnableInstructionVolatileRegister == 0u) 8008be0: 4b25 ldr r3, [pc, #148] @ (8008c78 ) 8008be2: 791b ldrb r3, [r3, #4] 8008be4: f003 0310 and.w r3, r3, #16 8008be8: b2db uxtb r3, r3 8008bea: 2b00 cmp r3, #0 8008bec: d104 bne.n 8008bf8 { Object->sfdp_private.DriverInfo.WriteWELCommand = SFDP_DRIVER_WRITE_ENABLE_50H_COMMAND; 8008bee: 687b ldr r3, [r7, #4] 8008bf0: 2250 movs r2, #80 @ 0x50 8008bf2: f883 2070 strb.w r2, [r3, #112] @ 0x70 8008bf6: e003 b.n 8008c00 } else { Object->sfdp_private.DriverInfo.WriteWELCommand = SFDP_DRIVER_WRITE_ENABLE_06H_COMMAND; 8008bf8: 687b ldr r3, [r7, #4] 8008bfa: 2206 movs r2, #6 8008bfc: f883 2070 strb.w r2, [r3, #112] @ 0x70 in either a volatile or non-volatile manner. Bits 1:0 in status register 1 are de-facto standard write enable and busy status and are excluded from the definitions below. */ /* xxx_xxx1b: Non-Volatile Status Register 1, powers-up to last written value, use instruction 06h to enable write */ if ((JEDEC_Basic.Params.Param_DWORD.D16.VolatileNonVolatileRegister_WriteEnable & 0x1u) != 0u) 8008c00: 4b1d ldr r3, [pc, #116] @ (8008c78 ) 8008c02: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8008c06: f3c3 0306 ubfx r3, r3, #0, #7 8008c0a: b2db uxtb r3, r3 8008c0c: f003 0301 and.w r3, r3, #1 8008c10: 2b00 cmp r3, #0 8008c12: d004 beq.n 8008c1e { Object->sfdp_private.DriverInfo.WriteWELCommand = SFDP_DRIVER_WRITE_ENABLE_06H_COMMAND; 8008c14: 687b ldr r3, [r7, #4] 8008c16: 2206 movs r2, #6 8008c18: f883 2070 strb.w r2, [r3, #112] @ 0x70 8008c1c: e046 b.n 8008cac } /* xxx_xx1xb: Volatile Status Register 1, status register powers-up with bits set to "1"s, use instruction 06h to enable write */ else if ((JEDEC_Basic.Params.Param_DWORD.D16.VolatileNonVolatileRegister_WriteEnable & 0x02u) != 0u) 8008c1e: 4b16 ldr r3, [pc, #88] @ (8008c78 ) 8008c20: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8008c24: f3c3 0306 ubfx r3, r3, #0, #7 8008c28: b2db uxtb r3, r3 8008c2a: f003 0302 and.w r3, r3, #2 8008c2e: 2b00 cmp r3, #0 8008c30: d004 beq.n 8008c3c { Object->sfdp_private.DriverInfo.WriteWELCommand = SFDP_DRIVER_WRITE_ENABLE_06H_COMMAND; 8008c32: 687b ldr r3, [r7, #4] 8008c34: 2206 movs r2, #6 8008c36: f883 2070 strb.w r2, [r3, #112] @ 0x70 8008c3a: e037 b.n 8008cac } /* xxx_x1xxb: Volatile Status Register 1, status register powers-up with bits set to "1"s, use instruction 50h to enable write */ else if ((JEDEC_Basic.Params.Param_DWORD.D16.VolatileNonVolatileRegister_WriteEnable & 0x04u) != 0u) 8008c3c: 4b0e ldr r3, [pc, #56] @ (8008c78 ) 8008c3e: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8008c42: f3c3 0306 ubfx r3, r3, #0, #7 8008c46: b2db uxtb r3, r3 8008c48: f003 0304 and.w r3, r3, #4 8008c4c: 2b00 cmp r3, #0 8008c4e: d004 beq.n 8008c5a { Object->sfdp_private.DriverInfo.WriteWELCommand = SFDP_DRIVER_WRITE_ENABLE_50H_COMMAND; 8008c50: 687b ldr r3, [r7, #4] 8008c52: 2250 movs r2, #80 @ 0x50 8008c54: f883 2070 strb.w r2, [r3, #112] @ 0x70 8008c58: e028 b.n 8008cac } /* xxx_1xxxb: Non-Volatile/Volatile status register 1 powers-up to last written value in the non-volatile status register, use instruction 06h to enable write to non-volatile status register. Volatile status register may be activated after power-up to override the non-volatile status register, use instruction 50h to enable write and activate the volatile status register.*/ else if ((JEDEC_Basic.Params.Param_DWORD.D16.VolatileNonVolatileRegister_WriteEnable & 0x08u) != 0u) 8008c5a: 4b07 ldr r3, [pc, #28] @ (8008c78 ) 8008c5c: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8008c60: f3c3 0306 ubfx r3, r3, #0, #7 8008c64: b2db uxtb r3, r3 8008c66: f003 0308 and.w r3, r3, #8 8008c6a: 2b00 cmp r3, #0 8008c6c: d00a beq.n 8008c84 { Object->sfdp_private.DriverInfo.WriteWELCommand = SFDP_DRIVER_WRITE_ENABLE_06H_COMMAND; 8008c6e: 687b ldr r3, [r7, #4] 8008c70: 2206 movs r2, #6 8008c72: f883 2070 strb.w r2, [r3, #112] @ 0x70 8008c76: e019 b.n 8008cac 8008c78: 24000340 .word 0x24000340 8008c7c: 0800a154 .word 0x0800a154 8008c80: 0800a15c .word 0x0800a15c } /* xx1_xxxxb: Status Register 1 contains a mix of volatile and non-volatile bits. The 06h instruction is used to enable writing of the register.*/ else if ((JEDEC_Basic.Params.Param_DWORD.D16.VolatileNonVolatileRegister_WriteEnable & 0x10u) != 0u) 8008c84: 4b66 ldr r3, [pc, #408] @ (8008e20 ) 8008c86: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8008c8a: f3c3 0306 ubfx r3, r3, #0, #7 8008c8e: b2db uxtb r3, r3 8008c90: f003 0310 and.w r3, r3, #16 8008c94: 2b00 cmp r3, #0 8008c96: d004 beq.n 8008ca2 { Object->sfdp_private.DriverInfo.WriteWELCommand = SFDP_DRIVER_WRITE_ENABLE_06H_COMMAND; 8008c98: 687b ldr r3, [r7, #4] 8008c9a: 2206 movs r2, #6 8008c9c: f883 2070 strb.w r2, [r3, #112] @ 0x70 8008ca0: e004 b.n 8008cac 1xx_xxxxb: Reserved NOTE If the status register is read-only then this field will contain all zeros in bits 4:0. */ else { retr = EXTMEM_SFDP_ERROR_JEDECBASIC_D16; 8008ca2: 230a movs r3, #10 8008ca4: f887 3027 strb.w r3, [r7, #39] @ 0x27 goto error; 8008ca8: f000 bc97 b.w 80095da } if (0u != (Object->sfdp_private.Sfdp_table_mask & (uint32_t)SFDP_PARAMID_STATUS_CONTROL_CONFIG_REGISTER_MAP)) 8008cac: 687b ldr r3, [r7, #4] 8008cae: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8008cb2: f403 7300 and.w r3, r3, #512 @ 0x200 8008cb6: 2b00 cmp r3, #0 8008cb8: d078 beq.n 8008dac { /* WIP */ if (0u != JEDEC_SCCR_Map.Param_DWORD.D5.WIPBitAvailable) 8008cba: 4b5a ldr r3, [pc, #360] @ (8008e24 ) 8008cbc: 7cdb ldrb r3, [r3, #19] 8008cbe: f023 037f bic.w r3, r3, #127 @ 0x7f 8008cc2: b2db uxtb r3, r3 8008cc4: 2b00 cmp r3, #0 8008cc6: d034 beq.n 8008d32 { Object->sfdp_private.DriverInfo.ReadWIPCommand = (uint8_t)JEDEC_SCCR_Map.Param_DWORD.D5.CommandReadAccess; 8008cc8: 4b56 ldr r3, [pc, #344] @ (8008e24 ) 8008cca: 7c5a ldrb r2, [r3, #17] 8008ccc: 687b ldr r3, [r7, #4] 8008cce: f883 206c strb.w r2, [r3, #108] @ 0x6c Object->sfdp_private.DriverInfo.WIPPosition = JEDEC_SCCR_Map.Param_DWORD.D5.WIPBitLocationRegister; 8008cd2: 4b54 ldr r3, [pc, #336] @ (8008e24 ) 8008cd4: 7cdb ldrb r3, [r3, #19] 8008cd6: f3c3 0302 ubfx r3, r3, #0, #3 8008cda: b2db uxtb r3, r3 8008cdc: 461a mov r2, r3 8008cde: 687b ldr r3, [r7, #4] 8008ce0: f883 206d strb.w r2, [r3, #109] @ 0x6d Object->sfdp_private.DriverInfo.WIPBusyPolarity = (uint8_t)JEDEC_SCCR_Map.Param_DWORD.D5.WIPpolarity; 8008ce4: 4b4f ldr r3, [pc, #316] @ (8008e24 ) 8008ce6: 7cdb ldrb r3, [r3, #19] 8008ce8: f3c3 1380 ubfx r3, r3, #6, #1 8008cec: b2db uxtb r3, r3 8008cee: 461a mov r2, r3 8008cf0: 687b ldr r3, [r7, #4] 8008cf2: f883 206e strb.w r2, [r3, #110] @ 0x6e Object->sfdp_private.DriverInfo.WIPPosition = JEDEC_SCCR_Map.Param_DWORD.D5.WIPBitLocationRegister; 8008cf6: 4b4b ldr r3, [pc, #300] @ (8008e24 ) 8008cf8: 7cdb ldrb r3, [r3, #19] 8008cfa: f3c3 0302 ubfx r3, r3, #0, #3 8008cfe: b2db uxtb r3, r3 8008d00: 461a mov r2, r3 8008d02: 687b ldr r3, [r7, #4] 8008d04: f883 206d strb.w r2, [r3, #109] @ 0x6d if (0u != JEDEC_SCCR_Map.Param_DWORD.D5.BitAccessedByCommandsUsingAddress) 8008d08: 4b46 ldr r3, [pc, #280] @ (8008e24 ) 8008d0a: 7cdb ldrb r3, [r3, #19] 8008d0c: f003 0310 and.w r3, r3, #16 8008d10: b2db uxtb r3, r3 8008d12: 2b00 cmp r3, #0 8008d14: d009 beq.n 8008d2a { /* Address management */ Object->sfdp_private.DriverInfo.WIPAddress = (uint8_t)JEDEC_SCCR_Map.Param_DWORD.D5.LocalAddressForWIP; 8008d16: 4b43 ldr r3, [pc, #268] @ (8008e24 ) 8008d18: 7cdb ldrb r3, [r3, #19] 8008d1a: f3c3 03c0 ubfx r3, r3, #3, #1 8008d1e: b2db uxtb r3, r3 8008d20: 461a mov r2, r3 8008d22: 687b ldr r3, [r7, #4] 8008d24: f883 206f strb.w r2, [r3, #111] @ 0x6f 8008d28: e003 b.n 8008d32 } else { /* in that case there is no address to manage, the value EXTMEM_ADDRESS_NONE is used to detect the difference */ Object->sfdp_private.DriverInfo.WIPAddress = EXTMEM_ADDRESS_NONE; 8008d2a: 687b ldr r3, [r7, #4] 8008d2c: 22ff movs r2, #255 @ 0xff 8008d2e: f883 206f strb.w r2, [r3, #111] @ 0x6f } } /* WEL */ if (0u != JEDEC_SCCR_Map.Param_DWORD.D6.WELBitAvailable) 8008d32: 4b3c ldr r3, [pc, #240] @ (8008e24 ) 8008d34: 7ddb ldrb r3, [r3, #23] 8008d36: f023 037f bic.w r3, r3, #127 @ 0x7f 8008d3a: b2db uxtb r3, r3 8008d3c: 2b00 cmp r3, #0 8008d3e: d073 beq.n 8008e28 { Object->sfdp_private.DriverInfo.ReadWELCommand = (uint8_t)JEDEC_SCCR_Map.Param_DWORD.D6.CommandReadAccess; 8008d40: 4b38 ldr r3, [pc, #224] @ (8008e24 ) 8008d42: 7d5a ldrb r2, [r3, #21] 8008d44: 687b ldr r3, [r7, #4] 8008d46: f883 2071 strb.w r2, [r3, #113] @ 0x71 Object->sfdp_private.DriverInfo.WELPosition = JEDEC_SCCR_Map.Param_DWORD.D6.WELBitLocationRegister; 8008d4a: 4b36 ldr r3, [pc, #216] @ (8008e24 ) 8008d4c: 7ddb ldrb r3, [r3, #23] 8008d4e: f3c3 0302 ubfx r3, r3, #0, #3 8008d52: b2db uxtb r3, r3 8008d54: 461a mov r2, r3 8008d56: 687b ldr r3, [r7, #4] 8008d58: f883 2072 strb.w r2, [r3, #114] @ 0x72 Object->sfdp_private.DriverInfo.WELBusyPolarity = (uint8_t)JEDEC_SCCR_Map.Param_DWORD.D6.WELpolarity; 8008d5c: 4b31 ldr r3, [pc, #196] @ (8008e24 ) 8008d5e: 7ddb ldrb r3, [r3, #23] 8008d60: f3c3 1380 ubfx r3, r3, #6, #1 8008d64: b2db uxtb r3, r3 8008d66: 461a mov r2, r3 8008d68: 687b ldr r3, [r7, #4] 8008d6a: f883 2073 strb.w r2, [r3, #115] @ 0x73 Object->sfdp_private.DriverInfo.WELPosition = JEDEC_SCCR_Map.Param_DWORD.D6.WELBitLocationRegister; 8008d6e: 4b2d ldr r3, [pc, #180] @ (8008e24 ) 8008d70: 7ddb ldrb r3, [r3, #23] 8008d72: f3c3 0302 ubfx r3, r3, #0, #3 8008d76: b2db uxtb r3, r3 8008d78: 461a mov r2, r3 8008d7a: 687b ldr r3, [r7, #4] 8008d7c: f883 2072 strb.w r2, [r3, #114] @ 0x72 if (0u != JEDEC_SCCR_Map.Param_DWORD.D5.BitAccessedByCommandsUsingAddress) 8008d80: 4b28 ldr r3, [pc, #160] @ (8008e24 ) 8008d82: 7cdb ldrb r3, [r3, #19] 8008d84: f003 0310 and.w r3, r3, #16 8008d88: b2db uxtb r3, r3 8008d8a: 2b00 cmp r3, #0 8008d8c: d009 beq.n 8008da2 { /* Address management */ Object->sfdp_private.DriverInfo.WELAddress = (uint8_t)JEDEC_SCCR_Map.Param_DWORD.D6.WELLocalAddress; 8008d8e: 4b25 ldr r3, [pc, #148] @ (8008e24 ) 8008d90: 7ddb ldrb r3, [r3, #23] 8008d92: f3c3 03c0 ubfx r3, r3, #3, #1 8008d96: b2db uxtb r3, r3 8008d98: 461a mov r2, r3 8008d9a: 687b ldr r3, [r7, #4] 8008d9c: f883 2074 strb.w r2, [r3, #116] @ 0x74 8008da0: e042 b.n 8008e28 } else { /* in that case there is no address to manage, the value EXTMEM_ADDRESS_NONE is used to detect the difference */ Object->sfdp_private.DriverInfo.WELAddress = EXTMEM_ADDRESS_NONE; 8008da2: 687b ldr r3, [r7, #4] 8008da4: 22ff movs r2, #255 @ 0xff 8008da6: f883 2074 strb.w r2, [r3, #116] @ 0x74 8008daa: e03d b.n 8008e28 } } } else { Object->sfdp_private.DriverInfo.WELPosition = 1; 8008dac: 687b ldr r3, [r7, #4] 8008dae: 2201 movs r2, #1 8008db0: f883 2072 strb.w r2, [r3, #114] @ 0x72 Object->sfdp_private.DriverInfo.WELBusyPolarity = 0; 8008db4: 687b ldr r3, [r7, #4] 8008db6: 2200 movs r2, #0 8008db8: f883 2073 strb.w r2, [r3, #115] @ 0x73 /* * WIP : Status register read management * Basic D14 Status register Polling device Busy */ if (0x01u == (JEDEC_Basic.Params.Param_DWORD.D14.StatusRegister & 0x01u)) 8008dbc: 4b18 ldr r3, [pc, #96] @ (8008e20 ) 8008dbe: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 8008dc2: f3c3 0385 ubfx r3, r3, #2, #6 8008dc6: b2db uxtb r3, r3 8008dc8: f003 0301 and.w r3, r3, #1 8008dcc: 2b00 cmp r3, #0 8008dce: d00c beq.n 8008dea { /* xx_xxx1b: Use of legacy polling is supported by reading the Status Register with 05h instruction and checking WIP bit[0] (0=ready; 1=busy). */ Object->sfdp_private.DriverInfo.ReadWIPCommand = SFDP_DRIVER_READ_STATUS_REGISTER_COMMAND; 8008dd0: 687b ldr r3, [r7, #4] 8008dd2: 2205 movs r2, #5 8008dd4: f883 206c strb.w r2, [r3, #108] @ 0x6c Object->sfdp_private.DriverInfo.WIPPosition = 0u; 8008dd8: 687b ldr r3, [r7, #4] 8008dda: 2200 movs r2, #0 8008ddc: f883 206d strb.w r2, [r3, #109] @ 0x6d Object->sfdp_private.DriverInfo.WIPBusyPolarity = 0u; 8008de0: 687b ldr r3, [r7, #4] 8008de2: 2200 movs r2, #0 8008de4: f883 206e strb.w r2, [r3, #110] @ 0x6e 8008de8: e01e b.n 8008e28 } else if (0x02u == (JEDEC_Basic.Params.Param_DWORD.D14.StatusRegister & 0x02u)) 8008dea: 4b0d ldr r3, [pc, #52] @ (8008e20 ) 8008dec: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 8008df0: f3c3 0385 ubfx r3, r3, #2, #6 8008df4: b2db uxtb r3, r3 8008df6: f003 0302 and.w r3, r3, #2 8008dfa: 2b00 cmp r3, #0 8008dfc: d00c beq.n 8008e18 { /* xx_xx1xb: Bit 7 of the Flag Status Register may be polled any time a Program, Erase, Suspend/Resume command is issued, or after a Reset command while the device is busy. The read instruction is 70h. Flag Status Register bit definitions: bit[7]: Program or erase controller status (0=busy; 1=ready)*/ Object->sfdp_private.DriverInfo.ReadWIPCommand = 0x70; 8008dfe: 687b ldr r3, [r7, #4] 8008e00: 2270 movs r2, #112 @ 0x70 8008e02: f883 206c strb.w r2, [r3, #108] @ 0x6c Object->sfdp_private.DriverInfo.WIPPosition = 7u; 8008e06: 687b ldr r3, [r7, #4] 8008e08: 2207 movs r2, #7 8008e0a: f883 206d strb.w r2, [r3, #109] @ 0x6d Object->sfdp_private.DriverInfo.WIPBusyPolarity = 0u; 8008e0e: 687b ldr r3, [r7, #4] 8008e10: 2200 movs r2, #0 8008e12: f883 206e strb.w r2, [r3, #110] @ 0x6e 8008e16: e007 b.n 8008e28 } else { retr = EXTMEM_SFDP_ERROR_JEDECBASIC_D14; 8008e18: 2309 movs r3, #9 8008e1a: f887 3027 strb.w r3, [r7, #39] @ 0x27 goto error; 8008e1e: e3dc b.n 80095da 8008e20: 24000340 .word 0x24000340 8008e24: 240003c0 .word 0x240003c0 } } /* Set default value for Read instruction */ Object->sfdp_private.DriverInfo.ReadInstruction = SFDP_DRIVER_READ_COMMAND; 8008e28: 687b ldr r3, [r7, #4] 8008e2a: 2203 movs r2, #3 8008e2c: f883 2076 strb.w r2, [r3, #118] @ 0x76 dummyCycles = 0; 8008e30: 2300 movs r3, #0 8008e32: 617b str r3, [r7, #20] (void)SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_DUMMY_CYCLES, (void *)&dummyCycles); 8008e34: 687b ldr r3, [r7, #4] 8008e36: 3308 adds r3, #8 8008e38: f107 0214 add.w r2, r7, #20 8008e3c: 2101 movs r1, #1 8008e3e: 4618 mov r0, r3 8008e40: f7fe fd12 bl 8007868 /* --------------------------------------------------- * command based on SFDP_PARAMID_BASIC_SPIPROTOCOL * --------------------------------------------------- */ if (((Object->sfdp_private.Sfdp_table_mask & (uint32_t)SFDP_PARAMID_BASIC_SPIPROTOCOL) 8008e44: 687b ldr r3, [r7, #4] 8008e46: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8008e4a: f003 0308 and.w r3, r3, #8 8008e4e: 2b00 cmp r3, #0 8008e50: f000 80b0 beq.w 8008fb4 == (uint32_t)SFDP_PARAMID_BASIC_SPIPROTOCOL) && (Object->sfdp_private.Config < EXTMEM_LINK_CONFIG_8LINES)) 8008e54: 687b ldr r3, [r7, #4] 8008e56: f893 305c ldrb.w r3, [r3, #92] @ 0x5c 8008e5a: 2b02 cmp r3, #2 8008e5c: f200 80aa bhi.w 8008fb4 { Object->sfdp_private.DriverInfo.SpiPhyLink = PHY_LINK_1S1S1S; 8008e60: 687b ldr r3, [r7, #4] 8008e62: 2200 movs r2, #0 8008e64: f883 2064 strb.w r2, [r3, #100] @ 0x64 if (Object->sfdp_private.Config > EXTMEM_LINK_CONFIG_1LINE) 8008e68: 687b ldr r3, [r7, #4] 8008e6a: f893 305c ldrb.w r3, [r3, #92] @ 0x5c 8008e6e: 2b00 cmp r3, #0 8008e70: d04c beq.n 8008f0c { /* control if read 1s1s2s is available */ if (JEDEC_Basic.Params.Param_DWORD.D4._1S1S2S_FastReadInstruction != 0u) 8008e72: 4bb6 ldr r3, [pc, #728] @ (800914c ) 8008e74: 7c5b ldrb r3, [r3, #17] 8008e76: 2b00 cmp r3, #0 8008e78: d015 beq.n 8008ea6 { dummyCycles = JEDEC_Basic.Params.Param_DWORD.D4._1S1S2S_DummyClock 8008e7a: 4bb4 ldr r3, [pc, #720] @ (800914c ) 8008e7c: 7c1b ldrb r3, [r3, #16] 8008e7e: f3c3 0304 ubfx r3, r3, #0, #5 8008e82: b2db uxtb r3, r3 8008e84: 461a mov r2, r3 + JEDEC_Basic.Params.Param_DWORD.D4._1S1S2S_ModeClock; 8008e86: 4bb1 ldr r3, [pc, #708] @ (800914c ) 8008e88: 7c1b ldrb r3, [r3, #16] 8008e8a: f3c3 1342 ubfx r3, r3, #5, #3 8008e8e: b2db uxtb r3, r3 8008e90: 4413 add r3, r2 dummyCycles = JEDEC_Basic.Params.Param_DWORD.D4._1S1S2S_DummyClock 8008e92: 617b str r3, [r7, #20] Object->sfdp_private.DriverInfo.ReadInstruction = (uint8_t)JEDEC_Basic.Params.Param_DWORD.D4._1S1S2S_FastReadInstruction; 8008e94: 4bad ldr r3, [pc, #692] @ (800914c ) 8008e96: 7c5a ldrb r2, [r3, #17] Object->sfdp_private.DriverInfo.ReadInstruction = 8008e98: 687b ldr r3, [r7, #4] 8008e9a: f883 2076 strb.w r2, [r3, #118] @ 0x76 Object->sfdp_private.DriverInfo.SpiPhyLink = PHY_LINK_1S1S2S; 8008e9e: 687b ldr r3, [r7, #4] 8008ea0: 2201 movs r2, #1 8008ea2: f883 2064 strb.w r2, [r3, #100] @ 0x64 } /* control if read 1S2S2S is available */ if (JEDEC_Basic.Params.Param_DWORD.D4._1S2S2S_FastReadInstruction != 0u) 8008ea6: 4ba9 ldr r3, [pc, #676] @ (800914c ) 8008ea8: 7cdb ldrb r3, [r3, #19] 8008eaa: 2b00 cmp r3, #0 8008eac: d015 beq.n 8008eda { dummyCycles = JEDEC_Basic.Params.Param_DWORD.D4._1S2S2S_DummyClock 8008eae: 4ba7 ldr r3, [pc, #668] @ (800914c ) 8008eb0: 7c9b ldrb r3, [r3, #18] 8008eb2: f3c3 0304 ubfx r3, r3, #0, #5 8008eb6: b2db uxtb r3, r3 8008eb8: 461a mov r2, r3 + JEDEC_Basic.Params.Param_DWORD.D4._1S2S2S_ModeClock; 8008eba: 4ba4 ldr r3, [pc, #656] @ (800914c ) 8008ebc: 7c9b ldrb r3, [r3, #18] 8008ebe: f3c3 1342 ubfx r3, r3, #5, #3 8008ec2: b2db uxtb r3, r3 8008ec4: 4413 add r3, r2 dummyCycles = JEDEC_Basic.Params.Param_DWORD.D4._1S2S2S_DummyClock 8008ec6: 617b str r3, [r7, #20] Object->sfdp_private.DriverInfo.ReadInstruction = (uint8_t)JEDEC_Basic.Params.Param_DWORD.D4._1S2S2S_FastReadInstruction; 8008ec8: 4ba0 ldr r3, [pc, #640] @ (800914c ) 8008eca: 7cda ldrb r2, [r3, #19] Object->sfdp_private.DriverInfo.ReadInstruction = 8008ecc: 687b ldr r3, [r7, #4] 8008ece: f883 2076 strb.w r2, [r3, #118] @ 0x76 Object->sfdp_private.DriverInfo.SpiPhyLink = PHY_LINK_1S2S2S; 8008ed2: 687b ldr r3, [r7, #4] 8008ed4: 2202 movs r2, #2 8008ed6: f883 2064 strb.w r2, [r3, #100] @ 0x64 } /* The memory work only in 2S2S2S */ if (JEDEC_Basic.Params.Param_DWORD.D5._2S2S2S_FastReadSupport != 0u) 8008eda: 4b9c ldr r3, [pc, #624] @ (800914c ) 8008edc: 7d1b ldrb r3, [r3, #20] 8008ede: f003 0301 and.w r3, r3, #1 8008ee2: b2db uxtb r3, r3 8008ee4: 2b00 cmp r3, #0 8008ee6: d011 beq.n 8008f0c { dummyCycles = JEDEC_Basic.Params.Param_DWORD.D6._2S2S2S_DummyClock 8008ee8: 4b98 ldr r3, [pc, #608] @ (800914c ) 8008eea: 7e9b ldrb r3, [r3, #26] 8008eec: f3c3 0304 ubfx r3, r3, #0, #5 8008ef0: b2db uxtb r3, r3 8008ef2: 461a mov r2, r3 + JEDEC_Basic.Params.Param_DWORD.D6._2S2S2S_ModeClock; 8008ef4: 4b95 ldr r3, [pc, #596] @ (800914c ) 8008ef6: 7e9b ldrb r3, [r3, #26] 8008ef8: f3c3 1342 ubfx r3, r3, #5, #3 8008efc: b2db uxtb r3, r3 8008efe: 4413 add r3, r2 dummyCycles = JEDEC_Basic.Params.Param_DWORD.D6._2S2S2S_DummyClock 8008f00: 617b str r3, [r7, #20] Object->sfdp_private.DriverInfo.ReadInstruction = (uint8_t)JEDEC_Basic.Params.Param_DWORD.D6._2S2S2S_FastReadInstruction; 8008f02: 4b92 ldr r3, [pc, #584] @ (800914c ) 8008f04: 7eda ldrb r2, [r3, #27] Object->sfdp_private.DriverInfo.ReadInstruction = 8008f06: 687b ldr r3, [r7, #4] 8008f08: f883 2076 strb.w r2, [r3, #118] @ 0x76 } } /* the command set is only based on this table */ /* determine the best line configuration */ if (Object->sfdp_private.Config > EXTMEM_LINK_CONFIG_2LINES) 8008f0c: 687b ldr r3, [r7, #4] 8008f0e: f893 305c ldrb.w r3, [r3, #92] @ 0x5c 8008f12: 2b01 cmp r3, #1 8008f14: d92f bls.n 8008f76 { if (JEDEC_Basic.Params.Param_DWORD.D5._4S4S4S_FastReadSupport != 0u) 8008f16: 4b8d ldr r3, [pc, #564] @ (800914c ) 8008f18: 7d1b ldrb r3, [r3, #20] 8008f1a: f003 0310 and.w r3, r3, #16 8008f1e: b2db uxtb r3, r3 8008f20: 2b00 cmp r3, #0 8008f22: d020 beq.n 8008f66 { dummyCycles = JEDEC_Basic.Params.Param_DWORD.D7._4S4S4S_DummyClock 8008f24: 4b89 ldr r3, [pc, #548] @ (800914c ) 8008f26: 7f9b ldrb r3, [r3, #30] 8008f28: f3c3 0304 ubfx r3, r3, #0, #5 8008f2c: b2db uxtb r3, r3 8008f2e: 461a mov r2, r3 + JEDEC_Basic.Params.Param_DWORD.D7._4S4S4S_ModeClock; 8008f30: 4b86 ldr r3, [pc, #536] @ (800914c ) 8008f32: 7f9b ldrb r3, [r3, #30] 8008f34: f3c3 1342 ubfx r3, r3, #5, #3 8008f38: b2db uxtb r3, r3 8008f3a: 4413 add r3, r2 dummyCycles = JEDEC_Basic.Params.Param_DWORD.D7._4S4S4S_DummyClock 8008f3c: 617b str r3, [r7, #20] Object->sfdp_private.DriverInfo.ReadInstruction = (uint8_t)JEDEC_Basic.Params.Param_DWORD.D7._4S4S4S_FastReadInstruction; 8008f3e: 4b83 ldr r3, [pc, #524] @ (800914c ) 8008f40: 7fda ldrb r2, [r3, #31] Object->sfdp_private.DriverInfo.ReadInstruction = 8008f42: 687b ldr r3, [r7, #4] 8008f44: f883 2076 strb.w r2, [r3, #118] @ 0x76 Object->sfdp_private.DriverInfo.SpiPhyLink = PHY_LINK_4S4S4S; 8008f48: 687b ldr r3, [r7, #4] 8008f4a: 2204 movs r2, #4 8008f4c: f883 2064 strb.w r2, [r3, #100] @ 0x64 retr = JEDEC_Basic_Manage4S4S4SEnableSequence(Object); 8008f50: 6878 ldr r0, [r7, #4] 8008f52: f000 ff3b bl 8009dcc 8008f56: 4603 mov r3, r0 8008f58: f887 3027 strb.w r3, [r7, #39] @ 0x27 if (retr != EXTMEM_SFDP_OK) 8008f5c: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 8008f60: 2b00 cmp r3, #0 8008f62: f040 8337 bne.w 80095d4 } else /* other configuration with more 4 lines */ { /* not yet handled */ } (void)SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_DUMMY_CYCLES, (void *)&dummyCycles); 8008f66: 687b ldr r3, [r7, #4] 8008f68: 3308 adds r3, #8 8008f6a: f107 0214 add.w r2, r7, #20 8008f6e: 2101 movs r1, #1 8008f70: 4618 mov r0, r3 8008f72: f7fe fc79 bl 8007868 #endif /* IS25WP032D_ENABLE_DTR */ } /* Configure the link */ if (HAL_OK != SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_PHY_LINK, 8008f76: 687b ldr r3, [r7, #4] 8008f78: f103 0008 add.w r0, r3, #8 &Object->sfdp_private.DriverInfo.SpiPhyLink)) 8008f7c: 687b ldr r3, [r7, #4] 8008f7e: 3364 adds r3, #100 @ 0x64 if (HAL_OK != SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_PHY_LINK, 8008f80: 461a mov r2, r3 8008f82: 2100 movs r1, #0 8008f84: f7fe fc70 bl 8007868 8008f88: 4603 mov r3, r0 8008f8a: 2b00 cmp r3, #0 8008f8c: d003 beq.n 8008f96 { retr = EXTMEM_SFDP_ERROR_DRIVER; 8008f8e: 230c movs r3, #12 8008f90: f887 3027 strb.w r3, [r7, #39] @ 0x27 goto error; 8008f94: e321 b.n 80095da } if (HAL_OK != SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_DUMMY_CYCLES, &dummyCycles)) 8008f96: 687b ldr r3, [r7, #4] 8008f98: 3308 adds r3, #8 8008f9a: f107 0214 add.w r2, r7, #20 8008f9e: 2101 movs r1, #1 8008fa0: 4618 mov r0, r3 8008fa2: f7fe fc61 bl 8007868 8008fa6: 4603 mov r3, r0 8008fa8: 2b00 cmp r3, #0 8008faa: d003 beq.n 8008fb4 { retr = EXTMEM_SFDP_ERROR_DRIVER; 8008fac: 230c movs r3, #12 8008fae: f887 3027 strb.w r3, [r7, #39] @ 0x27 goto error; 8008fb2: e312 b.n 80095da /* ----------------------------------------------------------------------------------------------------------------- If an octal DDR table is present and the target is 8D8D8D, when switch in octal DDR mode ----------------------------------------------------------------------------------------------------------------- */ if (((uint32_t)SFDP_PARAMID_OCTAL_DDR == (Object->sfdp_private.Sfdp_table_mask & (uint32_t)SFDP_PARAMID_OCTAL_DDR)) 8008fb4: 687b ldr r3, [r7, #4] 8008fb6: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8008fba: f403 5380 and.w r3, r3, #4096 @ 0x1000 8008fbe: 2b00 cmp r3, #0 8008fc0: f000 8087 beq.w 80090d2 && (EXTMEM_LINK_CONFIG_8LINES == Object->sfdp_private.Config)) 8008fc4: 687b ldr r3, [r7, #4] 8008fc6: f893 305c ldrb.w r3, [r3, #92] @ 0x5c 8008fca: 2b03 cmp r3, #3 8008fcc: f040 8081 bne.w 80090d2 { /* check if we are not already in octal mode */ if (PHY_LINK_8D8D8D == Object->sfdp_private.DriverInfo.SpiPhyLink) 8008fd0: 687b ldr r3, [r7, #4] 8008fd2: f893 3064 ldrb.w r3, [r3, #100] @ 0x64 8008fd6: 2b09 cmp r3, #9 8008fd8: d103 bne.n 8008fe2 { flag4byteAddress = 1u; 8008fda: 2301 movs r3, #1 8008fdc: f887 3026 strb.w r3, [r7, #38] @ 0x26 8008fe0: e044 b.n 800906c } else { /* Execute the flash command sequence to switch in octal DDR */ if (EXTMEM_SFDP_OK == sfdp_enter_octal_mode(Object)) 8008fe2: 6878 ldr r0, [r7, #4] 8008fe4: f000 fc6e bl 80098c4 8008fe8: 4603 mov r3, r0 8008fea: 2b00 cmp r3, #0 8008fec: d13e bne.n 800906c { /* switch the memory interface configuration according to the Access protocol field */ flag4byteAddress = 1u; 8008fee: 2301 movs r3, #1 8008ff0: f887 3026 strb.w r3, [r7, #38] @ 0x26 /* Specific case of GigaDevice memory GD25LX512ME whose Instruction mode remains on 8S (8bit commands) */ if (Object->sfdp_private.ManuID == EXTMEM_MANUFACTURER_GIGADEVICE) 8008ff4: 687b ldr r3, [r7, #4] 8008ff6: f893 305d ldrb.w r3, [r3, #93] @ 0x5d 8008ffa: 2bc8 cmp r3, #200 @ 0xc8 8008ffc: d104 bne.n 8009008 { Object->sfdp_private.DriverInfo.SpiPhyLink = PHY_LINK_8S8D8D; 8008ffe: 687b ldr r3, [r7, #4] 8009000: 2208 movs r2, #8 8009002: f883 2064 strb.w r2, [r3, #100] @ 0x64 8009006: e003 b.n 8009010 } else { Object->sfdp_private.DriverInfo.SpiPhyLink = PHY_LINK_8D8D8D; 8009008: 687b ldr r3, [r7, #4] 800900a: 2209 movs r2, #9 800900c: f883 2064 strb.w r2, [r3, #100] @ 0x64 } /* update the physical link */ if (HAL_OK != SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_PHY_LINK, 8009010: 687b ldr r3, [r7, #4] 8009012: f103 0008 add.w r0, r3, #8 &Object->sfdp_private.DriverInfo.SpiPhyLink)) 8009016: 687b ldr r3, [r7, #4] 8009018: 3364 adds r3, #100 @ 0x64 if (HAL_OK != SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_PHY_LINK, 800901a: 461a mov r2, r3 800901c: 2100 movs r1, #0 800901e: f7fe fc23 bl 8007868 8009022: 4603 mov r3, r0 8009024: 2b00 cmp r3, #0 8009026: d003 beq.n 8009030 { retr = EXTMEM_SFDP_ERROR_DRIVER; 8009028: 230c movs r3, #12 800902a: f887 3027 strb.w r3, [r7, #39] @ 0x27 goto error; 800902e: e2d4 b.n 80095da } if (Object->sfdp_private.Sfdp_AccessProtocol == 0xFDu) 8009030: 687b ldr r3, [r7, #4] 8009032: f893 309d ldrb.w r3, [r3, #157] @ 0x9d 8009036: 2bfd cmp r3, #253 @ 0xfd 8009038: d109 bne.n 800904e { /* set 20 wait state */ dummyCycles = 20; 800903a: 2314 movs r3, #20 800903c: 617b str r3, [r7, #20] (void)SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_DUMMY_CYCLES, (void *)&dummyCycles); 800903e: 687b ldr r3, [r7, #4] 8009040: 3308 adds r3, #8 8009042: f107 0214 add.w r2, r7, #20 8009046: 2101 movs r1, #1 8009048: 4618 mov r0, r3 800904a: f7fe fc0d bl 8007868 } if (Object->sfdp_private.Sfdp_AccessProtocol == 0xFEu) 800904e: 687b ldr r3, [r7, #4] 8009050: f893 309d ldrb.w r3, [r3, #157] @ 0x9d 8009054: 2bfe cmp r3, #254 @ 0xfe 8009056: d109 bne.n 800906c { /* set 8 wait state */ dummyCycles = 8; 8009058: 2308 movs r3, #8 800905a: 617b str r3, [r7, #20] (void)SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_DUMMY_CYCLES, (void *)&dummyCycles); 800905c: 687b ldr r3, [r7, #4] 800905e: 3308 adds r3, #8 8009060: f107 0214 add.w r2, r7, #20 8009064: 2101 movs r1, #1 8009066: 4618 mov r0, r3 8009068: f7fe fbfe bl 8007868 /* an error occurs when trying to switch the mode */ /* when continue the process and check if another mode could be targeted */ } } if ((0u != (Object->sfdp_private.Sfdp_table_mask & (uint32_t)SFDP_PARAMID_BASIC_SPIPROTOCOL)) && 800906c: 687b ldr r3, [r7, #4] 800906e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8009072: f003 0308 and.w r3, r3, #8 8009076: 2b00 cmp r3, #0 8009078: d019 beq.n 80090ae (JEDEC_Basic.size > 16u)) 800907a: 4b34 ldr r3, [pc, #208] @ (800914c ) 800907c: 681b ldr r3, [r3, #0] if ((0u != (Object->sfdp_private.Sfdp_table_mask & (uint32_t)SFDP_PARAMID_BASIC_SPIPROTOCOL)) && 800907e: 2b10 cmp r3, #16 8009080: d915 bls.n 80090ae /* 0b00 Command Extension is the same as the Command. (Command / Command Extension has the same value for the whole clock period.)*/ /* 0b01 Command Extension is the inverse of the Command. Command Extension acts as a confirmation of the Command */ /* 0b11 Command and Command Extension forms a 16-bit command word */ if (JEDEC_Basic.Params.Param_DWORD.D18.OctalDTRCommandExtension > 1u) 8009082: 4b32 ldr r3, [pc, #200] @ (800914c ) 8009084: f893 304b ldrb.w r3, [r3, #75] @ 0x4b 8009088: f3c3 1341 ubfx r3, r3, #5, #2 800908c: b2db uxtb r3, r3 800908e: 2b01 cmp r3, #1 8009090: d903 bls.n 800909a { retr = EXTMEM_SFDP_ERROR_NOTYETHANDLED; 8009092: 230f movs r3, #15 8009094: f887 3027 strb.w r3, [r7, #39] @ 0x27 goto error; 8009098: e29f b.n 80095da } SAL_XSPI_SET_COMMANDEXTENSION(Object->sfdp_private.SALObject, 800909a: 4b2c ldr r3, [pc, #176] @ (800914c ) 800909c: f893 304b ldrb.w r3, [r3, #75] @ 0x4b 80090a0: f3c3 1341 ubfx r3, r3, #5, #2 80090a4: b2db uxtb r3, r3 80090a6: 461a mov r2, r3 80090a8: 687b ldr r3, [r7, #4] 80090aa: f883 2058 strb.w r2, [r3, #88] @ 0x58 (uint8_t)JEDEC_Basic.Params.Param_DWORD.D18.OctalDTRCommandExtension); } /* In octal mode, check if JEDEC xSPI (Profile 1.0) Parameter Table is provided, and if yes, check value of SFDP command dummy cycles in 1st DWORD */ if ((Object->sfdp_private.Sfdp_table_mask & (uint32_t)SFDP_PARAMID_XSPI_V1_0) 80090ae: 687b ldr r3, [r7, #4] 80090b0: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 80090b4: f003 0380 and.w r3, r3, #128 @ 0x80 80090b8: 2b00 cmp r3, #0 80090ba: d00a beq.n 80090d2 == (uint32_t)SFDP_PARAMID_XSPI_V1_0) { if (JEDEC_XSPI10.Param_DWORD.D1.SFDPCommand_8D8D8DMode_DummyCycles == 1U) 80090bc: 4b24 ldr r3, [pc, #144] @ (8009150 ) 80090be: 78db ldrb r3, [r3, #3] 80090c0: f003 0340 and.w r3, r3, #64 @ 0x40 80090c4: b2db uxtb r3, r3 80090c6: 2b00 cmp r3, #0 80090c8: d003 beq.n 80090d2 { SAL_XSPI_SET_SFDPDUMMYCYLE(Object->sfdp_private.SALObject, EXTMEM_READ_SFDP_NB_DUMMY_CYCLES_OPI); 80090ca: 687b ldr r3, [r7, #4] 80090cc: 2214 movs r2, #20 80090ce: f883 2059 strb.w r2, [r3, #89] @ 0x59 } } } /* Check WIP flag with new access mode */ if (EXTMEM_DRIVER_NOR_SFDP_OK != driver_check_FlagBUSY(Object, 100u)) 80090d2: 2164 movs r1, #100 @ 0x64 80090d4: 6878 ldr r0, [r7, #4] 80090d6: f000 fa95 bl 8009604 80090da: 4603 mov r3, r0 80090dc: 2b00 cmp r3, #0 80090de: d003 beq.n 80090e8 { retr = EXTMEM_SFDP_ERROR_DRIVER; 80090e0: 230c movs r3, #12 80090e2: f887 3027 strb.w r3, [r7, #39] @ 0x27 goto error; 80090e6: e278 b.n 80095da } if ((Object->sfdp_private.Sfdp_table_mask & (uint32_t)SFDP_PARAMID_4BYTE_ADDRESS_INSTRUCTION) == 80090e8: 687b ldr r3, [r7, #4] 80090ea: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 80090ee: f003 0340 and.w r3, r3, #64 @ 0x40 80090f2: 2b00 cmp r3, #0 80090f4: f000 8182 beq.w 80093fc (uint32_t)SFDP_PARAMID_4BYTE_ADDRESS_INSTRUCTION) { if (0u == flag4byteAddress) 80090f8: f897 3026 ldrb.w r3, [r7, #38] @ 0x26 80090fc: 2b00 cmp r3, #0 80090fe: f040 8101 bne.w 8009304 { /* xxxx_xxx1b: issue instruction B7h (preceding write enable not required) */ if (0x01u == (JEDEC_Basic.Params.Param_DWORD.D16.Enter4ByteAddressing & 0x01u)) 8009102: 4b12 ldr r3, [pc, #72] @ (800914c ) 8009104: f893 3043 ldrb.w r3, [r3, #67] @ 0x43 8009108: f003 0301 and.w r3, r3, #1 800910c: 2b00 cmp r3, #0 800910e: d021 beq.n 8009154 { /* send command to enter 4-bytes Address mode */ if (HAL_OK != SAL_XSPI_CommandSendData(&Object->sfdp_private.SALObject, 0xB7, NULL, 0)) 8009110: 687b ldr r3, [r7, #4] 8009112: f103 0008 add.w r0, r3, #8 8009116: 2300 movs r3, #0 8009118: 2200 movs r2, #0 800911a: 21b7 movs r1, #183 @ 0xb7 800911c: f7fe fe87 bl 8007e2e 8009120: 4603 mov r3, r0 8009122: 2b00 cmp r3, #0 8009124: d003 beq.n 800912e { retr = EXTMEM_SFDP_ERROR_DRIVER; 8009126: 230c movs r3, #12 8009128: f887 3027 strb.w r3, [r7, #39] @ 0x27 goto error; 800912c: e255 b.n 80095da } /* Set 4-Byte addressing on PHY side */ if (HAL_OK != SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_ADDRESS_4BYTES, NULL)) 800912e: 687b ldr r3, [r7, #4] 8009130: 3308 adds r3, #8 8009132: 2200 movs r2, #0 8009134: 2102 movs r1, #2 8009136: 4618 mov r0, r3 8009138: f7fe fb96 bl 8007868 800913c: 4603 mov r3, r0 800913e: 2b00 cmp r3, #0 8009140: d072 beq.n 8009228 { retr = EXTMEM_SFDP_ERROR_DRIVER; 8009142: 230c movs r3, #12 8009144: f887 3027 strb.w r3, [r7, #39] @ 0x27 goto error; 8009148: e247 b.n 80095da 800914a: bf00 nop 800914c: 24000340 .word 0x24000340 8009150: 240003a8 .word 0x240003a8 } /* flag4byteAddress = 1u; this setting is not needed because variable is no more used */ } /* xxxx_xx1xb: issue write enable instruction 06h, then issue instruction B7h */ else if (0x2u == (JEDEC_Basic.Params.Param_DWORD.D16.Enter4ByteAddressing & 0x2u)) 8009154: 4b81 ldr r3, [pc, #516] @ (800935c ) 8009156: f893 3043 ldrb.w r3, [r3, #67] @ 0x43 800915a: f003 0302 and.w r3, r3, #2 800915e: 2b00 cmp r3, #0 8009160: d050 beq.n 8009204 { /* send command to write enable */ if (HAL_OK != SAL_XSPI_CommandSendData(&Object->sfdp_private.SALObject, 8009162: 687b ldr r3, [r7, #4] 8009164: f103 0008 add.w r0, r3, #8 8009168: 687b ldr r3, [r7, #4] 800916a: f893 1070 ldrb.w r1, [r3, #112] @ 0x70 800916e: 2300 movs r3, #0 8009170: 2200 movs r2, #0 8009172: f7fe fe5c bl 8007e2e 8009176: 4603 mov r3, r0 8009178: 2b00 cmp r3, #0 800917a: d003 beq.n 8009184 Object->sfdp_private.DriverInfo.WriteWELCommand, NULL, 0u)) { retr = EXTMEM_SFDP_ERROR_DRIVER; 800917c: 230c movs r3, #12 800917e: f887 3027 strb.w r3, [r7, #39] @ 0x27 goto error; 8009182: e22a b.n 80095da } /* control the write enable */ if (HAL_OK != SAL_XSPI_CheckStatusRegister(&Object->sfdp_private.SALObject, 8009184: 687b ldr r3, [r7, #4] 8009186: f103 0008 add.w r0, r3, #8 800918a: 687b ldr r3, [r7, #4] 800918c: f893 1071 ldrb.w r1, [r3, #113] @ 0x71 Object->sfdp_private.DriverInfo.ReadWELCommand, Object->sfdp_private.DriverInfo.WELAddress, 8009190: 687b ldr r3, [r7, #4] 8009192: f893 3074 ldrb.w r3, [r3, #116] @ 0x74 if (HAL_OK != SAL_XSPI_CheckStatusRegister(&Object->sfdp_private.SALObject, 8009196: 461e mov r6, r3 (((Object->sfdp_private.DriverInfo.WELBusyPolarity == 0u) ? 1u : 0u) 8009198: 687b ldr r3, [r7, #4] 800919a: f893 3073 ldrb.w r3, [r3, #115] @ 0x73 800919e: 2b00 cmp r3, #0 80091a0: d101 bne.n 80091a6 80091a2: 2301 movs r3, #1 80091a4: e000 b.n 80091a8 80091a6: 2300 movs r3, #0 << Object->sfdp_private.DriverInfo.WELPosition), 80091a8: 687a ldr r2, [r7, #4] 80091aa: f892 2072 ldrb.w r2, [r2, #114] @ 0x72 80091ae: 4093 lsls r3, r2 if (HAL_OK != SAL_XSPI_CheckStatusRegister(&Object->sfdp_private.SALObject, 80091b0: b2dc uxtb r4, r3 1u << Object->sfdp_private.DriverInfo.WELPosition, 80091b2: 687b ldr r3, [r7, #4] 80091b4: f893 3072 ldrb.w r3, [r3, #114] @ 0x72 80091b8: 461a mov r2, r3 80091ba: 2301 movs r3, #1 80091bc: 4093 lsls r3, r2 if (HAL_OK != SAL_XSPI_CheckStatusRegister(&Object->sfdp_private.SALObject, 80091be: b2db uxtb r3, r3 80091c0: 687a ldr r2, [r7, #4] 80091c2: f892 205d ldrb.w r2, [r2, #93] @ 0x5d 80091c6: f44f 757a mov.w r5, #1000 @ 0x3e8 80091ca: 9502 str r5, [sp, #8] 80091cc: 9201 str r2, [sp, #4] 80091ce: 9300 str r3, [sp, #0] 80091d0: 4623 mov r3, r4 80091d2: 4632 mov r2, r6 80091d4: f7fe ff38 bl 8008048 80091d8: 4603 mov r3, r0 80091da: 2b00 cmp r3, #0 80091dc: d003 beq.n 80091e6 Object->sfdp_private.ManuID, 1000)) { retr = EXTMEM_SFDP_ERROR_DRIVER; 80091de: 230c movs r3, #12 80091e0: f887 3027 strb.w r3, [r7, #39] @ 0x27 goto error; 80091e4: e1f9 b.n 80095da } /* send command to enter 4-bytes Address mode */ if (HAL_OK != SAL_XSPI_CommandSendData(&Object->sfdp_private.SALObject, 0xB7, NULL, 0u)) 80091e6: 687b ldr r3, [r7, #4] 80091e8: f103 0008 add.w r0, r3, #8 80091ec: 2300 movs r3, #0 80091ee: 2200 movs r2, #0 80091f0: 21b7 movs r1, #183 @ 0xb7 80091f2: f7fe fe1c bl 8007e2e 80091f6: 4603 mov r3, r0 80091f8: 2b00 cmp r3, #0 80091fa: d015 beq.n 8009228 { retr = EXTMEM_SFDP_ERROR_DRIVER; 80091fc: 230c movs r3, #12 80091fe: f887 3027 strb.w r3, [r7, #39] @ 0x27 goto error; 8009202: e1ea b.n 80095da } } /* x1xx_xxxxb: Always operates in 4-Byte address mode */ else if (0x40u == (JEDEC_Basic.Params.Param_DWORD.D16.Enter4ByteAddressing & 0x40u)) 8009204: 4b55 ldr r3, [pc, #340] @ (800935c ) 8009206: f893 3043 ldrb.w r3, [r3, #67] @ 0x43 800920a: f003 0340 and.w r3, r3, #64 @ 0x40 800920e: 2b00 cmp r3, #0 8009210: d10a bne.n 8009228 /* nothing to do */ /* flag4byteAddress = 1u; this setting is not needed because variable is no more used */ } /* xx1x_xxxxb: Supports dedicated 4-Byte address instruction set. Consult vendor data sheet for the instruction set definition.*/ else if (0x20u == (JEDEC_Basic.Params.Param_DWORD.D16.Enter4ByteAddressing & 0x20u)) 8009212: 4b52 ldr r3, [pc, #328] @ (800935c ) 8009214: f893 3043 ldrb.w r3, [r3, #67] @ 0x43 8009218: f003 0320 and.w r3, r3, #32 800921c: 2b00 cmp r3, #0 800921e: d103 bne.n 8009228 Read instruction is B5h. Bit[0] controls address mode [0=3-Byte;1=4-Byte]. Write configuration register instruction is B1h, data length is 2 bytes. */ else { retr = EXTMEM_SFDP_ERROR_NOTYETHANDLED; 8009220: 230f movs r3, #15 8009222: f887 3027 strb.w r3, [r7, #39] @ 0x27 goto error; 8009226: e1d8 b.n 80095da } /* Set 4 bytes addressing on PHY side */ if (HAL_OK != SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_ADDRESS_4BYTES, NULL)) 8009228: 687b ldr r3, [r7, #4] 800922a: 3308 adds r3, #8 800922c: 2200 movs r2, #0 800922e: 2102 movs r1, #2 8009230: 4618 mov r0, r3 8009232: f7fe fb19 bl 8007868 8009236: 4603 mov r3, r0 8009238: 2b00 cmp r3, #0 800923a: d003 beq.n 8009244 { retr = EXTMEM_SFDP_ERROR_DRIVER; 800923c: 230c movs r3, #12 800923e: f887 3027 strb.w r3, [r7, #39] @ 0x27 goto error; 8009242: e1ca b.n 80095da } /* Set the read and program instruction for 4 bytes Address */ if (PHY_LINK_1S1S1S == Object->sfdp_private.DriverInfo.SpiPhyLink) 8009244: 687b ldr r3, [r7, #4] 8009246: f893 3064 ldrb.w r3, [r3, #100] @ 0x64 800924a: 2b00 cmp r3, #0 800924c: d12a bne.n 80092a4 { if (0u != JEDEC_Address4Bytes.Param_DWORD.D1.Support_1S1S1S_ReadCommand) 800924e: 4b44 ldr r3, [pc, #272] @ (8009360 ) 8009250: 781b ldrb r3, [r3, #0] 8009252: f003 0301 and.w r3, r3, #1 8009256: b2db uxtb r3, r3 8009258: 2b00 cmp r3, #0 800925a: d003 beq.n 8009264 { Object->sfdp_private.DriverInfo.ReadInstruction = 0x13U; 800925c: 687b ldr r3, [r7, #4] 800925e: 2213 movs r2, #19 8009260: f883 2076 strb.w r2, [r3, #118] @ 0x76 } if (0u != JEDEC_Address4Bytes.Param_DWORD.D1.Support_1S1S1S_PageProgramCommand) 8009264: 4b3e ldr r3, [pc, #248] @ (8009360 ) 8009266: 781b ldrb r3, [r3, #0] 8009268: f003 0340 and.w r3, r3, #64 @ 0x40 800926c: b2db uxtb r3, r3 800926e: 2b00 cmp r3, #0 8009270: d003 beq.n 800927a { Object->sfdp_private.DriverInfo.PageProgramInstruction = 0x12u; 8009272: 687b ldr r3, [r7, #4] 8009274: 2212 movs r2, #18 8009276: f883 2075 strb.w r2, [r3, #117] @ 0x75 } if (0u != JEDEC_Address4Bytes.Param_DWORD.D1.Support_1S1S1S_FastReadCommand) 800927a: 4b39 ldr r3, [pc, #228] @ (8009360 ) 800927c: 781b ldrb r3, [r3, #0] 800927e: f003 0302 and.w r3, r3, #2 8009282: b2db uxtb r3, r3 8009284: 2b00 cmp r3, #0 8009286: d00d beq.n 80092a4 { Object->sfdp_private.DriverInfo.ReadInstruction = 0x0Cu; 8009288: 687b ldr r3, [r7, #4] 800928a: 220c movs r2, #12 800928c: f883 2076 strb.w r2, [r3, #118] @ 0x76 dummyCycles = EXTMEM_FAST_READ_NB_DUMMY_CYCLES_DEFAULT; 8009290: 2308 movs r3, #8 8009292: 617b str r3, [r7, #20] (void)SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_DUMMY_CYCLES, (void *)&dummyCycles); 8009294: 687b ldr r3, [r7, #4] 8009296: 3308 adds r3, #8 8009298: f107 0214 add.w r2, r7, #20 800929c: 2101 movs r1, #1 800929e: 4618 mov r0, r3 80092a0: f7fe fae2 bl 8007868 } } if (PHY_LINK_1S1S2S == Object->sfdp_private.DriverInfo.SpiPhyLink) 80092a4: 687b ldr r3, [r7, #4] 80092a6: f893 3064 ldrb.w r3, [r3, #100] @ 0x64 80092aa: 2b01 cmp r3, #1 80092ac: d10a bne.n 80092c4 { if (0u != JEDEC_Address4Bytes.Param_DWORD.D1.Support_1S1S2S_FastReadCommand) 80092ae: 4b2c ldr r3, [pc, #176] @ (8009360 ) 80092b0: 781b ldrb r3, [r3, #0] 80092b2: f003 0304 and.w r3, r3, #4 80092b6: b2db uxtb r3, r3 80092b8: 2b00 cmp r3, #0 80092ba: d003 beq.n 80092c4 { Object->sfdp_private.DriverInfo.ReadInstruction = 0x3CU; 80092bc: 687b ldr r3, [r7, #4] 80092be: 223c movs r2, #60 @ 0x3c 80092c0: f883 2076 strb.w r2, [r3, #118] @ 0x76 } } if (PHY_LINK_1S2S2S == Object->sfdp_private.DriverInfo.SpiPhyLink) 80092c4: 687b ldr r3, [r7, #4] 80092c6: f893 3064 ldrb.w r3, [r3, #100] @ 0x64 80092ca: 2b02 cmp r3, #2 80092cc: d10a bne.n 80092e4 { if (0u != JEDEC_Address4Bytes.Param_DWORD.D1.Support_1S2S2S_FastReadCommand) 80092ce: 4b24 ldr r3, [pc, #144] @ (8009360 ) 80092d0: 781b ldrb r3, [r3, #0] 80092d2: f003 0308 and.w r3, r3, #8 80092d6: b2db uxtb r3, r3 80092d8: 2b00 cmp r3, #0 80092da: d003 beq.n 80092e4 { Object->sfdp_private.DriverInfo.ReadInstruction = 0xBCU; 80092dc: 687b ldr r3, [r7, #4] 80092de: 22bc movs r2, #188 @ 0xbc 80092e0: f883 2076 strb.w r2, [r3, #118] @ 0x76 } } if (PHY_LINK_1S1D1D == Object->sfdp_private.DriverInfo.SpiPhyLink) 80092e4: 687b ldr r3, [r7, #4] 80092e6: f893 3064 ldrb.w r3, [r3, #100] @ 0x64 80092ea: 2b03 cmp r3, #3 80092ec: d10a bne.n 8009304 { if (0u != JEDEC_Address4Bytes.Param_DWORD.D1.Support_1S1D1D_DTRReadCommand) 80092ee: 4b1c ldr r3, [pc, #112] @ (8009360 ) 80092f0: 785b ldrb r3, [r3, #1] 80092f2: f003 0320 and.w r3, r3, #32 80092f6: b2db uxtb r3, r3 80092f8: 2b00 cmp r3, #0 80092fa: d003 beq.n 8009304 { Object->sfdp_private.DriverInfo.ReadInstruction = 0x0EU; 80092fc: 687b ldr r3, [r7, #4] 80092fe: 220e movs r2, #14 8009300: f883 2076 strb.w r2, [r3, #118] @ 0x76 } } } if ((EXTMEM_LINK_CONFIG_8LINES == Object->sfdp_private.Config) 8009304: 687b ldr r3, [r7, #4] 8009306: f893 305c ldrb.w r3, [r3, #92] @ 0x5c 800930a: 2b03 cmp r3, #3 800930c: d132 bne.n 8009374 && (PHY_LINK_1S1S1S == Object->sfdp_private.DriverInfo.SpiPhyLink)) 800930e: 687b ldr r3, [r7, #4] 8009310: f893 3064 ldrb.w r3, [r3, #100] @ 0x64 8009314: 2b00 cmp r3, #0 8009316: d12d bne.n 8009374 { /* check if we can switch to 1S8S8S */ if ((0u != JEDEC_Address4Bytes.Param_DWORD.D1.Support_1S8S8S_FastReadCommand) 8009318: 4b11 ldr r3, [pc, #68] @ (8009360 ) 800931a: 789b ldrb r3, [r3, #2] 800931c: f003 0320 and.w r3, r3, #32 8009320: b2db uxtb r3, r3 8009322: 2b00 cmp r3, #0 8009324: d026 beq.n 8009374 && (0u != JEDEC_Address4Bytes.Param_DWORD.D1.Support_1S8S8S_PageProgramCommand)) 8009326: 4b0e ldr r3, [pc, #56] @ (8009360 ) 8009328: 78db ldrb r3, [r3, #3] 800932a: f003 0301 and.w r3, r3, #1 800932e: b2db uxtb r3, r3 8009330: 2b00 cmp r3, #0 8009332: d01f beq.n 8009374 { /* Patch Micron write command 0x81 @0x0 0xE7 */ Object->sfdp_private.DriverInfo.SpiPhyLink = PHY_LINK_1S8S8S; 8009334: 687b ldr r3, [r7, #4] 8009336: 2207 movs r2, #7 8009338: f883 2064 strb.w r2, [r3, #100] @ 0x64 if (HAL_OK != SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_PHY_LINK, 800933c: 687b ldr r3, [r7, #4] 800933e: f103 0008 add.w r0, r3, #8 &Object->sfdp_private.DriverInfo.SpiPhyLink)) 8009342: 687b ldr r3, [r7, #4] 8009344: 3364 adds r3, #100 @ 0x64 if (HAL_OK != SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_PHY_LINK, 8009346: 461a mov r2, r3 8009348: 2100 movs r1, #0 800934a: f7fe fa8d bl 8007868 800934e: 4603 mov r3, r0 8009350: 2b00 cmp r3, #0 8009352: d007 beq.n 8009364 { retr = EXTMEM_SFDP_ERROR_DRIVER; 8009354: 230c movs r3, #12 8009356: f887 3027 strb.w r3, [r7, #39] @ 0x27 goto error; 800935a: e13e b.n 80095da 800935c: 24000340 .word 0x24000340 8009360: 240003a0 .word 0x240003a0 } Object->sfdp_private.DriverInfo.ReadInstruction = 0xCC; 8009364: 687b ldr r3, [r7, #4] 8009366: 22cc movs r2, #204 @ 0xcc 8009368: f883 2076 strb.w r2, [r3, #118] @ 0x76 Object->sfdp_private.DriverInfo.PageProgramInstruction = 0x8E; 800936c: 687b ldr r3, [r7, #4] 800936e: 228e movs r2, #142 @ 0x8e 8009370: f883 2075 strb.w r2, [r3, #117] @ 0x75 /* need to be study more; it seems that Macronix used it to define the command maybe because only one mode is supported in their case */ if (Object->sfdp_private.DriverInfo.SpiPhyLink == PHY_LINK_8S8D8D) 8009374: 687b ldr r3, [r7, #4] 8009376: f893 3064 ldrb.w r3, [r3, #100] @ 0x64 800937a: 2b08 cmp r3, #8 800937c: d12a bne.n 80093d4 { if (0u != JEDEC_Address4Bytes.Param_DWORD.D1.Support_1S8S8S_PageProgramCommand) 800937e: 4b9a ldr r3, [pc, #616] @ (80095e8 ) 8009380: 78db ldrb r3, [r3, #3] 8009382: f003 0301 and.w r3, r3, #1 8009386: b2db uxtb r3, r3 8009388: 2b00 cmp r3, #0 800938a: d003 beq.n 8009394 { Object->sfdp_private.DriverInfo.PageProgramInstruction = 0x02u; 800938c: 687b ldr r3, [r7, #4] 800938e: 2202 movs r2, #2 8009390: f883 2075 strb.w r2, [r3, #117] @ 0x75 } if (0u != JEDEC_Address4Bytes.Param_DWORD.D1.Support_1S8S8S_FastReadCommand) 8009394: 4b94 ldr r3, [pc, #592] @ (80095e8 ) 8009396: 789b ldrb r3, [r3, #2] 8009398: f003 0320 and.w r3, r3, #32 800939c: b2db uxtb r3, r3 800939e: 2b00 cmp r3, #0 80093a0: d00d beq.n 80093be { Object->sfdp_private.DriverInfo.ReadInstruction = 0xCCu; 80093a2: 687b ldr r3, [r7, #4] 80093a4: 22cc movs r2, #204 @ 0xcc 80093a6: f883 2076 strb.w r2, [r3, #118] @ 0x76 dummyCycles = EXTMEM_FAST_READ_NB_DUMMY_CYCLES_DEFAULT; 80093aa: 2308 movs r3, #8 80093ac: 617b str r3, [r7, #20] (void)SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_DUMMY_CYCLES, (void *)&dummyCycles); 80093ae: 687b ldr r3, [r7, #4] 80093b0: 3308 adds r3, #8 80093b2: f107 0214 add.w r2, r7, #20 80093b6: 2101 movs r1, #1 80093b8: 4618 mov r0, r3 80093ba: f7fe fa55 bl 8007868 } if (0u != JEDEC_Address4Bytes.Param_DWORD.D1.Support_1S8D8D_DTRReadCommand) 80093be: 4b8a ldr r3, [pc, #552] @ (80095e8 ) 80093c0: 789b ldrb r3, [r3, #2] 80093c2: f003 0340 and.w r3, r3, #64 @ 0x40 80093c6: b2db uxtb r3, r3 80093c8: 2b00 cmp r3, #0 80093ca: d003 beq.n 80093d4 { Object->sfdp_private.DriverInfo.ReadInstruction = 0xFDu; 80093cc: 687b ldr r3, [r7, #4] 80093ce: 22fd movs r2, #253 @ 0xfd 80093d0: f883 2076 strb.w r2, [r3, #118] @ 0x76 } } Object->sfdp_private.DriverInfo.EraseType1Command = (uint8_t)JEDEC_Address4Bytes.Param_DWORD.D2.InstructionEraseType1; 80093d4: 4b84 ldr r3, [pc, #528] @ (80095e8 ) 80093d6: 791a ldrb r2, [r3, #4] Object->sfdp_private.DriverInfo.EraseType1Command = 80093d8: 687b ldr r3, [r7, #4] 80093da: f883 2078 strb.w r2, [r3, #120] @ 0x78 Object->sfdp_private.DriverInfo.EraseType2Command = (uint8_t)JEDEC_Address4Bytes.Param_DWORD.D2.InstructionEraseType2; 80093de: 4b82 ldr r3, [pc, #520] @ (80095e8 ) 80093e0: 795a ldrb r2, [r3, #5] Object->sfdp_private.DriverInfo.EraseType2Command = 80093e2: 687b ldr r3, [r7, #4] 80093e4: f883 207a strb.w r2, [r3, #122] @ 0x7a Object->sfdp_private.DriverInfo.EraseType3Command = (uint8_t)JEDEC_Address4Bytes.Param_DWORD.D2.InstructionEraseType3; 80093e8: 4b7f ldr r3, [pc, #508] @ (80095e8 ) 80093ea: 799a ldrb r2, [r3, #6] Object->sfdp_private.DriverInfo.EraseType3Command = 80093ec: 687b ldr r3, [r7, #4] 80093ee: f883 207c strb.w r2, [r3, #124] @ 0x7c Object->sfdp_private.DriverInfo.EraseType4Command = (uint8_t)JEDEC_Address4Bytes.Param_DWORD.D2.InstructionEraseType4; 80093f2: 4b7d ldr r3, [pc, #500] @ (80095e8 ) 80093f4: 79da ldrb r2, [r3, #7] Object->sfdp_private.DriverInfo.EraseType4Command = 80093f6: 687b ldr r3, [r7, #4] 80093f8: f883 207e strb.w r2, [r3, #126] @ 0x7e } if (((uint32_t)SFDP_PARAMID_XSPI_V1_0 == (Object->sfdp_private.Sfdp_table_mask & (uint32_t)SFDP_PARAMID_XSPI_V1_0)) 80093fc: 687b ldr r3, [r7, #4] 80093fe: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8009402: f003 0380 and.w r3, r3, #128 @ 0x80 8009406: 2b00 cmp r3, #0 8009408: f000 80e6 beq.w 80095d8 && ((PHY_LINK_8D8D8D == Object->sfdp_private.DriverInfo.SpiPhyLink) 800940c: 687b ldr r3, [r7, #4] 800940e: f893 3064 ldrb.w r3, [r3, #100] @ 0x64 && 8009412: 2b09 cmp r3, #9 8009414: d005 beq.n 8009422 || (PHY_LINK_8S8D8D == Object->sfdp_private.DriverInfo.SpiPhyLink))) 8009416: 687b ldr r3, [r7, #4] 8009418: f893 3064 ldrb.w r3, [r3, #100] @ 0x64 800941c: 2b08 cmp r3, #8 800941e: f040 80db bne.w 80095d8 { uint32_t ClockOut = 0u; 8009422: 2300 movs r3, #0 8009424: 60fb str r3, [r7, #12] uint32_t MaxFreqMhz; /* Read command */ if (0u != JEDEC_XSPI10.Param_DWORD.D1.ReadFastCommand) 8009426: 4b71 ldr r3, [pc, #452] @ (80095ec ) 8009428: 785b ldrb r3, [r3, #1] 800942a: 2b00 cmp r3, #0 800942c: d004 beq.n 8009438 { Object->sfdp_private.DriverInfo.ReadInstruction = (uint8_t)JEDEC_XSPI10.Param_DWORD.D1.ReadFastCommand; 800942e: 4b6f ldr r3, [pc, #444] @ (80095ec ) 8009430: 785a ldrb r2, [r3, #1] 8009432: 687b ldr r3, [r7, #4] 8009434: f883 2076 strb.w r2, [r3, #118] @ 0x76 } if (JEDEC_XSPI10.Param_DWORD.D6._8D8D8DDefaultPOR_DummyCycle != 0u) 8009438: 4b6c ldr r3, [pc, #432] @ (80095ec ) 800943a: 7d1b ldrb r3, [r3, #20] 800943c: f003 031f and.w r3, r3, #31 8009440: b2db uxtb r3, r3 8009442: 2b00 cmp r3, #0 8009444: d00d beq.n 8009462 { /* Set the default dummy cycle of this mode */ dummyCycles = JEDEC_XSPI10.Param_DWORD.D6._8D8D8DDefaultPOR_DummyCycle; 8009446: 4b69 ldr r3, [pc, #420] @ (80095ec ) 8009448: 7d1b ldrb r3, [r3, #20] 800944a: f3c3 0304 ubfx r3, r3, #0, #5 800944e: b2db uxtb r3, r3 8009450: 617b str r3, [r7, #20] (void)SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_DUMMY_CYCLES, (void *)&dummyCycles); 8009452: 687b ldr r3, [r7, #4] 8009454: 3308 adds r3, #8 8009456: f107 0214 add.w r2, r7, #20 800945a: 2101 movs r1, #1 800945c: 4618 mov r0, r3 800945e: f7fe fa03 bl 8007868 } /* Adapt the memory interface frequency according to its capabilities */ MaxFreqMhz = sfdp_getfrequencevalue(JEDEC_Basic.Params.Param_DWORD.D20._8D8D8D_MaximumSpeedWithStrobe); 8009462: 4b63 ldr r3, [pc, #396] @ (80095f0 ) 8009464: f893 3053 ldrb.w r3, [r3, #83] @ 0x53 8009468: f3c3 1303 ubfx r3, r3, #4, #4 800946c: b2db uxtb r3, r3 800946e: 4618 mov r0, r3 8009470: f000 f906 bl 8009680 8009474: 61f8 str r0, [r7, #28] if (MaxFreqMhz > Object->sfdp_private.DriverInfo.ClockIn) 8009476: 687b ldr r3, [r7, #4] 8009478: 6e9b ldr r3, [r3, #104] @ 0x68 800947a: 69fa ldr r2, [r7, #28] 800947c: 429a cmp r2, r3 800947e: d902 bls.n 8009486 { /* Adjust the frequency with the ClockIn */ MaxFreqMhz = Object->sfdp_private.DriverInfo.ClockIn; 8009480: 687b ldr r3, [r7, #4] 8009482: 6e9b ldr r3, [r3, #104] @ 0x68 8009484: 61fb str r3, [r7, #28] } /* Adapt the memory interface frequency according to max requested frequency as defined in configuration table. */ if (Object->sfdp_public.MaxFreq != 0) 8009486: 687b ldr r3, [r7, #4] 8009488: 681b ldr r3, [r3, #0] 800948a: 2b00 cmp r3, #0 800948c: d007 beq.n 800949e { if (MaxFreqMhz > Object->sfdp_public.MaxFreq) 800948e: 687b ldr r3, [r7, #4] 8009490: 681b ldr r3, [r3, #0] 8009492: 69fa ldr r2, [r7, #28] 8009494: 429a cmp r2, r3 8009496: d902 bls.n 800949e { /* Adjust the frequency with the max clock frequency defined in configuration table */ MaxFreqMhz = Object->sfdp_public.MaxFreq; 8009498: 687b ldr r3, [r7, #4] 800949a: 681b ldr r3, [r3, #0] 800949c: 61fb str r3, [r7, #28] } } /* Update the clock to be aligned with selected configuration */ if (HAL_OK != SAL_XSPI_SetClock(&Object->sfdp_private.SALObject, Object->sfdp_private.DriverInfo.ClockIn, 800949e: 687b ldr r3, [r7, #4] 80094a0: f103 0008 add.w r0, r3, #8 80094a4: 687b ldr r3, [r7, #4] 80094a6: 6e99 ldr r1, [r3, #104] @ 0x68 80094a8: f107 030c add.w r3, r7, #12 80094ac: 69fa ldr r2, [r7, #28] 80094ae: f7fe f94f bl 8007750 80094b2: 4603 mov r3, r0 80094b4: 2b00 cmp r3, #0 80094b6: d003 beq.n 80094c0 MaxFreqMhz, &ClockOut)) { retr = EXTMEM_SFDP_ERROR_SETCLOCK; 80094b8: 230d movs r3, #13 80094ba: f887 3027 strb.w r3, [r7, #39] @ 0x27 goto error; 80094be: e08c b.n 80095da } *FreqUpdated = 1u; /* Used to indicate that the clock configuration has been updated */ 80094c0: 683b ldr r3, [r7, #0] 80094c2: 2201 movs r2, #1 80094c4: 701a strb r2, [r3, #0] /* get the dummy cycle value according to the real output clock */ if ((ClockOut >= CLOCK_200MHZ) && (JEDEC_XSPI10.Param_DWORD.D4.Operation200Mhz_DummyCycle != 0u)) 80094c6: 68fb ldr r3, [r7, #12] 80094c8: 4a4a ldr r2, [pc, #296] @ (80095f4 ) 80094ca: 4293 cmp r3, r2 80094cc: d913 bls.n 80094f6 80094ce: 4b47 ldr r3, [pc, #284] @ (80095ec ) 80094d0: 899b ldrh r3, [r3, #12] 80094d2: f403 6378 and.w r3, r3, #3968 @ 0xf80 80094d6: b29b uxth r3, r3 80094d8: 2b00 cmp r3, #0 80094da: d00c beq.n 80094f6 { dummyCycles = JEDEC_XSPI10.Param_DWORD.D4.Operation200Mhz_DummyCycle; 80094dc: 4b43 ldr r3, [pc, #268] @ (80095ec ) 80094de: 899b ldrh r3, [r3, #12] 80094e0: f3c3 13c4 ubfx r3, r3, #7, #5 80094e4: b2db uxtb r3, r3 80094e6: 617b str r3, [r7, #20] dummyCyclesValue = JEDEC_XSPI10.Param_DWORD.D4.Operation200Mhz_ConfigPattern; 80094e8: 4b40 ldr r3, [pc, #256] @ (80095ec ) 80094ea: 7b1b ldrb r3, [r3, #12] 80094ec: f3c3 0384 ubfx r3, r3, #2, #5 80094f0: b2db uxtb r3, r3 80094f2: 623b str r3, [r7, #32] 80094f4: e03b b.n 800956e } else if ((ClockOut >= CLOCK_166MHZ) && (JEDEC_XSPI10.Param_DWORD.D5.Operation166Mhz_DummyCycle != 0u)) 80094f6: 68fb ldr r3, [r7, #12] 80094f8: 4a3f ldr r2, [pc, #252] @ (80095f8 ) 80094fa: 4293 cmp r3, r2 80094fc: d913 bls.n 8009526 80094fe: 4b3b ldr r3, [pc, #236] @ (80095ec ) 8009500: 7cdb ldrb r3, [r3, #19] 8009502: f023 0307 bic.w r3, r3, #7 8009506: b2db uxtb r3, r3 8009508: 2b00 cmp r3, #0 800950a: d00c beq.n 8009526 { dummyCycles = JEDEC_XSPI10.Param_DWORD.D5.Operation166Mhz_DummyCycle; 800950c: 4b37 ldr r3, [pc, #220] @ (80095ec ) 800950e: 7cdb ldrb r3, [r3, #19] 8009510: f3c3 03c4 ubfx r3, r3, #3, #5 8009514: b2db uxtb r3, r3 8009516: 617b str r3, [r7, #20] dummyCyclesValue = JEDEC_XSPI10.Param_DWORD.D5.Operation166Mhz_ConfigPattern; 8009518: 4b34 ldr r3, [pc, #208] @ (80095ec ) 800951a: 8a5b ldrh r3, [r3, #18] 800951c: f3c3 1384 ubfx r3, r3, #6, #5 8009520: b2db uxtb r3, r3 8009522: 623b str r3, [r7, #32] 8009524: e023 b.n 800956e } else if ((ClockOut >= CLOCK_133MHZ) && (JEDEC_XSPI10.Param_DWORD.D5.Operation133Mhz_DummyCycle != 0u)) 8009526: 68fb ldr r3, [r7, #12] 8009528: 4a34 ldr r2, [pc, #208] @ (80095fc ) 800952a: 4293 cmp r3, r2 800952c: d913 bls.n 8009556 800952e: 4b2f ldr r3, [pc, #188] @ (80095ec ) 8009530: 7c9b ldrb r3, [r3, #18] 8009532: f003 033e and.w r3, r3, #62 @ 0x3e 8009536: b2db uxtb r3, r3 8009538: 2b00 cmp r3, #0 800953a: d00c beq.n 8009556 { dummyCycles = JEDEC_XSPI10.Param_DWORD.D5.Operation133Mhz_DummyCycle; 800953c: 4b2b ldr r3, [pc, #172] @ (80095ec ) 800953e: 7c9b ldrb r3, [r3, #18] 8009540: f3c3 0344 ubfx r3, r3, #1, #5 8009544: b2db uxtb r3, r3 8009546: 617b str r3, [r7, #20] dummyCyclesValue = JEDEC_XSPI10.Param_DWORD.D5.Operation133Mhz_ConfigPattern; 8009548: 4b28 ldr r3, [pc, #160] @ (80095ec ) 800954a: 691b ldr r3, [r3, #16] 800954c: f3c3 3304 ubfx r3, r3, #12, #5 8009550: b2db uxtb r3, r3 8009552: 623b str r3, [r7, #32] 8009554: e00b b.n 800956e } else /* if (ClockOut =< 100Mhz) */ { dummyCycles = JEDEC_XSPI10.Param_DWORD.D5.Operation100Mhz_DummyCycle; 8009556: 4b25 ldr r3, [pc, #148] @ (80095ec ) 8009558: 8a1b ldrh r3, [r3, #16] 800955a: f3c3 13c4 ubfx r3, r3, #7, #5 800955e: b2db uxtb r3, r3 8009560: 617b str r3, [r7, #20] dummyCyclesValue = JEDEC_XSPI10.Param_DWORD.D5.Operation100Mhz_ConfigPattern; 8009562: 4b22 ldr r3, [pc, #136] @ (80095ec ) 8009564: 7c1b ldrb r3, [r3, #16] 8009566: f3c3 0384 ubfx r3, r3, #2, #5 800956a: b2db uxtb r3, r3 800956c: 623b str r3, [r7, #32] } /* Specific case of GigaDevice memory with wrongly coded SFDP table in JEDEC_SCCR_Map.Param_DWORD.D9 */ if (Object->sfdp_private.ManuID == EXTMEM_MANUFACTURER_GIGADEVICE) 800956e: 687b ldr r3, [r7, #4] 8009570: f893 305d ldrb.w r3, [r3, #93] @ 0x5d 8009574: 2bc8 cmp r3, #200 @ 0xc8 8009576: d10a bne.n 800958e { dummyCycles = 16; 8009578: 2310 movs r3, #16 800957a: 617b str r3, [r7, #20] (void)SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_DUMMY_CYCLES, (void *)&dummyCycles); 800957c: 687b ldr r3, [r7, #4] 800957e: 3308 adds r3, #8 8009580: f107 0214 add.w r2, r7, #20 8009584: 2101 movs r1, #1 8009586: 4618 mov r0, r3 8009588: f7fe f96e bl 8007868 800958c: e025 b.n 80095da } else { /* Write the dummy cycle value in the configuration register using information coming from SCCR Map */ if ((0u != (Object->sfdp_private.Sfdp_table_mask & (uint32_t)SFDP_PARAMID_STATUS_CONTROL_CONFIG_REGISTER_MAP)) 800958e: 687b ldr r3, [r7, #4] 8009590: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8009594: f403 7300 and.w r3, r3, #512 @ 0x200 8009598: 2b00 cmp r3, #0 800959a: d017 beq.n 80095cc && (0u != JEDEC_SCCR_Map.Param_DWORD.D9.BitAvailable)) 800959c: 4b18 ldr r3, [pc, #96] @ (8009600 ) 800959e: f893 3023 ldrb.w r3, [r3, #35] @ 0x23 80095a2: f023 037f bic.w r3, r3, #127 @ 0x7f 80095a6: b2db uxtb r3, r3 80095a8: 2b00 cmp r3, #0 80095aa: d00f beq.n 80095cc { /* Update the frequency with MaxFreqMhz information */ if (sfdp_set_dummycycle(Object, dummyCyclesValue) == EXTMEM_SFDP_OK) 80095ac: 6a39 ldr r1, [r7, #32] 80095ae: 6878 ldr r0, [r7, #4] 80095b0: f000 fa6c bl 8009a8c 80095b4: 4603 mov r3, r0 80095b6: 2b00 cmp r3, #0 80095b8: d10f bne.n 80095da { /* Set the dummy cycle corresponding */ (void)SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_DUMMY_CYCLES, (void *)&dummyCycles); 80095ba: 687b ldr r3, [r7, #4] 80095bc: 3308 adds r3, #8 80095be: f107 0214 add.w r2, r7, #20 80095c2: 2101 movs r1, #1 80095c4: 4618 mov r0, r3 80095c6: f7fe f94f bl 8007868 if (sfdp_set_dummycycle(Object, dummyCyclesValue) == EXTMEM_SFDP_OK) 80095ca: e006 b.n 80095da } } else { retr = EXTMEM_SFDP_ERROR_CONFIGDUMMY; 80095cc: 230e movs r3, #14 80095ce: f887 3027 strb.w r3, [r7, #39] @ 0x27 goto error; 80095d2: e002 b.n 80095da goto error; 80095d4: bf00 nop 80095d6: e000 b.n 80095da } } } error : 80095d8: bf00 nop return retr; 80095da: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 } 80095de: 4618 mov r0, r3 80095e0: 372c adds r7, #44 @ 0x2c 80095e2: 46bd mov sp, r7 80095e4: bdf0 pop {r4, r5, r6, r7, pc} 80095e6: bf00 nop 80095e8: 240003a0 .word 0x240003a0 80095ec: 240003a8 .word 0x240003a8 80095f0: 24000340 .word 0x24000340 80095f4: 0bebc1ff .word 0x0bebc1ff 80095f8: 09e4f57f .word 0x09e4f57f 80095fc: 07ed6b3f .word 0x07ed6b3f 8009600: 240003c0 .word 0x240003c0 08009604 : * @retval EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef Status of the operation: EXTMEM_DRIVER_NOR_SFDP_OK if not busy, * error code otherwise. */ EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef driver_check_FlagBUSY(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *SFDPObject, uint32_t Timeout) { 8009604: b5f0 push {r4, r5, r6, r7, lr} 8009606: b089 sub sp, #36 @ 0x24 8009608: af04 add r7, sp, #16 800960a: 6078 str r0, [r7, #4] 800960c: 6039 str r1, [r7, #0] EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef retr = EXTMEM_DRIVER_NOR_SFDP_ERROR_BUSY; 800960e: 23fb movs r3, #251 @ 0xfb 8009610: 73fb strb r3, [r7, #15] SFDP_DEBUG_STR((uint8_t *)__func__) if (0u != SFDPObject->sfdp_private.DriverInfo.ReadWIPCommand) 8009612: 687b ldr r3, [r7, #4] 8009614: f893 306c ldrb.w r3, [r3, #108] @ 0x6c 8009618: 2b00 cmp r3, #0 800961a: d02b beq.n 8009674 { /* check that the WIP flag is not set */ if (HAL_OK == SAL_XSPI_CheckStatusRegister(&SFDPObject->sfdp_private.SALObject, 800961c: 687b ldr r3, [r7, #4] 800961e: f103 0008 add.w r0, r3, #8 8009622: 687b ldr r3, [r7, #4] 8009624: f893 406c ldrb.w r4, [r3, #108] @ 0x6c SFDPObject->sfdp_private.DriverInfo.ReadWIPCommand, SFDPObject->sfdp_private.DriverInfo.WIPAddress, 8009628: 687b ldr r3, [r7, #4] 800962a: f893 306f ldrb.w r3, [r3, #111] @ 0x6f if (HAL_OK == SAL_XSPI_CheckStatusRegister(&SFDPObject->sfdp_private.SALObject, 800962e: 461e mov r6, r3 SFDPObject->sfdp_private.DriverInfo.WIPBusyPolarity 8009630: 687b ldr r3, [r7, #4] 8009632: f893 306e ldrb.w r3, [r3, #110] @ 0x6e 8009636: 461a mov r2, r3 << SFDPObject->sfdp_private.DriverInfo.WIPPosition, 8009638: 687b ldr r3, [r7, #4] 800963a: f893 306d ldrb.w r3, [r3, #109] @ 0x6d 800963e: fa02 f303 lsl.w r3, r2, r3 if (HAL_OK == SAL_XSPI_CheckStatusRegister(&SFDPObject->sfdp_private.SALObject, 8009642: b2dd uxtb r5, r3 1u << SFDPObject->sfdp_private.DriverInfo.WIPPosition, 8009644: 687b ldr r3, [r7, #4] 8009646: f893 306d ldrb.w r3, [r3, #109] @ 0x6d 800964a: 461a mov r2, r3 800964c: 2301 movs r3, #1 800964e: 4093 lsls r3, r2 if (HAL_OK == SAL_XSPI_CheckStatusRegister(&SFDPObject->sfdp_private.SALObject, 8009650: b2db uxtb r3, r3 8009652: 687a ldr r2, [r7, #4] 8009654: f892 205d ldrb.w r2, [r2, #93] @ 0x5d 8009658: 6839 ldr r1, [r7, #0] 800965a: 9102 str r1, [sp, #8] 800965c: 9201 str r2, [sp, #4] 800965e: 9300 str r3, [sp, #0] 8009660: 462b mov r3, r5 8009662: 4632 mov r2, r6 8009664: 4621 mov r1, r4 8009666: f7fe fcef bl 8008048 800966a: 4603 mov r3, r0 800966c: 2b00 cmp r3, #0 800966e: d101 bne.n 8009674 SFDPObject->sfdp_private.ManuID, Timeout)) { retr = EXTMEM_DRIVER_NOR_SFDP_OK; 8009670: 2300 movs r3, #0 8009672: 73fb strb r3, [r7, #15] } } return retr; 8009674: f997 300f ldrsb.w r3, [r7, #15] } 8009678: 4618 mov r0, r3 800967a: 3714 adds r7, #20 800967c: 46bd mov sp, r7 800967e: bdf0 pop {r4, r5, r6, r7, pc} 08009680 : * @brief Returns the frequency value in Hz corresponding to a bit field. * @param BitField Bit field value from SFDP table. * @return Frequency value in Hz, or 0 if unknown. */ uint32_t sfdp_getfrequencevalue(uint32_t BitField) { 8009680: b4b0 push {r4, r5, r7} 8009682: b08b sub sp, #44 @ 0x2c 8009684: af00 add r7, sp, #0 8009686: 6078 str r0, [r7, #4] const uint16_t freqMhz_table[] = { 0x0, 33, 50, 66, 80, 100, 133, 166, 200, 250, 266, 333, 400 }; 8009688: 4b0e ldr r3, [pc, #56] @ (80096c4 ) 800968a: f107 040c add.w r4, r7, #12 800968e: 461d mov r5, r3 8009690: cd0f ldmia r5!, {r0, r1, r2, r3} 8009692: c40f stmia r4!, {r0, r1, r2, r3} 8009694: e895 0007 ldmia.w r5, {r0, r1, r2} 8009698: c403 stmia r4!, {r0, r1} 800969a: 8022 strh r2, [r4, #0] SFDP_DEBUG_STR(__func__); if (BitField < 0b1010u) 800969c: 687b ldr r3, [r7, #4] 800969e: 2b09 cmp r3, #9 80096a0: d80a bhi.n 80096b8 { return (uint32_t)freqMhz_table[BitField] * 1000000u; 80096a2: 687b ldr r3, [r7, #4] 80096a4: 005b lsls r3, r3, #1 80096a6: 3328 adds r3, #40 @ 0x28 80096a8: 443b add r3, r7 80096aa: f833 3c1c ldrh.w r3, [r3, #-28] 80096ae: 461a mov r2, r3 80096b0: 4b05 ldr r3, [pc, #20] @ (80096c8 ) 80096b2: fb02 f303 mul.w r3, r2, r3 80096b6: e000 b.n 80096ba } return 0; /* the max frequency is unknown */ 80096b8: 2300 movs r3, #0 } 80096ba: 4618 mov r0, r3 80096bc: 372c adds r7, #44 @ 0x2c 80096be: 46bd mov sp, r7 80096c0: bcb0 pop {r4, r5, r7} 80096c2: 4770 bx lr 80096c4: 0800a138 .word 0x0800a138 80096c8: 000f4240 .word 0x000f4240 080096cc : * @param Param_info Pointer to the parameter info structure to be filled. * @return SFDP_StatusTypeDef: EXTMEM_SFDP_OK if successful, error code otherwise. */ SFDP_StatusTypeDef sfdp_get_paraminfo(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object, uint32_t sfdp_address, SFDP_ParameterTable_t *Param_info) { 80096cc: b580 push {r7, lr} 80096ce: b088 sub sp, #32 80096d0: af00 add r7, sp, #0 80096d2: 60f8 str r0, [r7, #12] 80096d4: 60b9 str r1, [r7, #8] 80096d6: 607a str r2, [r7, #4] SFDP_StatusTypeDef retr = EXTMEM_SFDP_OK; 80096d8: 2300 movs r3, #0 80096da: 77fb strb r3, [r7, #31] SFDP_ParameterHeader_t sfdp_param_header = {0}; 80096dc: f107 0314 add.w r3, r7, #20 80096e0: 2200 movs r2, #0 80096e2: 601a str r2, [r3, #0] 80096e4: 605a str r2, [r3, #4] SFDP_DEBUG_STR(__func__); /* send the SFDP command to read the header */ if (HAL_OK != SAL_XSPI_GetSFDP(&Object->sfdp_private.SALObject, sfdp_address, 80096e6: 68fb ldr r3, [r7, #12] 80096e8: f103 0008 add.w r0, r3, #8 80096ec: f107 0214 add.w r2, r7, #20 80096f0: 2308 movs r3, #8 80096f2: 68b9 ldr r1, [r7, #8] 80096f4: f7fe fa0a bl 8007b0c 80096f8: 4603 mov r3, r0 80096fa: 2b00 cmp r3, #0 80096fc: d002 beq.n 8009704 (uint8_t *)&sfdp_param_header, SFDP_PARAM_HEADER_SIZE)) { retr = EXTMEM_SFDP_ERROR_SFDPREAD; 80096fe: 2303 movs r3, #3 8009700: 77fb strb r3, [r7, #31] goto error; 8009702: e0d9 b.n 80098b8 } Param_info->type = SFDP_PARAMID_UNKNOWN; 8009704: 687b ldr r3, [r7, #4] 8009706: 2200 movs r2, #0 8009708: 601a str r2, [r3, #0] Param_info->size = sfdp_param_header.Length ; 800970a: 7dfa ldrb r2, [r7, #23] 800970c: 687b ldr r3, [r7, #4] 800970e: 721a strb r2, [r3, #8] Param_info->address = (((uint32_t)sfdp_param_header.TableAddressPointer[2u] << 16u) 8009710: 7ebb ldrb r3, [r7, #26] 8009712: 041a lsls r2, r3, #16 | ((uint32_t)sfdp_param_header.TableAddressPointer[1u] << 8u) 8009714: 7e7b ldrb r3, [r7, #25] 8009716: 021b lsls r3, r3, #8 8009718: 4313 orrs r3, r2 | ((uint32_t)sfdp_param_header.TableAddressPointer[0u])); 800971a: 7e3a ldrb r2, [r7, #24] 800971c: 431a orrs r2, r3 Param_info->address = (((uint32_t)sfdp_param_header.TableAddressPointer[2u] << 16u) 800971e: 687b ldr r3, [r7, #4] 8009720: 605a str r2, [r3, #4] if ((sfdp_param_header.ID_msb > 0x00u) && (sfdp_param_header.ID_msb < 0x80u)) 8009722: 7efb ldrb r3, [r7, #27] 8009724: 2b00 cmp r3, #0 8009726: d010 beq.n 800974a 8009728: 7efb ldrb r3, [r7, #27] 800972a: b25b sxtb r3, r3 800972c: 2b00 cmp r3, #0 800972e: db0c blt.n 800974a { if ((sfdp_param_header.ID_lsb & 0x01u) == 0x01u) 8009730: 7d3b ldrb r3, [r7, #20] 8009732: f003 0301 and.w r3, r3, #1 8009736: 2b00 cmp r3, #0 8009738: d003 beq.n 8009742 { Param_info->type = SFDP_PARAMID_VENDOR; 800973a: 687b ldr r3, [r7, #4] 800973c: 2201 movs r2, #1 800973e: 601a str r2, [r3, #0] if ((sfdp_param_header.ID_lsb & 0x01u) == 0x01u) 8009740: e0ba b.n 80098b8 SFDP_DEBUG_STR("-> type SFDP_PARAMID_VENDOR"); } else { Param_info->type = SFDP_PARAMID_FUNCTION_VENDOR; 8009742: 687b ldr r3, [r7, #4] 8009744: 2202 movs r2, #2 8009746: 601a str r2, [r3, #0] if ((sfdp_param_header.ID_lsb & 0x01u) == 0x01u) 8009748: e0b6 b.n 80098b8 SFDP_DEBUG_STR("-> type SFDP_PARAMID_FUNCTION_VENDOR"); } } else if (sfdp_param_header.ID_msb >= 0x80u) 800974a: 7efb ldrb r3, [r7, #27] 800974c: b25b sxtb r3, r3 800974e: 2b00 cmp r3, #0 8009750: f280 80ae bge.w 80098b0 { if ((sfdp_param_header.ID_lsb & 0x01u) == 0x00u) 8009754: 7d3b ldrb r3, [r7, #20] 8009756: f003 0301 and.w r3, r3, #1 800975a: 2b00 cmp r3, #0 800975c: d102 bne.n 8009764 { Param_info->type = SFDP_PARAMID_FUNCTION_JEDEC; 800975e: 687b ldr r3, [r7, #4] 8009760: 2204 movs r2, #4 8009762: 601a str r2, [r3, #0] SFDP_DEBUG_STR("-> type SFDP_PARAMID_FUNCTION_JEDEC"); } if (sfdp_param_header.ID_msb == SFDP_BASIC_PARAMETER_TABLE_MSB) 8009764: 7efb ldrb r3, [r7, #27] 8009766: 2bff cmp r3, #255 @ 0xff 8009768: f040 80a6 bne.w 80098b8 { switch (sfdp_param_header.ID_lsb) 800976c: 7d3b ldrb r3, [r7, #20] 800976e: 2b0f cmp r3, #15 8009770: dc4c bgt.n 800980c 8009772: 2b00 cmp r3, #0 8009774: da24 bge.n 80097c0 Param_info->type = SFDP_PARAMID_RESERVED; SFDP_DEBUG_STR("-> info SFDP_PARAMID_RESERVED"); break; default : SFDP_DEBUG_STR("-> info SFDP_PARAMID_????"); break; 8009776: e09e b.n 80098b6 switch (sfdp_param_header.ID_lsb) 8009778: 3b81 subs r3, #129 @ 0x81 800977a: 2b0d cmp r3, #13 800977c: f200 809b bhi.w 80098b6 8009780: a201 add r2, pc, #4 @ (adr r2, 8009788 ) 8009782: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009786: bf00 nop 8009788: 0800982d .word 0x0800982d 800978c: 080098b7 .word 0x080098b7 8009790: 080098b7 .word 0x080098b7 8009794: 0800983d .word 0x0800983d 8009798: 080098b7 .word 0x080098b7 800979c: 080098b7 .word 0x080098b7 80097a0: 08009857 .word 0x08009857 80097a4: 08009861 .word 0x08009861 80097a8: 080098b7 .word 0x080098b7 80097ac: 080098b7 .word 0x080098b7 80097b0: 0800987f .word 0x0800987f 80097b4: 080098b7 .word 0x080098b7 80097b8: 08009893 .word 0x08009893 80097bc: 0800989d .word 0x0800989d 80097c0: 2b0f cmp r3, #15 80097c2: d878 bhi.n 80098b6 80097c4: a201 add r2, pc, #4 @ (adr r2, 80097cc ) 80097c6: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80097ca: bf00 nop 80097cc: 08009817 .word 0x08009817 80097d0: 080098b7 .word 0x080098b7 80097d4: 080098b7 .word 0x080098b7 80097d8: 08009835 .word 0x08009835 80097dc: 080098b7 .word 0x080098b7 80097e0: 08009845 .word 0x08009845 80097e4: 0800984d .word 0x0800984d 80097e8: 080098b7 .word 0x080098b7 80097ec: 080098b7 .word 0x080098b7 80097f0: 0800986b .word 0x0800986b 80097f4: 08009875 .word 0x08009875 80097f8: 080098b7 .word 0x080098b7 80097fc: 08009889 .word 0x08009889 8009800: 080098b7 .word 0x080098b7 8009804: 080098b7 .word 0x080098b7 8009808: 080098a7 .word 0x080098a7 800980c: 2b8e cmp r3, #142 @ 0x8e 800980e: dc52 bgt.n 80098b6 8009810: 2b81 cmp r3, #129 @ 0x81 8009812: dab1 bge.n 8009778 break; 8009814: e04f b.n 80098b6 Param_info->type = SFDP_PARAMID_BASIC_SPIPROTOCOL; 8009816: 687b ldr r3, [r7, #4] 8009818: 2208 movs r2, #8 800981a: 601a str r2, [r3, #0] Param_info->size = ((sfdp_param_header.Length) < SFDP_PARAMS_BASIC_TABLE_DEFAULTSIZE) 800981c: 7dfb ldrb r3, [r7, #23] ? sfdp_param_header.Length : SFDP_PARAMS_BASIC_TABLE_DEFAULTSIZE; 800981e: 2b17 cmp r3, #23 8009820: bf28 it cs 8009822: 2317 movcs r3, #23 8009824: b2da uxtb r2, r3 Param_info->size = ((sfdp_param_header.Length) < SFDP_PARAMS_BASIC_TABLE_DEFAULTSIZE) 8009826: 687b ldr r3, [r7, #4] 8009828: 721a strb r2, [r3, #8] break; 800982a: e045 b.n 80098b8 Param_info->type = SFDP_PARAMID_SECTORMAP; 800982c: 687b ldr r3, [r7, #4] 800982e: 2210 movs r2, #16 8009830: 601a str r2, [r3, #0] break; 8009832: e041 b.n 80098b8 Param_info->type = SFDP_PARAMID_RPMC; 8009834: 687b ldr r3, [r7, #4] 8009836: 2220 movs r2, #32 8009838: 601a str r2, [r3, #0] break; 800983a: e03d b.n 80098b8 Param_info->type = SFDP_PARAMID_4BYTE_ADDRESS_INSTRUCTION; 800983c: 687b ldr r3, [r7, #4] 800983e: 2240 movs r2, #64 @ 0x40 8009840: 601a str r2, [r3, #0] break; 8009842: e039 b.n 80098b8 Param_info->type = SFDP_PARAMID_XSPI_V1_0; 8009844: 687b ldr r3, [r7, #4] 8009846: 2280 movs r2, #128 @ 0x80 8009848: 601a str r2, [r3, #0] break; 800984a: e035 b.n 80098b8 Param_info->type = SFDP_PARAMID_XSPI_V2_0; 800984c: 687b ldr r3, [r7, #4] 800984e: f44f 7280 mov.w r2, #256 @ 0x100 8009852: 601a str r2, [r3, #0] break; 8009854: e030 b.n 80098b8 Param_info->type = SFDP_PARAMID_STATUS_CONTROL_CONFIG_REGISTER_MAP; 8009856: 687b ldr r3, [r7, #4] 8009858: f44f 7200 mov.w r2, #512 @ 0x200 800985c: 601a str r2, [r3, #0] break; 800985e: e02b b.n 80098b8 Param_info->type = SFDP_PARAMID_STATUS_CONTROL_CONFIG_REGISTER_MAP_MULTICHIP; 8009860: 687b ldr r3, [r7, #4] 8009862: f44f 6280 mov.w r2, #1024 @ 0x400 8009866: 601a str r2, [r3, #0] break; 8009868: e026 b.n 80098b8 Param_info->type = SFDP_PARAMID_STATUS_CONTROL_CONFIG_XSPI_V2_0; 800986a: 687b ldr r3, [r7, #4] 800986c: f44f 6200 mov.w r2, #2048 @ 0x800 8009870: 601a str r2, [r3, #0] break; 8009872: e021 b.n 80098b8 Param_info->type = SFDP_PARAMID_OCTAL_DDR; 8009874: 687b ldr r3, [r7, #4] 8009876: f44f 5280 mov.w r2, #4096 @ 0x1000 800987a: 601a str r2, [r3, #0] break; 800987c: e01c b.n 80098b8 Param_info->type = SFDP_PARAMID_MSPT; 800987e: 687b ldr r3, [r7, #4] 8009880: f44f 5200 mov.w r2, #8192 @ 0x2000 8009884: 601a str r2, [r3, #0] break; 8009886: e017 b.n 80098b8 Param_info->type = SFDP_PARAMID_X4QUAD_DS; 8009888: 687b ldr r3, [r7, #4] 800988a: f44f 4280 mov.w r2, #16384 @ 0x4000 800988e: 601a str r2, [r3, #0] break; 8009890: e012 b.n 80098b8 Param_info->type = SFDP_PARAMID_QUAD_DDR; 8009892: 687b ldr r3, [r7, #4] 8009894: f44f 4200 mov.w r2, #32768 @ 0x8000 8009898: 601a str r2, [r3, #0] break; 800989a: e00d b.n 80098b8 Param_info->type = SFDP_PARAMID_SECURE_PACKET_READ_WRITE; 800989c: 687b ldr r3, [r7, #4] 800989e: f44f 3280 mov.w r2, #65536 @ 0x10000 80098a2: 601a str r2, [r3, #0] break; 80098a4: e008 b.n 80098b8 Param_info->type = SFDP_PARAMID_RESERVED; 80098a6: 687b ldr r3, [r7, #4] 80098a8: f44f 3200 mov.w r2, #131072 @ 0x20000 80098ac: 601a str r2, [r3, #0] break; 80098ae: e003 b.n 80098b8 } else { /* Unexpected value for MSB field of SFDP Parameter ID */ SFDP_DEBUG_STR("-> Unexpected value for MSB field of SFDP Parameter ID"); retr = EXTMEM_SFDP_ERROR_SFDPREAD; 80098b0: 2303 movs r3, #3 80098b2: 77fb strb r3, [r7, #31] goto error; 80098b4: e000 b.n 80098b8 break; 80098b6: bf00 nop } error: return retr; 80098b8: 7ffb ldrb r3, [r7, #31] } 80098ba: 4618 mov r0, r3 80098bc: 3720 adds r7, #32 80098be: 46bd mov sp, r7 80098c0: bd80 pop {r7, pc} 80098c2: bf00 nop 080098c4 : * @brief Executes the octal DDR table to enter octal DDR mode. * @param Object Pointer to the NOR SFDP memory instance object descriptor. * @return SFDP_StatusTypeDef: EXTMEM_SFDP_OK if successful, error code otherwise. */ SFDP_StatusTypeDef sfdp_enter_octal_mode(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object) { 80098c4: b590 push {r4, r7, lr} 80098c6: b085 sub sp, #20 80098c8: af00 add r7, sp, #0 80098ca: 6078 str r0, [r7, #4] SFDP_StatusTypeDef retr = EXTMEM_SFDP_OK; 80098cc: 2300 movs r3, #0 80098ce: 73fb strb r3, [r7, #15] uint8_t data[7]; SFDP_DEBUG_STR(__func__); /* D1-D2 command */ if (0u != JEDEC_OctalDdr.Param_DWORD.D1.LengthCommand) 80098d0: 4b6d ldr r3, [pc, #436] @ (8009a88 ) 80098d2: 78db ldrb r3, [r3, #3] 80098d4: 2b00 cmp r3, #0 80098d6: d028 beq.n 800992a { data[0] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D1.Byte1CommandSequence; 80098d8: 4b6b ldr r3, [pc, #428] @ (8009a88 ) 80098da: 789b ldrb r3, [r3, #2] 80098dc: 723b strb r3, [r7, #8] data[1] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D1.Byte2CommandSequence; 80098de: 4b6a ldr r3, [pc, #424] @ (8009a88 ) 80098e0: 785b ldrb r3, [r3, #1] 80098e2: 727b strb r3, [r7, #9] data[2] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D1.Byte3CommandSequence; 80098e4: 4b68 ldr r3, [pc, #416] @ (8009a88 ) 80098e6: 781b ldrb r3, [r3, #0] 80098e8: 72bb strb r3, [r7, #10] data[3] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D2.Byte4CommandSequence; 80098ea: 4b67 ldr r3, [pc, #412] @ (8009a88 ) 80098ec: 79db ldrb r3, [r3, #7] 80098ee: 72fb strb r3, [r7, #11] data[4] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D2.Byte5CommandSequence; 80098f0: 4b65 ldr r3, [pc, #404] @ (8009a88 ) 80098f2: 799b ldrb r3, [r3, #6] 80098f4: 733b strb r3, [r7, #12] data[5] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D2.Byte6CommandSequence; 80098f6: 4b64 ldr r3, [pc, #400] @ (8009a88 ) 80098f8: 795b ldrb r3, [r3, #5] 80098fa: 737b strb r3, [r7, #13] data[6] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D2.Byte7CommandSequence; 80098fc: 4b62 ldr r3, [pc, #392] @ (8009a88 ) 80098fe: 791b ldrb r3, [r3, #4] 8009900: 73bb strb r3, [r7, #14] if (HAL_OK != SAL_XSPI_CommandSendData(&Object->sfdp_private.SALObject, data[0], &data[1], 8009902: 687b ldr r3, [r7, #4] 8009904: f103 0008 add.w r0, r3, #8 8009908: 7a39 ldrb r1, [r7, #8] (uint16_t)(JEDEC_OctalDdr.Param_DWORD.D1.LengthCommand - 1u))) 800990a: 4b5f ldr r3, [pc, #380] @ (8009a88 ) 800990c: 78db ldrb r3, [r3, #3] 800990e: 3b01 subs r3, #1 8009910: b29c uxth r4, r3 if (HAL_OK != SAL_XSPI_CommandSendData(&Object->sfdp_private.SALObject, data[0], &data[1], 8009912: f107 0308 add.w r3, r7, #8 8009916: 1c5a adds r2, r3, #1 8009918: 4623 mov r3, r4 800991a: f7fe fa88 bl 8007e2e 800991e: 4603 mov r3, r0 8009920: 2b00 cmp r3, #0 8009922: d002 beq.n 800992a { retr = EXTMEM_SFDP_ERROR_OCTALMODE; 8009924: 230b movs r3, #11 8009926: 73fb strb r3, [r7, #15] goto error; 8009928: e0a9 b.n 8009a7e } } /* D3-D4 command */ if (0u != JEDEC_OctalDdr.Param_DWORD.D3.LengthCommand) 800992a: 4b57 ldr r3, [pc, #348] @ (8009a88 ) 800992c: 7adb ldrb r3, [r3, #11] 800992e: 2b00 cmp r3, #0 8009930: d032 beq.n 8009998 { /* wait for busy flag clear */ if (EXTMEM_DRIVER_NOR_SFDP_OK != driver_check_FlagBUSY(Object, 100u)) 8009932: 2164 movs r1, #100 @ 0x64 8009934: 6878 ldr r0, [r7, #4] 8009936: f7ff fe65 bl 8009604 800993a: 4603 mov r3, r0 800993c: 2b00 cmp r3, #0 800993e: d002 beq.n 8009946 { retr = EXTMEM_SFDP_ERROR_DRIVER; 8009940: 230c movs r3, #12 8009942: 73fb strb r3, [r7, #15] goto error; 8009944: e09b b.n 8009a7e } data[0] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D3.Byte1CommandSequence; 8009946: 4b50 ldr r3, [pc, #320] @ (8009a88 ) 8009948: 7a9b ldrb r3, [r3, #10] 800994a: 723b strb r3, [r7, #8] data[1] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D3.Byte2CommandSequence; 800994c: 4b4e ldr r3, [pc, #312] @ (8009a88 ) 800994e: 7a5b ldrb r3, [r3, #9] 8009950: 727b strb r3, [r7, #9] data[2] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D3.Byte3CommandSequence; 8009952: 4b4d ldr r3, [pc, #308] @ (8009a88 ) 8009954: 7a1b ldrb r3, [r3, #8] 8009956: 72bb strb r3, [r7, #10] data[3] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D4.Byte4CommandSequence; 8009958: 4b4b ldr r3, [pc, #300] @ (8009a88 ) 800995a: 7bdb ldrb r3, [r3, #15] 800995c: 72fb strb r3, [r7, #11] data[4] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D4.Byte5CommandSequence; 800995e: 4b4a ldr r3, [pc, #296] @ (8009a88 ) 8009960: 7b9b ldrb r3, [r3, #14] 8009962: 733b strb r3, [r7, #12] data[5] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D4.Byte6CommandSequence; 8009964: 4b48 ldr r3, [pc, #288] @ (8009a88 ) 8009966: 7b5b ldrb r3, [r3, #13] 8009968: 737b strb r3, [r7, #13] data[6] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D4.Byte7CommandSequence; 800996a: 4b47 ldr r3, [pc, #284] @ (8009a88 ) 800996c: 7b1b ldrb r3, [r3, #12] 800996e: 73bb strb r3, [r7, #14] if (HAL_OK != SAL_XSPI_CommandSendData(&Object->sfdp_private.SALObject, data[0], &data[1], 8009970: 687b ldr r3, [r7, #4] 8009972: f103 0008 add.w r0, r3, #8 8009976: 7a39 ldrb r1, [r7, #8] (uint16_t)(JEDEC_OctalDdr.Param_DWORD.D3.LengthCommand - 1u))) 8009978: 4b43 ldr r3, [pc, #268] @ (8009a88 ) 800997a: 7adb ldrb r3, [r3, #11] 800997c: 3b01 subs r3, #1 800997e: b29c uxth r4, r3 if (HAL_OK != SAL_XSPI_CommandSendData(&Object->sfdp_private.SALObject, data[0], &data[1], 8009980: f107 0308 add.w r3, r7, #8 8009984: 1c5a adds r2, r3, #1 8009986: 4623 mov r3, r4 8009988: f7fe fa51 bl 8007e2e 800998c: 4603 mov r3, r0 800998e: 2b00 cmp r3, #0 8009990: d002 beq.n 8009998 { retr = EXTMEM_SFDP_ERROR_OCTALMODE; 8009992: 230b movs r3, #11 8009994: 73fb strb r3, [r7, #15] goto error; 8009996: e072 b.n 8009a7e } } /* D5-D6 command */ if (0u != JEDEC_OctalDdr.Param_DWORD.D5.LengthCommand) 8009998: 4b3b ldr r3, [pc, #236] @ (8009a88 ) 800999a: 7cdb ldrb r3, [r3, #19] 800999c: 2b00 cmp r3, #0 800999e: d032 beq.n 8009a06 { /* wait for busy flag clear */ if (EXTMEM_DRIVER_NOR_SFDP_OK != driver_check_FlagBUSY(Object, 100u)) 80099a0: 2164 movs r1, #100 @ 0x64 80099a2: 6878 ldr r0, [r7, #4] 80099a4: f7ff fe2e bl 8009604 80099a8: 4603 mov r3, r0 80099aa: 2b00 cmp r3, #0 80099ac: d002 beq.n 80099b4 { retr = EXTMEM_SFDP_ERROR_DRIVER; 80099ae: 230c movs r3, #12 80099b0: 73fb strb r3, [r7, #15] goto error; 80099b2: e064 b.n 8009a7e } data[0] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D5.Byte1CommandSequence; 80099b4: 4b34 ldr r3, [pc, #208] @ (8009a88 ) 80099b6: 7c9b ldrb r3, [r3, #18] 80099b8: 723b strb r3, [r7, #8] data[1] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D5.Byte2CommandSequence; 80099ba: 4b33 ldr r3, [pc, #204] @ (8009a88 ) 80099bc: 7c5b ldrb r3, [r3, #17] 80099be: 727b strb r3, [r7, #9] data[2] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D5.Byte3CommandSequence; 80099c0: 4b31 ldr r3, [pc, #196] @ (8009a88 ) 80099c2: 7c1b ldrb r3, [r3, #16] 80099c4: 72bb strb r3, [r7, #10] data[3] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D6.Byte4CommandSequence; 80099c6: 4b30 ldr r3, [pc, #192] @ (8009a88 ) 80099c8: 7ddb ldrb r3, [r3, #23] 80099ca: 72fb strb r3, [r7, #11] data[4] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D6.Byte5CommandSequence; 80099cc: 4b2e ldr r3, [pc, #184] @ (8009a88 ) 80099ce: 7d9b ldrb r3, [r3, #22] 80099d0: 733b strb r3, [r7, #12] data[5] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D6.Byte6CommandSequence; 80099d2: 4b2d ldr r3, [pc, #180] @ (8009a88 ) 80099d4: 7d5b ldrb r3, [r3, #21] 80099d6: 737b strb r3, [r7, #13] data[6] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D6.Byte7CommandSequence; 80099d8: 4b2b ldr r3, [pc, #172] @ (8009a88 ) 80099da: 7d1b ldrb r3, [r3, #20] 80099dc: 73bb strb r3, [r7, #14] if (HAL_OK != SAL_XSPI_CommandSendData(&Object->sfdp_private.SALObject, data[0], &data[1], 80099de: 687b ldr r3, [r7, #4] 80099e0: f103 0008 add.w r0, r3, #8 80099e4: 7a39 ldrb r1, [r7, #8] (uint16_t)(JEDEC_OctalDdr.Param_DWORD.D5.LengthCommand - 1u))) 80099e6: 4b28 ldr r3, [pc, #160] @ (8009a88 ) 80099e8: 7cdb ldrb r3, [r3, #19] 80099ea: 3b01 subs r3, #1 80099ec: b29c uxth r4, r3 if (HAL_OK != SAL_XSPI_CommandSendData(&Object->sfdp_private.SALObject, data[0], &data[1], 80099ee: f107 0308 add.w r3, r7, #8 80099f2: 1c5a adds r2, r3, #1 80099f4: 4623 mov r3, r4 80099f6: f7fe fa1a bl 8007e2e 80099fa: 4603 mov r3, r0 80099fc: 2b00 cmp r3, #0 80099fe: d002 beq.n 8009a06 { retr = EXTMEM_SFDP_ERROR_OCTALMODE; 8009a00: 230b movs r3, #11 8009a02: 73fb strb r3, [r7, #15] goto error; 8009a04: e03b b.n 8009a7e } } /* D7-D8 command */ if (0u != JEDEC_OctalDdr.Param_DWORD.D7.LengthCommand) 8009a06: 4b20 ldr r3, [pc, #128] @ (8009a88 ) 8009a08: 7edb ldrb r3, [r3, #27] 8009a0a: 2b00 cmp r3, #0 8009a0c: d032 beq.n 8009a74 { /* wait for busy flag clear */ if (EXTMEM_DRIVER_NOR_SFDP_OK != driver_check_FlagBUSY(Object, 100u)) 8009a0e: 2164 movs r1, #100 @ 0x64 8009a10: 6878 ldr r0, [r7, #4] 8009a12: f7ff fdf7 bl 8009604 8009a16: 4603 mov r3, r0 8009a18: 2b00 cmp r3, #0 8009a1a: d002 beq.n 8009a22 { retr = EXTMEM_SFDP_ERROR_DRIVER; 8009a1c: 230c movs r3, #12 8009a1e: 73fb strb r3, [r7, #15] goto error; 8009a20: e02d b.n 8009a7e } data[0] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D7.Byte1CommandSequence; 8009a22: 4b19 ldr r3, [pc, #100] @ (8009a88 ) 8009a24: 7e9b ldrb r3, [r3, #26] 8009a26: 723b strb r3, [r7, #8] data[1] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D7.Byte2CommandSequence; 8009a28: 4b17 ldr r3, [pc, #92] @ (8009a88 ) 8009a2a: 7e5b ldrb r3, [r3, #25] 8009a2c: 727b strb r3, [r7, #9] data[2] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D7.Byte3CommandSequence; 8009a2e: 4b16 ldr r3, [pc, #88] @ (8009a88 ) 8009a30: 7e1b ldrb r3, [r3, #24] 8009a32: 72bb strb r3, [r7, #10] data[3] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D8.Byte4CommandSequence; 8009a34: 4b14 ldr r3, [pc, #80] @ (8009a88 ) 8009a36: 7fdb ldrb r3, [r3, #31] 8009a38: 72fb strb r3, [r7, #11] data[4] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D8.Byte5CommandSequence; 8009a3a: 4b13 ldr r3, [pc, #76] @ (8009a88 ) 8009a3c: 7f9b ldrb r3, [r3, #30] 8009a3e: 733b strb r3, [r7, #12] data[5] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D8.Byte6CommandSequence; 8009a40: 4b11 ldr r3, [pc, #68] @ (8009a88 ) 8009a42: 7f5b ldrb r3, [r3, #29] 8009a44: 737b strb r3, [r7, #13] data[6] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D8.Byte7CommandSequence; 8009a46: 4b10 ldr r3, [pc, #64] @ (8009a88 ) 8009a48: 7f1b ldrb r3, [r3, #28] 8009a4a: 73bb strb r3, [r7, #14] if (HAL_OK != SAL_XSPI_CommandSendData(&Object->sfdp_private.SALObject, data[0], &data[1], 8009a4c: 687b ldr r3, [r7, #4] 8009a4e: f103 0008 add.w r0, r3, #8 8009a52: 7a39 ldrb r1, [r7, #8] (uint16_t)(JEDEC_OctalDdr.Param_DWORD.D7.LengthCommand - 1u))) 8009a54: 4b0c ldr r3, [pc, #48] @ (8009a88 ) 8009a56: 7edb ldrb r3, [r3, #27] 8009a58: 3b01 subs r3, #1 8009a5a: b29c uxth r4, r3 if (HAL_OK != SAL_XSPI_CommandSendData(&Object->sfdp_private.SALObject, data[0], &data[1], 8009a5c: f107 0308 add.w r3, r7, #8 8009a60: 1c5a adds r2, r3, #1 8009a62: 4623 mov r3, r4 8009a64: f7fe f9e3 bl 8007e2e 8009a68: 4603 mov r3, r0 8009a6a: 2b00 cmp r3, #0 8009a6c: d002 beq.n 8009a74 { retr = EXTMEM_SFDP_ERROR_OCTALMODE; 8009a6e: 230b movs r3, #11 8009a70: 73fb strb r3, [r7, #15] goto error; 8009a72: e004 b.n 8009a7e /* no more wait for busy flag clear here, as command format might have changed to Octal */ } /* Abort any ongoing transfer to avoid performance issue */ SAL_XSPI_Abort(&Object->sfdp_private.SALObject); 8009a74: 687b ldr r3, [r7, #4] 8009a76: 3308 adds r3, #8 8009a78: 4618 mov r0, r3 8009a7a: f7fe fc5a bl 8008332 error: return retr; 8009a7e: 7bfb ldrb r3, [r7, #15] } 8009a80: 4618 mov r0, r3 8009a82: 3714 adds r7, #20 8009a84: 46bd mov sp, r7 8009a86: bd90 pop {r4, r7, pc} 8009a88: 24000430 .word 0x24000430 08009a8c : * @param Object Pointer to the NOR SFDP memory instance object descriptor. * @param DummyValue Dummy cycle value to set. * @return SFDP_StatusTypeDef: EXTMEM_SFDP_OK if successful, error code otherwise. */ SFDP_StatusTypeDef sfdp_set_dummycycle(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object, uint32_t DummyValue) { 8009a8c: b5f0 push {r4, r5, r6, r7, lr} 8009a8e: b08b sub sp, #44 @ 0x2c 8009a90: af04 add r7, sp, #16 8009a92: 6078 str r0, [r7, #4] 8009a94: 6039 str r1, [r7, #0] const uint8_t MaskWaitStateValue[4] = { 0x3u, 0x7u, 0xFu, 0x1Fu }; 8009a96: 4b6d ldr r3, [pc, #436] @ (8009c4c ) 8009a98: 60fb str r3, [r7, #12] SFDP_StatusTypeDef retr = EXTMEM_SFDP_OK; 8009a9a: 2300 movs r3, #0 8009a9c: 75fb strb r3, [r7, #23] uint8_t localValue[2] = { 0 }; 8009a9e: 2300 movs r3, #0 8009aa0: 813b strh r3, [r7, #8] uint32_t Address; if ((JEDEC_SCCR_Map.Param_DWORD.D9.BitAccessedByCommandsUsingAddress == 0u) && 8009aa2: 4b6b ldr r3, [pc, #428] @ (8009c50 ) 8009aa4: f893 3023 ldrb.w r3, [r3, #35] @ 0x23 8009aa8: f003 0310 and.w r3, r3, #16 8009aac: b2db uxtb r3, r3 8009aae: 2b00 cmp r3, #0 8009ab0: d10a bne.n 8009ac8 (JEDEC_SCCR_Map.Param_DWORD.D9.BitAvailable == 1u)) 8009ab2: 4b67 ldr r3, [pc, #412] @ (8009c50 ) 8009ab4: f893 3023 ldrb.w r3, [r3, #35] @ 0x23 8009ab8: f023 037f bic.w r3, r3, #127 @ 0x7f 8009abc: b2db uxtb r3, r3 if ((JEDEC_SCCR_Map.Param_DWORD.D9.BitAccessedByCommandsUsingAddress == 0u) && 8009abe: 2b00 cmp r3, #0 8009ac0: d002 beq.n 8009ac8 { /* Not yet supported */ retr = EXTMEM_SFDP_ERROR_DRIVER; 8009ac2: 230c movs r3, #12 8009ac4: 75fb strb r3, [r7, #23] goto error; 8009ac6: e0bb b.n 8009c40 } /* Compute the Address */ if (JEDEC_SCCR_Map.Param_DWORD.D9.LocalAddress == 1u) 8009ac8: 4b61 ldr r3, [pc, #388] @ (8009c50 ) 8009aca: f893 3023 ldrb.w r3, [r3, #35] @ 0x23 8009ace: f003 0308 and.w r3, r3, #8 8009ad2: b2db uxtb r3, r3 8009ad4: 2b00 cmp r3, #0 8009ad6: d005 beq.n 8009ae4 { /* Local Address is found in Byte 1 of 32-bit address */ Address = JEDEC_SCCR_Map.Param_DWORD.D9.AddressRegisterOrModesSupported << 8; 8009ad8: 4b5d ldr r3, [pc, #372] @ (8009c50 ) 8009ada: f893 3022 ldrb.w r3, [r3, #34] @ 0x22 8009ade: 021b lsls r3, r3, #8 8009ae0: 613b str r3, [r7, #16] 8009ae2: e00b b.n 8009afc } else { /* Specific case of GigaDevice GD25LX512ME where register address is wrongly coded in SFDP table */ if (Object->sfdp_private.ManuID == 0xC8) 8009ae4: 687b ldr r3, [r7, #4] 8009ae6: f893 305d ldrb.w r3, [r3, #93] @ 0x5d 8009aea: 2bc8 cmp r3, #200 @ 0xc8 8009aec: d102 bne.n 8009af4 { /* Address value in datasheet : 1, address value coded in SFDP table 200 */ Address = 1U; 8009aee: 2301 movs r3, #1 8009af0: 613b str r3, [r7, #16] 8009af2: e003 b.n 8009afc } else { /* Local address for Variable Dummy Cycle Settings bits is found in last byte of the address */ Address = JEDEC_SCCR_Map.Param_DWORD.D9.AddressRegisterOrModesSupported; 8009af4: 4b56 ldr r3, [pc, #344] @ (8009c50 ) 8009af6: f893 3022 ldrb.w r3, [r3, #34] @ 0x22 8009afa: 613b str r3, [r7, #16] } } /* Read the configuration */ if (HAL_OK != SAL_XSPI_CommandSendReadAddress(&Object->sfdp_private.SALObject, 8009afc: 687b ldr r3, [r7, #4] 8009afe: f103 0008 add.w r0, r3, #8 (uint8_t)JEDEC_SCCR_Map.Param_DWORD.D9.CommandReadAccess, 8009b02: 4b53 ldr r3, [pc, #332] @ (8009c50 ) 8009b04: f893 1021 ldrb.w r1, [r3, #33] @ 0x21 if (HAL_OK != SAL_XSPI_CommandSendReadAddress(&Object->sfdp_private.SALObject, 8009b08: 687b ldr r3, [r7, #4] 8009b0a: f893 305d ldrb.w r3, [r3, #93] @ 0x5d 8009b0e: f107 0208 add.w r2, r7, #8 8009b12: 9301 str r3, [sp, #4] 8009b14: 2302 movs r3, #2 8009b16: 9300 str r3, [sp, #0] 8009b18: 4613 mov r3, r2 8009b1a: 693a ldr r2, [r7, #16] 8009b1c: f7fe fa2f bl 8007f7e 8009b20: 4603 mov r3, r0 8009b22: 2b00 cmp r3, #0 8009b24: d002 beq.n 8009b2c Address, (uint8_t *)localValue, 2u, Object->sfdp_private.ManuID)) { retr = EXTMEM_SFDP_ERROR_DRIVER; 8009b26: 230c movs r3, #12 8009b28: 75fb strb r3, [r7, #23] goto error; 8009b2a: e089 b.n 8009c40 } /* send command to write enable */ if (HAL_OK != SAL_XSPI_CommandSendData(&Object->sfdp_private.SALObject, 8009b2c: 687b ldr r3, [r7, #4] 8009b2e: f103 0008 add.w r0, r3, #8 8009b32: 687b ldr r3, [r7, #4] 8009b34: f893 1070 ldrb.w r1, [r3, #112] @ 0x70 8009b38: 2300 movs r3, #0 8009b3a: 2200 movs r2, #0 8009b3c: f7fe f977 bl 8007e2e 8009b40: 4603 mov r3, r0 8009b42: 2b00 cmp r3, #0 8009b44: d002 beq.n 8009b4c Object->sfdp_private.DriverInfo.WriteWELCommand, NULL, 0u)) { retr = EXTMEM_SFDP_ERROR_DRIVER; 8009b46: 230c movs r3, #12 8009b48: 75fb strb r3, [r7, #23] goto error; 8009b4a: e079 b.n 8009c40 } /* control the write enable */ if (HAL_OK != SAL_XSPI_CheckStatusRegister(&Object->sfdp_private.SALObject, 8009b4c: 687b ldr r3, [r7, #4] 8009b4e: f103 0008 add.w r0, r3, #8 8009b52: 687b ldr r3, [r7, #4] 8009b54: f893 1071 ldrb.w r1, [r3, #113] @ 0x71 Object->sfdp_private.DriverInfo.ReadWELCommand, Object->sfdp_private.DriverInfo.WELAddress, 8009b58: 687b ldr r3, [r7, #4] 8009b5a: f893 3074 ldrb.w r3, [r3, #116] @ 0x74 if (HAL_OK != SAL_XSPI_CheckStatusRegister(&Object->sfdp_private.SALObject, 8009b5e: 461e mov r6, r3 ((Object->sfdp_private.DriverInfo.WELBusyPolarity == 0u) ? 1u : 0u) 8009b60: 687b ldr r3, [r7, #4] 8009b62: f893 3073 ldrb.w r3, [r3, #115] @ 0x73 8009b66: 2b00 cmp r3, #0 8009b68: d101 bne.n 8009b6e 8009b6a: 2301 movs r3, #1 8009b6c: e000 b.n 8009b70 8009b6e: 2300 movs r3, #0 << Object->sfdp_private.DriverInfo.WELPosition, 8009b70: 687a ldr r2, [r7, #4] 8009b72: f892 2072 ldrb.w r2, [r2, #114] @ 0x72 8009b76: 4093 lsls r3, r2 if (HAL_OK != SAL_XSPI_CheckStatusRegister(&Object->sfdp_private.SALObject, 8009b78: b2dc uxtb r4, r3 1u << Object->sfdp_private.DriverInfo.WELPosition, 8009b7a: 687b ldr r3, [r7, #4] 8009b7c: f893 3072 ldrb.w r3, [r3, #114] @ 0x72 8009b80: 461a mov r2, r3 8009b82: 2301 movs r3, #1 8009b84: 4093 lsls r3, r2 if (HAL_OK != SAL_XSPI_CheckStatusRegister(&Object->sfdp_private.SALObject, 8009b86: b2db uxtb r3, r3 8009b88: 687a ldr r2, [r7, #4] 8009b8a: f892 205d ldrb.w r2, [r2, #93] @ 0x5d 8009b8e: f44f 757a mov.w r5, #1000 @ 0x3e8 8009b92: 9502 str r5, [sp, #8] 8009b94: 9201 str r2, [sp, #4] 8009b96: 9300 str r3, [sp, #0] 8009b98: 4623 mov r3, r4 8009b9a: 4632 mov r2, r6 8009b9c: f7fe fa54 bl 8008048 8009ba0: 4603 mov r3, r0 8009ba2: 2b00 cmp r3, #0 8009ba4: d002 beq.n 8009bac Object->sfdp_private.ManuID, 1000)) { retr = EXTMEM_SFDP_ERROR_DRIVER; 8009ba6: 230c movs r3, #12 8009ba8: 75fb strb r3, [r7, #23] goto error; 8009baa: e049 b.n 8009c40 } /* clear the value */ localValue[0] = localValue[0] & ~(MaskWaitStateValue[JEDEC_SCCR_Map.Param_DWORD.D9.NumberBitsUsedToSetWaitStates] 8009bac: 7a3b ldrb r3, [r7, #8] 8009bae: b25a sxtb r2, r3 8009bb0: 4b27 ldr r3, [pc, #156] @ (8009c50 ) 8009bb2: f893 3023 ldrb.w r3, [r3, #35] @ 0x23 8009bb6: f3c3 1341 ubfx r3, r3, #5, #2 8009bba: b2db uxtb r3, r3 8009bbc: 3318 adds r3, #24 8009bbe: 443b add r3, r7 8009bc0: f813 3c0c ldrb.w r3, [r3, #-12] 8009bc4: 4619 mov r1, r3 << JEDEC_SCCR_Map.Param_DWORD.D9.BitLocationLSBPhysicalBitsRegister); 8009bc6: 4b22 ldr r3, [pc, #136] @ (8009c50 ) 8009bc8: f893 3023 ldrb.w r3, [r3, #35] @ 0x23 8009bcc: f3c3 0302 ubfx r3, r3, #0, #3 8009bd0: b2db uxtb r3, r3 8009bd2: fa01 f303 lsl.w r3, r1, r3 localValue[0] = localValue[0] & ~(MaskWaitStateValue[JEDEC_SCCR_Map.Param_DWORD.D9.NumberBitsUsedToSetWaitStates] 8009bd6: b25b sxtb r3, r3 8009bd8: 43db mvns r3, r3 8009bda: b25b sxtb r3, r3 8009bdc: 4013 ands r3, r2 8009bde: b25b sxtb r3, r3 8009be0: b2db uxtb r3, r3 8009be2: 723b strb r3, [r7, #8] /* Apply the value with the mask */ localValue[0] = localValue[0] 8009be4: 7a3a ldrb r2, [r7, #8] | (uint8_t)(DummyValue << JEDEC_SCCR_Map.Param_DWORD.D9.BitLocationLSBPhysicalBitsRegister); 8009be6: 4b1a ldr r3, [pc, #104] @ (8009c50 ) 8009be8: f893 3023 ldrb.w r3, [r3, #35] @ 0x23 8009bec: f3c3 0302 ubfx r3, r3, #0, #3 8009bf0: b2db uxtb r3, r3 8009bf2: 4619 mov r1, r3 8009bf4: 683b ldr r3, [r7, #0] 8009bf6: 408b lsls r3, r1 8009bf8: b2db uxtb r3, r3 localValue[0] = localValue[0] 8009bfa: 4313 orrs r3, r2 8009bfc: b2db uxtb r3, r3 8009bfe: 723b strb r3, [r7, #8] localValue[1] = localValue[0]; 8009c00: 7a3b ldrb r3, [r7, #8] 8009c02: 727b strb r3, [r7, #9] /* Write de configuration */ if (HAL_OK != SAL_XSPI_Write(&Object->sfdp_private.SALObject, 8009c04: 687b ldr r3, [r7, #4] 8009c06: f103 0008 add.w r0, r3, #8 (uint8_t)JEDEC_SCCR_Map.Param_DWORD.D9.CommandWriteAccess, 8009c0a: 4b11 ldr r3, [pc, #68] @ (8009c50 ) 8009c0c: f893 1020 ldrb.w r1, [r3, #32] if (HAL_OK != SAL_XSPI_Write(&Object->sfdp_private.SALObject, 8009c10: f107 0308 add.w r3, r7, #8 8009c14: 2202 movs r2, #2 8009c16: 9200 str r2, [sp, #0] 8009c18: 693a ldr r2, [r7, #16] 8009c1a: f7fe f8bf bl 8007d9c 8009c1e: 4603 mov r3, r0 8009c20: 2b00 cmp r3, #0 8009c22: d002 beq.n 8009c2a Address, (uint8_t *)localValue, 2u)) { retr = EXTMEM_SFDP_ERROR_DRIVER; 8009c24: 230c movs r3, #12 8009c26: 75fb strb r3, [r7, #23] goto error; 8009c28: e00a b.n 8009c40 } /* wait for busy flag clear */ if (EXTMEM_DRIVER_NOR_SFDP_OK != driver_check_FlagBUSY(Object, 100u)) 8009c2a: 2164 movs r1, #100 @ 0x64 8009c2c: 6878 ldr r0, [r7, #4] 8009c2e: f7ff fce9 bl 8009604 8009c32: 4603 mov r3, r0 8009c34: 2b00 cmp r3, #0 8009c36: d002 beq.n 8009c3e { retr = EXTMEM_SFDP_ERROR_DRIVER; 8009c38: 230c movs r3, #12 8009c3a: 75fb strb r3, [r7, #23] goto error; 8009c3c: e000 b.n 8009c40 } error : 8009c3e: bf00 nop return retr; 8009c40: 7dfb ldrb r3, [r7, #23] } 8009c42: 4618 mov r0, r3 8009c44: 371c adds r7, #28 8009c46: 46bd mov sp, r7 8009c48: bdf0 pop {r4, r5, r6, r7, pc} 8009c4a: bf00 nop 8009c4c: 1f0f0703 .word 0x1f0f0703 8009c50: 240003c0 .word 0x240003c0 08009c54 : * @brief Manages the Quad Enable Requirement (QER) for the NOR memory device. * @param Object Pointer to the NOR SFDP memory instance object descriptor. * @return SFDP_StatusTypeDef: EXTMEM_SFDP_OK if successful, error code otherwise. */ SFDP_StatusTypeDef JEDEC_Basic_ManageQuadEnableRequirement(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object) { 8009c54: b580 push {r7, lr} 8009c56: b084 sub sp, #16 8009c58: af00 add r7, sp, #0 8009c5a: 6078 str r0, [r7, #4] SFDP_StatusTypeDef retr = EXTMEM_SFDP_ERROR_NOTYETHANDLED; 8009c5c: 230f movs r3, #15 8009c5e: 73fb strb r3, [r7, #15] uint8_t localValue[2]; /* switch the mode in QSPI if available */ switch (JEDEC_Basic.Params.Param_DWORD.D15.QuadEnableRequirement & 0x7u) 8009c60: 4b59 ldr r3, [pc, #356] @ (8009dc8 ) 8009c62: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 8009c66: f3c3 1302 ubfx r3, r3, #4, #3 8009c6a: b2db uxtb r3, r3 8009c6c: 2b07 cmp r3, #7 8009c6e: f200 80a4 bhi.w 8009dba 8009c72: a201 add r2, pc, #4 @ (adr r2, 8009c78 ) 8009c74: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009c78: 08009dbb .word 0x08009dbb 8009c7c: 08009dbb .word 0x08009dbb 8009c80: 08009c99 .word 0x08009c99 8009c84: 08009dbb .word 0x08009dbb 8009c88: 08009d19 .word 0x08009d19 8009c8c: 08009dbb .word 0x08009dbb 8009c90: 08009dbb .word 0x08009dbb 8009c94: 08009dbb .word 0x08009dbb case 0x2u: { /* 010b: QE is bit 6 of status register 1. It is set via Write Status with one data byte where bit 6 is one. It is cleared via Write Status with one data byte where bit 6 is zero. */ /* 1 - set the write enable */ if (HAL_OK != SAL_XSPI_SendReadCommand(&Object->sfdp_private.SALObject, 8009c98: 687b ldr r3, [r7, #4] 8009c9a: f103 0008 add.w r0, r3, #8 8009c9e: 687b ldr r3, [r7, #4] 8009ca0: f893 1070 ldrb.w r1, [r3, #112] @ 0x70 8009ca4: 2300 movs r3, #0 8009ca6: 2200 movs r2, #0 8009ca8: f7fe f915 bl 8007ed6 8009cac: 4603 mov r3, r0 8009cae: 2b00 cmp r3, #0 8009cb0: d002 beq.n 8009cb8 Object->sfdp_private.DriverInfo.WriteWELCommand, NULL, 0u)) { retr = EXTMEM_SFDP_ERROR_DRIVER; 8009cb2: 230c movs r3, #12 8009cb4: 73fb strb r3, [r7, #15] goto error; 8009cb6: e081 b.n 8009dbc } /* 2 - read the status register */ if (HAL_OK != SAL_XSPI_SendReadCommand(&Object->sfdp_private.SALObject, SFDP_DRIVER_READ_STATUS_REGISTER_COMMAND, 8009cb8: 687b ldr r3, [r7, #4] 8009cba: f103 0008 add.w r0, r3, #8 8009cbe: f107 020c add.w r2, r7, #12 8009cc2: 2301 movs r3, #1 8009cc4: 2105 movs r1, #5 8009cc6: f7fe f906 bl 8007ed6 8009cca: 4603 mov r3, r0 8009ccc: 2b00 cmp r3, #0 8009cce: d002 beq.n 8009cd6 (uint8_t *)&localValue[0], 1u)) { retr = EXTMEM_SFDP_ERROR_DRIVER; 8009cd0: 230c movs r3, #12 8009cd2: 73fb strb r3, [r7, #15] goto error; 8009cd4: e072 b.n 8009dbc } /* 3 - update the status register to enable QPI mode*/ localValue[0] = localValue[0] | 0x40u; 8009cd6: 7b3b ldrb r3, [r7, #12] 8009cd8: f043 0340 orr.w r3, r3, #64 @ 0x40 8009cdc: b2db uxtb r3, r3 8009cde: 733b strb r3, [r7, #12] /* 4 - write the status register with QPI mode to 1 */ if (HAL_OK != SAL_XSPI_CommandSendData(&Object->sfdp_private.SALObject, 0x1u, (uint8_t *)&localValue[0], 1u)) 8009ce0: 687b ldr r3, [r7, #4] 8009ce2: f103 0008 add.w r0, r3, #8 8009ce6: f107 020c add.w r2, r7, #12 8009cea: 2301 movs r3, #1 8009cec: 2101 movs r1, #1 8009cee: f7fe f89e bl 8007e2e 8009cf2: 4603 mov r3, r0 8009cf4: 2b00 cmp r3, #0 8009cf6: d002 beq.n 8009cfe { retr = EXTMEM_SFDP_ERROR_DRIVER; 8009cf8: 230c movs r3, #12 8009cfa: 73fb strb r3, [r7, #15] goto error; 8009cfc: e05e b.n 8009dbc } /* wait busy flag */ if (EXTMEM_DRIVER_NOR_SFDP_OK != driver_check_FlagBUSY(Object, 100)) 8009cfe: 2164 movs r1, #100 @ 0x64 8009d00: 6878 ldr r0, [r7, #4] 8009d02: f7ff fc7f bl 8009604 8009d06: 4603 mov r3, r0 8009d08: 2b00 cmp r3, #0 8009d0a: d002 beq.n 8009d12 { retr = EXTMEM_SFDP_ERROR_DRIVER; 8009d0c: 230c movs r3, #12 8009d0e: 73fb strb r3, [r7, #15] goto error; 8009d10: e054 b.n 8009dbc } retr = EXTMEM_SFDP_OK; 8009d12: 2300 movs r3, #0 8009d14: 73fb strb r3, [r7, #15] break; 8009d16: e051 b.n 8009dbc where bit 1 of the second byte is one. It is cleared via Write Status with two data bytes where bit 1 of the second byte is zero. In contrast to the 001b code, writing 1 byte to the status register does not modify status register 2.*/ /* Read the status register */ if (HAL_OK != SAL_XSPI_SendReadCommand(&Object->sfdp_private.SALObject, 0x5, (uint8_t *)&localValue[0], 2u)) 8009d18: 687b ldr r3, [r7, #4] 8009d1a: f103 0008 add.w r0, r3, #8 8009d1e: f107 020c add.w r2, r7, #12 8009d22: 2302 movs r3, #2 8009d24: 2105 movs r1, #5 8009d26: f7fe f8d6 bl 8007ed6 8009d2a: 4603 mov r3, r0 8009d2c: 2b00 cmp r3, #0 8009d2e: d002 beq.n 8009d36 { retr = EXTMEM_SFDP_ERROR_DRIVER; 8009d30: 230c movs r3, #12 8009d32: 73fb strb r3, [r7, #15] goto error; 8009d34: e042 b.n 8009dbc } /* Update the status register */ localValue[1] |= 2u; 8009d36: 7b7b ldrb r3, [r7, #13] 8009d38: f043 0302 orr.w r3, r3, #2 8009d3c: b2db uxtb r3, r3 8009d3e: 737b strb r3, [r7, #13] /* WEL */ if (HAL_OK != SAL_XSPI_SendReadCommand(&Object->sfdp_private.SALObject, 8009d40: 687b ldr r3, [r7, #4] 8009d42: f103 0008 add.w r0, r3, #8 8009d46: 687b ldr r3, [r7, #4] 8009d48: f893 1070 ldrb.w r1, [r3, #112] @ 0x70 8009d4c: 2300 movs r3, #0 8009d4e: 2200 movs r2, #0 8009d50: f7fe f8c1 bl 8007ed6 8009d54: 4603 mov r3, r0 8009d56: 2b00 cmp r3, #0 8009d58: d002 beq.n 8009d60 Object->sfdp_private.DriverInfo.WriteWELCommand, NULL, 0u)) { retr = EXTMEM_SFDP_ERROR_DRIVER; 8009d5a: 230c movs r3, #12 8009d5c: 73fb strb r3, [r7, #15] goto error; 8009d5e: e02d b.n 8009dbc } /* Write the status register */ if (HAL_OK != SAL_XSPI_CommandSendData(&Object->sfdp_private.SALObject, 0x1u, (uint8_t *)&localValue[0], 2u)) 8009d60: 687b ldr r3, [r7, #4] 8009d62: f103 0008 add.w r0, r3, #8 8009d66: f107 020c add.w r2, r7, #12 8009d6a: 2302 movs r3, #2 8009d6c: 2101 movs r1, #1 8009d6e: f7fe f85e bl 8007e2e 8009d72: 4603 mov r3, r0 8009d74: 2b00 cmp r3, #0 8009d76: d002 beq.n 8009d7e { retr = EXTMEM_SFDP_ERROR_DRIVER; 8009d78: 230c movs r3, #12 8009d7a: 73fb strb r3, [r7, #15] goto error; 8009d7c: e01e b.n 8009dbc } /* Wait busy flag */ if (EXTMEM_DRIVER_NOR_SFDP_OK != driver_check_FlagBUSY(Object, 100)) 8009d7e: 2164 movs r1, #100 @ 0x64 8009d80: 6878 ldr r0, [r7, #4] 8009d82: f7ff fc3f bl 8009604 8009d86: 4603 mov r3, r0 8009d88: 2b00 cmp r3, #0 8009d8a: d002 beq.n 8009d92 { retr = EXTMEM_SFDP_ERROR_DRIVER; 8009d8c: 230c movs r3, #12 8009d8e: 73fb strb r3, [r7, #15] goto error; 8009d90: e014 b.n 8009dbc } /* Optional : only for control read the status register and check write operation is OK */ localValue[1] = 0xFF; 8009d92: 23ff movs r3, #255 @ 0xff 8009d94: 737b strb r3, [r7, #13] if (HAL_OK != SAL_XSPI_SendReadCommand(&Object->sfdp_private.SALObject, 0x5, (uint8_t *)&localValue[0], 2u)) 8009d96: 687b ldr r3, [r7, #4] 8009d98: f103 0008 add.w r0, r3, #8 8009d9c: f107 020c add.w r2, r7, #12 8009da0: 2302 movs r3, #2 8009da2: 2105 movs r1, #5 8009da4: f7fe f897 bl 8007ed6 8009da8: 4603 mov r3, r0 8009daa: 2b00 cmp r3, #0 8009dac: d002 beq.n 8009db4 { retr = EXTMEM_SFDP_ERROR_DRIVER; 8009dae: 230c movs r3, #12 8009db0: 73fb strb r3, [r7, #15] goto error; 8009db2: e003 b.n 8009dbc } retr = EXTMEM_SFDP_OK; 8009db4: 2300 movs r3, #0 8009db6: 73fb strb r3, [r7, #15] break; 8009db8: e000 b.n 8009dbc It is cleared via Write Status Register instruction 31h with one data byte where bit 1 is zero.*/ break; case 0x7u: /*111b: Reserved */ break; default :/* Added for Misra */ break; 8009dba: bf00 nop } error : return retr; 8009dbc: 7bfb ldrb r3, [r7, #15] } 8009dbe: 4618 mov r0, r3 8009dc0: 3710 adds r7, #16 8009dc2: 46bd mov sp, r7 8009dc4: bd80 pop {r7, pc} 8009dc6: bf00 nop 8009dc8: 24000340 .word 0x24000340 08009dcc : * @brief Manages the 4S-4S-4S enable sequence for the NOR memory device. * @param Object Pointer to the NOR SFDP memory instance object descriptor. * @return SFDP_StatusTypeDef: EXTMEM_SFDP_OK if successful, error code otherwise. */ SFDP_StatusTypeDef JEDEC_Basic_Manage4S4S4SEnableSequence(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object) { 8009dcc: b580 push {r7, lr} 8009dce: b084 sub sp, #16 8009dd0: af00 add r7, sp, #0 8009dd2: 6078 str r0, [r7, #4] SFDP_StatusTypeDef retr = EXTMEM_SFDP_ERROR_NOTYETHANDLED; 8009dd4: 230f movs r3, #15 8009dd6: 73fb strb r3, [r7, #15] uint8_t instruction = 0x00u; 8009dd8: 2300 movs r3, #0 8009dda: 73bb strb r3, [r7, #14] /* 4-4-4 mode enable sequences; This field describes the supported methods to enter 4-4-4 mode from 1-1-1 mode */ /* x_xxx1b: set QE per QER description above, then issue instruction 38h */ if ((JEDEC_Basic.Params.Param_DWORD.D15._4S4S4S_EnableSequence & 0x1u) == 0x1u) 8009ddc: 4b1a ldr r3, [pc, #104] @ (8009e48 ) 8009dde: 8f9b ldrh r3, [r3, #60] @ 0x3c 8009de0: f3c3 1304 ubfx r3, r3, #4, #5 8009de4: b2db uxtb r3, r3 8009de6: f003 0301 and.w r3, r3, #1 8009dea: 2b00 cmp r3, #0 8009dec: d007 beq.n 8009dfe { retr = JEDEC_Basic_ManageQuadEnableRequirement(Object); 8009dee: 6878 ldr r0, [r7, #4] 8009df0: f7ff ff30 bl 8009c54 8009df4: 4603 mov r3, r0 8009df6: 73fb strb r3, [r7, #15] instruction = 0x38u; 8009df8: 2338 movs r3, #56 @ 0x38 8009dfa: 73bb strb r3, [r7, #14] 8009dfc: e00f b.n 8009e1e } /* x_x1xxb: issue instruction 35h */ else if ((JEDEC_Basic.Params.Param_DWORD.D15._4S4S4S_EnableSequence & 0x4u) == 0x4u) 8009dfe: 4b12 ldr r3, [pc, #72] @ (8009e48 ) 8009e00: 8f9b ldrh r3, [r3, #60] @ 0x3c 8009e02: f3c3 1304 ubfx r3, r3, #4, #5 8009e06: b2db uxtb r3, r3 8009e08: f003 0304 and.w r3, r3, #4 8009e0c: 2b00 cmp r3, #0 8009e0e: d006 beq.n 8009e1e { /* If QE bit exists, Quad Enable Requirement describes method to enable Quad operations */ retr = JEDEC_Basic_ManageQuadEnableRequirement(Object); 8009e10: 6878 ldr r0, [r7, #4] 8009e12: f7ff ff1f bl 8009c54 8009e16: 4603 mov r3, r0 8009e18: 73fb strb r3, [r7, #15] instruction = 0x35u; 8009e1a: 2335 movs r3, #53 @ 0x35 8009e1c: 73bb strb r3, [r7, #14] Read Volatile Enhanced Configuration Register using instruction 65h, no address is required, set bit 7 to 1. Write Volatile Enhanced Configuration Register using instruction 61h, no address is required. This configuration is volatile. NOTE If device is in 0-4-4 mode, then this mode must be exited before the 4-4-4 enable sequence is issued. */ if ((retr == EXTMEM_SFDP_OK) && (instruction != 0u)) 8009e1e: 7bfb ldrb r3, [r7, #15] 8009e20: 2b00 cmp r3, #0 8009e22: d10c bne.n 8009e3e 8009e24: 7bbb ldrb r3, [r7, #14] 8009e26: 2b00 cmp r3, #0 8009e28: d009 beq.n 8009e3e { (void)SAL_XSPI_SendReadCommand(&Object->sfdp_private.SALObject, instruction, NULL, 0u); 8009e2a: 687b ldr r3, [r7, #4] 8009e2c: f103 0008 add.w r0, r3, #8 8009e30: 7bb9 ldrb r1, [r7, #14] 8009e32: 2300 movs r3, #0 8009e34: 2200 movs r2, #0 8009e36: f7fe f84e bl 8007ed6 /* @note on memory W25Q64JV the command 38h does not exist so the control on command execution has been removed */ retr = EXTMEM_SFDP_OK; 8009e3a: 2300 movs r3, #0 8009e3c: 73fb strb r3, [r7, #15] } return retr; 8009e3e: 7bfb ldrb r3, [r7, #15] } 8009e40: 4618 mov r0, r3 8009e42: 3710 adds r7, #16 8009e44: 46bd mov sp, r7 8009e46: bd80 pop {r7, pc} 8009e48: 24000340 .word 0x24000340 08009e4c : * @param Object Pointer to the NOR SFDP memory instance object descriptor. * @param Signature Value of the SFDP signature to check. * @return SFDP_StatusTypeDef: EXTMEM_SFDP_OK if valid, error code otherwise. */ SFDP_StatusTypeDef CheckSFDP_Signature(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object, uint32_t Signature) { 8009e4c: b580 push {r7, lr} 8009e4e: b084 sub sp, #16 8009e50: af00 add r7, sp, #0 8009e52: 6078 str r0, [r7, #4] 8009e54: 6039 str r1, [r7, #0] SFDP_StatusTypeDef retr = EXTMEM_SFDP_ERROR_SIGNATURE; 8009e56: 2304 movs r3, #4 8009e58: 73fb strb r3, [r7, #15] /* check the magic number */ switch (Signature) 8009e5a: 683b ldr r3, [r7, #0] 8009e5c: 4a0e ldr r2, [pc, #56] @ (8009e98 ) 8009e5e: 4293 cmp r3, r2 8009e60: d006 beq.n 8009e70 8009e62: 683b ldr r3, [r7, #0] 8009e64: 4a0d ldr r2, [pc, #52] @ (8009e9c ) 8009e66: 4293 cmp r3, r2 8009e68: d10e bne.n 8009e88 { case SFDP_SIGNATURE : SFDP_DEBUG_STR("signature of the header: OK"); retr = EXTMEM_SFDP_OK; 8009e6a: 2300 movs r3, #0 8009e6c: 73fb strb r3, [r7, #15] break; 8009e6e: e00e b.n 8009e8e case SFDP_SIGNATURE_INVERTED : SFDP_DEBUG_STR("signature of the header: KO inverted data order"); /* Change the memory type settings */ if (HAL_OK == SAL_XSPI_UpdateMemoryType(&Object->sfdp_private.SALObject, SAL_XSPI_ORDERINVERTED)) 8009e70: 687b ldr r3, [r7, #4] 8009e72: 3308 adds r3, #8 8009e74: 2100 movs r1, #0 8009e76: 4618 mov r0, r3 8009e78: f7fe fa23 bl 80082c2 8009e7c: 4603 mov r3, r0 8009e7e: 2b00 cmp r3, #0 8009e80: d104 bne.n 8009e8c { retr = EXTMEM_SFDP_ERROR_SIGNATUREMTYPE; 8009e82: 2305 movs r3, #5 8009e84: 73fb strb r3, [r7, #15] } break; 8009e86: e001 b.n 8009e8c default : SFDP_DEBUG_STR("signature of the header: KO"); break; 8009e88: bf00 nop 8009e8a: e000 b.n 8009e8e break; 8009e8c: bf00 nop } return retr; 8009e8e: 7bfb ldrb r3, [r7, #15] } 8009e90: 4618 mov r0, r3 8009e92: 3710 adds r7, #16 8009e94: 46bd mov sp, r7 8009e96: bd80 pop {r7, pc} 8009e98: 44505346 .word 0x44505346 8009e9c: 50444653 .word 0x50444653 08009ea0 : * @retval EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef Status of the operation. */ EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef EXTMEM_DRIVER_NOR_SFDP_Init(void *Peripheral, EXTMEM_LinkConfig_TypeDef Config, uint32_t ClockInput, EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *SFDPObject) { 8009ea0: b580 push {r7, lr} 8009ea2: b08a sub sp, #40 @ 0x28 8009ea4: af00 add r7, sp, #0 8009ea6: 60f8 str r0, [r7, #12] 8009ea8: 607a str r2, [r7, #4] 8009eaa: 603b str r3, [r7, #0] 8009eac: 460b mov r3, r1 8009eae: 72fb strb r3, [r7, #11] EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef retr = EXTMEM_DRIVER_NOR_SFDP_OK; 8009eb0: 2300 movs r3, #0 8009eb2: f887 3027 strb.w r3, [r7, #39] @ 0x27 SFDP_HeaderTypeDef JEDEC_SFDP_Header; uint8_t FreqUpdate = 0u; 8009eb6: 2300 movs r3, #0 8009eb8: 76fb strb r3, [r7, #27] uint8_t DataID[6]; uint32_t ClockOut; /* Reset data of SFDPObject to zero */ SFDP_DEBUG_STR("1 - reset data SFDPObject to zero") (void)memset((void *)&SFDPObject->sfdp_private, 0x0, sizeof(SFDPObject->sfdp_private)); 8009eba: 683b ldr r3, [r7, #0] 8009ebc: 3308 adds r3, #8 8009ebe: 2298 movs r2, #152 @ 0x98 8009ec0: 2100 movs r1, #0 8009ec2: 4618 mov r0, r3 8009ec4: f000 f8e6 bl 800a094 /* Initialize the SFDPObject */ SFDP_DEBUG_STR("2 - initialize the SFDPObject") SFDPObject->sfdp_private.Config = Config; 8009ec8: 683b ldr r3, [r7, #0] 8009eca: 7afa ldrb r2, [r7, #11] 8009ecc: f883 205c strb.w r2, [r3, #92] @ 0x5c SFDPObject->sfdp_private.DriverInfo.SpiPhyLink = PHY_LINK_1S1S1S; 8009ed0: 683b ldr r3, [r7, #0] 8009ed2: 2200 movs r2, #0 8009ed4: f883 2064 strb.w r2, [r3, #100] @ 0x64 SFDPObject->sfdp_private.DriverInfo.ClockIn = ClockInput; 8009ed8: 683b ldr r3, [r7, #0] 8009eda: 687a ldr r2, [r7, #4] 8009edc: 669a str r2, [r3, #104] @ 0x68 SAL_XSPI_SET_SFDPDUMMYCYLE(SFDPObject->sfdp_private.SALObject, EXTMEM_READ_SFDP_NB_DUMMY_CYCLES_DEFAULT); 8009ede: 683b ldr r3, [r7, #0] 8009ee0: 2208 movs r2, #8 8009ee2: f883 2059 strb.w r2, [r3, #89] @ 0x59 /* Set memory speed to 50Mhz maximum */ SFDP_DEBUG_STR("3 - set memory link and speed to 50Mhz maximum") (void)SAL_XSPI_Init(&SFDPObject->sfdp_private.SALObject, Peripheral); 8009ee6: 683b ldr r3, [r7, #0] 8009ee8: 3308 adds r3, #8 8009eea: 68f9 ldr r1, [r7, #12] 8009eec: 4618 mov r0, r3 8009eee: f7fd fc6f bl 80077d0 (void)SAL_XSPI_SetClock(&SFDPObject->sfdp_private.SALObject, ClockInput, DRIVER_SFDP_DEFAULT_CLOCK, &ClockOut); 8009ef2: 683b ldr r3, [r7, #0] 8009ef4: f103 0008 add.w r0, r3, #8 8009ef8: f107 0310 add.w r3, r7, #16 8009efc: 4a41 ldr r2, [pc, #260] @ (800a004 ) 8009efe: 6879 ldr r1, [r7, #4] 8009f00: f7fd fc26 bl 8007750 /* Abort any ongoing XSPI action */ (void)SAL_XSPI_DisableMapMode(&SFDPObject->sfdp_private.SALObject); 8009f04: 683b ldr r3, [r7, #0] 8009f06: 3308 adds r3, #8 8009f08: 4618 mov r0, r3 8009f0a: f7fe f9c9 bl 80082a0 /* Analyze the SFDP structure to get driver information */ SFDP_DEBUG_STR("4 - analyze the SFDP structure to get driver information") if (EXTMEM_SFDP_OK != SFDP_GetHeader(SFDPObject, &JEDEC_SFDP_Header)) 8009f0e: f107 031c add.w r3, r7, #28 8009f12: 4619 mov r1, r3 8009f14: 6838 ldr r0, [r7, #0] 8009f16: f7fe fb0d bl 8008534 8009f1a: 4603 mov r3, r0 8009f1c: 2b00 cmp r3, #0 8009f1e: d003 beq.n 8009f28 { /* Perform SFDP Header reading (several modes are tried) */ SFDP_DEBUG_STR("ERROR::EXTMEM_DRIVER_NOR_SFDP_ERROR_SFDP") retr = EXTMEM_DRIVER_NOR_SFDP_ERROR_SFDP; 8009f20: 23ff movs r3, #255 @ 0xff 8009f22: f887 3027 strb.w r3, [r7, #39] @ 0x27 goto error; 8009f26: e067 b.n 8009ff8 } /* Reset the memory */ SFDP_DEBUG_STR("5 - reset the memory") if (EXTMEM_SFDP_OK != SFDP_MemoryReset(SFDPObject)) 8009f28: 6838 ldr r0, [r7, #0] 8009f2a: f7fe fc3d bl 80087a8 Try to continue Initialisation procedure anyway. */ SFDP_DEBUG_STR("ERROR::on the call of SFDP_MemoryReset but no error returned") } /* Wait few ms after the reset operation, this is done to avoid issue on SFDP read */ HAL_Delay(10); 8009f2e: 200a movs r0, #10 8009f30: f7f6 feea bl 8000d08 /* Analyze the SFDP structure to get driver information after the reset */ SFDP_DEBUG_STR("6 - analyze the SFDP structure to get driver information") if (EXTMEM_SFDP_OK != SFDP_GetHeader(SFDPObject, &JEDEC_SFDP_Header)) 8009f34: f107 031c add.w r3, r7, #28 8009f38: 4619 mov r1, r3 8009f3a: 6838 ldr r0, [r7, #0] 8009f3c: f7fe fafa bl 8008534 8009f40: 4603 mov r3, r0 8009f42: 2b00 cmp r3, #0 8009f44: d003 beq.n 8009f4e { /* SFDP header reading is considered unsuccessful. Abort Initialisation procedure. */ SFDP_DEBUG_STR("ERROR::EXTMEM_DRIVER_NOR_SFDP_ERROR_SFDP") retr = EXTMEM_DRIVER_NOR_SFDP_ERROR_SFDP; 8009f46: 23ff movs r3, #255 @ 0xff 8009f48: f887 3027 strb.w r3, [r7, #39] @ 0x27 goto error; 8009f4c: e054 b.n 8009ff8 } /* Save information from the SFDP table Nb of parameters starts at 0 (0 means 1 parameter) */ if (JEDEC_SFDP_Header.param_number >= SFDP_MAX_NB_OF_PARAM) 8009f4e: f897 3022 ldrb.w r3, [r7, #34] @ 0x22 8009f52: 2b09 cmp r3, #9 8009f54: d904 bls.n 8009f60 { SFDPObject->sfdp_private.Sfdp_param_number = SFDP_MAX_NB_OF_PARAM - 1; 8009f56: 683b ldr r3, [r7, #0] 8009f58: 2209 movs r2, #9 8009f5a: f883 209c strb.w r2, [r3, #156] @ 0x9c 8009f5e: e004 b.n 8009f6a } else { SFDPObject->sfdp_private.Sfdp_param_number = JEDEC_SFDP_Header.param_number; 8009f60: f897 2022 ldrb.w r2, [r7, #34] @ 0x22 8009f64: 683b ldr r3, [r7, #0] 8009f66: f883 209c strb.w r2, [r3, #156] @ 0x9c } SFDPObject->sfdp_private.Sfdp_AccessProtocol = JEDEC_SFDP_Header.AccessProtocol; 8009f6a: f897 2023 ldrb.w r2, [r7, #35] @ 0x23 8009f6e: 683b ldr r3, [r7, #0] 8009f70: f883 209d strb.w r2, [r3, #157] @ 0x9d /* Read the flash ID. This Flash ID could later be used to perform specific operations for some identified references. */ SFDP_DEBUG_STR("7 - read the flash ID") (void)SAL_XSPI_GetId(&SFDPObject->sfdp_private.SALObject, DataID, EXTMEM_READ_JEDEC_ID_SIZE); 8009f74: 683b ldr r3, [r7, #0] 8009f76: 3308 adds r3, #8 8009f78: f107 0114 add.w r1, r7, #20 8009f7c: 2204 movs r2, #4 8009f7e: 4618 mov r0, r3 8009f80: f7fd fe24 bl 8007bcc DEBUG_ID(DataID); /* Keep manufacturer information, it could be used to help in building of consistent driver */ SFDPObject->sfdp_private.ManuID = DataID[0]; 8009f84: 7d3a ldrb r2, [r7, #20] 8009f86: 683b ldr r3, [r7, #0] 8009f88: f883 205d strb.w r2, [r3, #93] @ 0x5d /* Get the complete SFDP data */ SFDP_DEBUG_STR("8 - collect the SFDP data") if (EXTMEM_SFDP_OK != SFDP_CollectData(SFDPObject)) 8009f8c: 6838 ldr r0, [r7, #0] 8009f8e: f7fe fb2f bl 80085f0 8009f92: 4603 mov r3, r0 8009f94: 2b00 cmp r3, #0 8009f96: d003 beq.n 8009fa0 { SFDP_DEBUG_STR("ERROR::EXTMEM_DRIVER_NOR_SFDP_ERROR_SFDP") retr = EXTMEM_DRIVER_NOR_SFDP_ERROR_SFDP; 8009f98: 23ff movs r3, #255 @ 0xff 8009f9a: f887 3027 strb.w r3, [r7, #39] @ 0x27 goto error; 8009f9e: e02b b.n 8009ff8 } /* Setup the generic driver information and prepare the physical layer */ SFDP_DEBUG_STR("9 - build the generic driver information and prepare the physical layer") if (EXTMEM_SFDP_OK != SFDP_BuildGenericDriver(SFDPObject, &FreqUpdate)) 8009fa0: f107 031b add.w r3, r7, #27 8009fa4: 4619 mov r1, r3 8009fa6: 6838 ldr r0, [r7, #0] 8009fa8: f7fe fcda bl 8008960 8009fac: 4603 mov r3, r0 8009fae: 2b00 cmp r3, #0 8009fb0: d003 beq.n 8009fba { SFDP_DEBUG_STR("ERROR::EXTMEM_DRIVER_NOR_SFDP_ERROR_BUILD") retr = EXTMEM_DRIVER_NOR_SFDP_ERROR_BUILD; 8009fb2: 23fd movs r3, #253 @ 0xfd 8009fb4: f887 3027 strb.w r3, [r7, #39] @ 0x27 goto error; 8009fb8: e01e b.n 8009ff8 } /* Adjust frequency supplied to memory, if required */ SFDP_DEBUG_STR("10 - adjust the frequency if required") if ((FreqUpdate == 0u) && (SFDPObject->sfdp_public.MaxFreq != 0u)) 8009fba: 7efb ldrb r3, [r7, #27] 8009fbc: 2b00 cmp r3, #0 8009fbe: d10d bne.n 8009fdc 8009fc0: 683b ldr r3, [r7, #0] 8009fc2: 681b ldr r3, [r3, #0] 8009fc4: 2b00 cmp r3, #0 8009fc6: d009 beq.n 8009fdc { (void)SAL_XSPI_SetClock(&SFDPObject->sfdp_private.SALObject, ClockInput, 8009fc8: 683b ldr r3, [r7, #0] 8009fca: f103 0008 add.w r0, r3, #8 8009fce: 683b ldr r3, [r7, #0] 8009fd0: 681a ldr r2, [r3, #0] 8009fd2: f107 0310 add.w r3, r7, #16 8009fd6: 6879 ldr r1, [r7, #4] 8009fd8: f7fd fbba bl 8007750 SFDP_DEBUG_STR("--> new freq configured"); } /* Read again SFDP header to confirm memory access is properly setup */ SFDP_DEBUG_STR("11 - read again the SFDP header to adjust memory type if necessary") if (EXTMEM_SFDP_OK != SFDP_ReadHeader(SFDPObject, &JEDEC_SFDP_Header)) 8009fdc: f107 031c add.w r3, r7, #28 8009fe0: 4619 mov r1, r3 8009fe2: 6838 ldr r0, [r7, #0] 8009fe4: f7fe fa68 bl 80084b8 8009fe8: 4603 mov r3, r0 8009fea: 2b00 cmp r3, #0 8009fec: d003 beq.n 8009ff6 { SFDP_DEBUG_STR("ERROR::EXTMEM_DRIVER_NOR_SFDP_MEMTYPE_CHECK") retr = EXTMEM_DRIVER_NOR_SFDP_ERROR_MEMTYPE_CHECK; 8009fee: 23f2 movs r3, #242 @ 0xf2 8009ff0: f887 3027 strb.w r3, [r7, #39] @ 0x27 goto error; 8009ff4: e000 b.n 8009ff8 } error: 8009ff6: bf00 nop return retr; 8009ff8: f997 3027 ldrsb.w r3, [r7, #39] @ 0x27 } 8009ffc: 4618 mov r0, r3 8009ffe: 3728 adds r7, #40 @ 0x28 800a000: 46bd mov sp, r7 800a002: bd80 pop {r7, pc} 800a004: 02faf080 .word 0x02faf080 0800a008 : * * @param SFDPObject Memory object * @return @ref EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef **/ EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef EXTMEM_DRIVER_NOR_SFDP_DeInit(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *SFDPObject) { 800a008: b480 push {r7} 800a00a: b083 sub sp, #12 800a00c: af00 add r7, sp, #0 800a00e: 6078 str r0, [r7, #4] SFDPObject->sfdp_private.FlashSize = 0; 800a010: 687b ldr r3, [r7, #4] 800a012: 2200 movs r2, #0 800a014: f883 205e strb.w r2, [r3, #94] @ 0x5e return EXTMEM_DRIVER_NOR_SFDP_OK; 800a018: 2300 movs r3, #0 } 800a01a: 4618 mov r0, r3 800a01c: 370c adds r7, #12 800a01e: 46bd mov sp, r7 800a020: f85d 7b04 ldr.w r7, [sp], #4 800a024: 4770 bx lr 0800a026 : * @param SFDPObject Memory object * @return @ref EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef **/ EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef EXTMEM_DRIVER_NOR_SFDP_Enable_MemoryMappedMode( EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *SFDPObject) { 800a026: b590 push {r4, r7, lr} 800a028: b087 sub sp, #28 800a02a: af02 add r7, sp, #8 800a02c: 6078 str r0, [r7, #4] EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef retr = EXTMEM_DRIVER_NOR_SFDP_OK; 800a02e: 2300 movs r3, #0 800a030: 73fb strb r3, [r7, #15] /* Enter the mapped mode */ if (HAL_OK != SAL_XSPI_EnableMapMode(&SFDPObject->sfdp_private.SALObject, 800a032: 687b ldr r3, [r7, #4] 800a034: f103 0008 add.w r0, r3, #8 800a038: 687b ldr r3, [r7, #4] 800a03a: f893 1076 ldrb.w r1, [r3, #118] @ 0x76 SFDPObject->sfdp_private.DriverInfo.ReadInstruction, (uint8_t)SFDPObject->sfdp_private.SALObject.Commandbase.DummyCycles, 800a03e: 687b ldr r3, [r7, #4] 800a040: 6d1b ldr r3, [r3, #80] @ 0x50 if (HAL_OK != SAL_XSPI_EnableMapMode(&SFDPObject->sfdp_private.SALObject, 800a042: b2da uxtb r2, r3 800a044: 687b ldr r3, [r7, #4] 800a046: f893 3075 ldrb.w r3, [r3, #117] @ 0x75 800a04a: 2400 movs r4, #0 800a04c: 9400 str r4, [sp, #0] 800a04e: f7fe f8b0 bl 80081b2 800a052: 4603 mov r3, r0 800a054: 2b00 cmp r3, #0 800a056: d001 beq.n 800a05c SFDPObject->sfdp_private.DriverInfo.PageProgramInstruction, 0)) { retr = EXTMEM_DRIVER_NOR_SFDP_ERROR_MAP_ENABLE; 800a058: 23f3 movs r3, #243 @ 0xf3 800a05a: 73fb strb r3, [r7, #15] } return retr; 800a05c: f997 300f ldrsb.w r3, [r7, #15] } 800a060: 4618 mov r0, r3 800a062: 3714 adds r7, #20 800a064: 46bd mov sp, r7 800a066: bd90 pop {r4, r7, pc} 0800a068 : * @param SFDPObject Memory object * @return @ref EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef **/ EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef EXTMEM_DRIVER_NOR_SFDP_Disable_MemoryMappedMode( EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *SFDPObject) { 800a068: b580 push {r7, lr} 800a06a: b084 sub sp, #16 800a06c: af00 add r7, sp, #0 800a06e: 6078 str r0, [r7, #4] EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef retr = EXTMEM_DRIVER_NOR_SFDP_OK; 800a070: 2300 movs r3, #0 800a072: 73fb strb r3, [r7, #15] /* Exit the mapped mode */ if (HAL_OK != SAL_XSPI_DisableMapMode(&SFDPObject->sfdp_private.SALObject)) 800a074: 687b ldr r3, [r7, #4] 800a076: 3308 adds r3, #8 800a078: 4618 mov r0, r3 800a07a: f7fe f911 bl 80082a0 800a07e: 4603 mov r3, r0 800a080: 2b00 cmp r3, #0 800a082: d001 beq.n 800a088 { retr = EXTMEM_DRIVER_NOR_SFDP_ERROR_MAP_ENABLE; 800a084: 23f3 movs r3, #243 @ 0xf3 800a086: 73fb strb r3, [r7, #15] } return retr; 800a088: f997 300f ldrsb.w r3, [r7, #15] } 800a08c: 4618 mov r0, r3 800a08e: 3710 adds r7, #16 800a090: 46bd mov sp, r7 800a092: bd80 pop {r7, pc} 0800a094 : 800a094: 4402 add r2, r0 800a096: 4603 mov r3, r0 800a098: 4293 cmp r3, r2 800a09a: d100 bne.n 800a09e 800a09c: 4770 bx lr 800a09e: f803 1b01 strb.w r1, [r3], #1 800a0a2: e7f9 b.n 800a098 0800a0a4 <__libc_init_array>: 800a0a4: b570 push {r4, r5, r6, lr} 800a0a6: 4b0d ldr r3, [pc, #52] @ (800a0dc <__libc_init_array+0x38>) 800a0a8: 4d0d ldr r5, [pc, #52] @ (800a0e0 <__libc_init_array+0x3c>) 800a0aa: 1b5b subs r3, r3, r5 800a0ac: 109c asrs r4, r3, #2 800a0ae: 2600 movs r6, #0 800a0b0: 42a6 cmp r6, r4 800a0b2: d109 bne.n 800a0c8 <__libc_init_array+0x24> 800a0b4: f000 f828 bl 800a108 <_init> 800a0b8: 4d0a ldr r5, [pc, #40] @ (800a0e4 <__libc_init_array+0x40>) 800a0ba: 4b0b ldr r3, [pc, #44] @ (800a0e8 <__libc_init_array+0x44>) 800a0bc: 1b5b subs r3, r3, r5 800a0be: 109c asrs r4, r3, #2 800a0c0: 2600 movs r6, #0 800a0c2: 42a6 cmp r6, r4 800a0c4: d105 bne.n 800a0d2 <__libc_init_array+0x2e> 800a0c6: bd70 pop {r4, r5, r6, pc} 800a0c8: f855 3b04 ldr.w r3, [r5], #4 800a0cc: 4798 blx r3 800a0ce: 3601 adds r6, #1 800a0d0: e7ee b.n 800a0b0 <__libc_init_array+0xc> 800a0d2: f855 3b04 ldr.w r3, [r5], #4 800a0d6: 4798 blx r3 800a0d8: 3601 adds r6, #1 800a0da: e7f2 b.n 800a0c2 <__libc_init_array+0x1e> 800a0dc: 0800a16c .word 0x0800a16c 800a0e0: 0800a16c .word 0x0800a16c 800a0e4: 0800a16c .word 0x0800a16c 800a0e8: 0800a170 .word 0x0800a170 0800a0ec : 800a0ec: 440a add r2, r1 800a0ee: 4291 cmp r1, r2 800a0f0: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff 800a0f4: d100 bne.n 800a0f8 800a0f6: 4770 bx lr 800a0f8: b510 push {r4, lr} 800a0fa: f811 4b01 ldrb.w r4, [r1], #1 800a0fe: f803 4f01 strb.w r4, [r3, #1]! 800a102: 4291 cmp r1, r2 800a104: d1f9 bne.n 800a0fa 800a106: bd10 pop {r4, pc} 0800a108 <_init>: 800a108: b5f8 push {r3, r4, r5, r6, r7, lr} 800a10a: bf00 nop 800a10c: bcf8 pop {r3, r4, r5, r6, r7} 800a10e: bc08 pop {r3} 800a110: 469e mov lr, r3 800a112: 4770 bx lr 0800a114 <_fini>: 800a114: b5f8 push {r3, r4, r5, r6, r7, lr} 800a116: bf00 nop 800a118: bcf8 pop {r3, r4, r5, r6, r7} 800a11a: bc08 pop {r3} 800a11c: 469e mov lr, r3 800a11e: 4770 bx lr