thomas/CelloEffects
1
0 Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
cubemx-sd-spi4-st67-prep
CelloEffects/Appli/Core/Src/stm32h7rsxx_it.c
T
thomasandClaude Sonnet 5.5 66bb319423 CubeMX: SPI4 + SDMMC1/FatFs + I2S6, audio BSP et debug VS Code (Linux) 
Regeneration CubeMX (Appli) preparant le driver ST67W611M1 et la carte SD :
- SPI4 (PE12/13/14, CS PF8) + DMA GPDMA1 canaux 4/5, SPI_RDY (PD12/EXTI12),
  CHIP_EN (PD13) et BOOT (PD15) pour la X-NUCLEO-67W61M1 sur l'Arduino
- SDMMC1 + FatFs (appels d'init non generes dans main, IRQ SDMMC1 prio 14),
  PM14 en open-drain ; I2S6_CK sur PA5 pour liberer PC12 (SDMMC1_CK)
- HAL UART retire ; USE_BSP_COM_FEATURE=0
- Audio preserve : ADF 4/16/24, prio IRQ 2, DMA canal 0 en priorite haute,
  GPDMA1_Channel2_IRQHandler deplace dans audio_irq.c (hors fichiers generes),
  BSP_MX_I2S6_Init (renommage dans le BSP pour eviter le conflit avec CubeMX)
- Middlewares/ST/ST67W6X_Network_Driver, FatFs et sources HAL SPI/SD ajoutes
  (driver ST67 pas encore integre au build)

Build et debug sous Linux :
- gcc/toolchain-env.sh, gdbserver.sh, arm-gdb.sh : outils de STM32CubeIDE par
  glob ; flash.sh les retrouve ; ruby_compat.rb pour Ruby >= 3.2 (TouchGFX)
- makefile_appli : sources SD/SPI/FatFs/audio_irq ; chmod +x des .out TouchGFX
- Objets de build (*.o, *.d, *.su) retires de l'index (deja dans .gitignore)
- AGENTS.md : toolchain Linux, configs VS Code (cppdbg et ST stlinkgdbtarget),
  pieges de l'extension ST (.settings/ide.store.json, preRunCommands reset)

Verifie sur carte : audio OK, debug Appli/Boot OK.

Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
2026-10-23 22:49:06 +02:00

403 lines
10 KiB
C
Raw Permalink Blame History

/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32h7rsxx_it.c
* @brief Interrupt Service Routines.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "stm32h7rsxx_it.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/* External variables --------------------------------------------------------*/
extern DMA_NodeTypeDef Node_GPDMA1_Channel0;
extern DMA_QListTypeDef List_GPDMA1_Channel0;
extern DMA_HandleTypeDef handle_GPDMA1_Channel0;
extern MDF_HandleTypeDef AdfHandle0;
extern DMA2D_HandleTypeDef hdma2d;
extern GPU2D_HandleTypeDef hgpu2d;
extern DMA_HandleTypeDef handle_HPDMA1_Channel1;
extern DMA_HandleTypeDef handle_HPDMA1_Channel0;
extern JPEG_HandleTypeDef hjpeg;
extern LTDC_HandleTypeDef hltdc;
extern SD_HandleTypeDef hsd1;
extern DMA_HandleTypeDef handle_GPDMA1_Channel5;
extern DMA_HandleTypeDef handle_GPDMA1_Channel4;
extern SPI_HandleTypeDef hspi4;
extern TIM_HandleTypeDef htim6;
/* USER CODE BEGIN EV */
/* USER CODE END EV */
/******************************************************************************/
/* Cortex Processor Interruption and Exception Handlers */
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
{
}
/* USER CODE END NonMaskableInt_IRQn 1 */
}
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_HardFault_IRQn 0 */
/* USER CODE END W1_HardFault_IRQn 0 */
}
}
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
/* USER CODE END W1_MemoryManagement_IRQn 0 */
}
}
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_BusFault_IRQn 0 */
/* USER CODE END W1_BusFault_IRQn 0 */
}
}
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_UsageFault_IRQn 0 */
/* USER CODE END W1_UsageFault_IRQn 0 */
}
}
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
/* USER CODE BEGIN DebugMonitor_IRQn 0 */
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
/******************************************************************************/
/* STM32H7RSxx Peripheral Interrupt Handlers */
/* Add here the Interrupt Handlers for the used peripherals. */
/* For the available peripheral interrupt handler names, */
/* please refer to the startup file (startup_stm32h7rsxx.s). */
/******************************************************************************/
/**
* @brief This function handles EXTI line3 interrupt.
*/
void EXTI3_IRQHandler(void)
{
/* USER CODE BEGIN EXTI3_IRQn 0 */
/* USER CODE END EXTI3_IRQn 0 */
HAL_GPIO_EXTI_IRQHandler(TP_IRQ_Pin);
/* USER CODE BEGIN EXTI3_IRQn 1 */
/* USER CODE END EXTI3_IRQn 1 */
}
/**
* @brief This function handles EXTI line12 interrupt.
*/
void EXTI12_IRQHandler(void)
{
/* USER CODE BEGIN EXTI12_IRQn 0 */
/* USER CODE END EXTI12_IRQn 0 */
HAL_GPIO_EXTI_IRQHandler(SPI_RDY_Pin);
/* USER CODE BEGIN EXTI12_IRQn 1 */
/* USER CODE END EXTI12_IRQn 1 */
}
/**
* @brief This function handles GPDMA1 Channel 0 global interrupt.
*/
void GPDMA1_Channel0_IRQHandler(void)
{
/* USER CODE BEGIN GPDMA1_Channel0_IRQn 0 */
/* USER CODE END GPDMA1_Channel0_IRQn 0 */
HAL_DMA_IRQHandler(&handle_GPDMA1_Channel0);
/* USER CODE BEGIN GPDMA1_Channel0_IRQn 1 */
/* USER CODE END GPDMA1_Channel0_IRQn 1 */
}
/**
* @brief This function handles GPDMA1 Channel 4 global interrupt.
*/
void GPDMA1_Channel4_IRQHandler(void)
{
/* USER CODE BEGIN GPDMA1_Channel4_IRQn 0 */
/* USER CODE END GPDMA1_Channel4_IRQn 0 */
HAL_DMA_IRQHandler(&handle_GPDMA1_Channel4);
/* USER CODE BEGIN GPDMA1_Channel4_IRQn 1 */
/* USER CODE END GPDMA1_Channel4_IRQn 1 */
}
/**
* @brief This function handles GPDMA1 Channel 5 global interrupt.
*/
void GPDMA1_Channel5_IRQHandler(void)
{
/* USER CODE BEGIN GPDMA1_Channel5_IRQn 0 */
/* USER CODE END GPDMA1_Channel5_IRQn 0 */
HAL_DMA_IRQHandler(&handle_GPDMA1_Channel5);
/* USER CODE BEGIN GPDMA1_Channel5_IRQn 1 */
/* USER CODE END GPDMA1_Channel5_IRQn 1 */
}
/**
* @brief This function handles TIM6 global interrupt.
*/
void TIM6_IRQHandler(void)
{
/* USER CODE BEGIN TIM6_IRQn 0 */
/* USER CODE END TIM6_IRQn 0 */
HAL_TIM_IRQHandler(&htim6);
/* USER CODE BEGIN TIM6_IRQn 1 */
/* USER CODE END TIM6_IRQn 1 */
}
/**
* @brief This function handles SPI4 global interrupt.
*/
void SPI4_IRQHandler(void)
{
/* USER CODE BEGIN SPI4_IRQn 0 */
/* USER CODE END SPI4_IRQn 0 */
HAL_SPI_IRQHandler(&hspi4);
/* USER CODE BEGIN SPI4_IRQn 1 */
/* USER CODE END SPI4_IRQn 1 */
}
/**
* @brief This function handles HPDMA1 Channel 0 global interrupt.
*/
void HPDMA1_Channel0_IRQHandler(void)
{
/* USER CODE BEGIN HPDMA1_Channel0_IRQn 0 */
/* USER CODE END HPDMA1_Channel0_IRQn 0 */
HAL_DMA_IRQHandler(&handle_HPDMA1_Channel0);
/* USER CODE BEGIN HPDMA1_Channel0_IRQn 1 */
/* USER CODE END HPDMA1_Channel0_IRQn 1 */
}
/**
* @brief This function handles HPDMA1 Channel 1 global interrupt.
*/
void HPDMA1_Channel1_IRQHandler(void)
{
/* USER CODE BEGIN HPDMA1_Channel1_IRQn 0 */
/* USER CODE END HPDMA1_Channel1_IRQn 0 */
HAL_DMA_IRQHandler(&handle_HPDMA1_Channel1);
/* USER CODE BEGIN HPDMA1_Channel1_IRQn 1 */
/* USER CODE END HPDMA1_Channel1_IRQn 1 */
}
/**
* @brief This function handles LTDC global interrupt.
*/
void LTDC_IRQHandler(void)
{
/* USER CODE BEGIN LTDC_IRQn 0 */
/* USER CODE END LTDC_IRQn 0 */
HAL_LTDC_IRQHandler(&hltdc);
/* USER CODE BEGIN LTDC_IRQn 1 */
/* USER CODE END LTDC_IRQn 1 */
}
/**
* @brief This function handles DMA2D global interrupt.
*/
void DMA2D_IRQHandler(void)
{
/* USER CODE BEGIN DMA2D_IRQn 0 */
/* USER CODE END DMA2D_IRQn 0 */
HAL_DMA2D_IRQHandler(&hdma2d);
/* USER CODE BEGIN DMA2D_IRQn 1 */
/* USER CODE END DMA2D_IRQn 1 */
}
/**
* @brief This function handles JPEG global interrupt.
*/
void JPEG_IRQHandler(void)
{
/* USER CODE BEGIN JPEG_IRQn 0 */
/* USER CODE END JPEG_IRQn 0 */
HAL_JPEG_IRQHandler(&hjpeg);
/* USER CODE BEGIN JPEG_IRQn 1 */
/* USER CODE END JPEG_IRQn 1 */
}
/**
* @brief This function handles SDMMC1 global interrupt.
*/
void SDMMC1_IRQHandler(void)
{
/* USER CODE BEGIN SDMMC1_IRQn 0 */
/* USER CODE END SDMMC1_IRQn 0 */
HAL_SD_IRQHandler(&hsd1);
/* USER CODE BEGIN SDMMC1_IRQn 1 */
/* USER CODE END SDMMC1_IRQn 1 */
}
/**
* @brief This function handles ADF1 Filter 0 global Interrupt.
*/
void ADF1_FLT0_IRQHandler(void)
{
/* USER CODE BEGIN ADF1_FLT0_IRQn 0 */
/* USER CODE END ADF1_FLT0_IRQn 0 */
HAL_MDF_IRQHandler(&AdfHandle0);
/* USER CODE BEGIN ADF1_FLT0_IRQn 1 */
/* USER CODE END ADF1_FLT0_IRQn 1 */
}
/**
* @brief This function handles GPU2D global interrupt.
*/
void GPU2D_IRQHandler(void)
{
/* USER CODE BEGIN GPU2D_IRQn 0 */
/* USER CODE END GPU2D_IRQn 0 */
HAL_GPU2D_IRQHandler(&hgpu2d);
/* USER CODE BEGIN GPU2D_IRQn 1 */
/* USER CODE END GPU2D_IRQn 1 */
}
/**
* @brief This function handles GPU2D Error interrupt.
*/
void GPU2D_ER_IRQHandler(void)
{
/* USER CODE BEGIN GPU2D_ER_IRQn 0 */
/* USER CODE END GPU2D_ER_IRQn 0 */
HAL_GPU2D_ER_IRQHandler(&hgpu2d);
/* USER CODE BEGIN GPU2D_ER_IRQn 1 */
/* USER CODE END GPU2D_ER_IRQn 1 */
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
Reference in new issue View Git Blame Copy Permalink