305 lines
10 KiB
C
305 lines
10 KiB
C
/**
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******************************************************************************
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* @file system_stm32h7rsxx.c
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* @author MCD Application Team
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* @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2022 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*
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* This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32h7rsxx.s" file.
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*
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* - SystemCoreClock variable: Contains the core clock (sys_cpu_ck), it can
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* be used by the user application to setup the
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* SysTick timer or configure other parameters.
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*
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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* be called whenever the core clock is changed
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* during program execution.
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*
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* After each device reset the HSI (64 MHz) is used as system clock source.
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* Then SystemInit() function is called, in "startup_stm32h7rsxx.s" file, to
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* optionally configure the system clock before to branch to main program.
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*
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*=============================================================================
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup STM32H7RSxx_System
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* @{
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*/
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/** @addtogroup STM32H7RSxx_System_Private_Includes
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* @{
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*/
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#include "stm32h7rsxx.h"
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#include <math.h>
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/**
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* @}
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*/
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/** @addtogroup STM32H7RSxx_System_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32H7RSxx_System_Private_Defines
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* @{
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*/
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#if !defined (HSE_VALUE)
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#define HSE_VALUE 24000000UL /*!< Value of the High-Speed External oscillator in Hz */
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#endif /* HSE_VALUE */
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#if !defined (HSI_VALUE)
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#define HSI_VALUE 64000000UL /*!< Value of the High-Speed Internal oscillator in Hz */
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#endif /* HSI_VALUE */
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#if !defined (CSI_VALUE)
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#define CSI_VALUE 4000000UL /*!< Value of the Low-power Internal oscillator in Hz */
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#endif /* CSI_VALUE */
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/* Note: Following vector table addresses must be defined in line with linker
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configuration. */
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/*!< Uncomment the following line or define USER_VECT_TAB_ADDRESS at compiler level if you need
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to relocate the vector table anywhere in Flash or Sram, else the vector table is kept at
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the automatic remap of the selected boot address */
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/* #define USER_VECT_TAB_ADDRESS */
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#if defined(USER_VECT_TAB_ADDRESS)
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/*!< Uncomment the following line or define VECT_TAB_SRAM at compiler level if you need
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to relocate your vector Table in Sram else user remap will be done in Flash. */
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/* #define VECT_TAB_SRAM */
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#if defined(VECT_TAB_SRAM)
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#if !defined(VECT_TAB_BASE_ADDRESS)
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#define VECT_TAB_BASE_ADDRESS ITCM_BASE /*!< Vector Table base address field.
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This value must be a multiple of 0x400. */
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#endif
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#if !defined(VECT_TAB_OFFSET)
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#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
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This value must be a multiple of 0x400. */
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#endif
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#else
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#if !defined(VECT_TAB_BASE_ADDRESS)
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#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
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This value must be a multiple of 0x400. */
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#endif
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#if !defined(VECT_TAB_OFFSET)
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#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
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This value must be a multiple of 0x400. */
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#endif
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#endif /* VECT_TAB_SRAM */
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#endif /* USER_VECT_TAB_ADDRESS */
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/******************************************************************************/
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/**
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* @}
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*/
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/** @addtogroup STM32H7RSxx_System_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32H7RSxx_System_Private_Variables
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* @{
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*/
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/* The SystemCoreClock variable is updated in two ways:
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1) by calling CMSIS function SystemCoreClockUpdate()
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2) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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Note: If you use this function to configure the system clock; then there
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is no need to call the first function listed above, since SystemCoreClock
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variable is updated automatically.
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*/
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uint32_t SystemCoreClock = HSI_VALUE;
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/**
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* @}
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*/
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/** @addtogroup STM32H7RSxx_System_Private_FunctionPrototypes
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32H7RSxx_System_Private_Functions
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* @{
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*/
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/**
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* @brief Setup the microcontroller system.
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* @retval None
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*/
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void SystemInit(void)
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{
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/* Configure the Vector Table location -------------------------------------*/
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#if defined(USER_VECT_TAB_ADDRESS)
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SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
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#endif
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/* FPU settings ------------------------------------------------------------*/
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
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#endif
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}
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/**
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* @brief Update SystemCoreClock variable according to RCC registers values.
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* The SystemCoreClock variable contains the core clock (sys_cpu_ck), it can
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* be used by the user application to setup the SysTick timer or configure
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* other parameters.
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*
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* @note Each time the core clock changes, this function must be called
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* to update SystemCoreClock variable value. Otherwise, any configuration
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* based on this variable will be incorrect.
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*
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* @note - The system frequency computed by this function is not the real
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* frequency in the chip. It is calculated based on the predefined
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* constant and the selected clock source:
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*
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* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
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*
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* - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(**)
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*
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* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
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*
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* - If SYSCLK source is PLL, SystemCoreClock will contain the HSI_VALUE(*)
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* or CSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
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*
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* (*) HSI_VALUE is a constant defined in stm32h7rsxx_hal.h file (default value
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* 64 MHz) but the real value may vary depending on the variations
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* in voltage and temperature.
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*
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* (**) CSI_VALUE is a constant defined in stm32h7rsxx_hal.h file (default value
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* 4 MHz) but the real value may vary depending on the variations
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* in voltage and temperature.
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*
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* (***) HSE_VALUE is a constant defined in stm32h7rsxx_hal.h file (default value
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* 24 MHz), user has to ensure that HSE_VALUE is same as the real
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* frequency of the crystal used. Otherwise, this function may
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* have wrong result.
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*
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* - The result of this function could be not correct when using fractional
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* value for HSE crystal.
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*
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* @retval None
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*/
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void SystemCoreClockUpdate(void)
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{
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uint32_t sysclk, hsivalue, pllsource, pllm, pllp, core_presc;
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float_t pllfracn, pllvco;
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/* Get SYSCLK source -------------------------------------------------------*/
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switch (RCC->CFGR & RCC_CFGR_SWS)
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{
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case 0x00: /* HSI used as system clock source (default after reset) */
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sysclk = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos));
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break;
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case 0x08: /* CSI used as system clock source */
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sysclk = CSI_VALUE;
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break;
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case 0x10: /* HSE used as system clock source */
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sysclk = HSE_VALUE;
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break;
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case 0x18: /* PLL1 used as system clock source */
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/* PLL1_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
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SYSCLK = PLL1_VCO / PLL1R
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*/
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pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
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pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) ;
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if ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) != 0U)
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{
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pllfracn = (float_t)(uint32_t)(((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN)>> RCC_PLL1FRACR_FRACN_Pos));
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}
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else
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{
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pllfracn = (float_t)0U;
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}
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if (pllm != 0U)
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{
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switch (pllsource)
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{
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case 0x02: /* HSE used as PLL1 clock source */
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pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) + (pllfracn/(float_t)0x2000) +(float_t)1 );
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break;
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case 0x01: /* CSI used as PLL1 clock source */
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pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) + (pllfracn/(float_t)0x2000) +(float_t)1 );
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break;
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case 0x00: /* HSI used as PLL1 clock source */
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default:
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hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos));
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pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) + (pllfracn/(float_t)0x2000) +(float_t)1 );
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break;
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}
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pllp = (((RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVP) >> RCC_PLL1DIVR1_DIVP_Pos) + 1U ) ;
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sysclk = (uint32_t)(float_t)(pllvco/(float_t)pllp);
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}
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else
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{
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sysclk = 0U;
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}
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break;
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default: /* Unexpected, default to HSI used as system clock source (default after reset) */
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sysclk = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos));
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break;
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}
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/* system clock frequency : CM7 CPU frequency */
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core_presc = (RCC->CDCFGR & RCC_CDCFGR_CPRE);
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if (core_presc >= 8U)
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{
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SystemCoreClock = (sysclk >> (core_presc - RCC_CDCFGR_CPRE_3 + 1U));
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}
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else
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{
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SystemCoreClock = sysclk;
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}
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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