thomasandClaude Sonnet 5.5
66bb319423
Regeneration CubeMX (Appli) preparant le driver ST67W611M1 et la carte SD : - SPI4 (PE12/13/14, CS PF8) + DMA GPDMA1 canaux 4/5, SPI_RDY (PD12/EXTI12), CHIP_EN (PD13) et BOOT (PD15) pour la X-NUCLEO-67W61M1 sur l'Arduino - SDMMC1 + FatFs (appels d'init non generes dans main, IRQ SDMMC1 prio 14), PM14 en open-drain ; I2S6_CK sur PA5 pour liberer PC12 (SDMMC1_CK) - HAL UART retire ; USE_BSP_COM_FEATURE=0 - Audio preserve : ADF 4/16/24, prio IRQ 2, DMA canal 0 en priorite haute, GPDMA1_Channel2_IRQHandler deplace dans audio_irq.c (hors fichiers generes), BSP_MX_I2S6_Init (renommage dans le BSP pour eviter le conflit avec CubeMX) - Middlewares/ST/ST67W6X_Network_Driver, FatFs et sources HAL SPI/SD ajoutes (driver ST67 pas encore integre au build) Build et debug sous Linux : - gcc/toolchain-env.sh, gdbserver.sh, arm-gdb.sh : outils de STM32CubeIDE par glob ; flash.sh les retrouve ; ruby_compat.rb pour Ruby >= 3.2 (TouchGFX) - makefile_appli : sources SD/SPI/FatFs/audio_irq ; chmod +x des .out TouchGFX - Objets de build (*.o, *.d, *.su) retires de l'index (deja dans .gitignore) - AGENTS.md : toolchain Linux, configs VS Code (cppdbg et ST stlinkgdbtarget), pieges de l'extension ST (.settings/ide.store.json, preRunCommands reset) Verifie sur carte : audio OK, debug Appli/Boot OK. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
380 lines
10 KiB
C
380 lines
10 KiB
C
/* USER CODE BEGIN Header */
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/**
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******************************************************************************
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* @file spi_port.c
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* @author ST67 Application Team
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* @brief SPI bus interface porting layer implementation
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2026 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* USER CODE END Header */
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/**
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* This file is based on QCC74xSDK provided by Qualcomm.
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* See https://git.codelinaro.org/clo/qcc7xx/QCCSDK-QCC74x for more information.
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*
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* Reference source: examples/stm32_spi_host/QCC743_SPI_HOST/Core/Src/spi_iface.c
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*/
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/* Includes ------------------------------------------------------------------*/
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#include <stdio.h>
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#include <stdint.h>
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#include <string.h>
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#include <stdlib.h>
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#include "bsp_conf.h"
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#include "spi_port.h"
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#include "logging.h"
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#include "main.h"
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/* USER CODE BEGIN Includes */
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/* USER CODE END Includes */
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/* Global variables ----------------------------------------------------------*/
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/* USER CODE BEGIN GV */
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/* USER CODE END GV */
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/* Private typedef -----------------------------------------------------------*/
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/* USER CODE BEGIN PTD */
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/* USER CODE END PTD */
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/* Private defines -----------------------------------------------------------*/
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/* USER CODE BEGIN PD */
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/* USER CODE END PD */
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/* Private macros ------------------------------------------------------------*/
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/** SysTick Reload Value Register */
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#define SYSTICK_LOAD ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
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/** SysTick Current Value Register */
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#define SYSTICK_VALUE ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
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/**
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* @brief Wait function to ensure a minimum wait time (in CPU cycles)
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* @param _start_tick Tick value when the wait period started
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* @param _nb_tick Number of ticks to wait
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* @retval None
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*/
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#define WAIT_FROM(_start_tick, _nb_tick) do \
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{\
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int32_t _end_tick = (_start_tick) - (_nb_tick); \
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if (_end_tick < 0) /* Wrap */ \
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{ \
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_end_tick += SYSTICK_LOAD; \
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} \
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while( SYSTICK_VALUE> _end_tick) {} \
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}while(0)
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/** Convert microseconds to ticks */
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#define MICROSECOND_TO_TICK( _us ) ( (_us) * (SystemCoreClock>>20) )
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/* USER CODE BEGIN PM */
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/* USER CODE END PM */
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/* Private variables ---------------------------------------------------------*/
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/** SPI transaction complete callback */
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static spi_transaction_complete_t spi_port_transaction_complete_cb = NULL;
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static const char spi_port_error_str[] = "SPI not initialized\n";
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/* USER CODE BEGIN PV */
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/* USER CODE END PV */
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/* Private function prototypes -----------------------------------------------*/
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/* USER CODE BEGIN PFP */
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/* USER CODE END PFP */
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/* Functions Definition ------------------------------------------------------*/
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void *spi_port_memcpy(void *dest, const void *src, unsigned int len)
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{
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/* USER CODE BEGIN memcpy_1 */
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/* USER CODE END memcpy_1 */
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uint8_t *d = (uint8_t *)dest;
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const uint8_t *s = (const uint8_t *)src;
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/* Copy bytes until the destination address is aligned to 4 bytes */
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while (((uint32_t) d % 4 != 0) && len > 0)
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{
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*d++ = *s++;
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len--;
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}
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/* Copy 4-byte blocks */
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uint32_t *d32 = (uint32_t *)d;
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const uint32_t *s32 = (const uint32_t *)s;
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while (len >= 4U)
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{
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*d32++ = *s32++;
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len -= 4U;
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}
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/* Copy remaining bytes */
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d = (uint8_t *)d32;
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s = (const uint8_t *)s32;
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while (len > 0U)
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{
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*d++ = *s++;
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len--;
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}
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/* USER CODE BEGIN memcpy_2 */
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/* USER CODE END memcpy_2 */
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return dest;
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/* USER CODE BEGIN memcpy_End */
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/* USER CODE END memcpy_End */
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}
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int32_t spi_port_init(spi_transaction_complete_t transaction_complete_cb)
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{
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/* USER CODE BEGIN spi_port_init_1 */
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/* USER CODE END spi_port_init_1 */
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if (NCP_SPI_HANDLE.State == HAL_SPI_STATE_RESET)
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{
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LogError(spi_port_error_str);
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return -1;
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}
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/* Powering up the NCP using GPIO CHIP_EN */
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HAL_GPIO_WritePin(CHIP_EN_GPIO_Port, CHIP_EN_Pin, GPIO_PIN_SET);
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if (transaction_complete_cb != NULL)
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{
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spi_port_transaction_complete_cb = transaction_complete_cb;
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}
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/* USER CODE BEGIN spi_port_init_2 */
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/* USER CODE END spi_port_init_2 */
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return 0;
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/* USER CODE BEGIN spi_port_init_End */
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/* USER CODE END spi_port_init_End */
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}
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int32_t spi_port_deinit(void)
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{
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/* USER CODE BEGIN spi_port_deinit_1 */
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/* USER CODE END spi_port_deinit_1 */
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/* Switch off the NCP using GPIO CHIP_EN */
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HAL_GPIO_WritePin(CHIP_EN_GPIO_Port, CHIP_EN_Pin, GPIO_PIN_RESET);
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spi_port_transaction_complete_cb = NULL;
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/* USER CODE BEGIN spi_port_deinit_2 */
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/* USER CODE END spi_port_deinit_2 */
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return 0;
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/* USER CODE BEGIN spi_port_deinit_End */
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/* USER CODE END spi_port_deinit_End */
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}
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int32_t spi_port_transfer(void *tx_buf, void *rx_buf, uint16_t len, uint32_t timeout)
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{
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/* USER CODE BEGIN spi_port_transfer_1 */
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/* USER CODE END spi_port_transfer_1 */
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HAL_StatusTypeDef status;
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if (NCP_SPI_HANDLE.State == HAL_SPI_STATE_RESET)
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{
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LogError(spi_port_error_str);
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return -1;
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}
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#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
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SCB_CleanInvalidateDCache_by_Addr(rx_buf, len);
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#endif /* __DCACHE_PRESENT */
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/* Check whether host data is to be transmitted to the NCP, otherwise read only data from the NCP */
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if (tx_buf != NULL)
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{
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#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
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SCB_CleanDCache_by_Addr(tx_buf, len);
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#endif /* __DCACHE_PRESENT */
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status = HAL_SPI_TransmitReceive(&NCP_SPI_HANDLE, tx_buf, rx_buf, len, timeout);
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}
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else
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{
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assert_param(len <= SPI_DMA_XFER_SIZE_THRESHOLD);
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uint8_t tx_dummy[SPI_DMA_XFER_SIZE_THRESHOLD] = {0};
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status = HAL_SPI_TransmitReceive(&NCP_SPI_HANDLE, tx_dummy, rx_buf, len, timeout);
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}
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/* USER CODE BEGIN spi_port_transfer_2 */
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/* USER CODE END spi_port_transfer_2 */
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return ((status == HAL_OK) ? 0 : -1);
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/* USER CODE BEGIN spi_port_transfer_End */
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/* USER CODE END spi_port_transfer_End */
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}
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int32_t spi_port_transfer_dma(void *tx_buf, void *rx_buf, uint16_t len)
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{
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/* USER CODE BEGIN spi_port_transfer_dma_1 */
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/* USER CODE END spi_port_transfer_dma_1 */
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HAL_StatusTypeDef status;
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if (NCP_SPI_HANDLE.State == HAL_SPI_STATE_RESET)
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{
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LogError(spi_port_error_str);
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return -1;
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}
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#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
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SCB_CleanInvalidateDCache_by_Addr(rx_buf, len);
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#endif /* __DCACHE_PRESENT */
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/* Check whether host data is to be transmitted to the NCP, otherwise read only data from the NCP */
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if (tx_buf != NULL)
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{
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#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
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SCB_CleanDCache_by_Addr(tx_buf, len);
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#endif /* __DCACHE_PRESENT */
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/* USER CODE BEGIN spi_port_transfer_dma_trx */
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status = HAL_SPI_TransmitReceive_DMA(&NCP_SPI_HANDLE, tx_buf, rx_buf, len);
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/* USER CODE END spi_port_transfer_dma_trx */
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}
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else
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{
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/* USER CODE BEGIN spi_port_transfer_dma_rx */
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status = HAL_SPI_Receive_DMA(&NCP_SPI_HANDLE, rx_buf, len);
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/* USER CODE END spi_port_transfer_dma_rx */
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}
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/* USER CODE BEGIN spi_port_transfer_dma_2 */
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/* USER CODE END spi_port_transfer_dma_2 */
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return ((status == HAL_OK) ? 0 : -1);
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/* USER CODE BEGIN spi_port_transfer_dma_End */
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/* USER CODE END spi_port_transfer_dma_End */
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}
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int32_t spi_port_is_ready(void)
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{
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/* USER CODE BEGIN spi_port_is_ready_1 */
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/* USER CODE END spi_port_is_ready_1 */
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/* Check whether NCP data are available on the SPI bus */
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return (int32_t)HAL_GPIO_ReadPin(SPI_RDY_GPIO_Port, SPI_RDY_Pin);
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/* USER CODE BEGIN spi_port_is_ready_End */
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/* USER CODE END spi_port_is_ready_End */
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}
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int32_t spi_port_set_cs(int32_t state)
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{
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static int32_t last_falling_tick;
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/* USER CODE BEGIN spi_port_set_cs_1 */
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/* USER CODE END spi_port_set_cs_1 */
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if (state == 1)
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{
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WAIT_FROM(last_falling_tick, MICROSECOND_TO_TICK(2));
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/* Activate Chip Select before starting transfer */
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HAL_GPIO_WritePin(SPI_CS_GPIO_Port, SPI_CS_Pin, GPIO_PIN_SET);
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}
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else
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{
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/* Disable Chip Select when transfer is complete */
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HAL_GPIO_WritePin(SPI_CS_GPIO_Port, SPI_CS_Pin, GPIO_PIN_RESET);
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last_falling_tick = SYSTICK_VALUE;
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}
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/* USER CODE BEGIN spi_port_set_cs_2 */
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/* USER CODE END spi_port_set_cs_2 */
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return 0;
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/* USER CODE BEGIN spi_port_set_cs_End */
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/* USER CODE END spi_port_set_cs_End */
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}
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/* USER CODE BEGIN FD */
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/* USER CODE END FD */
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/* Weak functions redefinition -----------------------------------------------*/
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void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
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{
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/* USER CODE BEGIN HAL_SPI_TxCpltCallback_1 */
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/* USER CODE END HAL_SPI_TxCpltCallback_1 */
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if (hspi == &NCP_SPI_HANDLE)
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{
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spi_port_transaction_complete_cb();
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}
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/* USER CODE BEGIN HAL_SPI_TxCpltCallback_End */
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/* USER CODE END HAL_SPI_TxCpltCallback_End */
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}
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void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
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{
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/* USER CODE BEGIN HAL_SPI_RxCpltCallback_1 */
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/* USER CODE END HAL_SPI_RxCpltCallback_1 */
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if (hspi == &NCP_SPI_HANDLE)
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{
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spi_port_transaction_complete_cb();
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}
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/* USER CODE BEGIN HAL_SPI_RxCpltCallback_End */
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/* USER CODE END HAL_SPI_RxCpltCallback_End */
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}
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void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
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{
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/* USER CODE BEGIN HAL_SPI_TxRxCpltCallback_1 */
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/* USER CODE END HAL_SPI_TxRxCpltCallback_1 */
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if (hspi == &NCP_SPI_HANDLE)
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{
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spi_port_transaction_complete_cb();
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}
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/* USER CODE BEGIN HAL_SPI_TxRxCpltCallback_End */
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/* USER CODE END HAL_SPI_TxRxCpltCallback_End */
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}
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void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
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{
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/* USER CODE BEGIN HAL_SPI_ErrorCallback_1 */
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/* USER CODE END HAL_SPI_ErrorCallback_1 */
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if (hspi == &NCP_SPI_HANDLE)
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{
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Error_Handler();
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}
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/* USER CODE BEGIN HAL_SPI_ErrorCallback_End */
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/* USER CODE END HAL_SPI_ErrorCallback_End */
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}
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/* USER CODE BEGIN WFR */
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/* USER CODE END WFR */
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